From: Anup Patel <anup@brainfault.org> To: Weiwei Li <liweiwei@iscas.ac.cn> Cc: "Wei Wu (吴伟)" <lazyparser@gmail.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, wangjunqiang@iscas.ac.cn, "Bin Meng" <bin.meng@windriver.com>, "QEMU Developers" <qemu-devel@nongnu.org>, "Alistair Francis" <alistair.francis@wdc.com>, "Palmer Dabbelt" <palmer@dabbelt.com> Subject: Re: [PATCH v2 2/3] target/riscv: add support for svinval extension Date: Sat, 1 Jan 2022 18:45:36 +0530 [thread overview] Message-ID: <CAAhSdy32+q_oT4hE2ohsVnNcaEK29=BWnqyu5V3MQuXUMA7Rvg@mail.gmail.com> (raw) In-Reply-To: <20211231080923.24252-3-liweiwei@iscas.ac.cn> On Fri, Dec 31, 2021 at 1:43 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 7 ++ > target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++ > target/riscv/translate.c | 1 + > 5 files changed, 85 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cbcb7f522b..77ef0f85fe 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > + DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false), Please drop the "x-" prefix. The Svinval extension is already ratified. Regards, Anup > DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false), > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 1fbbde28c6..5dd9e53293 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -315,6 +315,7 @@ struct RISCVCPU { > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; > + bool ext_svinval; > bool ext_svnapot; > bool ext_zfh; > bool ext_zfhmin; > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 8617307b29..809464113a 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -784,3 +784,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm > fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm > fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm > fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm > + > +# *** Svinval Standard Extension *** > +sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma > +sfence_w_inval 0001100 00000 00000 000 00000 1110011 > +sfence_inval_ir 0001100 00001 00000 000 00000 1110011 > +hinval_vvma 0011011 ..... ..... 000 00000 1110011 @hfence_vvma > +hinval_gvma 0111011 ..... ..... 000 00000 1110011 @hfence_gvma > diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc > new file mode 100644 > index 0000000000..1dde665661 > --- /dev/null > +++ b/target/riscv/insn_trans/trans_svinval.c.inc > @@ -0,0 +1,75 @@ > +/* > + * RISC-V translation routines for the Svinval Standard Instruction Set. > + * > + * Copyright (c) 2020-2021 PLCT lab > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#define REQUIRE_SVINVAL(ctx) do { \ > + if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \ > + return false; \ > + } \ > +} while (0) > + > +static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a) > +{ > + REQUIRE_SVINVAL(ctx); > + /* Do the same as sfence.vma currently */ > + REQUIRE_EXT(ctx, RVS); > +#ifndef CONFIG_USER_ONLY > + gen_helper_tlb_flush(cpu_env); > + return true; > +#endif > + return false; > +} > + > +static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a) > +{ > + REQUIRE_SVINVAL(ctx); > + REQUIRE_EXT(ctx, RVS); > + /* Do nothing currently */ > + return true; > +} > + > +static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a) > +{ > + REQUIRE_SVINVAL(ctx); > + REQUIRE_EXT(ctx, RVS); > + /* Do nothing currently */ > + return true; > +} > + > +static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a) > +{ > + REQUIRE_SVINVAL(ctx); > + /* Do the same as hfence.vvma currently */ > + REQUIRE_EXT(ctx, RVH); > +#ifndef CONFIG_USER_ONLY > + gen_helper_hyp_tlb_flush(cpu_env); > + return true; > +#endif > + return false; > +} > + > +static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a) > +{ > + REQUIRE_SVINVAL(ctx); > + /* Do the same as hfence.gvma currently */ > + REQUIRE_EXT(ctx, RVH); > +#ifndef CONFIG_USER_ONLY > + gen_helper_hyp_gvma_tlb_flush(cpu_env); > + return true; > +#endif > + return false; > +} > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 5df6c0d800..47541a4db0 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -651,6 +651,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > #include "insn_trans/trans_rvb.c.inc" > #include "insn_trans/trans_rvzfh.c.inc" > #include "insn_trans/trans_privileged.c.inc" > +#include "insn_trans/trans_svinval.c.inc" > > /* Include the auto-generated decoder for 16 bit insn */ > #include "decode-insn16.c.inc" > -- > 2.17.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Weiwei Li <liweiwei@iscas.ac.cn> Cc: "Palmer Dabbelt" <palmer@dabbelt.com>, "Alistair Francis" <alistair.francis@wdc.com>, "Bin Meng" <bin.meng@windriver.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "QEMU Developers" <qemu-devel@nongnu.org>, wangjunqiang@iscas.ac.cn, "Wei Wu (吴伟)" <lazyparser@gmail.com> Subject: Re: [PATCH v2 2/3] target/riscv: add support for svinval extension Date: Sat, 1 Jan 2022 18:45:36 +0530 [thread overview] Message-ID: <CAAhSdy32+q_oT4hE2ohsVnNcaEK29=BWnqyu5V3MQuXUMA7Rvg@mail.gmail.com> (raw) In-Reply-To: <20211231080923.24252-3-liweiwei@iscas.ac.cn> On Fri, Dec 31, 2021 at 1:43 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 7 ++ > target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++ > target/riscv/translate.c | 1 + > 5 files changed, 85 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cbcb7f522b..77ef0f85fe 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > + DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false), Please drop the "x-" prefix. The Svinval extension is already ratified. Regards, Anup > DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false), > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 1fbbde28c6..5dd9e53293 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -315,6 +315,7 @@ struct RISCVCPU { > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; > + bool ext_svinval; > bool ext_svnapot; > bool ext_zfh; > bool ext_zfhmin; > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 8617307b29..809464113a 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -784,3 +784,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm > fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm > fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm > fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm > + > +# *** Svinval Standard Extension *** > +sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma > +sfence_w_inval 0001100 00000 00000 000 00000 1110011 > +sfence_inval_ir 0001100 00001 00000 000 00000 1110011 > +hinval_vvma 0011011 ..... ..... 000 00000 1110011 @hfence_vvma > +hinval_gvma 0111011 ..... ..... 000 00000 1110011 @hfence_gvma > diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc > new file mode 100644 > index 0000000000..1dde665661 > --- /dev/null > +++ b/target/riscv/insn_trans/trans_svinval.c.inc > @@ -0,0 +1,75 @@ > +/* > + * RISC-V translation routines for the Svinval Standard Instruction Set. > + * > + * Copyright (c) 2020-2021 PLCT lab > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#define REQUIRE_SVINVAL(ctx) do { \ > + if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \ > + return false; \ > + } \ > +} while (0) > + > +static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a) > +{ > + REQUIRE_SVINVAL(ctx); > + /* Do the same as sfence.vma currently */ > + REQUIRE_EXT(ctx, RVS); > +#ifndef CONFIG_USER_ONLY > + gen_helper_tlb_flush(cpu_env); > + return true; > +#endif > + return false; > +} > + > +static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a) > +{ > + REQUIRE_SVINVAL(ctx); > + REQUIRE_EXT(ctx, RVS); > + /* Do nothing currently */ > + return true; > +} > + > +static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a) > +{ > + REQUIRE_SVINVAL(ctx); > + REQUIRE_EXT(ctx, RVS); > + /* Do nothing currently */ > + return true; > +} > + > +static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a) > +{ > + REQUIRE_SVINVAL(ctx); > + /* Do the same as hfence.vvma currently */ > + REQUIRE_EXT(ctx, RVH); > +#ifndef CONFIG_USER_ONLY > + gen_helper_hyp_tlb_flush(cpu_env); > + return true; > +#endif > + return false; > +} > + > +static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a) > +{ > + REQUIRE_SVINVAL(ctx); > + /* Do the same as hfence.gvma currently */ > + REQUIRE_EXT(ctx, RVH); > +#ifndef CONFIG_USER_ONLY > + gen_helper_hyp_gvma_tlb_flush(cpu_env); > + return true; > +#endif > + return false; > +} > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 5df6c0d800..47541a4db0 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -651,6 +651,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > #include "insn_trans/trans_rvb.c.inc" > #include "insn_trans/trans_rvzfh.c.inc" > #include "insn_trans/trans_privileged.c.inc" > +#include "insn_trans/trans_svinval.c.inc" > > /* Include the auto-generated decoder for 16 bit insn */ > #include "decode-insn16.c.inc" > -- > 2.17.1 > >
next prev parent reply other threads:[~2022-01-01 13:16 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-31 8:09 [PATCH v2 0/3] support subsets of virtual memory extension Weiwei Li 2021-12-31 8:09 ` Weiwei Li 2021-12-31 8:09 ` [PATCH v2 1/3] target/riscv: add support for svnapot extension Weiwei Li 2021-12-31 8:09 ` Weiwei Li 2022-01-01 13:17 ` Anup Patel 2022-01-01 13:17 ` Anup Patel 2021-12-31 8:09 ` [PATCH v2 2/3] target/riscv: add support for svinval extension Weiwei Li 2021-12-31 8:09 ` Weiwei Li 2022-01-01 13:15 ` Anup Patel [this message] 2022-01-01 13:15 ` Anup Patel 2022-01-02 5:41 ` Weiwei Li 2022-01-02 5:41 ` Weiwei Li 2021-12-31 8:09 ` [PATCH v2 3/3] target/riscv: add support for svpbmt extension Weiwei Li 2021-12-31 8:09 ` Weiwei Li 2022-01-01 13:19 ` Anup Patel 2022-01-01 13:19 ` Anup Patel
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