From: Anup Patel <anup@brainfault.org> To: Weiwei Li <liweiwei@iscas.ac.cn> Cc: "Wei Wu (吴伟)" <lazyparser@gmail.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, wangjunqiang@iscas.ac.cn, "Bin Meng" <bin.meng@windriver.com>, "QEMU Developers" <qemu-devel@nongnu.org>, "Alistair Francis" <alistair.francis@wdc.com>, "Palmer Dabbelt" <palmer@dabbelt.com> Subject: Re: [PATCH v2 1/3] target/riscv: add support for svnapot extension Date: Sat, 1 Jan 2022 18:47:06 +0530 [thread overview] Message-ID: <CAAhSdy1jr-_ntceCCmHLCfcVcLnDrj4eVMugWaAMwxcvruHs2w@mail.gmail.com> (raw) In-Reply-To: <20211231080923.24252-2-liweiwei@iscas.ac.cn> On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/cpu_bits.h | 1 + > target/riscv/cpu_helper.c | 20 ++++++++++++++++---- > 4 files changed, 19 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6ef3314bce..cbcb7f522b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > + DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false), Please drop the "x-" prefix here as well. The Svnapot extension is already ratified. Regards, Anup > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index dc10f27093..1fbbde28c6 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -315,6 +315,7 @@ struct RISCVCPU { > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; > + bool ext_svnapot; > bool ext_zfh; > bool ext_zfhmin; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 1e31f4d35f..1156c941cb 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -483,6 +483,7 @@ typedef enum { > #define PTE_A 0x040 /* Accessed */ > #define PTE_D 0x080 /* Dirty */ > #define PTE_SOFT 0x300 /* Reserved for Software */ > +#define PTE_N 0x8000000000000000 /* NAPOT translation */ > > /* Page table PPN shift amount */ > #define PTE_PPN_SHIFT 10 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 10f3baba53..e044153986 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -619,9 +619,12 @@ restart: > return TRANSLATE_FAIL; > } > > - hwaddr ppn = pte >> PTE_PPN_SHIFT; > + hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT; > > - if (!(pte & PTE_V)) { > + RISCVCPU *cpu = env_archcpu(env); > + if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) { > + return TRANSLATE_FAIL; > + } else if (!(pte & PTE_V)) { > /* Invalid PTE */ > return TRANSLATE_FAIL; > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > @@ -699,8 +702,17 @@ restart: > /* for superpage mappings, make a fake leaf PTE for the TLB's > benefit. */ > target_ulong vpn = addr >> PGSHIFT; > - *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | > - (addr & ~TARGET_PAGE_MASK); > + > + int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0); > + if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) || > + (napot_bits != 0 && napot_bits != 4)) { > + return TRANSLATE_FAIL; > + } > + > + *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) | > + (vpn & (((target_ulong)1 << napot_bits) - 1)) | > + (vpn & (((target_ulong)1 << ptshift) - 1)) > + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); > > /* set permissions on the TLB entry */ > if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { > -- > 2.17.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Weiwei Li <liweiwei@iscas.ac.cn> Cc: "Palmer Dabbelt" <palmer@dabbelt.com>, "Alistair Francis" <alistair.francis@wdc.com>, "Bin Meng" <bin.meng@windriver.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "QEMU Developers" <qemu-devel@nongnu.org>, wangjunqiang@iscas.ac.cn, "Wei Wu (吴伟)" <lazyparser@gmail.com> Subject: Re: [PATCH v2 1/3] target/riscv: add support for svnapot extension Date: Sat, 1 Jan 2022 18:47:06 +0530 [thread overview] Message-ID: <CAAhSdy1jr-_ntceCCmHLCfcVcLnDrj4eVMugWaAMwxcvruHs2w@mail.gmail.com> (raw) In-Reply-To: <20211231080923.24252-2-liweiwei@iscas.ac.cn> On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/cpu_bits.h | 1 + > target/riscv/cpu_helper.c | 20 ++++++++++++++++---- > 4 files changed, 19 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6ef3314bce..cbcb7f522b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > + DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false), Please drop the "x-" prefix here as well. The Svnapot extension is already ratified. Regards, Anup > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index dc10f27093..1fbbde28c6 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -315,6 +315,7 @@ struct RISCVCPU { > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; > + bool ext_svnapot; > bool ext_zfh; > bool ext_zfhmin; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 1e31f4d35f..1156c941cb 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -483,6 +483,7 @@ typedef enum { > #define PTE_A 0x040 /* Accessed */ > #define PTE_D 0x080 /* Dirty */ > #define PTE_SOFT 0x300 /* Reserved for Software */ > +#define PTE_N 0x8000000000000000 /* NAPOT translation */ > > /* Page table PPN shift amount */ > #define PTE_PPN_SHIFT 10 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 10f3baba53..e044153986 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -619,9 +619,12 @@ restart: > return TRANSLATE_FAIL; > } > > - hwaddr ppn = pte >> PTE_PPN_SHIFT; > + hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT; > > - if (!(pte & PTE_V)) { > + RISCVCPU *cpu = env_archcpu(env); > + if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) { > + return TRANSLATE_FAIL; > + } else if (!(pte & PTE_V)) { > /* Invalid PTE */ > return TRANSLATE_FAIL; > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > @@ -699,8 +702,17 @@ restart: > /* for superpage mappings, make a fake leaf PTE for the TLB's > benefit. */ > target_ulong vpn = addr >> PGSHIFT; > - *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | > - (addr & ~TARGET_PAGE_MASK); > + > + int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0); > + if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) || > + (napot_bits != 0 && napot_bits != 4)) { > + return TRANSLATE_FAIL; > + } > + > + *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) | > + (vpn & (((target_ulong)1 << napot_bits) - 1)) | > + (vpn & (((target_ulong)1 << ptshift) - 1)) > + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); > > /* set permissions on the TLB entry */ > if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { > -- > 2.17.1 > >
next prev parent reply other threads:[~2022-01-01 13:18 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-31 8:09 [PATCH v2 0/3] support subsets of virtual memory extension Weiwei Li 2021-12-31 8:09 ` Weiwei Li 2021-12-31 8:09 ` [PATCH v2 1/3] target/riscv: add support for svnapot extension Weiwei Li 2021-12-31 8:09 ` Weiwei Li 2022-01-01 13:17 ` Anup Patel [this message] 2022-01-01 13:17 ` Anup Patel 2021-12-31 8:09 ` [PATCH v2 2/3] target/riscv: add support for svinval extension Weiwei Li 2021-12-31 8:09 ` Weiwei Li 2022-01-01 13:15 ` Anup Patel 2022-01-01 13:15 ` Anup Patel 2022-01-02 5:41 ` Weiwei Li 2022-01-02 5:41 ` Weiwei Li 2021-12-31 8:09 ` [PATCH v2 3/3] target/riscv: add support for svpbmt extension Weiwei Li 2021-12-31 8:09 ` Weiwei Li 2022-01-01 13:19 ` Anup Patel 2022-01-01 13:19 ` Anup Patel
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