* [U-Boot] [PATCH] ARM: cpu: Add ARMv7 barrier operations support
2015-03-20 15:16 [U-Boot] [PATCH] ARM: cpu: Add ARMv7 barrier operations support Vladimir Barinov
@ 2015-03-25 7:47 ` Nobuhiro Iwamatsu
2015-04-16 12:06 ` Albert ARIBAUD
2015-08-20 20:02 ` Vladimir Barinov
2 siblings, 0 replies; 4+ messages in thread
From: Nobuhiro Iwamatsu @ 2015-03-25 7:47 UTC (permalink / raw)
To: u-boot
Hi,
2015-03-21 0:16 GMT+09:00 Vladimir Barinov
<vladimir.barinov@cogentembedded.com>:
> From: Valentine Barshak <valentine.barshak@cogentembedded.com>
>
> This enables ARMv7 barrier operations support when
> march=armv7-a is enabled.
>
> Using CP15 barriers causes U-Boot bootm command crash when
> transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU.
> Using ARMv7 barrier operations instead of the deprecated CP15 barriers
> helps to avoid these issues.
>
> Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Best regards,
Nobuhiro
> ---
> arch/arm/cpu/armv7/cache_v7.c | 14 +++++++-------
> arch/arm/include/asm/armv7.h | 10 ++++++++++
> 2 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
> index 0f9d837..e8ee875 100644
> --- a/arch/arm/cpu/armv7/cache_v7.c
> +++ b/arch/arm/cpu/armv7/cache_v7.c
> @@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
> }
> }
> /* DSB to make sure the operation is complete */
> - CP15DSB;
> + DSB;
> }
>
> static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
> @@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
> }
> }
> /* DSB to make sure the operation is complete */
> - CP15DSB;
> + DSB;
> }
>
> static void v7_maint_dcache_level_setway(u32 level, u32 operation)
> @@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
> }
>
> /* DSB to make sure the operation is complete */
> - CP15DSB;
> + DSB;
> }
>
> /* Invalidate TLB */
> @@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
> /* Invalidate entire instruction TLB */
> asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
> /* Full system DSB - make sure that the invalidation is complete */
> - CP15DSB;
> + DSB;
> /* Full system ISB - make sure the instruction stream sees it */
> - CP15ISB;
> + ISB;
> }
>
> void invalidate_dcache_all(void)
> @@ -343,10 +343,10 @@ void invalidate_icache_all(void)
> asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
>
> /* Full system DSB - make sure that the invalidation is complete */
> - CP15DSB;
> + DSB;
>
> /* ISB - make sure the instruction stream sees it */
> - CP15ISB;
> + ISB;
> }
> #else
> void invalidate_icache_all(void)
> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
> index a13da23..189f3f0 100644
> --- a/arch/arm/include/asm/armv7.h
> +++ b/arch/arm/include/asm/armv7.h
> @@ -70,6 +70,16 @@
> #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
> #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
>
> +#ifdef __ARM_ARCH_7A__
> +#define ISB asm volatile ("isb" : : : "memory")
> +#define DSB asm volatile ("dsb" : : : "memory")
> +#define DMB asm volatile ("dmb" : : : "memory")
> +#else
> +#define ISB CP15ISB
> +#define DSB CP15DSB
> +#define DMB CP15DMB
> +#endif
> +
> /*
> * Workaround for ARM errata # 798870
> * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
> --
> 1.9.3
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
--
Nobuhiro Iwamatsu
^ permalink raw reply [flat|nested] 4+ messages in thread* [U-Boot] [PATCH] ARM: cpu: Add ARMv7 barrier operations support
2015-03-20 15:16 [U-Boot] [PATCH] ARM: cpu: Add ARMv7 barrier operations support Vladimir Barinov
2015-03-25 7:47 ` Nobuhiro Iwamatsu
@ 2015-04-16 12:06 ` Albert ARIBAUD
2015-08-20 20:02 ` Vladimir Barinov
2 siblings, 0 replies; 4+ messages in thread
From: Albert ARIBAUD @ 2015-04-16 12:06 UTC (permalink / raw)
To: u-boot
Hello Vladimir,
On Fri, 20 Mar 2015 18:16:17 +0300, Vladimir Barinov <vladimir.barinov@cogentembedded.com> wrote:
> From: Valentine Barshak <valentine.barshak@cogentembedded.com>
>
> This enables ARMv7 barrier operations support when
> march=armv7-a is enabled.
>
> Using CP15 barriers causes U-Boot bootm command crash when
> transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU.
> Using ARMv7 barrier operations instead of the deprecated CP15 barriers
> helps to avoid these issues.
>
> Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> ---
> arch/arm/cpu/armv7/cache_v7.c | 14 +++++++-------
> arch/arm/include/asm/armv7.h | 10 ++++++++++
> 2 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
> index 0f9d837..e8ee875 100644
> --- a/arch/arm/cpu/armv7/cache_v7.c
> +++ b/arch/arm/cpu/armv7/cache_v7.c
> @@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
> }
> }
> /* DSB to make sure the operation is complete */
> - CP15DSB;
> + DSB;
> }
>
> static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
> @@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
> }
> }
> /* DSB to make sure the operation is complete */
> - CP15DSB;
> + DSB;
> }
>
> static void v7_maint_dcache_level_setway(u32 level, u32 operation)
> @@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
> }
>
> /* DSB to make sure the operation is complete */
> - CP15DSB;
> + DSB;
> }
>
> /* Invalidate TLB */
> @@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
> /* Invalidate entire instruction TLB */
> asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
> /* Full system DSB - make sure that the invalidation is complete */
> - CP15DSB;
> + DSB;
> /* Full system ISB - make sure the instruction stream sees it */
> - CP15ISB;
> + ISB;
> }
>
> void invalidate_dcache_all(void)
> @@ -343,10 +343,10 @@ void invalidate_icache_all(void)
> asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
>
> /* Full system DSB - make sure that the invalidation is complete */
> - CP15DSB;
> + DSB;
>
> /* ISB - make sure the instruction stream sees it */
> - CP15ISB;
> + ISB;
> }
> #else
> void invalidate_icache_all(void)
> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
> index a13da23..189f3f0 100644
> --- a/arch/arm/include/asm/armv7.h
> +++ b/arch/arm/include/asm/armv7.h
> @@ -70,6 +70,16 @@
> #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
> #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
>
> +#ifdef __ARM_ARCH_7A__
> +#define ISB asm volatile ("isb" : : : "memory")
> +#define DSB asm volatile ("dsb" : : : "memory")
> +#define DMB asm volatile ("dmb" : : : "memory")
> +#else
> +#define ISB CP15ISB
> +#define DSB CP15DSB
> +#define DMB CP15DMB
> +#endif
> +
> /*
> * Workaround for ARM errata # 798870
> * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
> --
> 1.9.3
>
Applied to u-boot-arm/master, thanks!
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 4+ messages in thread* [U-Boot] [PATCH] ARM: cpu: Add ARMv7 barrier operations support
2015-03-20 15:16 [U-Boot] [PATCH] ARM: cpu: Add ARMv7 barrier operations support Vladimir Barinov
2015-03-25 7:47 ` Nobuhiro Iwamatsu
2015-04-16 12:06 ` Albert ARIBAUD
@ 2015-08-20 20:02 ` Vladimir Barinov
2 siblings, 0 replies; 4+ messages in thread
From: Vladimir Barinov @ 2015-08-20 20:02 UTC (permalink / raw)
To: u-boot
Hello Albert,
Could you provide any response on this patch.
TIA,
Vladimir
On 20.03.2015 18:16, Vladimir Barinov wrote:
> From: Valentine Barshak <valentine.barshak@cogentembedded.com>
>
> This enables ARMv7 barrier operations support when
> march=armv7-a is enabled.
>
> Using CP15 barriers causes U-Boot bootm command crash when
> transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU.
> Using ARMv7 barrier operations instead of the deprecated CP15 barriers
> helps to avoid these issues.
>
> Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> ---
> arch/arm/cpu/armv7/cache_v7.c | 14 +++++++-------
> arch/arm/include/asm/armv7.h | 10 ++++++++++
> 2 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
> index 0f9d837..e8ee875 100644
> --- a/arch/arm/cpu/armv7/cache_v7.c
> +++ b/arch/arm/cpu/armv7/cache_v7.c
> @@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
> }
> }
> /* DSB to make sure the operation is complete */
> - CP15DSB;
> + DSB;
> }
>
> static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
> @@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
> }
> }
> /* DSB to make sure the operation is complete */
> - CP15DSB;
> + DSB;
> }
>
> static void v7_maint_dcache_level_setway(u32 level, u32 operation)
> @@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
> }
>
> /* DSB to make sure the operation is complete */
> - CP15DSB;
> + DSB;
> }
>
> /* Invalidate TLB */
> @@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
> /* Invalidate entire instruction TLB */
> asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
> /* Full system DSB - make sure that the invalidation is complete */
> - CP15DSB;
> + DSB;
> /* Full system ISB - make sure the instruction stream sees it */
> - CP15ISB;
> + ISB;
> }
>
> void invalidate_dcache_all(void)
> @@ -343,10 +343,10 @@ void invalidate_icache_all(void)
> asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
>
> /* Full system DSB - make sure that the invalidation is complete */
> - CP15DSB;
> + DSB;
>
> /* ISB - make sure the instruction stream sees it */
> - CP15ISB;
> + ISB;
> }
> #else
> void invalidate_icache_all(void)
> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
> index a13da23..189f3f0 100644
> --- a/arch/arm/include/asm/armv7.h
> +++ b/arch/arm/include/asm/armv7.h
> @@ -70,6 +70,16 @@
> #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
> #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
>
> +#ifdef __ARM_ARCH_7A__
> +#define ISB asm volatile ("isb" : : : "memory")
> +#define DSB asm volatile ("dsb" : : : "memory")
> +#define DMB asm volatile ("dmb" : : : "memory")
> +#else
> +#define ISB CP15ISB
> +#define DSB CP15DSB
> +#define DMB CP15DMB
> +#endif
> +
> /*
> * Workaround for ARM errata # 798870
> * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
^ permalink raw reply [flat|nested] 4+ messages in thread