* [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv
@ 2019-02-06 5:28 Richard Henderson
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 1/3] target/arm: Force result size into dp after operation Richard Henderson
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Richard Henderson @ 2019-02-06 5:28 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Changes since v1:
* Typo fixed in patch 2, which had scrogged FMOV
* Return 0 for NaN, as for any other ARM fp conversion.
r~
Richard Henderson (3):
target/arm: Force result size into dp after operation
target/arm: Restructure disas_fp_int_conv
target/arm: Implement ARMv8.3-JSConv
target/arm/cpu.h | 10 ++++
target/arm/helper.h | 2 +
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 2 +
target/arm/op_helper.c | 76 +++++++++++++++++++++++
target/arm/translate-a64.c | 120 +++++++++++++++++++++++--------------
target/arm/translate.c | 47 ++++++++++-----
7 files changed, 197 insertions(+), 61 deletions(-)
--
2.17.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 1/3] target/arm: Force result size into dp after operation
2019-02-06 5:28 [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
@ 2019-02-06 5:28 ` Richard Henderson
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 2/3] target/arm: Restructure disas_fp_int_conv Richard Henderson
` (2 subsequent siblings)
3 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-02-06 5:28 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Rather than a complex set of cases testing for writeback,
adjust DP after performing the operation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 66cf28c8cb..eb25895876 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3970,6 +3970,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
tcg_gen_or_i32(tmp, tmp, tmp2);
tcg_temp_free_i32(tmp2);
gen_vfp_msr(tmp);
+ dp = 0; /* always a single precision result */
break;
}
case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */
@@ -3993,20 +3994,25 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
tcg_gen_or_i32(tmp, tmp, tmp2);
tcg_temp_free_i32(tmp2);
gen_vfp_msr(tmp);
+ dp = 0; /* always a single precision result */
break;
}
case 8: /* cmp */
gen_vfp_cmp(dp);
+ dp = -1; /* no write back */
break;
case 9: /* cmpe */
gen_vfp_cmpe(dp);
+ dp = -1; /* no write back */
break;
case 10: /* cmpz */
gen_vfp_cmp(dp);
+ dp = -1; /* no write back */
break;
case 11: /* cmpez */
gen_vfp_F1_ld0(dp);
gen_vfp_cmpe(dp);
+ dp = -1; /* no write back */
break;
case 12: /* vrintr */
{
@@ -4047,10 +4053,12 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
break;
}
case 15: /* single<->double conversion */
- if (dp)
+ if (dp) {
gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
- else
+ } else {
gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
+ }
+ dp = !dp; /* result size is opposite */
break;
case 16: /* fuito */
gen_vfp_uito(dp, 0);
@@ -4084,15 +4092,19 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
break;
case 24: /* ftoui */
gen_vfp_toui(dp, 0);
+ dp = 0; /* always an integer result */
break;
case 25: /* ftouiz */
gen_vfp_touiz(dp, 0);
+ dp = 0; /* always an integer result */
break;
case 26: /* ftosi */
gen_vfp_tosi(dp, 0);
+ dp = 0; /* always an integer result */
break;
case 27: /* ftosiz */
gen_vfp_tosiz(dp, 0);
+ dp = 0; /* always an integer result */
break;
case 28: /* ftosh */
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
@@ -4126,20 +4138,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
return 1;
}
- /* Write back the result. */
- if (op == 15 && (rn >= 8 && rn <= 11)) {
- /* Comparison, do nothing. */
- } else if (op == 15 && dp && ((rn & 0x1c) == 0x18 ||
- (rn & 0x1e) == 0x6)) {
- /* VCVT double to int: always integer result.
- * VCVT double to half precision is always a single
- * precision result.
- */
- gen_mov_vreg_F0(0, rd);
- } else if (op == 15 && rn == 15) {
- /* conversion */
- gen_mov_vreg_F0(!dp, rd);
- } else {
+ /* Write back the result, if any. */
+ if (dp >= 0) {
gen_mov_vreg_F0(dp, rd);
}
--
2.17.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 2/3] target/arm: Restructure disas_fp_int_conv
2019-02-06 5:28 [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 1/3] target/arm: Force result size into dp after operation Richard Henderson
@ 2019-02-06 5:28 ` Richard Henderson
2019-02-14 13:52 ` Peter Maydell
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
2019-02-14 13:53 ` [Qemu-devel] [PATCH v2 0/3] " Peter Maydell
3 siblings, 1 reply; 11+ messages in thread
From: Richard Henderson @ 2019-02-06 5:28 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
For opcodes 0-5, move some if conditions into the structure
of a switch statement. For opcodes 6 & 7, decode everything
at once with a second switch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 94 ++++++++++++++++++++------------------
1 file changed, 49 insertions(+), 45 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e002251ac6..2f849a6951 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6541,68 +6541,72 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
int type = extract32(insn, 22, 2);
bool sbit = extract32(insn, 29, 1);
bool sf = extract32(insn, 31, 1);
+ bool itof = false;
if (sbit) {
- unallocated_encoding(s);
- return;
+ goto do_unallocated;
}
- if (opcode > 5) {
- /* FMOV */
- bool itof = opcode & 1;
-
- if (rmode >= 2) {
- unallocated_encoding(s);
- return;
- }
-
- switch (sf << 3 | type << 1 | rmode) {
- case 0x0: /* 32 bit */
- case 0xa: /* 64 bit */
- case 0xd: /* 64 bit to top half of quad */
- break;
- case 0x6: /* 16-bit float, 32-bit int */
- case 0xe: /* 16-bit float, 64-bit int */
- if (dc_isar_feature(aa64_fp16, s)) {
- break;
- }
- /* fallthru */
- default:
- /* all other sf/type/rmode combinations are invalid */
- unallocated_encoding(s);
- return;
- }
-
- if (!fp_access_check(s)) {
- return;
- }
- handle_fmov(s, rd, rn, type, itof);
- } else {
- /* actual FP conversions */
- bool itof = extract32(opcode, 1, 1);
-
- if (rmode != 0 && opcode > 1) {
- unallocated_encoding(s);
- return;
+ switch (opcode) {
+ case 2: /* SCVTF */
+ case 3: /* UCVTF */
+ itof = true;
+ /* fallthru */
+ case 4: /* FCVTAS */
+ case 5: /* FCVTAU */
+ if (rmode != 0) {
+ goto do_unallocated;
}
+ /* fallthru */
+ case 0: /* FCVT[NPMZ]S */
+ case 1: /* FCVT[NPMZ]U */
switch (type) {
case 0: /* float32 */
case 1: /* float64 */
break;
case 3: /* float16 */
- if (dc_isar_feature(aa64_fp16, s)) {
- break;
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ goto do_unallocated;
}
- /* fallthru */
+ break;
default:
- unallocated_encoding(s);
- return;
+ goto do_unallocated;
}
-
if (!fp_access_check(s)) {
return;
}
handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
+ break;
+
+ default:
+ switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
+ case 0b01100110: /* FMOV half <-> 32-bit int */
+ case 0b01100111:
+ case 0b11100110: /* FMOV half <-> 64-bit int */
+ case 0b11100111:
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ goto do_unallocated;
+ }
+ /* fallthru */
+ case 0b00000110: /* FMOV 32-bit */
+ case 0b00000111:
+ case 0b10100110: /* FMOV 64-bit */
+ case 0b10100111:
+ case 0b11001110: /* FMOV top half of 128-bit */
+ case 0b11001111:
+ if (!fp_access_check(s)) {
+ return;
+ }
+ itof = opcode & 1;
+ handle_fmov(s, rd, rn, type, itof);
+ break;
+
+ default:
+ do_unallocated:
+ unallocated_encoding(s);
+ return;
+ }
+ break;
}
}
--
2.17.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.3-JSConv
2019-02-06 5:28 [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 1/3] target/arm: Force result size into dp after operation Richard Henderson
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 2/3] target/arm: Restructure disas_fp_int_conv Richard Henderson
@ 2019-02-06 5:28 ` Richard Henderson
2019-02-06 7:03 ` Laurent Desnogues
2019-02-14 13:51 ` Peter Maydell
2019-02-14 13:53 ` [Qemu-devel] [PATCH v2 0/3] " Peter Maydell
3 siblings, 2 replies; 11+ messages in thread
From: Richard Henderson @ 2019-02-06 5:28 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Return 0 for NaN
---
target/arm/cpu.h | 10 +++++
target/arm/helper.h | 2 +
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 2 +
target/arm/op_helper.c | 76 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-a64.c | 26 +++++++++++++
target/arm/translate.c | 15 ++++++++
7 files changed, 132 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 47238e4245..bfc532f0ca 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3227,6 +3227,11 @@ static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
}
+static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
+}
+
static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
@@ -3305,6 +3310,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
}
+static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
+}
+
static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 53a38188c6..6998f7e8d5 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -218,6 +218,8 @@ DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr)
DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr)
DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
+DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr)
+
/* neon_helper.c */
DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index edf6e0e1f1..8ea6569088 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2001,6 +2001,7 @@ static void arm_max_initfn(Object *obj)
cpu->isar.id_isar5 = t;
t = cpu->isar.id_isar6;
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
cpu->isar.id_isar6 = t;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index eff0f164dd..69e4134f79 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -311,6 +311,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_aa64isar0 = t;
t = cpu->isar.id_aa64isar1;
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
@@ -344,6 +345,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_isar5 = u;
u = cpu->isar.id_isar6;
+ u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
cpu->isar.id_isar6 = u;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index c998eadfaa..be555c44e4 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -24,6 +24,7 @@
#include "internals.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
+#include "fpu/softfloat.h"
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
@@ -1376,3 +1377,78 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
return ((uint32_t)x >> shift) | (x << (32 - shift));
}
}
+
+/*
+ * Implement float64 to int32_t conversion without saturation;
+ * the result is supplied modulo 2^32.
+ */
+uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
+{
+ float_status *status = vstatus;
+ uint32_t exp, sign;
+ uint64_t frac;
+ uint32_t inexact = 1; /* !Z */
+
+ sign = extract64(value, 63, 1);
+ exp = extract64(value, 52, 11);
+ frac = extract64(value, 0, 52);
+
+ if (exp == 0) {
+ /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
+ inexact = sign;
+ if (frac != 0) {
+ if (status->flush_inputs_to_zero) {
+ float_raise(float_flag_input_denormal, status);
+ } else {
+ float_raise(float_flag_inexact, status);
+ inexact = 1;
+ }
+ }
+ frac = 0;
+ } else if (exp == 0x7ff) {
+ /* This operation raises Invalid for both NaN and overflow (Inf). */
+ float_raise(float_flag_invalid, status);
+ frac = 0;
+ } else {
+ int true_exp = exp - 1023;
+ int shift = true_exp - 52;
+
+ /* Restore implicit bit. */
+ frac |= 1ull << 52;
+
+ /* Shift the fraction into place. */
+ if (shift >= 0) {
+ /* The number is so large we must shift the fraction left. */
+ if (shift >= 64) {
+ /* The the fraction is shifted out entirely. */
+ frac = 0;
+ } else {
+ frac <<= shift;
+ }
+ } else if (shift > -64) {
+ /* Normal case -- shift right and notice if bits shift out. */
+ inexact = (frac << (64 + shift)) != 0;
+ frac >>= -shift;
+ } else {
+ /* The fraction is shifted out entirely. */
+ frac = 0;
+ }
+
+ /* Notice overflow or inexact exceptions. */
+ if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) {
+ /* Overflow, for which this operation raises invalid. */
+ float_raise(float_flag_invalid, status);
+ inexact = 1;
+ } else if (inexact) {
+ float_raise(float_flag_inexact, status);
+ }
+
+ /* Honor the sign. */
+ if (sign) {
+ frac = -frac;
+ }
+ }
+
+ /* Pack the result and the env->ZF representation of Z together. */
+ return deposit64(frac, 32, 32, inexact);
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2f849a6951..b03e592edd 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6526,6 +6526,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
}
}
+static void handle_fjcvtzs(DisasContext *s, int rd, int rn)
+{
+ TCGv_i64 t = read_fp_dreg(s, rn);
+ TCGv_ptr fpstatus = get_fpstatus_ptr(false);
+
+ gen_helper_fjcvtzs(t, t, fpstatus);
+
+ tcg_temp_free_ptr(fpstatus);
+
+ tcg_gen_ext32u_i64(cpu_reg(s, rd), t);
+ tcg_gen_extrh_i64_i32(cpu_ZF, t);
+ tcg_gen_movi_i32(cpu_CF, 0);
+ tcg_gen_movi_i32(cpu_NF, 0);
+ tcg_gen_movi_i32(cpu_VF, 0);
+
+ tcg_temp_free_i64(t);
+}
+
/* Floating point <-> integer conversions
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
@@ -6601,6 +6619,14 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
handle_fmov(s, rd, rn, type, itof);
break;
+ case 0b00111110: /* FJCVTZS */
+ if (!dc_isar_feature(aa64_jscvt, s)) {
+ goto do_unallocated;
+ } else if (fp_access_check(s)) {
+ handle_fjcvtzs(s, rd, rn);
+ }
+ break;
+
default:
do_unallocated:
unallocated_encoding(s);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index eb25895876..a92d06b05b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4066,6 +4066,21 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
case 17: /* fsito */
gen_vfp_sito(dp, 0);
break;
+ case 19: /* vjcvt */
+ if (!dp || !dc_isar_feature(aa32_jscvt, s)) {
+ return 1;
+ } else {
+ TCGv_ptr fpst = get_fpstatus_ptr(0);
+ gen_helper_fjcvtzs(cpu_F0d, cpu_F0d, fpst);
+ tcg_temp_free_ptr(fpst);
+
+ tcg_gen_extr_i64_i32(cpu_F0s, cpu_ZF, cpu_F0d);
+ tcg_gen_movi_i32(cpu_NF, 0);
+ tcg_gen_movi_i32(cpu_CF, 0);
+ tcg_gen_movi_i32(cpu_VF, 0);
+ dp = 0; /* always a single precision result */
+ }
+ break;
case 20: /* fshto */
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
return 1;
--
2.17.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.3-JSConv
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
@ 2019-02-06 7:03 ` Laurent Desnogues
2019-02-14 13:51 ` Peter Maydell
1 sibling, 0 replies; 11+ messages in thread
From: Laurent Desnogues @ 2019-02-06 7:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Peter Maydell
Hello,
On Wed, Feb 6, 2019 at 6:32 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Thanks,
Laurent
> ---
> v2: Return 0 for NaN
> ---
> target/arm/cpu.h | 10 +++++
> target/arm/helper.h | 2 +
> target/arm/cpu.c | 1 +
> target/arm/cpu64.c | 2 +
> target/arm/op_helper.c | 76 ++++++++++++++++++++++++++++++++++++++
> target/arm/translate-a64.c | 26 +++++++++++++
> target/arm/translate.c | 15 ++++++++
> 7 files changed, 132 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 47238e4245..bfc532f0ca 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -3227,6 +3227,11 @@ static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
> return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
> }
>
> +static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
> +{
> + return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
> +}
> +
> static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
> {
> return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
> @@ -3305,6 +3310,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
> return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
> }
>
> +static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
> +{
> + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
> +}
> +
> static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
> {
> return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
> diff --git a/target/arm/helper.h b/target/arm/helper.h
> index 53a38188c6..6998f7e8d5 100644
> --- a/target/arm/helper.h
> +++ b/target/arm/helper.h
> @@ -218,6 +218,8 @@ DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr)
> DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr)
> DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
>
> +DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr)
> +
> /* neon_helper.c */
> DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32)
> DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32)
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index edf6e0e1f1..8ea6569088 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2001,6 +2001,7 @@ static void arm_max_initfn(Object *obj)
> cpu->isar.id_isar5 = t;
>
> t = cpu->isar.id_isar6;
> + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
> t = FIELD_DP32(t, ID_ISAR6, DP, 1);
> cpu->isar.id_isar6 = t;
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index eff0f164dd..69e4134f79 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -311,6 +311,7 @@ static void aarch64_max_initfn(Object *obj)
> cpu->isar.id_aa64isar0 = t;
>
> t = cpu->isar.id_aa64isar1;
> + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
> t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
> t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
> t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
> @@ -344,6 +345,7 @@ static void aarch64_max_initfn(Object *obj)
> cpu->isar.id_isar5 = u;
>
> u = cpu->isar.id_isar6;
> + u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
> u = FIELD_DP32(u, ID_ISAR6, DP, 1);
> cpu->isar.id_isar6 = u;
>
> diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
> index c998eadfaa..be555c44e4 100644
> --- a/target/arm/op_helper.c
> +++ b/target/arm/op_helper.c
> @@ -24,6 +24,7 @@
> #include "internals.h"
> #include "exec/exec-all.h"
> #include "exec/cpu_ldst.h"
> +#include "fpu/softfloat.h"
>
> #define SIGNBIT (uint32_t)0x80000000
> #define SIGNBIT64 ((uint64_t)1 << 63)
> @@ -1376,3 +1377,78 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
> return ((uint32_t)x >> shift) | (x << (32 - shift));
> }
> }
> +
> +/*
> + * Implement float64 to int32_t conversion without saturation;
> + * the result is supplied modulo 2^32.
> + */
> +uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
> +{
> + float_status *status = vstatus;
> + uint32_t exp, sign;
> + uint64_t frac;
> + uint32_t inexact = 1; /* !Z */
> +
> + sign = extract64(value, 63, 1);
> + exp = extract64(value, 52, 11);
> + frac = extract64(value, 0, 52);
> +
> + if (exp == 0) {
> + /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
> + inexact = sign;
> + if (frac != 0) {
> + if (status->flush_inputs_to_zero) {
> + float_raise(float_flag_input_denormal, status);
> + } else {
> + float_raise(float_flag_inexact, status);
> + inexact = 1;
> + }
> + }
> + frac = 0;
> + } else if (exp == 0x7ff) {
> + /* This operation raises Invalid for both NaN and overflow (Inf). */
> + float_raise(float_flag_invalid, status);
> + frac = 0;
> + } else {
> + int true_exp = exp - 1023;
> + int shift = true_exp - 52;
> +
> + /* Restore implicit bit. */
> + frac |= 1ull << 52;
> +
> + /* Shift the fraction into place. */
> + if (shift >= 0) {
> + /* The number is so large we must shift the fraction left. */
> + if (shift >= 64) {
> + /* The the fraction is shifted out entirely. */
> + frac = 0;
> + } else {
> + frac <<= shift;
> + }
> + } else if (shift > -64) {
> + /* Normal case -- shift right and notice if bits shift out. */
> + inexact = (frac << (64 + shift)) != 0;
> + frac >>= -shift;
> + } else {
> + /* The fraction is shifted out entirely. */
> + frac = 0;
> + }
> +
> + /* Notice overflow or inexact exceptions. */
> + if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) {
> + /* Overflow, for which this operation raises invalid. */
> + float_raise(float_flag_invalid, status);
> + inexact = 1;
> + } else if (inexact) {
> + float_raise(float_flag_inexact, status);
> + }
> +
> + /* Honor the sign. */
> + if (sign) {
> + frac = -frac;
> + }
> + }
> +
> + /* Pack the result and the env->ZF representation of Z together. */
> + return deposit64(frac, 32, 32, inexact);
> +}
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 2f849a6951..b03e592edd 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -6526,6 +6526,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
> }
> }
>
> +static void handle_fjcvtzs(DisasContext *s, int rd, int rn)
> +{
> + TCGv_i64 t = read_fp_dreg(s, rn);
> + TCGv_ptr fpstatus = get_fpstatus_ptr(false);
> +
> + gen_helper_fjcvtzs(t, t, fpstatus);
> +
> + tcg_temp_free_ptr(fpstatus);
> +
> + tcg_gen_ext32u_i64(cpu_reg(s, rd), t);
> + tcg_gen_extrh_i64_i32(cpu_ZF, t);
> + tcg_gen_movi_i32(cpu_CF, 0);
> + tcg_gen_movi_i32(cpu_NF, 0);
> + tcg_gen_movi_i32(cpu_VF, 0);
> +
> + tcg_temp_free_i64(t);
> +}
> +
> /* Floating point <-> integer conversions
> * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
> * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
> @@ -6601,6 +6619,14 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
> handle_fmov(s, rd, rn, type, itof);
> break;
>
> + case 0b00111110: /* FJCVTZS */
> + if (!dc_isar_feature(aa64_jscvt, s)) {
> + goto do_unallocated;
> + } else if (fp_access_check(s)) {
> + handle_fjcvtzs(s, rd, rn);
> + }
> + break;
> +
> default:
> do_unallocated:
> unallocated_encoding(s);
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index eb25895876..a92d06b05b 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -4066,6 +4066,21 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
> case 17: /* fsito */
> gen_vfp_sito(dp, 0);
> break;
> + case 19: /* vjcvt */
> + if (!dp || !dc_isar_feature(aa32_jscvt, s)) {
> + return 1;
> + } else {
> + TCGv_ptr fpst = get_fpstatus_ptr(0);
> + gen_helper_fjcvtzs(cpu_F0d, cpu_F0d, fpst);
> + tcg_temp_free_ptr(fpst);
> +
> + tcg_gen_extr_i64_i32(cpu_F0s, cpu_ZF, cpu_F0d);
> + tcg_gen_movi_i32(cpu_NF, 0);
> + tcg_gen_movi_i32(cpu_CF, 0);
> + tcg_gen_movi_i32(cpu_VF, 0);
> + dp = 0; /* always a single precision result */
> + }
> + break;
> case 20: /* fshto */
> if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
> return 1;
> --
> 2.17.2
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.3-JSConv
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
2019-02-06 7:03 ` Laurent Desnogues
@ 2019-02-14 13:51 ` Peter Maydell
1 sibling, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2019-02-14 13:51 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Wed, 6 Feb 2019 at 05:29, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v2: Return 0 for NaN
> ---
> + /* The the fraction is shifted out entirely. */
"The the"...
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index eb25895876..a92d06b05b 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -4066,6 +4066,21 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
> case 17: /* fsito */
> gen_vfp_sito(dp, 0);
> break;
> + case 19: /* vjcvt */
> + if (!dp || !dc_isar_feature(aa32_jscvt, s)) {
> + return 1;
> + } else {
> + TCGv_ptr fpst = get_fpstatus_ptr(0);
> + gen_helper_fjcvtzs(cpu_F0d, cpu_F0d, fpst);
> + tcg_temp_free_ptr(fpst);
> +
> + tcg_gen_extr_i64_i32(cpu_F0s, cpu_ZF, cpu_F0d);
> + tcg_gen_movi_i32(cpu_NF, 0);
> + tcg_gen_movi_i32(cpu_CF, 0);
> + tcg_gen_movi_i32(cpu_VF, 0);
> + dp = 0; /* always a single precision result */
> + }
The AArch32 version of the instruction sets the NZCV bits in
the FPSCR, not the main PSTATE ones. (It passes Is64 == FALSE
to the pseudocode FPToFixedJS().)
> + break;
> case 20: /* fshto */
> if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
> return 1;
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/3] target/arm: Restructure disas_fp_int_conv
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 2/3] target/arm: Restructure disas_fp_int_conv Richard Henderson
@ 2019-02-14 13:52 ` Peter Maydell
0 siblings, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2019-02-14 13:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Wed, 6 Feb 2019 at 05:29, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> For opcodes 0-5, move some if conditions into the structure
> of a switch statement. For opcodes 6 & 7, decode everything
> at once with a second switch.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv
2019-02-06 5:28 [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
` (2 preceding siblings ...)
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
@ 2019-02-14 13:53 ` Peter Maydell
2019-02-14 21:10 ` Richard Henderson
3 siblings, 1 reply; 11+ messages in thread
From: Peter Maydell @ 2019-02-14 13:53 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Wed, 6 Feb 2019 at 05:29, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Changes since v1:
> * Typo fixed in patch 2, which had scrogged FMOV
> * Return 0 for NaN, as for any other ARM fp conversion.
>
>
> r~
>
>
> Richard Henderson (3):
> target/arm: Force result size into dp after operation
> target/arm: Restructure disas_fp_int_conv
> target/arm: Implement ARMv8.3-JSConv
I've applied patches 1 and 2 to target-arm.next; 3 has a bug in it,
I think.
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv
2019-02-14 13:53 ` [Qemu-devel] [PATCH v2 0/3] " Peter Maydell
@ 2019-02-14 21:10 ` Richard Henderson
2019-02-14 21:28 ` Richard Henderson
0 siblings, 1 reply; 11+ messages in thread
From: Richard Henderson @ 2019-02-14 21:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On 2/14/19 5:53 AM, Peter Maydell wrote:
> On Wed, 6 Feb 2019 at 05:29, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Changes since v1:
>> * Typo fixed in patch 2, which had scrogged FMOV
>> * Return 0 for NaN, as for any other ARM fp conversion.
>>
>>
>> r~
>>
>>
>> Richard Henderson (3):
>> target/arm: Force result size into dp after operation
>> target/arm: Restructure disas_fp_int_conv
>> target/arm: Implement ARMv8.3-JSConv
>
> I've applied patches 1 and 2 to target-arm.next; 3 has a bug in it,
> I think.
Please dequeue patch 2; patch 3 has more than one bug in it, and I need to
rewrite patch 2 as well.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv
2019-02-14 21:10 ` Richard Henderson
@ 2019-02-14 21:28 ` Richard Henderson
2019-02-15 9:57 ` Peter Maydell
0 siblings, 1 reply; 11+ messages in thread
From: Richard Henderson @ 2019-02-14 21:28 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On 2/14/19 1:10 PM, Richard Henderson wrote:
> On 2/14/19 5:53 AM, Peter Maydell wrote:
>> On Wed, 6 Feb 2019 at 05:29, Richard Henderson
>> <richard.henderson@linaro.org> wrote:
>>>
>>> Changes since v1:
>>> * Typo fixed in patch 2, which had scrogged FMOV
>>> * Return 0 for NaN, as for any other ARM fp conversion.
>>>
>>>
>>> r~
>>>
>>>
>>> Richard Henderson (3):
>>> target/arm: Force result size into dp after operation
>>> target/arm: Restructure disas_fp_int_conv
>>> target/arm: Implement ARMv8.3-JSConv
>>
>> I've applied patches 1 and 2 to target-arm.next; 3 has a bug in it,
>> I think.
>
> Please dequeue patch 2; patch 3 has more than one bug in it, and I need to
> rewrite patch 2 as well.
Grr. That's patch 1, "force result size into dp" that I want dequeued.
Of course, now I've seen your pull request, so if that's already gone through,
I guess I can smoosh a revert with my rewrite?
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv
2019-02-14 21:28 ` Richard Henderson
@ 2019-02-15 9:57 ` Peter Maydell
0 siblings, 0 replies; 11+ messages in thread
From: Peter Maydell @ 2019-02-15 9:57 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 14 Feb 2019 at 21:28, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 2/14/19 1:10 PM, Richard Henderson wrote:
> > On 2/14/19 5:53 AM, Peter Maydell wrote:
> >> On Wed, 6 Feb 2019 at 05:29, Richard Henderson
> >> <richard.henderson@linaro.org> wrote:
> >>>
> >>> Changes since v1:
> >>> * Typo fixed in patch 2, which had scrogged FMOV
> >>> * Return 0 for NaN, as for any other ARM fp conversion.
> >>>
> >>>
> >>> r~
> >>>
> >>>
> >>> Richard Henderson (3):
> >>> target/arm: Force result size into dp after operation
> >>> target/arm: Restructure disas_fp_int_conv
> >>> target/arm: Implement ARMv8.3-JSConv
> >>
> >> I've applied patches 1 and 2 to target-arm.next; 3 has a bug in it,
> >> I think.
> >
> > Please dequeue patch 2; patch 3 has more than one bug in it, and I need to
> > rewrite patch 2 as well.
>
> Grr. That's patch 1, "force result size into dp" that I want dequeued.
> Of course, now I've seen your pull request, so if that's already gone through,
> I guess I can smoosh a revert with my rewrite?
I saw this before pushing the merge, so I've removed both patches 1 and
2 from target-arm.next and will resend the pullreq.
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-02-15 9:57 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-06 5:28 [Qemu-devel] [PATCH v2 0/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 1/3] target/arm: Force result size into dp after operation Richard Henderson
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 2/3] target/arm: Restructure disas_fp_int_conv Richard Henderson
2019-02-14 13:52 ` Peter Maydell
2019-02-06 5:28 ` [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.3-JSConv Richard Henderson
2019-02-06 7:03 ` Laurent Desnogues
2019-02-14 13:51 ` Peter Maydell
2019-02-14 13:53 ` [Qemu-devel] [PATCH v2 0/3] " Peter Maydell
2019-02-14 21:10 ` Richard Henderson
2019-02-14 21:28 ` Richard Henderson
2019-02-15 9:57 ` Peter Maydell
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