Re: [PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller

From: Joel Stanley <joel@jms.id.au>
To: Rob Herring <robh@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	Mark Rutland <mark.rutland@arm.com>,
	devicetree <devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Andrew Jeffery <andrew@aj.id.au>
Subject: Re: [PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller
Date: Mon, 3 Jul 2017 16:21:29 +0930	[thread overview]
Message-ID: <CACPK8Xd86gAtR5sLb1LAy49Rc-dw4mAnZtk9_vwYvBe+Qefa1Q@mail.gmail.com> (raw)
In-Reply-To: <20170607204916.n3wh3fkwbfctdv6s@rob-hp-laptop>

On Thu, Jun 8, 2017 at 6:19 AM, Rob Herring <robh@kernel.org> wrote:
> On Tue, May 30, 2017 at 03:38:50PM +0930, Joel Stanley wrote:
>> This adds the bindings documentation for a basic single-register reset
>> controller.
>>
>> The bindings describe a single 32-bit register that contains up to 32
>> reset lines, each deasserted by clearing the appropriate bit in the
>> register. Optionally a property can be provided that changes this
>> behaviour to assert on clear.
>>
>
> I think this is a good idea for kernel code, but not for bindings. We
> don't really want per register bindings.
>
> The problem with any generic/simple/basic binding is they always start
> that way. Then we add one property at a time not in any well planned
> way. I can easily come up with additions. For example, what about
> self-clearing reset bits. Or 2 bits per reset. Or multiple resets that
> have to be controlled together. 8 or 16-bit registers.

Thanks for the explanation. I will send a v3 with aspeed specific bindings.

How should I handle the driver? Were you suggesting I keep it generic,
but with my aspeed compatible?

Cheers,

Joel

>
> IRQs and GPIOs could also be described in some cases with just groups of
> 32-bit registers for set,clear,status,mask,etc., but we don't do that in
> bindings for the same reasons.
>
> Rob