* [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
Hi,
This series adds a new SPI driver using the spi-mem interface for the
Aspeed static memory controllers of the AST2600, AST2500 and AST2400
SoCs.
* AST2600 Firmware SPI Memory Controller (FMC)
* AST2600 SPI Flash Controller (SPI1 and SPI2)
* AST2500 Firmware SPI Memory Controller (FMC)
* AST2500 SPI Flash Controller (SPI1 and SPI2)
* AST2400 New Static Memory Controller (also referred as FMC)
* AST2400 SPI Flash Controller (SPI)
It is based on the current OpenBMC kernel driver [1], using directly
the MTD SPI-NOR interface and on a patchset [2] previously proposed
adding support for the AST2600 only. This driver takes a slightly
different approach to cover all 6 controllers.
It does not make use of the controller register disabling Address and
Data byte lanes because is not available on the AST2400 SoC. We could
introduce a specific handler for new features available on recent SoCs
if needed. As there is not much difference on performance, the driver
chooses the common denominator: "User mode" which has been heavily
tested in [1]. "User mode" is also used as a fall back method when
flash device mapping window is too small.
Problems to address with spi-mem were the configuration of the mapping
windows and the calibration of the read timings. The driver handles
them in the direct mapping handler when some knowledge on the size of
the flash device is know. It is not perfect but not incorrect either.
The algorithm is one from [1] because it doesn't require the DMA
registers which are not available on all controllers.
Direct mapping for writes is not supported (yet). I have seen some
corruption with writes and I preferred to use the safer and proven
method of the initial driver [1]. We can improve that later.
The driver supports Quad SPI RX transfers on the AST2600 SoC but it
didn't have the expected results. Therefore it is not activated yet.
There are some issues on the pinctrl to investigate first.
The series does not remove the current Aspeed SMC driver but prepares
ground for its removal by changing its CONFIG option. This last step
can be addressed as a followup when the new driver using the spi-mem
interface has been sufficiently exposed.
Tested on:
* OpenPOWER Palmetto (AST2400)
* Facebook Wedge 100 BMC (AST2400) by Tao Ren <rentao.bupt@gmail.com>
* Evaluation board (AST2500)
* Inspur FP5280G2 BMC (AST2500) by John Wang <wangzq.jn@gmail.com>
* Facebook Backpack CMM BMC (AST2500) by Tao Ren <rentao.bupt@gmail.com>
* OpenPOWER Witherspoon (AST2500)
* Evaluation board (AST2600 A0 and A3)
* Rainier board (AST2600)
[1] https://github.com/openbmc/linux/blob/dev-5.15/drivers/mtd/spi-nor/controllers/aspeed-smc.c
[2] https://patchwork.ozlabs.org/project/linux-aspeed/list/?series=212394
Thanks,
C.
Changes in v2:
- Fixed dt_binding_check warnings (Rob)
- New entry in MAINTAINERS
- Addressed Lukas comments regarding the SPI controller registration
and device removal. Checked with driver bind/unbind
- Introduced setup and cleanup handlers and removed routine looping
on the DT children properties (Pratyush)
- Clarified in commit log requirements for training.
- Removed defconfig changes of patch 1 since they were reverted in
the last patch (Joel)
Cédric Le Goater (10):
mtd: spi-nor: aspeed: Rename Kconfig option
ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
dt-bindings: spi: Add Aspeed SMC controllers device tree binding
spi: spi-mem: Add driver for Aspeed SMC controllers
spi: aspeed: Add support for direct mapping
spi: aspeed: Adjust direct mapping to device size
spi: aspeed: Workaround AST2500 limitations
spi: aspeed: Add support for the AST2400 SPI controller
spi: aspeed: Calibrate read timings
ARM: dts: aspeed: Enable Dual SPI RX transfers
drivers/spi/spi-aspeed-smc.c | 1186 +++++++++++++++++
.../bindings/spi/aspeed,ast2600-fmc.yaml | 90 ++
MAINTAINERS | 10 +
arch/arm/boot/dts/aspeed-g4.dtsi | 12 +-
arch/arm/boot/dts/aspeed-g5.dtsi | 16 +-
arch/arm/boot/dts/aspeed-g6.dtsi | 17 +-
drivers/mtd/spi-nor/controllers/Kconfig | 4 +-
drivers/mtd/spi-nor/controllers/Makefile | 2 +-
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
10 files changed, 1330 insertions(+), 19 deletions(-)
create mode 100644 drivers/spi/spi-aspeed-smc.c
create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
--
2.34.1
^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
Hi,
This series adds a new SPI driver using the spi-mem interface for the
Aspeed static memory controllers of the AST2600, AST2500 and AST2400
SoCs.
* AST2600 Firmware SPI Memory Controller (FMC)
* AST2600 SPI Flash Controller (SPI1 and SPI2)
* AST2500 Firmware SPI Memory Controller (FMC)
* AST2500 SPI Flash Controller (SPI1 and SPI2)
* AST2400 New Static Memory Controller (also referred as FMC)
* AST2400 SPI Flash Controller (SPI)
It is based on the current OpenBMC kernel driver [1], using directly
the MTD SPI-NOR interface and on a patchset [2] previously proposed
adding support for the AST2600 only. This driver takes a slightly
different approach to cover all 6 controllers.
It does not make use of the controller register disabling Address and
Data byte lanes because is not available on the AST2400 SoC. We could
introduce a specific handler for new features available on recent SoCs
if needed. As there is not much difference on performance, the driver
chooses the common denominator: "User mode" which has been heavily
tested in [1]. "User mode" is also used as a fall back method when
flash device mapping window is too small.
Problems to address with spi-mem were the configuration of the mapping
windows and the calibration of the read timings. The driver handles
them in the direct mapping handler when some knowledge on the size of
the flash device is know. It is not perfect but not incorrect either.
The algorithm is one from [1] because it doesn't require the DMA
registers which are not available on all controllers.
Direct mapping for writes is not supported (yet). I have seen some
corruption with writes and I preferred to use the safer and proven
method of the initial driver [1]. We can improve that later.
The driver supports Quad SPI RX transfers on the AST2600 SoC but it
didn't have the expected results. Therefore it is not activated yet.
There are some issues on the pinctrl to investigate first.
The series does not remove the current Aspeed SMC driver but prepares
ground for its removal by changing its CONFIG option. This last step
can be addressed as a followup when the new driver using the spi-mem
interface has been sufficiently exposed.
Tested on:
* OpenPOWER Palmetto (AST2400)
* Facebook Wedge 100 BMC (AST2400) by Tao Ren <rentao.bupt@gmail.com>
* Evaluation board (AST2500)
* Inspur FP5280G2 BMC (AST2500) by John Wang <wangzq.jn@gmail.com>
* Facebook Backpack CMM BMC (AST2500) by Tao Ren <rentao.bupt@gmail.com>
* OpenPOWER Witherspoon (AST2500)
* Evaluation board (AST2600 A0 and A3)
* Rainier board (AST2600)
[1] https://github.com/openbmc/linux/blob/dev-5.15/drivers/mtd/spi-nor/controllers/aspeed-smc.c
[2] https://patchwork.ozlabs.org/project/linux-aspeed/list/?series=212394
Thanks,
C.
Changes in v2:
- Fixed dt_binding_check warnings (Rob)
- New entry in MAINTAINERS
- Addressed Lukas comments regarding the SPI controller registration
and device removal. Checked with driver bind/unbind
- Introduced setup and cleanup handlers and removed routine looping
on the DT children properties (Pratyush)
- Clarified in commit log requirements for training.
- Removed defconfig changes of patch 1 since they were reverted in
the last patch (Joel)
Cédric Le Goater (10):
mtd: spi-nor: aspeed: Rename Kconfig option
ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
dt-bindings: spi: Add Aspeed SMC controllers device tree binding
spi: spi-mem: Add driver for Aspeed SMC controllers
spi: aspeed: Add support for direct mapping
spi: aspeed: Adjust direct mapping to device size
spi: aspeed: Workaround AST2500 limitations
spi: aspeed: Add support for the AST2400 SPI controller
spi: aspeed: Calibrate read timings
ARM: dts: aspeed: Enable Dual SPI RX transfers
drivers/spi/spi-aspeed-smc.c | 1186 +++++++++++++++++
.../bindings/spi/aspeed,ast2600-fmc.yaml | 90 ++
MAINTAINERS | 10 +
arch/arm/boot/dts/aspeed-g4.dtsi | 12 +-
arch/arm/boot/dts/aspeed-g5.dtsi | 16 +-
arch/arm/boot/dts/aspeed-g6.dtsi | 17 +-
drivers/mtd/spi-nor/controllers/Kconfig | 4 +-
drivers/mtd/spi-nor/controllers/Makefile | 2 +-
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
10 files changed, 1330 insertions(+), 19 deletions(-)
create mode 100644 drivers/spi/spi-aspeed-smc.c
create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
Hi,
This series adds a new SPI driver using the spi-mem interface for the
Aspeed static memory controllers of the AST2600, AST2500 and AST2400
SoCs.
* AST2600 Firmware SPI Memory Controller (FMC)
* AST2600 SPI Flash Controller (SPI1 and SPI2)
* AST2500 Firmware SPI Memory Controller (FMC)
* AST2500 SPI Flash Controller (SPI1 and SPI2)
* AST2400 New Static Memory Controller (also referred as FMC)
* AST2400 SPI Flash Controller (SPI)
It is based on the current OpenBMC kernel driver [1], using directly
the MTD SPI-NOR interface and on a patchset [2] previously proposed
adding support for the AST2600 only. This driver takes a slightly
different approach to cover all 6 controllers.
It does not make use of the controller register disabling Address and
Data byte lanes because is not available on the AST2400 SoC. We could
introduce a specific handler for new features available on recent SoCs
if needed. As there is not much difference on performance, the driver
chooses the common denominator: "User mode" which has been heavily
tested in [1]. "User mode" is also used as a fall back method when
flash device mapping window is too small.
Problems to address with spi-mem were the configuration of the mapping
windows and the calibration of the read timings. The driver handles
them in the direct mapping handler when some knowledge on the size of
the flash device is know. It is not perfect but not incorrect either.
The algorithm is one from [1] because it doesn't require the DMA
registers which are not available on all controllers.
Direct mapping for writes is not supported (yet). I have seen some
corruption with writes and I preferred to use the safer and proven
method of the initial driver [1]. We can improve that later.
The driver supports Quad SPI RX transfers on the AST2600 SoC but it
didn't have the expected results. Therefore it is not activated yet.
There are some issues on the pinctrl to investigate first.
The series does not remove the current Aspeed SMC driver but prepares
ground for its removal by changing its CONFIG option. This last step
can be addressed as a followup when the new driver using the spi-mem
interface has been sufficiently exposed.
Tested on:
* OpenPOWER Palmetto (AST2400)
* Facebook Wedge 100 BMC (AST2400) by Tao Ren <rentao.bupt@gmail.com>
* Evaluation board (AST2500)
* Inspur FP5280G2 BMC (AST2500) by John Wang <wangzq.jn@gmail.com>
* Facebook Backpack CMM BMC (AST2500) by Tao Ren <rentao.bupt@gmail.com>
* OpenPOWER Witherspoon (AST2500)
* Evaluation board (AST2600 A0 and A3)
* Rainier board (AST2600)
[1] https://github.com/openbmc/linux/blob/dev-5.15/drivers/mtd/spi-nor/controllers/aspeed-smc.c
[2] https://patchwork.ozlabs.org/project/linux-aspeed/list/?series=212394
Thanks,
C.
Changes in v2:
- Fixed dt_binding_check warnings (Rob)
- New entry in MAINTAINERS
- Addressed Lukas comments regarding the SPI controller registration
and device removal. Checked with driver bind/unbind
- Introduced setup and cleanup handlers and removed routine looping
on the DT children properties (Pratyush)
- Clarified in commit log requirements for training.
- Removed defconfig changes of patch 1 since they were reverted in
the last patch (Joel)
Cédric Le Goater (10):
mtd: spi-nor: aspeed: Rename Kconfig option
ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
dt-bindings: spi: Add Aspeed SMC controllers device tree binding
spi: spi-mem: Add driver for Aspeed SMC controllers
spi: aspeed: Add support for direct mapping
spi: aspeed: Adjust direct mapping to device size
spi: aspeed: Workaround AST2500 limitations
spi: aspeed: Add support for the AST2400 SPI controller
spi: aspeed: Calibrate read timings
ARM: dts: aspeed: Enable Dual SPI RX transfers
drivers/spi/spi-aspeed-smc.c | 1186 +++++++++++++++++
.../bindings/spi/aspeed,ast2600-fmc.yaml | 90 ++
MAINTAINERS | 10 +
arch/arm/boot/dts/aspeed-g4.dtsi | 12 +-
arch/arm/boot/dts/aspeed-g5.dtsi | 16 +-
arch/arm/boot/dts/aspeed-g6.dtsi | 17 +-
drivers/mtd/spi-nor/controllers/Kconfig | 4 +-
drivers/mtd/spi-nor/controllers/Makefile | 2 +-
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
10 files changed, 1330 insertions(+), 19 deletions(-)
create mode 100644 drivers/spi/spi-aspeed-smc.c
create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v2 01/10] mtd: spi-nor: aspeed: Rename Kconfig option
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
To prepare transition to the new Aspeed SMC SPI controller driver using
the spi-mem interface, change the kernel CONFIG option of the current
driver to reflect that the implementation uses the MTD SPI-NOR interface.
Once the new driver is sufficiently exposed, we should remove the old one.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/mtd/spi-nor/controllers/Kconfig | 2 +-
drivers/mtd/spi-nor/controllers/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
index 5c0e0ec2e6d1..876a47042fec 100644
--- a/drivers/mtd/spi-nor/controllers/Kconfig
+++ b/drivers/mtd/spi-nor/controllers/Kconfig
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
-config SPI_ASPEED_SMC
+config SPI_ASPEED_SMC_MTD_SPI_NOR
tristate "Aspeed flash controllers in SPI mode"
depends on ARCH_ASPEED || COMPILE_TEST
depends on HAS_IOMEM && OF
diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile
index e7abba491d98..1e28297fb1e8 100644
--- a/drivers/mtd/spi-nor/controllers/Makefile
+++ b/drivers/mtd/spi-nor/controllers/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
+obj-$(CONFIG_SPI_ASPEED_SMC_MTD_SPI_NOR) += aspeed-smc.o
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 01/10] mtd: spi-nor: aspeed: Rename Kconfig option
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
To prepare transition to the new Aspeed SMC SPI controller driver using
the spi-mem interface, change the kernel CONFIG option of the current
driver to reflect that the implementation uses the MTD SPI-NOR interface.
Once the new driver is sufficiently exposed, we should remove the old one.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/mtd/spi-nor/controllers/Kconfig | 2 +-
drivers/mtd/spi-nor/controllers/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
index 5c0e0ec2e6d1..876a47042fec 100644
--- a/drivers/mtd/spi-nor/controllers/Kconfig
+++ b/drivers/mtd/spi-nor/controllers/Kconfig
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
-config SPI_ASPEED_SMC
+config SPI_ASPEED_SMC_MTD_SPI_NOR
tristate "Aspeed flash controllers in SPI mode"
depends on ARCH_ASPEED || COMPILE_TEST
depends on HAS_IOMEM && OF
diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile
index e7abba491d98..1e28297fb1e8 100644
--- a/drivers/mtd/spi-nor/controllers/Makefile
+++ b/drivers/mtd/spi-nor/controllers/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
+obj-$(CONFIG_SPI_ASPEED_SMC_MTD_SPI_NOR) += aspeed-smc.o
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 01/10] mtd: spi-nor: aspeed: Rename Kconfig option
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
To prepare transition to the new Aspeed SMC SPI controller driver using
the spi-mem interface, change the kernel CONFIG option of the current
driver to reflect that the implementation uses the MTD SPI-NOR interface.
Once the new driver is sufficiently exposed, we should remove the old one.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/mtd/spi-nor/controllers/Kconfig | 2 +-
drivers/mtd/spi-nor/controllers/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
index 5c0e0ec2e6d1..876a47042fec 100644
--- a/drivers/mtd/spi-nor/controllers/Kconfig
+++ b/drivers/mtd/spi-nor/controllers/Kconfig
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
-config SPI_ASPEED_SMC
+config SPI_ASPEED_SMC_MTD_SPI_NOR
tristate "Aspeed flash controllers in SPI mode"
depends on ARCH_ASPEED || COMPILE_TEST
depends on HAS_IOMEM && OF
diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile
index e7abba491d98..1e28297fb1e8 100644
--- a/drivers/mtd/spi-nor/controllers/Makefile
+++ b/drivers/mtd/spi-nor/controllers/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
+obj-$(CONFIG_SPI_ASPEED_SMC_MTD_SPI_NOR) += aspeed-smc.o
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 02/10] ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
This is compatible with the current driver and addresses issues when
running 'make dt_binding_check'.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++----
arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++------
arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++------
3 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index f14dace34c5a..9ae67e83cf60 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -54,8 +54,7 @@ ahb {
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0x94
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
@@ -91,8 +90,7 @@ flash@4 {
};
spi: spi@1e630000 {
- reg = < 0x1e630000 0x18
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 7495f93c5069..c3e0a8e13c8a 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -55,8 +55,7 @@ ahb {
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
@@ -84,8 +83,7 @@ flash@2 {
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x08000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
@@ -106,8 +104,7 @@ flash@1 {
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x38000000 0x08000000 >;
+ reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index c32e87fad4dc..1ad05dde19d2 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -95,8 +95,7 @@ gic: interrupt-controller@40461000 {
};
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-fmc";
@@ -124,8 +123,7 @@ flash@2 {
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
@@ -146,8 +144,7 @@ flash@1 {
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x50000000 0x10000000 >;
+ reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 02/10] ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
This is compatible with the current driver and addresses issues when
running 'make dt_binding_check'.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++----
arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++------
arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++------
3 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index f14dace34c5a..9ae67e83cf60 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -54,8 +54,7 @@ ahb {
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0x94
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
@@ -91,8 +90,7 @@ flash@4 {
};
spi: spi@1e630000 {
- reg = < 0x1e630000 0x18
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 7495f93c5069..c3e0a8e13c8a 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -55,8 +55,7 @@ ahb {
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
@@ -84,8 +83,7 @@ flash@2 {
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x08000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
@@ -106,8 +104,7 @@ flash@1 {
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x38000000 0x08000000 >;
+ reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index c32e87fad4dc..1ad05dde19d2 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -95,8 +95,7 @@ gic: interrupt-controller@40461000 {
};
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-fmc";
@@ -124,8 +123,7 @@ flash@2 {
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
@@ -146,8 +144,7 @@ flash@1 {
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x50000000 0x10000000 >;
+ reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 02/10] ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
This is compatible with the current driver and addresses issues when
running 'make dt_binding_check'.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++----
arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++------
arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++------
3 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index f14dace34c5a..9ae67e83cf60 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -54,8 +54,7 @@ ahb {
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0x94
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
@@ -91,8 +90,7 @@ flash@4 {
};
spi: spi@1e630000 {
- reg = < 0x1e630000 0x18
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 7495f93c5069..c3e0a8e13c8a 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -55,8 +55,7 @@ ahb {
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
@@ -84,8 +83,7 @@ flash@2 {
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x08000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
@@ -106,8 +104,7 @@ flash@1 {
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x38000000 0x08000000 >;
+ reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index c32e87fad4dc..1ad05dde19d2 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -95,8 +95,7 @@ gic: interrupt-controller@40461000 {
};
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-fmc";
@@ -124,8 +123,7 @@ flash@2 {
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
@@ -146,8 +144,7 @@ flash@1 {
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x50000000 0x10000000 >;
+ reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
The "interrupt" property is optional because it is only necessary for
controllers supporting DMAs (Not implemented yet in the new driver).
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
.../bindings/spi/aspeed,ast2600-fmc.yaml | 90 +++++++++++++++++++
MAINTAINERS | 9 ++
2 files changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
new file mode 100644
index 000000000000..0289a4f52196
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SMC controllers bindings
+
+maintainers:
+ - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
+ - Cédric Le Goater <clg@kaod.org>
+
+description: |
+ This binding describes the Aspeed Static Memory Controllers (FMC and
+ SPI) of the AST2400, AST2500 and AST2600 SOCs.
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-fmc
+ - aspeed,ast2600-spi
+ - aspeed,ast2500-fmc
+ - aspeed,ast2500-spi
+ - aspeed,ast2400-fmc
+ - aspeed,ast2400-spi
+
+ reg:
+ items:
+ - description: registers
+ - description: memory mapping
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+patternProperties:
+ "@[0-9a-f]+":
+ type: object
+
+ properties:
+ spi-rx-bus-width:
+ enum: [1, 2, 4]
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
+ #include <dt-bindings/clock/ast2600-clock.h>
+
+ spi@1e620000 {
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2600-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
+ };
+ flash@2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 4175103e928d..f5ab77548ef6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2925,6 +2925,15 @@ S: Maintained
F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
F: drivers/mmc/host/sdhci-of-aspeed*
+ASPEED SMC SPI DRIVER
+M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
+M: Cédric Le Goater <clg@kaod.org>
+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
+L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
+L: linux-spi@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
+
ASPEED VIDEO ENGINE DRIVER
M: Eddie James <eajames@linux.ibm.com>
L: linux-media@vger.kernel.org
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
The "interrupt" property is optional because it is only necessary for
controllers supporting DMAs (Not implemented yet in the new driver).
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
.../bindings/spi/aspeed,ast2600-fmc.yaml | 90 +++++++++++++++++++
MAINTAINERS | 9 ++
2 files changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
new file mode 100644
index 000000000000..0289a4f52196
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SMC controllers bindings
+
+maintainers:
+ - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
+ - Cédric Le Goater <clg@kaod.org>
+
+description: |
+ This binding describes the Aspeed Static Memory Controllers (FMC and
+ SPI) of the AST2400, AST2500 and AST2600 SOCs.
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-fmc
+ - aspeed,ast2600-spi
+ - aspeed,ast2500-fmc
+ - aspeed,ast2500-spi
+ - aspeed,ast2400-fmc
+ - aspeed,ast2400-spi
+
+ reg:
+ items:
+ - description: registers
+ - description: memory mapping
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+patternProperties:
+ "@[0-9a-f]+":
+ type: object
+
+ properties:
+ spi-rx-bus-width:
+ enum: [1, 2, 4]
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
+ #include <dt-bindings/clock/ast2600-clock.h>
+
+ spi@1e620000 {
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2600-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
+ };
+ flash@2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 4175103e928d..f5ab77548ef6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2925,6 +2925,15 @@ S: Maintained
F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
F: drivers/mmc/host/sdhci-of-aspeed*
+ASPEED SMC SPI DRIVER
+M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
+M: Cédric Le Goater <clg@kaod.org>
+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
+L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
+L: linux-spi@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
+
ASPEED VIDEO ENGINE DRIVER
M: Eddie James <eajames@linux.ibm.com>
L: linux-media@vger.kernel.org
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
The "interrupt" property is optional because it is only necessary for
controllers supporting DMAs (Not implemented yet in the new driver).
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
.../bindings/spi/aspeed,ast2600-fmc.yaml | 90 +++++++++++++++++++
MAINTAINERS | 9 ++
2 files changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
new file mode 100644
index 000000000000..0289a4f52196
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SMC controllers bindings
+
+maintainers:
+ - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
+ - Cédric Le Goater <clg@kaod.org>
+
+description: |
+ This binding describes the Aspeed Static Memory Controllers (FMC and
+ SPI) of the AST2400, AST2500 and AST2600 SOCs.
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-fmc
+ - aspeed,ast2600-spi
+ - aspeed,ast2500-fmc
+ - aspeed,ast2500-spi
+ - aspeed,ast2400-fmc
+ - aspeed,ast2400-spi
+
+ reg:
+ items:
+ - description: registers
+ - description: memory mapping
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+patternProperties:
+ "@[0-9a-f]+":
+ type: object
+
+ properties:
+ spi-rx-bus-width:
+ enum: [1, 2, 4]
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
+ #include <dt-bindings/clock/ast2600-clock.h>
+
+ spi@1e620000 {
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2600-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
+ };
+ flash@2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 4175103e928d..f5ab77548ef6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2925,6 +2925,15 @@ S: Maintained
F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
F: drivers/mmc/host/sdhci-of-aspeed*
+ASPEED SMC SPI DRIVER
+M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
+M: Cédric Le Goater <clg@kaod.org>
+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
+L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
+L: linux-spi@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
+
ASPEED VIDEO ENGINE DRIVER
M: Eddie James <eajames@linux.ibm.com>
L: linux-media@vger.kernel.org
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 04/10] spi: spi-mem: Add driver for Aspeed SMC controllers
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
This SPI driver adds support for the Aspeed static memory controllers
of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
* AST2600 Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. Only supports SPI type flash memory
. different segment register interface
. single, dual and quad mode.
* AST2600 SPI Flash Controller (SPI1 and SPI2)
. host firmware
. 2 chip select pins (CE0 ~ CE1)
. different segment register interface
. single, dual and quad mode.
* AST2500 Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. supports SPI type flash memory (CE0-CE1)
. CE2 can be of NOR type flash but this is not supported by the driver
. single, dual mode.
* AST2500 SPI Flash Controller (SPI1 and SPI2)
. host firmware
. 2 chip select pins (CE0 ~ CE1)
. single, dual mode.
* AST2400 New Static Memory Controller (also referred as FMC)
. BMC firmware
. New register set
. 5 chip select pins (CE0 ∼ CE4)
. supports NOR flash, NAND flash and SPI flash memory.
. single, dual and quad mode.
Each controller has a memory range on which flash devices contents are
mapped. Each device is assigned a window that can be changed at bootime
with the Segment Address Registers.
Each SPI flash device can then be accessed in two modes: Command and
User. When in User mode, SPI transfers are initiated with accesses to
the memory segment of a device. When in Command mode, memory
operations on the memory segment of a device generate SPI commands
automatically using a Control Register for the settings.
This initial patch adds support for User mode. Command mode needs a little
more work to check that the memory window on the AHB bus fits the device
size. It will come later when support for direct mapping is added.
Single and dual mode RX transfers are supported. Other types than SPI
are not supported.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 711 ++++++++++++++++++++++++
MAINTAINERS | 1 +
drivers/mtd/spi-nor/controllers/Kconfig | 2 +-
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
5 files changed, 725 insertions(+), 1 deletion(-)
create mode 100644 drivers/spi/spi-aspeed-smc.c
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
new file mode 100644
index 000000000000..688f9472e0d7
--- /dev/null
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -0,0 +1,711 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * ASPEED FMC/SPI Memory Controller Driver
+ *
+ * Copyright (c) 2015-2022, IBM Corporation.
+ * Copyright (c) 2020, ASPEED Corporation.
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+#define DEVICE_NAME "spi-aspeed-smc"
+
+#define ASPEED_SPI_DEFAULT_FREQ 50000000
+
+/* Type setting Register */
+#define CONFIG_REG 0x0
+#define CONFIG_TYPE_SPI 0x2
+
+/* CE Control Register */
+#define CE_CTRL_REG 0x4
+
+/* CEx Control Register */
+#define CE0_CTRL_REG 0x10
+#define CTRL_IO_MODE_MASK GENMASK(30, 28)
+#define CTRL_IO_SINGLE_DATA 0x0
+#define CTRL_IO_DUAL_DATA BIT(29)
+#define CTRL_IO_QUAD_DATA BIT(30)
+#define CTRL_COMMAND_SHIFT 16
+#define CTRL_IO_DUMMY_SET(dummy) \
+ (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
+#define CTRL_CE_STOP_ACTIVE BIT(2)
+#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
+#define CTRL_IO_MODE_NORMAL 0x0
+#define CTRL_IO_MODE_READ 0x1
+#define CTRL_IO_MODE_WRITE 0x2
+#define CTRL_IO_MODE_USER 0x3
+
+#define CTRL_IO_CMD_MASK 0xf0ff40c3
+
+/* CEx Address Decoding Range Register */
+#define CE0_SEGMENT_ADDR_REG 0x30
+
+enum aspeed_spi_ctl_reg_value {
+ ASPEED_SPI_BASE,
+ ASPEED_SPI_READ,
+ ASPEED_SPI_WRITE,
+ ASPEED_SPI_MAX,
+};
+
+struct aspeed_spi;
+
+struct aspeed_spi_chip {
+ struct aspeed_spi *aspi;
+ u32 cs;
+ void __iomem *ctl;
+ void __iomem *ahb_base;
+ u32 ahb_window_size;
+ u32 ctl_val[ASPEED_SPI_MAX];
+ u32 clk_freq;
+};
+
+struct aspeed_spi_data {
+ u32 ctl0;
+ u32 max_cs;
+ bool hastype;
+ u32 mode_bits;
+ u32 we0;
+
+ u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
+ u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
+ u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
+};
+
+#define ASPEED_SPI_MAX_NUM_CS 5
+
+struct aspeed_spi {
+ const struct aspeed_spi_data *data;
+
+ void __iomem *regs;
+ void __iomem *ahb_base;
+ u32 ahb_base_phy;
+ u32 ahb_window_size;
+ struct device *dev;
+
+ struct clk *clk;
+ u32 clk_freq;
+
+ struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS];
+};
+
+static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
+{
+ switch (op->data.buswidth) {
+ case 1:
+ return CTRL_IO_SINGLE_DATA;
+ case 2:
+ return CTRL_IO_DUAL_DATA;
+ case 4:
+ return CTRL_IO_QUAD_DATA;
+ default:
+ return CTRL_IO_SINGLE_DATA;
+ }
+}
+
+static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
+{
+ u32 ctl;
+
+ if (io_mode > 0) {
+ ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
+ ctl |= io_mode;
+ writel(ctl, chip->ctl);
+ }
+}
+
+static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
+{
+ u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
+
+ ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
+ writel(ctl, chip->ctl);
+
+ ctl &= ~CTRL_CE_STOP_ACTIVE;
+ writel(ctl, chip->ctl);
+}
+
+static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
+{
+ u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
+ CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
+
+ writel(ctl, chip->ctl);
+
+ /* Restore defaults */
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+}
+
+static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
+{
+ size_t offset = 0;
+
+ if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
+ IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
+ ioread32_rep(src, buf, len >> 2);
+ offset = len & ~0x3;
+ len -= offset;
+ }
+ ioread8_rep(src, (u8 *)buf + offset, len);
+ return 0;
+}
+
+static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
+{
+ size_t offset = 0;
+
+ if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
+ IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
+ iowrite32_rep(dst, buf, len >> 2);
+ offset = len & ~0x3;
+ len -= offset;
+ }
+ iowrite8_rep(dst, (const u8 *)buf + offset, len);
+ return 0;
+}
+
+static void aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
+ u64 offset, u32 opcode)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ __be32 temp;
+ u32 cmdaddr;
+
+ switch (addr_nbytes) {
+ default:
+ dev_warn_once(aspi->dev, "Unexpected address width %u, defaulting to 3",
+ addr_nbytes);
+ fallthrough;
+ case 3:
+ cmdaddr = offset & 0xFFFFFF;
+ cmdaddr |= opcode << 24;
+
+ temp = cpu_to_be32(cmdaddr);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
+ break;
+ case 4:
+ temp = cpu_to_be32(offset);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
+ break;
+ }
+}
+
+static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op)
+{
+ aspeed_spi_start_user(chip);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
+ aspeed_spi_read_from_ahb(op->data.buf.in,
+ chip->ahb_base, op->data.nbytes);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op)
+{
+ aspeed_spi_start_user(chip);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
+ aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
+ op->data.nbytes);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op,
+ u64 offset, size_t len, void *buf)
+{
+ int io_mode = aspeed_spi_get_io_mode(op);
+ u8 dummy = 0xFF;
+ int i;
+
+ aspeed_spi_start_user(chip);
+ aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
+ if (op->dummy.buswidth && op->dummy.nbytes) {
+ for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
+ aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
+ }
+
+ aspeed_spi_set_io_mode(chip, io_mode);
+
+ aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op)
+{
+ aspeed_spi_start_user(chip);
+ aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
+ aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+/* support for 1-1-1, 1-1-2 or 1-1-4 */
+static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ if (op->cmd.buswidth > 1)
+ return false;
+
+ if (op->addr.nbytes != 0) {
+ if (op->addr.buswidth > 1 || op->addr.nbytes > 4)
+ return false;
+ }
+
+ if (op->dummy.nbytes != 0) {
+ if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
+ return false;
+ }
+
+ if (op->data.nbytes != 0 && op->data.buswidth > 4)
+ return false;
+
+ return spi_mem_default_supports_op(mem, op);
+}
+
+static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
+ struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
+ u32 addr_mode, addr_mode_backup;
+ u32 ctl_val;
+ int ret = 0;
+
+ dev_dbg(aspi->dev,
+ "CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
+ chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
+ op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
+ op->dummy.buswidth, op->data.buswidth,
+ op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
+
+ addr_mode = readl(aspi->regs + CE_CTRL_REG);
+ addr_mode_backup = addr_mode;
+
+ ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
+ ctl_val &= ~CTRL_IO_CMD_MASK;
+
+ ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
+
+ /* 4BYTE address mode */
+ if (op->addr.nbytes) {
+ if (op->addr.nbytes == 4)
+ addr_mode |= (0x11 << chip->cs);
+ else
+ addr_mode &= ~(0x11 << chip->cs);
+ }
+
+ if (op->dummy.buswidth && op->dummy.nbytes)
+ ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
+
+ if (op->data.nbytes != 0) {
+ if (op->data.buswidth)
+ ctl_val |= aspeed_spi_get_io_mode(op);
+ }
+
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ ctl_val |= CTRL_IO_MODE_WRITE;
+ else
+ ctl_val |= CTRL_IO_MODE_READ;
+
+ if (addr_mode != addr_mode_backup)
+ writel(addr_mode, aspi->regs + CE_CTRL_REG);
+ writel(ctl_val, chip->ctl);
+
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ if (!op->addr.nbytes)
+ ret = aspeed_spi_read_reg(chip, op);
+ else
+ ret = aspeed_spi_read_user(chip, op, op->addr.val,
+ op->data.nbytes, op->data.buf.in);
+ } else {
+ if (!op->addr.nbytes)
+ ret = aspeed_spi_write_reg(chip, op);
+ else
+ ret = aspeed_spi_write_user(chip, op);
+ }
+
+ /* Restore defaults */
+ if (addr_mode != addr_mode_backup)
+ writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+ return ret;
+}
+
+static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ int ret;
+
+ ret = do_aspeed_spi_exec_op(mem, op);
+ if (ret)
+ dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
+ return ret;
+}
+
+static const char *aspeed_spi_get_name(struct spi_mem *mem)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
+ struct device *dev = aspi->dev;
+
+ return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
+}
+
+struct aspeed_spi_window {
+ u32 cs;
+ u32 offset;
+ u32 size;
+};
+
+static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
+ struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS])
+{
+ const struct aspeed_spi_data *data = aspi->data;
+ u32 reg_val;
+ u32 cs;
+
+ for (cs = 0; cs < aspi->data->max_cs; cs++) {
+ reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
+ windows[cs].cs = cs;
+ windows[cs].size = data->segment_end(aspi, reg_val) -
+ data->segment_start(aspi, reg_val);
+ windows[cs].offset = cs ? windows[cs - 1].offset + windows[cs - 1].size : 0;
+ dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
+ windows[cs].offset, windows[cs].size);
+ }
+}
+
+/*
+ * On the AST2600, some CE windows are closed by default at reset but
+ * U-Boot should open all.
+ */
+static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
+ struct aspeed_spi_window *win = &windows[chip->cs];
+
+ aspeed_spi_get_windows(aspi, windows);
+
+ chip->ahb_base = aspi->ahb_base + win->offset;
+ chip->ahb_window_size = win->size;
+
+ dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
+ chip->cs, aspi->ahb_base_phy + win->offset,
+ aspi->ahb_base_phy + win->offset + win->size - 1,
+ win->size >> 20);
+
+ return chip->ahb_window_size ? 0 : -1;
+}
+
+static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
+ .supports_op = aspeed_spi_supports_op,
+ .exec_op = aspeed_spi_exec_op,
+ .get_name = aspeed_spi_get_name,
+};
+
+static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
+{
+ u32 reg;
+
+ reg = readl(aspi->regs + CONFIG_REG);
+ reg &= ~(0x3 << (cs * 2));
+ reg |= type << (cs * 2);
+ writel(reg, aspi->regs + CONFIG_REG);
+}
+
+static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
+{
+ u32 we_bit = BIT(aspi->data->we0 + cs);
+ u32 reg = readl(aspi->regs + CONFIG_REG);
+
+ if (enable)
+ reg |= we_bit;
+ else
+ reg &= ~we_bit;
+ writel(reg, aspi->regs + CONFIG_REG);
+}
+
+static int aspeed_spi_setup(struct spi_device *spi)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
+ const struct aspeed_spi_data *data = aspi->data;
+ unsigned int cs = spi->chip_select;
+ struct aspeed_spi_chip *chip = &aspi->chips[cs];
+
+ chip->aspi = aspi;
+ chip->cs = cs;
+ chip->ctl = aspi->regs + data->ctl0 + cs * 4;
+
+ /* The driver only supports SPI type flash */
+ if (data->hastype)
+ aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
+
+ if (aspeed_spi_chip_set_default_window(chip) < 0) {
+ dev_warn(aspi->dev, "CE%d window invalid", cs);
+ return -EINVAL;
+ }
+
+ aspeed_spi_chip_enable(aspi, cs, true);
+
+ chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
+
+ dev_dbg(aspi->dev, "CE%d setup done\n", cs);
+ return 0;
+}
+
+static void aspeed_spi_cleanup(struct spi_device *spi)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
+ unsigned int cs = spi->chip_select;
+
+ aspeed_spi_chip_enable(aspi, cs, false);
+
+ dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
+}
+
+static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
+{
+ int cs;
+
+ for (cs = 0; cs < aspi->data->max_cs; cs++)
+ aspeed_spi_chip_enable(aspi, cs, enable);
+}
+
+static int aspeed_spi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct aspeed_spi_data *data;
+ struct spi_controller *ctlr;
+ struct aspeed_spi *aspi;
+ struct resource *res;
+ int ret;
+
+ data = of_device_get_match_data(&pdev->dev);
+ if (!data)
+ return -ENODEV;
+
+ ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
+ if (!ctlr)
+ return -ENOMEM;
+
+ aspi = spi_controller_get_devdata(ctlr);
+ platform_set_drvdata(pdev, aspi);
+ aspi->data = data;
+ aspi->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ aspi->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(aspi->regs)) {
+ dev_err(dev, "missing AHB register window\n");
+ return PTR_ERR(aspi->regs);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ aspi->ahb_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(aspi->ahb_base)) {
+ dev_err(dev, "missing AHB mapping window\n");
+ return PTR_ERR(aspi->ahb_base);
+ }
+
+ aspi->ahb_window_size = resource_size(res);
+ aspi->ahb_base_phy = res->start;
+
+ aspi->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(aspi->clk)) {
+ dev_err(dev, "missing clock\n");
+ return PTR_ERR(aspi->clk);
+ }
+
+ aspi->clk_freq = clk_get_rate(aspi->clk);
+ if (!aspi->clk_freq) {
+ dev_err(dev, "invalid clock\n");
+ return -EINVAL;
+ }
+
+ ret = clk_prepare_enable(aspi->clk);
+ if (ret) {
+ dev_err(dev, "can not enable the clock\n");
+ return ret;
+ }
+
+ /* IRQ is for DMA, which the driver doesn't support yet */
+
+ ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
+ ctlr->bus_num = pdev->id;
+ ctlr->mem_ops = &aspeed_spi_mem_ops;
+ ctlr->setup = aspeed_spi_setup;
+ ctlr->cleanup = aspeed_spi_cleanup;
+ ctlr->num_chipselect = data->max_cs;
+ ctlr->dev.of_node = dev->of_node;
+
+ ret = devm_spi_register_controller(dev, ctlr);
+ if (ret) {
+ dev_err(&pdev->dev, "spi_register_controller failed\n");
+ goto disable_clk;
+ }
+ return 0;
+
+disable_clk:
+ clk_disable_unprepare(aspi->clk);
+ return ret;
+}
+
+static int aspeed_spi_remove(struct platform_device *pdev)
+{
+ struct aspeed_spi *aspi = platform_get_drvdata(pdev);
+
+ aspeed_spi_enable(aspi, false);
+ clk_disable_unprepare(aspi->clk);
+ return 0;
+}
+
+/*
+ * AHB mappings
+ */
+
+/*
+ * The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
+ * The address range is encoded with absolute addresses in the overall
+ * mapping window.
+ */
+static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
+{
+ return ((reg >> 16) & 0xFF) << 23;
+}
+
+static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
+{
+ return ((reg >> 24) & 0xFF) << 23;
+}
+
+static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
+{
+ return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
+}
+
+/*
+ * The Segment Registers of the AST2600 use a 1MB unit. The address
+ * range is encoded with offsets in the overall mapping window.
+ */
+
+#define AST2600_SEG_ADDR_MASK 0x0ff00000
+
+static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
+ u32 reg)
+{
+ u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
+
+ return aspi->ahb_base_phy + start_offset;
+}
+
+static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
+ u32 reg)
+{
+ u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
+
+ /* segment is disabled */
+ if (!end_offset)
+ return aspi->ahb_base_phy;
+
+ return aspi->ahb_base_phy + end_offset + 0x100000;
+}
+
+static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
+ u32 start, u32 end)
+{
+ /* disable zero size segments */
+ if (start == end)
+ return 0;
+
+ return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
+ ((end - 1) & AST2600_SEG_ADDR_MASK);
+}
+
+/*
+ * Platform definitions
+ */
+static const struct aspeed_spi_data ast2400_fmc_data = {
+ .max_cs = 5,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_start,
+ .segment_end = aspeed_spi_segment_end,
+ .segment_reg = aspeed_spi_segment_reg,
+};
+
+static const struct aspeed_spi_data ast2500_fmc_data = {
+ .max_cs = 3,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_start,
+ .segment_end = aspeed_spi_segment_end,
+ .segment_reg = aspeed_spi_segment_reg,
+};
+
+static const struct aspeed_spi_data ast2500_spi_data = {
+ .max_cs = 2,
+ .hastype = false,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_start,
+ .segment_end = aspeed_spi_segment_end,
+ .segment_reg = aspeed_spi_segment_reg,
+};
+
+static const struct aspeed_spi_data ast2600_fmc_data = {
+ .max_cs = 3,
+ .hastype = false,
+ .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_ast2600_start,
+ .segment_end = aspeed_spi_segment_ast2600_end,
+ .segment_reg = aspeed_spi_segment_ast2600_reg,
+};
+
+static const struct aspeed_spi_data ast2600_spi_data = {
+ .max_cs = 2,
+ .hastype = false,
+ .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_ast2600_start,
+ .segment_end = aspeed_spi_segment_ast2600_end,
+ .segment_reg = aspeed_spi_segment_ast2600_reg,
+};
+
+static const struct of_device_id aspeed_spi_matches[] = {
+ { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
+ { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
+ { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
+ { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
+ { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
+ { }
+};
+MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
+
+static struct platform_driver aspeed_spi_driver = {
+ .probe = aspeed_spi_probe,
+ .remove = aspeed_spi_remove,
+ .driver = {
+ .name = DEVICE_NAME,
+ .of_match_table = aspeed_spi_matches,
+ }
+};
+
+module_platform_driver(aspeed_spi_driver);
+
+MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
+MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>");
+MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/MAINTAINERS b/MAINTAINERS
index f5ab77548ef6..cb163052fe61 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2933,6 +2933,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
L: linux-spi@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
+F: drivers/spi/spi-aspeed-smc.c
ASPEED VIDEO ENGINE DRIVER
M: Eddie James <eajames@linux.ibm.com>
diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
index 876a47042fec..35f18c01b1d8 100644
--- a/drivers/mtd/spi-nor/controllers/Kconfig
+++ b/drivers/mtd/spi-nor/controllers/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config SPI_ASPEED_SMC_MTD_SPI_NOR
tristate "Aspeed flash controllers in SPI mode"
- depends on ARCH_ASPEED || COMPILE_TEST
+ depends on (ARCH_ASPEED && !SPI_ASPEED_SMC) || COMPILE_TEST
depends on HAS_IOMEM && OF
help
This enables support for the Firmware Memory controller (FMC)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 83e352b0c8f9..dc44493439fb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -101,6 +101,17 @@ config SPI_ARMADA_3700
This enables support for the SPI controller present on the
Marvell Armada 3700 SoCs.
+config SPI_ASPEED_SMC
+ tristate "Aspeed flash controllers in SPI mode"
+ depends on (ARCH_ASPEED && !CONFIG_SPI_ASPEED_SMC_MTD_SPI_NOR) || COMPILE_TEST
+ depends on OF
+ help
+ This enables support for the Firmware Memory controller (FMC)
+ in the Aspeed AST2600, AST2500 and AST2400 SoCs when attached
+ to SPI NOR chips, and support for the SPI flash memory
+ controller (SPI) for the host firmware. The implementation
+ only supports SPI NOR.
+
config SPI_ATMEL
tristate "Atmel SPI Controller"
depends on ARCH_AT91 || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 699db95c8441..3dd0e649be94 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
+obj-$(CONFIG_SPI_ASPEED_SMC) += spi-aspeed-smc.o
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
obj-$(CONFIG_SPI_AT91_USART) += spi-at91-usart.o
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 04/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
This SPI driver adds support for the Aspeed static memory controllers
of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
* AST2600 Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. Only supports SPI type flash memory
. different segment register interface
. single, dual and quad mode.
* AST2600 SPI Flash Controller (SPI1 and SPI2)
. host firmware
. 2 chip select pins (CE0 ~ CE1)
. different segment register interface
. single, dual and quad mode.
* AST2500 Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. supports SPI type flash memory (CE0-CE1)
. CE2 can be of NOR type flash but this is not supported by the driver
. single, dual mode.
* AST2500 SPI Flash Controller (SPI1 and SPI2)
. host firmware
. 2 chip select pins (CE0 ~ CE1)
. single, dual mode.
* AST2400 New Static Memory Controller (also referred as FMC)
. BMC firmware
. New register set
. 5 chip select pins (CE0 ∼ CE4)
. supports NOR flash, NAND flash and SPI flash memory.
. single, dual and quad mode.
Each controller has a memory range on which flash devices contents are
mapped. Each device is assigned a window that can be changed at bootime
with the Segment Address Registers.
Each SPI flash device can then be accessed in two modes: Command and
User. When in User mode, SPI transfers are initiated with accesses to
the memory segment of a device. When in Command mode, memory
operations on the memory segment of a device generate SPI commands
automatically using a Control Register for the settings.
This initial patch adds support for User mode. Command mode needs a little
more work to check that the memory window on the AHB bus fits the device
size. It will come later when support for direct mapping is added.
Single and dual mode RX transfers are supported. Other types than SPI
are not supported.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 711 ++++++++++++++++++++++++
MAINTAINERS | 1 +
drivers/mtd/spi-nor/controllers/Kconfig | 2 +-
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
5 files changed, 725 insertions(+), 1 deletion(-)
create mode 100644 drivers/spi/spi-aspeed-smc.c
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
new file mode 100644
index 000000000000..688f9472e0d7
--- /dev/null
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -0,0 +1,711 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * ASPEED FMC/SPI Memory Controller Driver
+ *
+ * Copyright (c) 2015-2022, IBM Corporation.
+ * Copyright (c) 2020, ASPEED Corporation.
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+#define DEVICE_NAME "spi-aspeed-smc"
+
+#define ASPEED_SPI_DEFAULT_FREQ 50000000
+
+/* Type setting Register */
+#define CONFIG_REG 0x0
+#define CONFIG_TYPE_SPI 0x2
+
+/* CE Control Register */
+#define CE_CTRL_REG 0x4
+
+/* CEx Control Register */
+#define CE0_CTRL_REG 0x10
+#define CTRL_IO_MODE_MASK GENMASK(30, 28)
+#define CTRL_IO_SINGLE_DATA 0x0
+#define CTRL_IO_DUAL_DATA BIT(29)
+#define CTRL_IO_QUAD_DATA BIT(30)
+#define CTRL_COMMAND_SHIFT 16
+#define CTRL_IO_DUMMY_SET(dummy) \
+ (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
+#define CTRL_CE_STOP_ACTIVE BIT(2)
+#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
+#define CTRL_IO_MODE_NORMAL 0x0
+#define CTRL_IO_MODE_READ 0x1
+#define CTRL_IO_MODE_WRITE 0x2
+#define CTRL_IO_MODE_USER 0x3
+
+#define CTRL_IO_CMD_MASK 0xf0ff40c3
+
+/* CEx Address Decoding Range Register */
+#define CE0_SEGMENT_ADDR_REG 0x30
+
+enum aspeed_spi_ctl_reg_value {
+ ASPEED_SPI_BASE,
+ ASPEED_SPI_READ,
+ ASPEED_SPI_WRITE,
+ ASPEED_SPI_MAX,
+};
+
+struct aspeed_spi;
+
+struct aspeed_spi_chip {
+ struct aspeed_spi *aspi;
+ u32 cs;
+ void __iomem *ctl;
+ void __iomem *ahb_base;
+ u32 ahb_window_size;
+ u32 ctl_val[ASPEED_SPI_MAX];
+ u32 clk_freq;
+};
+
+struct aspeed_spi_data {
+ u32 ctl0;
+ u32 max_cs;
+ bool hastype;
+ u32 mode_bits;
+ u32 we0;
+
+ u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
+ u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
+ u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
+};
+
+#define ASPEED_SPI_MAX_NUM_CS 5
+
+struct aspeed_spi {
+ const struct aspeed_spi_data *data;
+
+ void __iomem *regs;
+ void __iomem *ahb_base;
+ u32 ahb_base_phy;
+ u32 ahb_window_size;
+ struct device *dev;
+
+ struct clk *clk;
+ u32 clk_freq;
+
+ struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS];
+};
+
+static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
+{
+ switch (op->data.buswidth) {
+ case 1:
+ return CTRL_IO_SINGLE_DATA;
+ case 2:
+ return CTRL_IO_DUAL_DATA;
+ case 4:
+ return CTRL_IO_QUAD_DATA;
+ default:
+ return CTRL_IO_SINGLE_DATA;
+ }
+}
+
+static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
+{
+ u32 ctl;
+
+ if (io_mode > 0) {
+ ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
+ ctl |= io_mode;
+ writel(ctl, chip->ctl);
+ }
+}
+
+static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
+{
+ u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
+
+ ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
+ writel(ctl, chip->ctl);
+
+ ctl &= ~CTRL_CE_STOP_ACTIVE;
+ writel(ctl, chip->ctl);
+}
+
+static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
+{
+ u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
+ CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
+
+ writel(ctl, chip->ctl);
+
+ /* Restore defaults */
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+}
+
+static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
+{
+ size_t offset = 0;
+
+ if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
+ IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
+ ioread32_rep(src, buf, len >> 2);
+ offset = len & ~0x3;
+ len -= offset;
+ }
+ ioread8_rep(src, (u8 *)buf + offset, len);
+ return 0;
+}
+
+static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
+{
+ size_t offset = 0;
+
+ if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
+ IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
+ iowrite32_rep(dst, buf, len >> 2);
+ offset = len & ~0x3;
+ len -= offset;
+ }
+ iowrite8_rep(dst, (const u8 *)buf + offset, len);
+ return 0;
+}
+
+static void aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
+ u64 offset, u32 opcode)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ __be32 temp;
+ u32 cmdaddr;
+
+ switch (addr_nbytes) {
+ default:
+ dev_warn_once(aspi->dev, "Unexpected address width %u, defaulting to 3",
+ addr_nbytes);
+ fallthrough;
+ case 3:
+ cmdaddr = offset & 0xFFFFFF;
+ cmdaddr |= opcode << 24;
+
+ temp = cpu_to_be32(cmdaddr);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
+ break;
+ case 4:
+ temp = cpu_to_be32(offset);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
+ break;
+ }
+}
+
+static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op)
+{
+ aspeed_spi_start_user(chip);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
+ aspeed_spi_read_from_ahb(op->data.buf.in,
+ chip->ahb_base, op->data.nbytes);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op)
+{
+ aspeed_spi_start_user(chip);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
+ aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
+ op->data.nbytes);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op,
+ u64 offset, size_t len, void *buf)
+{
+ int io_mode = aspeed_spi_get_io_mode(op);
+ u8 dummy = 0xFF;
+ int i;
+
+ aspeed_spi_start_user(chip);
+ aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
+ if (op->dummy.buswidth && op->dummy.nbytes) {
+ for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
+ aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
+ }
+
+ aspeed_spi_set_io_mode(chip, io_mode);
+
+ aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op)
+{
+ aspeed_spi_start_user(chip);
+ aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
+ aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+/* support for 1-1-1, 1-1-2 or 1-1-4 */
+static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ if (op->cmd.buswidth > 1)
+ return false;
+
+ if (op->addr.nbytes != 0) {
+ if (op->addr.buswidth > 1 || op->addr.nbytes > 4)
+ return false;
+ }
+
+ if (op->dummy.nbytes != 0) {
+ if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
+ return false;
+ }
+
+ if (op->data.nbytes != 0 && op->data.buswidth > 4)
+ return false;
+
+ return spi_mem_default_supports_op(mem, op);
+}
+
+static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
+ struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
+ u32 addr_mode, addr_mode_backup;
+ u32 ctl_val;
+ int ret = 0;
+
+ dev_dbg(aspi->dev,
+ "CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
+ chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
+ op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
+ op->dummy.buswidth, op->data.buswidth,
+ op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
+
+ addr_mode = readl(aspi->regs + CE_CTRL_REG);
+ addr_mode_backup = addr_mode;
+
+ ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
+ ctl_val &= ~CTRL_IO_CMD_MASK;
+
+ ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
+
+ /* 4BYTE address mode */
+ if (op->addr.nbytes) {
+ if (op->addr.nbytes == 4)
+ addr_mode |= (0x11 << chip->cs);
+ else
+ addr_mode &= ~(0x11 << chip->cs);
+ }
+
+ if (op->dummy.buswidth && op->dummy.nbytes)
+ ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
+
+ if (op->data.nbytes != 0) {
+ if (op->data.buswidth)
+ ctl_val |= aspeed_spi_get_io_mode(op);
+ }
+
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ ctl_val |= CTRL_IO_MODE_WRITE;
+ else
+ ctl_val |= CTRL_IO_MODE_READ;
+
+ if (addr_mode != addr_mode_backup)
+ writel(addr_mode, aspi->regs + CE_CTRL_REG);
+ writel(ctl_val, chip->ctl);
+
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ if (!op->addr.nbytes)
+ ret = aspeed_spi_read_reg(chip, op);
+ else
+ ret = aspeed_spi_read_user(chip, op, op->addr.val,
+ op->data.nbytes, op->data.buf.in);
+ } else {
+ if (!op->addr.nbytes)
+ ret = aspeed_spi_write_reg(chip, op);
+ else
+ ret = aspeed_spi_write_user(chip, op);
+ }
+
+ /* Restore defaults */
+ if (addr_mode != addr_mode_backup)
+ writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+ return ret;
+}
+
+static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ int ret;
+
+ ret = do_aspeed_spi_exec_op(mem, op);
+ if (ret)
+ dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
+ return ret;
+}
+
+static const char *aspeed_spi_get_name(struct spi_mem *mem)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
+ struct device *dev = aspi->dev;
+
+ return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
+}
+
+struct aspeed_spi_window {
+ u32 cs;
+ u32 offset;
+ u32 size;
+};
+
+static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
+ struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS])
+{
+ const struct aspeed_spi_data *data = aspi->data;
+ u32 reg_val;
+ u32 cs;
+
+ for (cs = 0; cs < aspi->data->max_cs; cs++) {
+ reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
+ windows[cs].cs = cs;
+ windows[cs].size = data->segment_end(aspi, reg_val) -
+ data->segment_start(aspi, reg_val);
+ windows[cs].offset = cs ? windows[cs - 1].offset + windows[cs - 1].size : 0;
+ dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
+ windows[cs].offset, windows[cs].size);
+ }
+}
+
+/*
+ * On the AST2600, some CE windows are closed by default at reset but
+ * U-Boot should open all.
+ */
+static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
+ struct aspeed_spi_window *win = &windows[chip->cs];
+
+ aspeed_spi_get_windows(aspi, windows);
+
+ chip->ahb_base = aspi->ahb_base + win->offset;
+ chip->ahb_window_size = win->size;
+
+ dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
+ chip->cs, aspi->ahb_base_phy + win->offset,
+ aspi->ahb_base_phy + win->offset + win->size - 1,
+ win->size >> 20);
+
+ return chip->ahb_window_size ? 0 : -1;
+}
+
+static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
+ .supports_op = aspeed_spi_supports_op,
+ .exec_op = aspeed_spi_exec_op,
+ .get_name = aspeed_spi_get_name,
+};
+
+static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
+{
+ u32 reg;
+
+ reg = readl(aspi->regs + CONFIG_REG);
+ reg &= ~(0x3 << (cs * 2));
+ reg |= type << (cs * 2);
+ writel(reg, aspi->regs + CONFIG_REG);
+}
+
+static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
+{
+ u32 we_bit = BIT(aspi->data->we0 + cs);
+ u32 reg = readl(aspi->regs + CONFIG_REG);
+
+ if (enable)
+ reg |= we_bit;
+ else
+ reg &= ~we_bit;
+ writel(reg, aspi->regs + CONFIG_REG);
+}
+
+static int aspeed_spi_setup(struct spi_device *spi)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
+ const struct aspeed_spi_data *data = aspi->data;
+ unsigned int cs = spi->chip_select;
+ struct aspeed_spi_chip *chip = &aspi->chips[cs];
+
+ chip->aspi = aspi;
+ chip->cs = cs;
+ chip->ctl = aspi->regs + data->ctl0 + cs * 4;
+
+ /* The driver only supports SPI type flash */
+ if (data->hastype)
+ aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
+
+ if (aspeed_spi_chip_set_default_window(chip) < 0) {
+ dev_warn(aspi->dev, "CE%d window invalid", cs);
+ return -EINVAL;
+ }
+
+ aspeed_spi_chip_enable(aspi, cs, true);
+
+ chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
+
+ dev_dbg(aspi->dev, "CE%d setup done\n", cs);
+ return 0;
+}
+
+static void aspeed_spi_cleanup(struct spi_device *spi)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
+ unsigned int cs = spi->chip_select;
+
+ aspeed_spi_chip_enable(aspi, cs, false);
+
+ dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
+}
+
+static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
+{
+ int cs;
+
+ for (cs = 0; cs < aspi->data->max_cs; cs++)
+ aspeed_spi_chip_enable(aspi, cs, enable);
+}
+
+static int aspeed_spi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct aspeed_spi_data *data;
+ struct spi_controller *ctlr;
+ struct aspeed_spi *aspi;
+ struct resource *res;
+ int ret;
+
+ data = of_device_get_match_data(&pdev->dev);
+ if (!data)
+ return -ENODEV;
+
+ ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
+ if (!ctlr)
+ return -ENOMEM;
+
+ aspi = spi_controller_get_devdata(ctlr);
+ platform_set_drvdata(pdev, aspi);
+ aspi->data = data;
+ aspi->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ aspi->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(aspi->regs)) {
+ dev_err(dev, "missing AHB register window\n");
+ return PTR_ERR(aspi->regs);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ aspi->ahb_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(aspi->ahb_base)) {
+ dev_err(dev, "missing AHB mapping window\n");
+ return PTR_ERR(aspi->ahb_base);
+ }
+
+ aspi->ahb_window_size = resource_size(res);
+ aspi->ahb_base_phy = res->start;
+
+ aspi->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(aspi->clk)) {
+ dev_err(dev, "missing clock\n");
+ return PTR_ERR(aspi->clk);
+ }
+
+ aspi->clk_freq = clk_get_rate(aspi->clk);
+ if (!aspi->clk_freq) {
+ dev_err(dev, "invalid clock\n");
+ return -EINVAL;
+ }
+
+ ret = clk_prepare_enable(aspi->clk);
+ if (ret) {
+ dev_err(dev, "can not enable the clock\n");
+ return ret;
+ }
+
+ /* IRQ is for DMA, which the driver doesn't support yet */
+
+ ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
+ ctlr->bus_num = pdev->id;
+ ctlr->mem_ops = &aspeed_spi_mem_ops;
+ ctlr->setup = aspeed_spi_setup;
+ ctlr->cleanup = aspeed_spi_cleanup;
+ ctlr->num_chipselect = data->max_cs;
+ ctlr->dev.of_node = dev->of_node;
+
+ ret = devm_spi_register_controller(dev, ctlr);
+ if (ret) {
+ dev_err(&pdev->dev, "spi_register_controller failed\n");
+ goto disable_clk;
+ }
+ return 0;
+
+disable_clk:
+ clk_disable_unprepare(aspi->clk);
+ return ret;
+}
+
+static int aspeed_spi_remove(struct platform_device *pdev)
+{
+ struct aspeed_spi *aspi = platform_get_drvdata(pdev);
+
+ aspeed_spi_enable(aspi, false);
+ clk_disable_unprepare(aspi->clk);
+ return 0;
+}
+
+/*
+ * AHB mappings
+ */
+
+/*
+ * The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
+ * The address range is encoded with absolute addresses in the overall
+ * mapping window.
+ */
+static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
+{
+ return ((reg >> 16) & 0xFF) << 23;
+}
+
+static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
+{
+ return ((reg >> 24) & 0xFF) << 23;
+}
+
+static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
+{
+ return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
+}
+
+/*
+ * The Segment Registers of the AST2600 use a 1MB unit. The address
+ * range is encoded with offsets in the overall mapping window.
+ */
+
+#define AST2600_SEG_ADDR_MASK 0x0ff00000
+
+static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
+ u32 reg)
+{
+ u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
+
+ return aspi->ahb_base_phy + start_offset;
+}
+
+static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
+ u32 reg)
+{
+ u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
+
+ /* segment is disabled */
+ if (!end_offset)
+ return aspi->ahb_base_phy;
+
+ return aspi->ahb_base_phy + end_offset + 0x100000;
+}
+
+static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
+ u32 start, u32 end)
+{
+ /* disable zero size segments */
+ if (start == end)
+ return 0;
+
+ return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
+ ((end - 1) & AST2600_SEG_ADDR_MASK);
+}
+
+/*
+ * Platform definitions
+ */
+static const struct aspeed_spi_data ast2400_fmc_data = {
+ .max_cs = 5,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_start,
+ .segment_end = aspeed_spi_segment_end,
+ .segment_reg = aspeed_spi_segment_reg,
+};
+
+static const struct aspeed_spi_data ast2500_fmc_data = {
+ .max_cs = 3,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_start,
+ .segment_end = aspeed_spi_segment_end,
+ .segment_reg = aspeed_spi_segment_reg,
+};
+
+static const struct aspeed_spi_data ast2500_spi_data = {
+ .max_cs = 2,
+ .hastype = false,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_start,
+ .segment_end = aspeed_spi_segment_end,
+ .segment_reg = aspeed_spi_segment_reg,
+};
+
+static const struct aspeed_spi_data ast2600_fmc_data = {
+ .max_cs = 3,
+ .hastype = false,
+ .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_ast2600_start,
+ .segment_end = aspeed_spi_segment_ast2600_end,
+ .segment_reg = aspeed_spi_segment_ast2600_reg,
+};
+
+static const struct aspeed_spi_data ast2600_spi_data = {
+ .max_cs = 2,
+ .hastype = false,
+ .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_ast2600_start,
+ .segment_end = aspeed_spi_segment_ast2600_end,
+ .segment_reg = aspeed_spi_segment_ast2600_reg,
+};
+
+static const struct of_device_id aspeed_spi_matches[] = {
+ { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
+ { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
+ { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
+ { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
+ { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
+ { }
+};
+MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
+
+static struct platform_driver aspeed_spi_driver = {
+ .probe = aspeed_spi_probe,
+ .remove = aspeed_spi_remove,
+ .driver = {
+ .name = DEVICE_NAME,
+ .of_match_table = aspeed_spi_matches,
+ }
+};
+
+module_platform_driver(aspeed_spi_driver);
+
+MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
+MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>");
+MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/MAINTAINERS b/MAINTAINERS
index f5ab77548ef6..cb163052fe61 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2933,6 +2933,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
L: linux-spi@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
+F: drivers/spi/spi-aspeed-smc.c
ASPEED VIDEO ENGINE DRIVER
M: Eddie James <eajames@linux.ibm.com>
diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
index 876a47042fec..35f18c01b1d8 100644
--- a/drivers/mtd/spi-nor/controllers/Kconfig
+++ b/drivers/mtd/spi-nor/controllers/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config SPI_ASPEED_SMC_MTD_SPI_NOR
tristate "Aspeed flash controllers in SPI mode"
- depends on ARCH_ASPEED || COMPILE_TEST
+ depends on (ARCH_ASPEED && !SPI_ASPEED_SMC) || COMPILE_TEST
depends on HAS_IOMEM && OF
help
This enables support for the Firmware Memory controller (FMC)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 83e352b0c8f9..dc44493439fb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -101,6 +101,17 @@ config SPI_ARMADA_3700
This enables support for the SPI controller present on the
Marvell Armada 3700 SoCs.
+config SPI_ASPEED_SMC
+ tristate "Aspeed flash controllers in SPI mode"
+ depends on (ARCH_ASPEED && !CONFIG_SPI_ASPEED_SMC_MTD_SPI_NOR) || COMPILE_TEST
+ depends on OF
+ help
+ This enables support for the Firmware Memory controller (FMC)
+ in the Aspeed AST2600, AST2500 and AST2400 SoCs when attached
+ to SPI NOR chips, and support for the SPI flash memory
+ controller (SPI) for the host firmware. The implementation
+ only supports SPI NOR.
+
config SPI_ATMEL
tristate "Atmel SPI Controller"
depends on ARCH_AT91 || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 699db95c8441..3dd0e649be94 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
+obj-$(CONFIG_SPI_ASPEED_SMC) += spi-aspeed-smc.o
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
obj-$(CONFIG_SPI_AT91_USART) += spi-at91-usart.o
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 04/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
This SPI driver adds support for the Aspeed static memory controllers
of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
* AST2600 Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. Only supports SPI type flash memory
. different segment register interface
. single, dual and quad mode.
* AST2600 SPI Flash Controller (SPI1 and SPI2)
. host firmware
. 2 chip select pins (CE0 ~ CE1)
. different segment register interface
. single, dual and quad mode.
* AST2500 Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. supports SPI type flash memory (CE0-CE1)
. CE2 can be of NOR type flash but this is not supported by the driver
. single, dual mode.
* AST2500 SPI Flash Controller (SPI1 and SPI2)
. host firmware
. 2 chip select pins (CE0 ~ CE1)
. single, dual mode.
* AST2400 New Static Memory Controller (also referred as FMC)
. BMC firmware
. New register set
. 5 chip select pins (CE0 ∼ CE4)
. supports NOR flash, NAND flash and SPI flash memory.
. single, dual and quad mode.
Each controller has a memory range on which flash devices contents are
mapped. Each device is assigned a window that can be changed at bootime
with the Segment Address Registers.
Each SPI flash device can then be accessed in two modes: Command and
User. When in User mode, SPI transfers are initiated with accesses to
the memory segment of a device. When in Command mode, memory
operations on the memory segment of a device generate SPI commands
automatically using a Control Register for the settings.
This initial patch adds support for User mode. Command mode needs a little
more work to check that the memory window on the AHB bus fits the device
size. It will come later when support for direct mapping is added.
Single and dual mode RX transfers are supported. Other types than SPI
are not supported.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 711 ++++++++++++++++++++++++
MAINTAINERS | 1 +
drivers/mtd/spi-nor/controllers/Kconfig | 2 +-
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
5 files changed, 725 insertions(+), 1 deletion(-)
create mode 100644 drivers/spi/spi-aspeed-smc.c
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
new file mode 100644
index 000000000000..688f9472e0d7
--- /dev/null
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -0,0 +1,711 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * ASPEED FMC/SPI Memory Controller Driver
+ *
+ * Copyright (c) 2015-2022, IBM Corporation.
+ * Copyright (c) 2020, ASPEED Corporation.
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+#define DEVICE_NAME "spi-aspeed-smc"
+
+#define ASPEED_SPI_DEFAULT_FREQ 50000000
+
+/* Type setting Register */
+#define CONFIG_REG 0x0
+#define CONFIG_TYPE_SPI 0x2
+
+/* CE Control Register */
+#define CE_CTRL_REG 0x4
+
+/* CEx Control Register */
+#define CE0_CTRL_REG 0x10
+#define CTRL_IO_MODE_MASK GENMASK(30, 28)
+#define CTRL_IO_SINGLE_DATA 0x0
+#define CTRL_IO_DUAL_DATA BIT(29)
+#define CTRL_IO_QUAD_DATA BIT(30)
+#define CTRL_COMMAND_SHIFT 16
+#define CTRL_IO_DUMMY_SET(dummy) \
+ (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
+#define CTRL_CE_STOP_ACTIVE BIT(2)
+#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
+#define CTRL_IO_MODE_NORMAL 0x0
+#define CTRL_IO_MODE_READ 0x1
+#define CTRL_IO_MODE_WRITE 0x2
+#define CTRL_IO_MODE_USER 0x3
+
+#define CTRL_IO_CMD_MASK 0xf0ff40c3
+
+/* CEx Address Decoding Range Register */
+#define CE0_SEGMENT_ADDR_REG 0x30
+
+enum aspeed_spi_ctl_reg_value {
+ ASPEED_SPI_BASE,
+ ASPEED_SPI_READ,
+ ASPEED_SPI_WRITE,
+ ASPEED_SPI_MAX,
+};
+
+struct aspeed_spi;
+
+struct aspeed_spi_chip {
+ struct aspeed_spi *aspi;
+ u32 cs;
+ void __iomem *ctl;
+ void __iomem *ahb_base;
+ u32 ahb_window_size;
+ u32 ctl_val[ASPEED_SPI_MAX];
+ u32 clk_freq;
+};
+
+struct aspeed_spi_data {
+ u32 ctl0;
+ u32 max_cs;
+ bool hastype;
+ u32 mode_bits;
+ u32 we0;
+
+ u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
+ u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
+ u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
+};
+
+#define ASPEED_SPI_MAX_NUM_CS 5
+
+struct aspeed_spi {
+ const struct aspeed_spi_data *data;
+
+ void __iomem *regs;
+ void __iomem *ahb_base;
+ u32 ahb_base_phy;
+ u32 ahb_window_size;
+ struct device *dev;
+
+ struct clk *clk;
+ u32 clk_freq;
+
+ struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS];
+};
+
+static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
+{
+ switch (op->data.buswidth) {
+ case 1:
+ return CTRL_IO_SINGLE_DATA;
+ case 2:
+ return CTRL_IO_DUAL_DATA;
+ case 4:
+ return CTRL_IO_QUAD_DATA;
+ default:
+ return CTRL_IO_SINGLE_DATA;
+ }
+}
+
+static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
+{
+ u32 ctl;
+
+ if (io_mode > 0) {
+ ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
+ ctl |= io_mode;
+ writel(ctl, chip->ctl);
+ }
+}
+
+static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
+{
+ u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
+
+ ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
+ writel(ctl, chip->ctl);
+
+ ctl &= ~CTRL_CE_STOP_ACTIVE;
+ writel(ctl, chip->ctl);
+}
+
+static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
+{
+ u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
+ CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
+
+ writel(ctl, chip->ctl);
+
+ /* Restore defaults */
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+}
+
+static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
+{
+ size_t offset = 0;
+
+ if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
+ IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
+ ioread32_rep(src, buf, len >> 2);
+ offset = len & ~0x3;
+ len -= offset;
+ }
+ ioread8_rep(src, (u8 *)buf + offset, len);
+ return 0;
+}
+
+static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
+{
+ size_t offset = 0;
+
+ if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
+ IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
+ iowrite32_rep(dst, buf, len >> 2);
+ offset = len & ~0x3;
+ len -= offset;
+ }
+ iowrite8_rep(dst, (const u8 *)buf + offset, len);
+ return 0;
+}
+
+static void aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
+ u64 offset, u32 opcode)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ __be32 temp;
+ u32 cmdaddr;
+
+ switch (addr_nbytes) {
+ default:
+ dev_warn_once(aspi->dev, "Unexpected address width %u, defaulting to 3",
+ addr_nbytes);
+ fallthrough;
+ case 3:
+ cmdaddr = offset & 0xFFFFFF;
+ cmdaddr |= opcode << 24;
+
+ temp = cpu_to_be32(cmdaddr);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
+ break;
+ case 4:
+ temp = cpu_to_be32(offset);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
+ break;
+ }
+}
+
+static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op)
+{
+ aspeed_spi_start_user(chip);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
+ aspeed_spi_read_from_ahb(op->data.buf.in,
+ chip->ahb_base, op->data.nbytes);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op)
+{
+ aspeed_spi_start_user(chip);
+ aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
+ aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
+ op->data.nbytes);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op,
+ u64 offset, size_t len, void *buf)
+{
+ int io_mode = aspeed_spi_get_io_mode(op);
+ u8 dummy = 0xFF;
+ int i;
+
+ aspeed_spi_start_user(chip);
+ aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
+ if (op->dummy.buswidth && op->dummy.nbytes) {
+ for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
+ aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
+ }
+
+ aspeed_spi_set_io_mode(chip, io_mode);
+
+ aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
+ const struct spi_mem_op *op)
+{
+ aspeed_spi_start_user(chip);
+ aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
+ aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
+ aspeed_spi_stop_user(chip);
+ return 0;
+}
+
+/* support for 1-1-1, 1-1-2 or 1-1-4 */
+static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ if (op->cmd.buswidth > 1)
+ return false;
+
+ if (op->addr.nbytes != 0) {
+ if (op->addr.buswidth > 1 || op->addr.nbytes > 4)
+ return false;
+ }
+
+ if (op->dummy.nbytes != 0) {
+ if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
+ return false;
+ }
+
+ if (op->data.nbytes != 0 && op->data.buswidth > 4)
+ return false;
+
+ return spi_mem_default_supports_op(mem, op);
+}
+
+static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
+ struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
+ u32 addr_mode, addr_mode_backup;
+ u32 ctl_val;
+ int ret = 0;
+
+ dev_dbg(aspi->dev,
+ "CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
+ chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
+ op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
+ op->dummy.buswidth, op->data.buswidth,
+ op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
+
+ addr_mode = readl(aspi->regs + CE_CTRL_REG);
+ addr_mode_backup = addr_mode;
+
+ ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
+ ctl_val &= ~CTRL_IO_CMD_MASK;
+
+ ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
+
+ /* 4BYTE address mode */
+ if (op->addr.nbytes) {
+ if (op->addr.nbytes == 4)
+ addr_mode |= (0x11 << chip->cs);
+ else
+ addr_mode &= ~(0x11 << chip->cs);
+ }
+
+ if (op->dummy.buswidth && op->dummy.nbytes)
+ ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
+
+ if (op->data.nbytes != 0) {
+ if (op->data.buswidth)
+ ctl_val |= aspeed_spi_get_io_mode(op);
+ }
+
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ ctl_val |= CTRL_IO_MODE_WRITE;
+ else
+ ctl_val |= CTRL_IO_MODE_READ;
+
+ if (addr_mode != addr_mode_backup)
+ writel(addr_mode, aspi->regs + CE_CTRL_REG);
+ writel(ctl_val, chip->ctl);
+
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ if (!op->addr.nbytes)
+ ret = aspeed_spi_read_reg(chip, op);
+ else
+ ret = aspeed_spi_read_user(chip, op, op->addr.val,
+ op->data.nbytes, op->data.buf.in);
+ } else {
+ if (!op->addr.nbytes)
+ ret = aspeed_spi_write_reg(chip, op);
+ else
+ ret = aspeed_spi_write_user(chip, op);
+ }
+
+ /* Restore defaults */
+ if (addr_mode != addr_mode_backup)
+ writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+ return ret;
+}
+
+static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ int ret;
+
+ ret = do_aspeed_spi_exec_op(mem, op);
+ if (ret)
+ dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
+ return ret;
+}
+
+static const char *aspeed_spi_get_name(struct spi_mem *mem)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
+ struct device *dev = aspi->dev;
+
+ return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
+}
+
+struct aspeed_spi_window {
+ u32 cs;
+ u32 offset;
+ u32 size;
+};
+
+static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
+ struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS])
+{
+ const struct aspeed_spi_data *data = aspi->data;
+ u32 reg_val;
+ u32 cs;
+
+ for (cs = 0; cs < aspi->data->max_cs; cs++) {
+ reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
+ windows[cs].cs = cs;
+ windows[cs].size = data->segment_end(aspi, reg_val) -
+ data->segment_start(aspi, reg_val);
+ windows[cs].offset = cs ? windows[cs - 1].offset + windows[cs - 1].size : 0;
+ dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
+ windows[cs].offset, windows[cs].size);
+ }
+}
+
+/*
+ * On the AST2600, some CE windows are closed by default at reset but
+ * U-Boot should open all.
+ */
+static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
+ struct aspeed_spi_window *win = &windows[chip->cs];
+
+ aspeed_spi_get_windows(aspi, windows);
+
+ chip->ahb_base = aspi->ahb_base + win->offset;
+ chip->ahb_window_size = win->size;
+
+ dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
+ chip->cs, aspi->ahb_base_phy + win->offset,
+ aspi->ahb_base_phy + win->offset + win->size - 1,
+ win->size >> 20);
+
+ return chip->ahb_window_size ? 0 : -1;
+}
+
+static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
+ .supports_op = aspeed_spi_supports_op,
+ .exec_op = aspeed_spi_exec_op,
+ .get_name = aspeed_spi_get_name,
+};
+
+static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
+{
+ u32 reg;
+
+ reg = readl(aspi->regs + CONFIG_REG);
+ reg &= ~(0x3 << (cs * 2));
+ reg |= type << (cs * 2);
+ writel(reg, aspi->regs + CONFIG_REG);
+}
+
+static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
+{
+ u32 we_bit = BIT(aspi->data->we0 + cs);
+ u32 reg = readl(aspi->regs + CONFIG_REG);
+
+ if (enable)
+ reg |= we_bit;
+ else
+ reg &= ~we_bit;
+ writel(reg, aspi->regs + CONFIG_REG);
+}
+
+static int aspeed_spi_setup(struct spi_device *spi)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
+ const struct aspeed_spi_data *data = aspi->data;
+ unsigned int cs = spi->chip_select;
+ struct aspeed_spi_chip *chip = &aspi->chips[cs];
+
+ chip->aspi = aspi;
+ chip->cs = cs;
+ chip->ctl = aspi->regs + data->ctl0 + cs * 4;
+
+ /* The driver only supports SPI type flash */
+ if (data->hastype)
+ aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
+
+ if (aspeed_spi_chip_set_default_window(chip) < 0) {
+ dev_warn(aspi->dev, "CE%d window invalid", cs);
+ return -EINVAL;
+ }
+
+ aspeed_spi_chip_enable(aspi, cs, true);
+
+ chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
+
+ dev_dbg(aspi->dev, "CE%d setup done\n", cs);
+ return 0;
+}
+
+static void aspeed_spi_cleanup(struct spi_device *spi)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
+ unsigned int cs = spi->chip_select;
+
+ aspeed_spi_chip_enable(aspi, cs, false);
+
+ dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
+}
+
+static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
+{
+ int cs;
+
+ for (cs = 0; cs < aspi->data->max_cs; cs++)
+ aspeed_spi_chip_enable(aspi, cs, enable);
+}
+
+static int aspeed_spi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct aspeed_spi_data *data;
+ struct spi_controller *ctlr;
+ struct aspeed_spi *aspi;
+ struct resource *res;
+ int ret;
+
+ data = of_device_get_match_data(&pdev->dev);
+ if (!data)
+ return -ENODEV;
+
+ ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
+ if (!ctlr)
+ return -ENOMEM;
+
+ aspi = spi_controller_get_devdata(ctlr);
+ platform_set_drvdata(pdev, aspi);
+ aspi->data = data;
+ aspi->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ aspi->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(aspi->regs)) {
+ dev_err(dev, "missing AHB register window\n");
+ return PTR_ERR(aspi->regs);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ aspi->ahb_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(aspi->ahb_base)) {
+ dev_err(dev, "missing AHB mapping window\n");
+ return PTR_ERR(aspi->ahb_base);
+ }
+
+ aspi->ahb_window_size = resource_size(res);
+ aspi->ahb_base_phy = res->start;
+
+ aspi->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(aspi->clk)) {
+ dev_err(dev, "missing clock\n");
+ return PTR_ERR(aspi->clk);
+ }
+
+ aspi->clk_freq = clk_get_rate(aspi->clk);
+ if (!aspi->clk_freq) {
+ dev_err(dev, "invalid clock\n");
+ return -EINVAL;
+ }
+
+ ret = clk_prepare_enable(aspi->clk);
+ if (ret) {
+ dev_err(dev, "can not enable the clock\n");
+ return ret;
+ }
+
+ /* IRQ is for DMA, which the driver doesn't support yet */
+
+ ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
+ ctlr->bus_num = pdev->id;
+ ctlr->mem_ops = &aspeed_spi_mem_ops;
+ ctlr->setup = aspeed_spi_setup;
+ ctlr->cleanup = aspeed_spi_cleanup;
+ ctlr->num_chipselect = data->max_cs;
+ ctlr->dev.of_node = dev->of_node;
+
+ ret = devm_spi_register_controller(dev, ctlr);
+ if (ret) {
+ dev_err(&pdev->dev, "spi_register_controller failed\n");
+ goto disable_clk;
+ }
+ return 0;
+
+disable_clk:
+ clk_disable_unprepare(aspi->clk);
+ return ret;
+}
+
+static int aspeed_spi_remove(struct platform_device *pdev)
+{
+ struct aspeed_spi *aspi = platform_get_drvdata(pdev);
+
+ aspeed_spi_enable(aspi, false);
+ clk_disable_unprepare(aspi->clk);
+ return 0;
+}
+
+/*
+ * AHB mappings
+ */
+
+/*
+ * The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
+ * The address range is encoded with absolute addresses in the overall
+ * mapping window.
+ */
+static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
+{
+ return ((reg >> 16) & 0xFF) << 23;
+}
+
+static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
+{
+ return ((reg >> 24) & 0xFF) << 23;
+}
+
+static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
+{
+ return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
+}
+
+/*
+ * The Segment Registers of the AST2600 use a 1MB unit. The address
+ * range is encoded with offsets in the overall mapping window.
+ */
+
+#define AST2600_SEG_ADDR_MASK 0x0ff00000
+
+static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
+ u32 reg)
+{
+ u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
+
+ return aspi->ahb_base_phy + start_offset;
+}
+
+static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
+ u32 reg)
+{
+ u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
+
+ /* segment is disabled */
+ if (!end_offset)
+ return aspi->ahb_base_phy;
+
+ return aspi->ahb_base_phy + end_offset + 0x100000;
+}
+
+static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
+ u32 start, u32 end)
+{
+ /* disable zero size segments */
+ if (start == end)
+ return 0;
+
+ return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
+ ((end - 1) & AST2600_SEG_ADDR_MASK);
+}
+
+/*
+ * Platform definitions
+ */
+static const struct aspeed_spi_data ast2400_fmc_data = {
+ .max_cs = 5,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_start,
+ .segment_end = aspeed_spi_segment_end,
+ .segment_reg = aspeed_spi_segment_reg,
+};
+
+static const struct aspeed_spi_data ast2500_fmc_data = {
+ .max_cs = 3,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_start,
+ .segment_end = aspeed_spi_segment_end,
+ .segment_reg = aspeed_spi_segment_reg,
+};
+
+static const struct aspeed_spi_data ast2500_spi_data = {
+ .max_cs = 2,
+ .hastype = false,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_start,
+ .segment_end = aspeed_spi_segment_end,
+ .segment_reg = aspeed_spi_segment_reg,
+};
+
+static const struct aspeed_spi_data ast2600_fmc_data = {
+ .max_cs = 3,
+ .hastype = false,
+ .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_ast2600_start,
+ .segment_end = aspeed_spi_segment_ast2600_end,
+ .segment_reg = aspeed_spi_segment_ast2600_reg,
+};
+
+static const struct aspeed_spi_data ast2600_spi_data = {
+ .max_cs = 2,
+ .hastype = false,
+ .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
+ .we0 = 16,
+ .ctl0 = CE0_CTRL_REG,
+ .segment_start = aspeed_spi_segment_ast2600_start,
+ .segment_end = aspeed_spi_segment_ast2600_end,
+ .segment_reg = aspeed_spi_segment_ast2600_reg,
+};
+
+static const struct of_device_id aspeed_spi_matches[] = {
+ { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
+ { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
+ { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
+ { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
+ { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
+ { }
+};
+MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
+
+static struct platform_driver aspeed_spi_driver = {
+ .probe = aspeed_spi_probe,
+ .remove = aspeed_spi_remove,
+ .driver = {
+ .name = DEVICE_NAME,
+ .of_match_table = aspeed_spi_matches,
+ }
+};
+
+module_platform_driver(aspeed_spi_driver);
+
+MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
+MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>");
+MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/MAINTAINERS b/MAINTAINERS
index f5ab77548ef6..cb163052fe61 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2933,6 +2933,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
L: linux-spi@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
+F: drivers/spi/spi-aspeed-smc.c
ASPEED VIDEO ENGINE DRIVER
M: Eddie James <eajames@linux.ibm.com>
diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
index 876a47042fec..35f18c01b1d8 100644
--- a/drivers/mtd/spi-nor/controllers/Kconfig
+++ b/drivers/mtd/spi-nor/controllers/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config SPI_ASPEED_SMC_MTD_SPI_NOR
tristate "Aspeed flash controllers in SPI mode"
- depends on ARCH_ASPEED || COMPILE_TEST
+ depends on (ARCH_ASPEED && !SPI_ASPEED_SMC) || COMPILE_TEST
depends on HAS_IOMEM && OF
help
This enables support for the Firmware Memory controller (FMC)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 83e352b0c8f9..dc44493439fb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -101,6 +101,17 @@ config SPI_ARMADA_3700
This enables support for the SPI controller present on the
Marvell Armada 3700 SoCs.
+config SPI_ASPEED_SMC
+ tristate "Aspeed flash controllers in SPI mode"
+ depends on (ARCH_ASPEED && !CONFIG_SPI_ASPEED_SMC_MTD_SPI_NOR) || COMPILE_TEST
+ depends on OF
+ help
+ This enables support for the Firmware Memory controller (FMC)
+ in the Aspeed AST2600, AST2500 and AST2400 SoCs when attached
+ to SPI NOR chips, and support for the SPI flash memory
+ controller (SPI) for the host firmware. The implementation
+ only supports SPI NOR.
+
config SPI_ATMEL
tristate "Atmel SPI Controller"
depends on ARCH_AT91 || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 699db95c8441..3dd0e649be94 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
+obj-$(CONFIG_SPI_ASPEED_SMC) += spi-aspeed-smc.o
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
obj-$(CONFIG_SPI_AT91_USART) += spi-at91-usart.o
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 05/10] spi: aspeed: Add support for direct mapping
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
Use direct mapping to read the flash device contents. This operation
mode is called "Command mode" on Aspeed SoC SMC controllers. It uses a
Control Register for the settings to apply when a memory operation is
performed on the flash device mapping window.
If the window is not big enough, fall back to the "User mode" to
perform the read.
Since direct mapping now handles all reads of the flash device
contents, also use memcpy_fromio for other address spaces, such as
SFDP.
Direct mapping for writes will come later when validated.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 67 ++++++++++++++++++++++++++++++++++--
1 file changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 688f9472e0d7..b4854b521477 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -324,8 +324,8 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
if (!op->addr.nbytes)
ret = aspeed_spi_read_reg(chip, op);
else
- ret = aspeed_spi_read_user(chip, op, op->addr.val,
- op->data.nbytes, op->data.buf.in);
+ memcpy_fromio(op->data.buf.in, chip->ahb_base + op->addr.val,
+ op->data.nbytes);
} else {
if (!op->addr.nbytes)
ret = aspeed_spi_write_reg(chip, op);
@@ -405,10 +405,73 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
return chip->ahb_window_size ? 0 : -1;
}
+static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
+ struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ u32 ctl_val;
+ int ret = 0;
+
+ chip->clk_freq = desc->mem->spi->max_speed_hz;
+
+ /* Only for reads */
+ if (op->data.dir != SPI_MEM_DATA_IN)
+ return -EOPNOTSUPP;
+
+ if (desc->info.length > chip->ahb_window_size)
+ dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
+ chip->cs, chip->ahb_window_size >> 20);
+
+ /* Define the default IO read settings */
+ ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
+ ctl_val |= aspeed_spi_get_io_mode(op) |
+ op->cmd.opcode << CTRL_COMMAND_SHIFT |
+ CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth) |
+ CTRL_IO_MODE_READ;
+
+ /* Tune 4BYTE address mode */
+ if (op->addr.nbytes) {
+ u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
+
+ if (op->addr.nbytes == 4)
+ addr_mode |= (0x11 << chip->cs);
+ else
+ addr_mode &= ~(0x11 << chip->cs);
+ writel(addr_mode, aspi->regs + CE_CTRL_REG);
+ }
+
+ /* READ mode is the controller default setting */
+ chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+
+ dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
+ chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
+
+ return ret;
+}
+
+static int aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offset, size_t len, void *buf)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
+ struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
+
+ /* Switch to USER command mode if mapping window is too small */
+ if (chip->ahb_window_size < offset + len)
+ aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
+ else
+ memcpy_fromio(buf, chip->ahb_base + offset, len);
+
+ return len;
+}
+
static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
.supports_op = aspeed_spi_supports_op,
.exec_op = aspeed_spi_exec_op,
.get_name = aspeed_spi_get_name,
+ .dirmap_create = aspeed_spi_dirmap_create,
+ .dirmap_read = aspeed_spi_dirmap_read,
};
static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 05/10] spi: aspeed: Add support for direct mapping
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
Use direct mapping to read the flash device contents. This operation
mode is called "Command mode" on Aspeed SoC SMC controllers. It uses a
Control Register for the settings to apply when a memory operation is
performed on the flash device mapping window.
If the window is not big enough, fall back to the "User mode" to
perform the read.
Since direct mapping now handles all reads of the flash device
contents, also use memcpy_fromio for other address spaces, such as
SFDP.
Direct mapping for writes will come later when validated.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 67 ++++++++++++++++++++++++++++++++++--
1 file changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 688f9472e0d7..b4854b521477 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -324,8 +324,8 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
if (!op->addr.nbytes)
ret = aspeed_spi_read_reg(chip, op);
else
- ret = aspeed_spi_read_user(chip, op, op->addr.val,
- op->data.nbytes, op->data.buf.in);
+ memcpy_fromio(op->data.buf.in, chip->ahb_base + op->addr.val,
+ op->data.nbytes);
} else {
if (!op->addr.nbytes)
ret = aspeed_spi_write_reg(chip, op);
@@ -405,10 +405,73 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
return chip->ahb_window_size ? 0 : -1;
}
+static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
+ struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ u32 ctl_val;
+ int ret = 0;
+
+ chip->clk_freq = desc->mem->spi->max_speed_hz;
+
+ /* Only for reads */
+ if (op->data.dir != SPI_MEM_DATA_IN)
+ return -EOPNOTSUPP;
+
+ if (desc->info.length > chip->ahb_window_size)
+ dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
+ chip->cs, chip->ahb_window_size >> 20);
+
+ /* Define the default IO read settings */
+ ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
+ ctl_val |= aspeed_spi_get_io_mode(op) |
+ op->cmd.opcode << CTRL_COMMAND_SHIFT |
+ CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth) |
+ CTRL_IO_MODE_READ;
+
+ /* Tune 4BYTE address mode */
+ if (op->addr.nbytes) {
+ u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
+
+ if (op->addr.nbytes == 4)
+ addr_mode |= (0x11 << chip->cs);
+ else
+ addr_mode &= ~(0x11 << chip->cs);
+ writel(addr_mode, aspi->regs + CE_CTRL_REG);
+ }
+
+ /* READ mode is the controller default setting */
+ chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+
+ dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
+ chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
+
+ return ret;
+}
+
+static int aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offset, size_t len, void *buf)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
+ struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
+
+ /* Switch to USER command mode if mapping window is too small */
+ if (chip->ahb_window_size < offset + len)
+ aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
+ else
+ memcpy_fromio(buf, chip->ahb_base + offset, len);
+
+ return len;
+}
+
static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
.supports_op = aspeed_spi_supports_op,
.exec_op = aspeed_spi_exec_op,
.get_name = aspeed_spi_get_name,
+ .dirmap_create = aspeed_spi_dirmap_create,
+ .dirmap_read = aspeed_spi_dirmap_read,
};
static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 05/10] spi: aspeed: Add support for direct mapping
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
Use direct mapping to read the flash device contents. This operation
mode is called "Command mode" on Aspeed SoC SMC controllers. It uses a
Control Register for the settings to apply when a memory operation is
performed on the flash device mapping window.
If the window is not big enough, fall back to the "User mode" to
perform the read.
Since direct mapping now handles all reads of the flash device
contents, also use memcpy_fromio for other address spaces, such as
SFDP.
Direct mapping for writes will come later when validated.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 67 ++++++++++++++++++++++++++++++++++--
1 file changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 688f9472e0d7..b4854b521477 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -324,8 +324,8 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
if (!op->addr.nbytes)
ret = aspeed_spi_read_reg(chip, op);
else
- ret = aspeed_spi_read_user(chip, op, op->addr.val,
- op->data.nbytes, op->data.buf.in);
+ memcpy_fromio(op->data.buf.in, chip->ahb_base + op->addr.val,
+ op->data.nbytes);
} else {
if (!op->addr.nbytes)
ret = aspeed_spi_write_reg(chip, op);
@@ -405,10 +405,73 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
return chip->ahb_window_size ? 0 : -1;
}
+static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
+ struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ u32 ctl_val;
+ int ret = 0;
+
+ chip->clk_freq = desc->mem->spi->max_speed_hz;
+
+ /* Only for reads */
+ if (op->data.dir != SPI_MEM_DATA_IN)
+ return -EOPNOTSUPP;
+
+ if (desc->info.length > chip->ahb_window_size)
+ dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
+ chip->cs, chip->ahb_window_size >> 20);
+
+ /* Define the default IO read settings */
+ ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
+ ctl_val |= aspeed_spi_get_io_mode(op) |
+ op->cmd.opcode << CTRL_COMMAND_SHIFT |
+ CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth) |
+ CTRL_IO_MODE_READ;
+
+ /* Tune 4BYTE address mode */
+ if (op->addr.nbytes) {
+ u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
+
+ if (op->addr.nbytes == 4)
+ addr_mode |= (0x11 << chip->cs);
+ else
+ addr_mode &= ~(0x11 << chip->cs);
+ writel(addr_mode, aspi->regs + CE_CTRL_REG);
+ }
+
+ /* READ mode is the controller default setting */
+ chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+
+ dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
+ chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
+
+ return ret;
+}
+
+static int aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offset, size_t len, void *buf)
+{
+ struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
+ struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
+
+ /* Switch to USER command mode if mapping window is too small */
+ if (chip->ahb_window_size < offset + len)
+ aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
+ else
+ memcpy_fromio(buf, chip->ahb_base + offset, len);
+
+ return len;
+}
+
static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
.supports_op = aspeed_spi_supports_op,
.exec_op = aspeed_spi_exec_op,
.get_name = aspeed_spi_get_name,
+ .dirmap_create = aspeed_spi_dirmap_create,
+ .dirmap_read = aspeed_spi_dirmap_read,
};
static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 06/10] spi: aspeed: Adjust direct mapping to device size
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
The segment registers of the FMC/SPI controllers provide a way to
configure the mapping window of the flash device contents on the AHB
bus. Adjust this window to the size of the spi-mem mapping.
Things get more complex with multiple devices. The driver needs to
also adjust the window of the next device to make sure that there is
no overlap, even if there is no available device. The proposal below
is not perfect but it is covering all the cases we have seen on
different boards with one and two devices on the same bus.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 88 ++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index b4854b521477..974ab215ec34 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -405,6 +405,92 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
return chip->ahb_window_size ? 0 : -1;
}
+static int aspeed_spi_set_window(struct aspeed_spi *aspi,
+ const struct aspeed_spi_window *win)
+{
+ u32 start = aspi->ahb_base_phy + win->offset;
+ u32 end = start + win->size;
+ void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
+ u32 seg_val_backup = readl(seg_reg);
+ u32 seg_val = aspi->data->segment_reg(aspi, start, end);
+
+ if (seg_val == seg_val_backup)
+ return 0;
+
+ writel(seg_val, seg_reg);
+
+ /*
+ * Restore initial value if something goes wrong else we could
+ * loose access to the chip.
+ */
+ if (seg_val != readl(seg_reg)) {
+ dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
+ win->cs, start, end - 1, win->size >> 20);
+ writel(seg_val_backup, seg_reg);
+ return -EIO;
+ }
+
+ if (win->size)
+ dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
+ win->cs, start, end - 1, win->size >> 20);
+ else
+ dev_dbg(aspi->dev, "CE%d window closed", win->cs);
+
+ return 0;
+}
+
+/*
+ * Yet to be done when possible :
+ * - Align mappings on flash size (we don't have the info)
+ * - ioremap each window, not strictly necessary since the overall window
+ * is correct.
+ */
+static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
+ u32 local_offset, u32 size)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
+ struct aspeed_spi_window *win = &windows[chip->cs];
+ int ret;
+
+ aspeed_spi_get_windows(aspi, windows);
+
+ /* Adjust this chip window */
+ win->offset += local_offset;
+ win->size = size;
+
+ if (win->offset + win->size > aspi->ahb_window_size) {
+ win->size = aspi->ahb_window_size - win->offset;
+ dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
+ }
+
+ ret = aspeed_spi_set_window(aspi, win);
+ if (ret)
+ return ret;
+
+ /* Update chip mapping info */
+ chip->ahb_base = aspi->ahb_base + win->offset;
+ chip->ahb_window_size = win->size;
+
+ /*
+ * Also adjust next chip window to make sure that it does not
+ * overlap with the current window.
+ */
+ if (chip->cs < aspi->data->max_cs - 1) {
+ struct aspeed_spi_window *next = &windows[chip->cs + 1];
+
+ /* Change offset and size to keep the same end address */
+ if ((next->offset + next->size) > (win->offset + win->size))
+ next->size = (next->offset + next->size) - (win->offset + win->size);
+ else
+ next->size = 0;
+ next->offset = win->offset + win->size;
+
+ aspeed_spi_set_window(aspi, next);
+ }
+ return 0;
+}
+
static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
@@ -419,6 +505,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
if (op->data.dir != SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
+ aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
+
if (desc->info.length > chip->ahb_window_size)
dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
chip->cs, chip->ahb_window_size >> 20);
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 06/10] spi: aspeed: Adjust direct mapping to device size
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
The segment registers of the FMC/SPI controllers provide a way to
configure the mapping window of the flash device contents on the AHB
bus. Adjust this window to the size of the spi-mem mapping.
Things get more complex with multiple devices. The driver needs to
also adjust the window of the next device to make sure that there is
no overlap, even if there is no available device. The proposal below
is not perfect but it is covering all the cases we have seen on
different boards with one and two devices on the same bus.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 88 ++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index b4854b521477..974ab215ec34 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -405,6 +405,92 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
return chip->ahb_window_size ? 0 : -1;
}
+static int aspeed_spi_set_window(struct aspeed_spi *aspi,
+ const struct aspeed_spi_window *win)
+{
+ u32 start = aspi->ahb_base_phy + win->offset;
+ u32 end = start + win->size;
+ void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
+ u32 seg_val_backup = readl(seg_reg);
+ u32 seg_val = aspi->data->segment_reg(aspi, start, end);
+
+ if (seg_val == seg_val_backup)
+ return 0;
+
+ writel(seg_val, seg_reg);
+
+ /*
+ * Restore initial value if something goes wrong else we could
+ * loose access to the chip.
+ */
+ if (seg_val != readl(seg_reg)) {
+ dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
+ win->cs, start, end - 1, win->size >> 20);
+ writel(seg_val_backup, seg_reg);
+ return -EIO;
+ }
+
+ if (win->size)
+ dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
+ win->cs, start, end - 1, win->size >> 20);
+ else
+ dev_dbg(aspi->dev, "CE%d window closed", win->cs);
+
+ return 0;
+}
+
+/*
+ * Yet to be done when possible :
+ * - Align mappings on flash size (we don't have the info)
+ * - ioremap each window, not strictly necessary since the overall window
+ * is correct.
+ */
+static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
+ u32 local_offset, u32 size)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
+ struct aspeed_spi_window *win = &windows[chip->cs];
+ int ret;
+
+ aspeed_spi_get_windows(aspi, windows);
+
+ /* Adjust this chip window */
+ win->offset += local_offset;
+ win->size = size;
+
+ if (win->offset + win->size > aspi->ahb_window_size) {
+ win->size = aspi->ahb_window_size - win->offset;
+ dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
+ }
+
+ ret = aspeed_spi_set_window(aspi, win);
+ if (ret)
+ return ret;
+
+ /* Update chip mapping info */
+ chip->ahb_base = aspi->ahb_base + win->offset;
+ chip->ahb_window_size = win->size;
+
+ /*
+ * Also adjust next chip window to make sure that it does not
+ * overlap with the current window.
+ */
+ if (chip->cs < aspi->data->max_cs - 1) {
+ struct aspeed_spi_window *next = &windows[chip->cs + 1];
+
+ /* Change offset and size to keep the same end address */
+ if ((next->offset + next->size) > (win->offset + win->size))
+ next->size = (next->offset + next->size) - (win->offset + win->size);
+ else
+ next->size = 0;
+ next->offset = win->offset + win->size;
+
+ aspeed_spi_set_window(aspi, next);
+ }
+ return 0;
+}
+
static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
@@ -419,6 +505,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
if (op->data.dir != SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
+ aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
+
if (desc->info.length > chip->ahb_window_size)
dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
chip->cs, chip->ahb_window_size >> 20);
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 06/10] spi: aspeed: Adjust direct mapping to device size
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
The segment registers of the FMC/SPI controllers provide a way to
configure the mapping window of the flash device contents on the AHB
bus. Adjust this window to the size of the spi-mem mapping.
Things get more complex with multiple devices. The driver needs to
also adjust the window of the next device to make sure that there is
no overlap, even if there is no available device. The proposal below
is not perfect but it is covering all the cases we have seen on
different boards with one and two devices on the same bus.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 88 ++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index b4854b521477..974ab215ec34 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -405,6 +405,92 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
return chip->ahb_window_size ? 0 : -1;
}
+static int aspeed_spi_set_window(struct aspeed_spi *aspi,
+ const struct aspeed_spi_window *win)
+{
+ u32 start = aspi->ahb_base_phy + win->offset;
+ u32 end = start + win->size;
+ void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
+ u32 seg_val_backup = readl(seg_reg);
+ u32 seg_val = aspi->data->segment_reg(aspi, start, end);
+
+ if (seg_val == seg_val_backup)
+ return 0;
+
+ writel(seg_val, seg_reg);
+
+ /*
+ * Restore initial value if something goes wrong else we could
+ * loose access to the chip.
+ */
+ if (seg_val != readl(seg_reg)) {
+ dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
+ win->cs, start, end - 1, win->size >> 20);
+ writel(seg_val_backup, seg_reg);
+ return -EIO;
+ }
+
+ if (win->size)
+ dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
+ win->cs, start, end - 1, win->size >> 20);
+ else
+ dev_dbg(aspi->dev, "CE%d window closed", win->cs);
+
+ return 0;
+}
+
+/*
+ * Yet to be done when possible :
+ * - Align mappings on flash size (we don't have the info)
+ * - ioremap each window, not strictly necessary since the overall window
+ * is correct.
+ */
+static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
+ u32 local_offset, u32 size)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
+ struct aspeed_spi_window *win = &windows[chip->cs];
+ int ret;
+
+ aspeed_spi_get_windows(aspi, windows);
+
+ /* Adjust this chip window */
+ win->offset += local_offset;
+ win->size = size;
+
+ if (win->offset + win->size > aspi->ahb_window_size) {
+ win->size = aspi->ahb_window_size - win->offset;
+ dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
+ }
+
+ ret = aspeed_spi_set_window(aspi, win);
+ if (ret)
+ return ret;
+
+ /* Update chip mapping info */
+ chip->ahb_base = aspi->ahb_base + win->offset;
+ chip->ahb_window_size = win->size;
+
+ /*
+ * Also adjust next chip window to make sure that it does not
+ * overlap with the current window.
+ */
+ if (chip->cs < aspi->data->max_cs - 1) {
+ struct aspeed_spi_window *next = &windows[chip->cs + 1];
+
+ /* Change offset and size to keep the same end address */
+ if ((next->offset + next->size) > (win->offset + win->size))
+ next->size = (next->offset + next->size) - (win->offset + win->size);
+ else
+ next->size = 0;
+ next->offset = win->offset + win->size;
+
+ aspeed_spi_set_window(aspi, next);
+ }
+ return 0;
+}
+
static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
@@ -419,6 +505,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
if (op->data.dir != SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
+ aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
+
if (desc->info.length > chip->ahb_window_size)
dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
chip->cs, chip->ahb_window_size >> 20);
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 07/10] spi: aspeed: Workaround AST2500 limitations
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
It is not possible to configure a full 128MB window for a chip of the
same size on the AST2500 SPI controller. For his case, the maximum
window size is restricted to 120MB for CE0.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 974ab215ec34..e133984d3c95 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -445,6 +445,8 @@ static int aspeed_spi_set_window(struct aspeed_spi *aspi,
* - ioremap each window, not strictly necessary since the overall window
* is correct.
*/
+static const struct aspeed_spi_data ast2500_spi_data;
+
static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
u32 local_offset, u32 size)
{
@@ -453,6 +455,16 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
struct aspeed_spi_window *win = &windows[chip->cs];
int ret;
+ /*
+ * Due to an HW issue on the AST2500 SPI controller, the CE0
+ * window size should be smaller than the maximum 128MB.
+ */
+ if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
+ size = 120 << 20;
+ dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
+ chip->cs, size >> 20);
+ }
+
aspeed_spi_get_windows(aspi, windows);
/* Adjust this chip window */
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 07/10] spi: aspeed: Workaround AST2500 limitations
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
It is not possible to configure a full 128MB window for a chip of the
same size on the AST2500 SPI controller. For his case, the maximum
window size is restricted to 120MB for CE0.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 974ab215ec34..e133984d3c95 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -445,6 +445,8 @@ static int aspeed_spi_set_window(struct aspeed_spi *aspi,
* - ioremap each window, not strictly necessary since the overall window
* is correct.
*/
+static const struct aspeed_spi_data ast2500_spi_data;
+
static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
u32 local_offset, u32 size)
{
@@ -453,6 +455,16 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
struct aspeed_spi_window *win = &windows[chip->cs];
int ret;
+ /*
+ * Due to an HW issue on the AST2500 SPI controller, the CE0
+ * window size should be smaller than the maximum 128MB.
+ */
+ if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
+ size = 120 << 20;
+ dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
+ chip->cs, size >> 20);
+ }
+
aspeed_spi_get_windows(aspi, windows);
/* Adjust this chip window */
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 07/10] spi: aspeed: Workaround AST2500 limitations
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
It is not possible to configure a full 128MB window for a chip of the
same size on the AST2500 SPI controller. For his case, the maximum
window size is restricted to 120MB for CE0.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 974ab215ec34..e133984d3c95 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -445,6 +445,8 @@ static int aspeed_spi_set_window(struct aspeed_spi *aspi,
* - ioremap each window, not strictly necessary since the overall window
* is correct.
*/
+static const struct aspeed_spi_data ast2500_spi_data;
+
static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
u32 local_offset, u32 size)
{
@@ -453,6 +455,16 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
struct aspeed_spi_window *win = &windows[chip->cs];
int ret;
+ /*
+ * Due to an HW issue on the AST2500 SPI controller, the CE0
+ * window size should be smaller than the maximum 128MB.
+ */
+ if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
+ size = 120 << 20;
+ dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
+ chip->cs, size >> 20);
+ }
+
aspeed_spi_get_windows(aspi, windows);
/* Adjust this chip window */
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 08/10] spi: aspeed: Add support for the AST2400 SPI controller
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
Extend the driver for the AST2400 SPI Flash Controller (SPI). This
controller has a slightly different interface which requires
adaptation of the 4B handling. Summary of features :
. host Firmware
. 1 chip select pin (CE0)
. slightly different register set, between AST2500 and the legacy
controller
. no segment registers
. single, dual mode.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index e133984d3c95..8c6d7f79d97f 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -32,6 +32,7 @@
#define CTRL_IO_DUAL_DATA BIT(29)
#define CTRL_IO_QUAD_DATA BIT(30)
#define CTRL_COMMAND_SHIFT 16
+#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
#define CTRL_IO_DUMMY_SET(dummy) \
(((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
#define CTRL_CE_STOP_ACTIVE BIT(2)
@@ -272,6 +273,8 @@ static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op
return spi_mem_default_supports_op(mem, op);
}
+static const struct aspeed_spi_data ast2400_spi_data;
+
static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
@@ -301,6 +304,9 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
addr_mode |= (0x11 << chip->cs);
else
addr_mode &= ~(0x11 << chip->cs);
+
+ if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
+ ctl_val |= CTRL_IO_ADDRESS_4B;
}
if (op->dummy.buswidth && op->dummy.nbytes)
@@ -392,7 +398,13 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
struct aspeed_spi_window *win = &windows[chip->cs];
- aspeed_spi_get_windows(aspi, windows);
+ /* No segment registers for the AST2400 SPI controller */
+ if (aspi->data == &ast2400_spi_data) {
+ win->offset = 0;
+ win->size = aspi->ahb_window_size;
+ } else {
+ aspeed_spi_get_windows(aspi, windows);
+ }
chip->ahb_base = aspi->ahb_base + win->offset;
chip->ahb_window_size = win->size;
@@ -455,6 +467,10 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
struct aspeed_spi_window *win = &windows[chip->cs];
int ret;
+ /* No segment registers for the AST2400 SPI controller */
+ if (aspi->data == &ast2400_spi_data)
+ return 0;
+
/*
* Due to an HW issue on the AST2500 SPI controller, the CE0
* window size should be smaller than the maximum 128MB.
@@ -539,6 +555,12 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
else
addr_mode &= ~(0x11 << chip->cs);
writel(addr_mode, aspi->regs + CE_CTRL_REG);
+
+ /* AST2400 SPI controller sets 4BYTE address mode in
+ * CE0 Control Register
+ */
+ if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
+ ctl_val |= CTRL_IO_ADDRESS_4B;
}
/* READ mode is the controller default setting */
@@ -805,6 +827,14 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
.segment_reg = aspeed_spi_segment_reg,
};
+static const struct aspeed_spi_data ast2400_spi_data = {
+ .max_cs = 1,
+ .hastype = false,
+ .we0 = 0,
+ .ctl0 = 0x04,
+ /* No segment registers */
+};
+
static const struct aspeed_spi_data ast2500_fmc_data = {
.max_cs = 3,
.hastype = true,
@@ -849,6 +879,7 @@ static const struct aspeed_spi_data ast2600_spi_data = {
static const struct of_device_id aspeed_spi_matches[] = {
{ .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
+ { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
{ .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
{ .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
{ .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 08/10] spi: aspeed: Add support for the AST2400 SPI controller
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
Extend the driver for the AST2400 SPI Flash Controller (SPI). This
controller has a slightly different interface which requires
adaptation of the 4B handling. Summary of features :
. host Firmware
. 1 chip select pin (CE0)
. slightly different register set, between AST2500 and the legacy
controller
. no segment registers
. single, dual mode.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index e133984d3c95..8c6d7f79d97f 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -32,6 +32,7 @@
#define CTRL_IO_DUAL_DATA BIT(29)
#define CTRL_IO_QUAD_DATA BIT(30)
#define CTRL_COMMAND_SHIFT 16
+#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
#define CTRL_IO_DUMMY_SET(dummy) \
(((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
#define CTRL_CE_STOP_ACTIVE BIT(2)
@@ -272,6 +273,8 @@ static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op
return spi_mem_default_supports_op(mem, op);
}
+static const struct aspeed_spi_data ast2400_spi_data;
+
static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
@@ -301,6 +304,9 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
addr_mode |= (0x11 << chip->cs);
else
addr_mode &= ~(0x11 << chip->cs);
+
+ if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
+ ctl_val |= CTRL_IO_ADDRESS_4B;
}
if (op->dummy.buswidth && op->dummy.nbytes)
@@ -392,7 +398,13 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
struct aspeed_spi_window *win = &windows[chip->cs];
- aspeed_spi_get_windows(aspi, windows);
+ /* No segment registers for the AST2400 SPI controller */
+ if (aspi->data == &ast2400_spi_data) {
+ win->offset = 0;
+ win->size = aspi->ahb_window_size;
+ } else {
+ aspeed_spi_get_windows(aspi, windows);
+ }
chip->ahb_base = aspi->ahb_base + win->offset;
chip->ahb_window_size = win->size;
@@ -455,6 +467,10 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
struct aspeed_spi_window *win = &windows[chip->cs];
int ret;
+ /* No segment registers for the AST2400 SPI controller */
+ if (aspi->data == &ast2400_spi_data)
+ return 0;
+
/*
* Due to an HW issue on the AST2500 SPI controller, the CE0
* window size should be smaller than the maximum 128MB.
@@ -539,6 +555,12 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
else
addr_mode &= ~(0x11 << chip->cs);
writel(addr_mode, aspi->regs + CE_CTRL_REG);
+
+ /* AST2400 SPI controller sets 4BYTE address mode in
+ * CE0 Control Register
+ */
+ if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
+ ctl_val |= CTRL_IO_ADDRESS_4B;
}
/* READ mode is the controller default setting */
@@ -805,6 +827,14 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
.segment_reg = aspeed_spi_segment_reg,
};
+static const struct aspeed_spi_data ast2400_spi_data = {
+ .max_cs = 1,
+ .hastype = false,
+ .we0 = 0,
+ .ctl0 = 0x04,
+ /* No segment registers */
+};
+
static const struct aspeed_spi_data ast2500_fmc_data = {
.max_cs = 3,
.hastype = true,
@@ -849,6 +879,7 @@ static const struct aspeed_spi_data ast2600_spi_data = {
static const struct of_device_id aspeed_spi_matches[] = {
{ .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
+ { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
{ .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
{ .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
{ .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 08/10] spi: aspeed: Add support for the AST2400 SPI controller
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
Extend the driver for the AST2400 SPI Flash Controller (SPI). This
controller has a slightly different interface which requires
adaptation of the 4B handling. Summary of features :
. host Firmware
. 1 chip select pin (CE0)
. slightly different register set, between AST2500 and the legacy
controller
. no segment registers
. single, dual mode.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index e133984d3c95..8c6d7f79d97f 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -32,6 +32,7 @@
#define CTRL_IO_DUAL_DATA BIT(29)
#define CTRL_IO_QUAD_DATA BIT(30)
#define CTRL_COMMAND_SHIFT 16
+#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
#define CTRL_IO_DUMMY_SET(dummy) \
(((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
#define CTRL_CE_STOP_ACTIVE BIT(2)
@@ -272,6 +273,8 @@ static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op
return spi_mem_default_supports_op(mem, op);
}
+static const struct aspeed_spi_data ast2400_spi_data;
+
static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
@@ -301,6 +304,9 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
addr_mode |= (0x11 << chip->cs);
else
addr_mode &= ~(0x11 << chip->cs);
+
+ if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
+ ctl_val |= CTRL_IO_ADDRESS_4B;
}
if (op->dummy.buswidth && op->dummy.nbytes)
@@ -392,7 +398,13 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
struct aspeed_spi_window *win = &windows[chip->cs];
- aspeed_spi_get_windows(aspi, windows);
+ /* No segment registers for the AST2400 SPI controller */
+ if (aspi->data == &ast2400_spi_data) {
+ win->offset = 0;
+ win->size = aspi->ahb_window_size;
+ } else {
+ aspeed_spi_get_windows(aspi, windows);
+ }
chip->ahb_base = aspi->ahb_base + win->offset;
chip->ahb_window_size = win->size;
@@ -455,6 +467,10 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
struct aspeed_spi_window *win = &windows[chip->cs];
int ret;
+ /* No segment registers for the AST2400 SPI controller */
+ if (aspi->data == &ast2400_spi_data)
+ return 0;
+
/*
* Due to an HW issue on the AST2500 SPI controller, the CE0
* window size should be smaller than the maximum 128MB.
@@ -539,6 +555,12 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
else
addr_mode &= ~(0x11 << chip->cs);
writel(addr_mode, aspi->regs + CE_CTRL_REG);
+
+ /* AST2400 SPI controller sets 4BYTE address mode in
+ * CE0 Control Register
+ */
+ if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
+ ctl_val |= CTRL_IO_ADDRESS_4B;
}
/* READ mode is the controller default setting */
@@ -805,6 +827,14 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
.segment_reg = aspeed_spi_segment_reg,
};
+static const struct aspeed_spi_data ast2400_spi_data = {
+ .max_cs = 1,
+ .hastype = false,
+ .we0 = 0,
+ .ctl0 = 0x04,
+ /* No segment registers */
+};
+
static const struct aspeed_spi_data ast2500_fmc_data = {
.max_cs = 3,
.hastype = true,
@@ -849,6 +879,7 @@ static const struct aspeed_spi_data ast2600_spi_data = {
static const struct of_device_id aspeed_spi_matches[] = {
{ .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
+ { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
{ .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
{ .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
{ .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 09/10] spi: aspeed: Calibrate read timings
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
To accommodate the different response time of SPI transfers on different
boards and different SPI NOR devices, the Aspeed controllers provide a
set of Read Timing Compensation registers to tune the timing delays
depending on the frequency being used. The AST2600 SoC has one of
these registers per device. On the AST2500 and AST2400 SoCs, the
timing register is shared by all devices which is a bit problematic to
get good results other than for one device.
The algorithm first reads a golden buffer at low speed and then performs
reads with different clocks and delay cycle settings to find a breaking
point. This selects a default good frequency for the CEx control register.
The current settings are bit optimistic as we pick the first delay giving
good results. A safer approach would be to determine an interval and
choose the middle value.
Calibration is performed when the direct mapping for reads is created.
Since the underlying spi-nor object needs to be initialized to create
the spi_mem operation for direct mapping, we should be fine. Having a
specific API would clarify the requirements though.
Cc: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 281 +++++++++++++++++++++++++++++++++++
1 file changed, 281 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 8c6d7f79d97f..dce25dfe6913 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -35,6 +35,8 @@
#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
#define CTRL_IO_DUMMY_SET(dummy) \
(((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
+#define CTRL_FREQ_SEL_SHIFT 8
+#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
#define CTRL_CE_STOP_ACTIVE BIT(2)
#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
#define CTRL_IO_MODE_NORMAL 0x0
@@ -47,6 +49,9 @@
/* CEx Address Decoding Range Register */
#define CE0_SEGMENT_ADDR_REG 0x30
+/* CEx Read timing compensation register */
+#define CE0_TIMING_COMPENSATION_REG 0x94
+
enum aspeed_spi_ctl_reg_value {
ASPEED_SPI_BASE,
ASPEED_SPI_READ,
@@ -72,10 +77,15 @@ struct aspeed_spi_data {
bool hastype;
u32 mode_bits;
u32 we0;
+ u32 timing;
+ u32 hclk_mask;
+ u32 hdiv_max;
u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
+ int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf);
};
#define ASPEED_SPI_MAX_NUM_CS 5
@@ -519,6 +529,8 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
return 0;
}
+static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
+
static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
@@ -567,6 +579,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+ ret = aspeed_spi_do_calibration(chip);
+
dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
@@ -814,6 +828,249 @@ static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
((end - 1) & AST2600_SEG_ADDR_MASK);
}
+/*
+ * Read timing compensation sequences
+ */
+
+#define CALIBRATE_BUF_SIZE SZ_16K
+
+static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
+ if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
+#if defined(VERBOSE_DEBUG)
+ print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
+ test_buf, 0x100);
+#endif
+ return false;
+ }
+ }
+ return true;
+}
+
+#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
+
+/*
+ * The timing register is shared by all devices. Only update for CE0.
+ */
+static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ const struct aspeed_spi_data *data = aspi->data;
+ int i;
+ int good_pass = -1, pass_count = 0;
+ u32 shift = (hdiv - 1) << 2;
+ u32 mask = ~(0xfu << shift);
+ u32 fread_timing_val = 0;
+
+ /* Try HCLK delay 0..5, each one with/without delay and look for a
+ * good pair.
+ */
+ for (i = 0; i < 12; i++) {
+ bool pass;
+
+ if (chip->cs == 0) {
+ fread_timing_val &= mask;
+ fread_timing_val |= FREAD_TPASS(i) << shift;
+ writel(fread_timing_val, aspi->regs + data->timing);
+ }
+ pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(aspi->dev,
+ " * [%08x] %d HCLK delay, %dns DI delay : %s",
+ fread_timing_val, i / 2, (i & 1) ? 0 : 4,
+ pass ? "PASS" : "FAIL");
+ if (pass) {
+ pass_count++;
+ if (pass_count == 3) {
+ good_pass = i - 1;
+ break;
+ }
+ } else {
+ pass_count = 0;
+ }
+ }
+
+ /* No good setting for this frequency */
+ if (good_pass < 0)
+ return -1;
+
+ /* We have at least one pass of margin, let's use first pass */
+ if (chip->cs == 0) {
+ fread_timing_val &= mask;
+ fread_timing_val |= FREAD_TPASS(good_pass) << shift;
+ writel(fread_timing_val, aspi->regs + data->timing);
+ }
+ dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
+ good_pass, fread_timing_val);
+ return 0;
+}
+
+static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
+{
+ const u32 *tb32 = (const u32 *)test_buf;
+ u32 i, cnt = 0;
+
+ /* We check if we have enough words that are neither all 0
+ * nor all 1's so the calibration can be considered valid.
+ *
+ * I use an arbitrary threshold for now of 64
+ */
+ size >>= 2;
+ for (i = 0; i < size; i++) {
+ if (tb32[i] != 0 && tb32[i] != 0xffffffff)
+ cnt++;
+ }
+ return cnt >= 64;
+}
+
+static const u32 aspeed_spi_hclk_divs[] = {
+ 0xf, /* HCLK */
+ 0x7, /* HCLK/2 */
+ 0xe, /* HCLK/3 */
+ 0x6, /* HCLK/4 */
+ 0xd, /* HCLK/5 */
+};
+
+#define ASPEED_SPI_HCLK_DIV(i) \
+ (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
+
+static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ const struct aspeed_spi_data *data = aspi->data;
+ u32 ahb_freq = aspi->clk_freq;
+ u32 max_freq = chip->clk_freq;
+ u32 ctl_val;
+ u8 *golden_buf = NULL;
+ u8 *test_buf = NULL;
+ int i, rc, best_div = -1;
+
+ dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
+ ahb_freq / 1000000);
+
+ /*
+ * use the related low frequency to get check calibration data
+ * and get golden data.
+ */
+ ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
+ writel(ctl_val, chip->ctl);
+
+ test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
+ if (!test_buf)
+ return -ENOMEM;
+
+ golden_buf = test_buf + CALIBRATE_BUF_SIZE;
+
+ memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
+ if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
+ dev_info(aspi->dev, "Calibration area too uniform, using low speed");
+ goto no_calib;
+ }
+
+#if defined(VERBOSE_DEBUG)
+ print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
+ golden_buf, 0x100);
+#endif
+
+ /* Now we iterate the HCLK dividers until we find our breaking point */
+ for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
+ u32 tv, freq;
+
+ freq = ahb_freq / i;
+ if (freq > max_freq)
+ continue;
+
+ /* Set the timing */
+ tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
+ writel(tv, chip->ctl);
+ dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
+ rc = data->calibrate(chip, i, golden_buf, test_buf);
+ if (rc == 0)
+ best_div = i;
+ }
+
+ /* Nothing found ? */
+ if (best_div < 0) {
+ dev_warn(aspi->dev, "No good frequency, using dumb slow");
+ } else {
+ dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
+
+ /* Record the freq */
+ for (i = 0; i < ASPEED_SPI_MAX; i++)
+ chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
+ ASPEED_SPI_HCLK_DIV(best_div);
+ }
+
+no_calib:
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+ kfree(test_buf);
+ return 0;
+}
+
+#define TIMING_DELAY_DI BIT(3)
+#define TIMING_DELAY_HCYCLE_MAX 5
+#define TIMING_REG_AST2600(chip) \
+ ((chip)->aspi->regs + (chip)->aspi->data->timing + \
+ (chip)->cs * 4)
+
+static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ int hcycle;
+ u32 shift = (hdiv - 2) << 3;
+ u32 mask = ~(0xfu << shift);
+ u32 fread_timing_val = 0;
+
+ for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
+ int delay_ns;
+ bool pass = false;
+
+ fread_timing_val &= mask;
+ fread_timing_val |= hcycle << shift;
+
+ /* no DI input delay first */
+ writel(fread_timing_val, TIMING_REG_AST2600(chip));
+ pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(aspi->dev,
+ " * [%08x] %d HCLK delay, DI delay none : %s",
+ fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
+ if (pass)
+ return 0;
+
+ /* Add DI input delays */
+ fread_timing_val &= mask;
+ fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
+
+ for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
+ fread_timing_val &= ~(0xf << (4 + shift));
+ fread_timing_val |= delay_ns << (4 + shift);
+
+ writel(fread_timing_val, TIMING_REG_AST2600(chip));
+ pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(aspi->dev,
+ " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
+ fread_timing_val, hcycle, (delay_ns + 1) / 2,
+ (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
+ /*
+ * TODO: This is optimistic. We should look
+ * for a working interval and save the middle
+ * value in the read timing register.
+ */
+ if (pass)
+ return 0;
+ }
+ }
+
+ /* No good setting for this frequency */
+ return -1;
+}
+
/*
* Platform definitions
*/
@@ -822,6 +1079,10 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
.hastype = true,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
.segment_start = aspeed_spi_segment_start,
.segment_end = aspeed_spi_segment_end,
.segment_reg = aspeed_spi_segment_reg,
@@ -832,6 +1093,10 @@ static const struct aspeed_spi_data ast2400_spi_data = {
.hastype = false,
.we0 = 0,
.ctl0 = 0x04,
+ .timing = 0x14,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
/* No segment registers */
};
@@ -840,6 +1105,10 @@ static const struct aspeed_spi_data ast2500_fmc_data = {
.hastype = true,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
.segment_start = aspeed_spi_segment_start,
.segment_end = aspeed_spi_segment_end,
.segment_reg = aspeed_spi_segment_reg,
@@ -850,6 +1119,10 @@ static const struct aspeed_spi_data ast2500_spi_data = {
.hastype = false,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
.segment_start = aspeed_spi_segment_start,
.segment_end = aspeed_spi_segment_end,
.segment_reg = aspeed_spi_segment_reg,
@@ -861,6 +1134,10 @@ static const struct aspeed_spi_data ast2600_fmc_data = {
.mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xf0fff0ff,
+ .hdiv_max = 2,
+ .calibrate = aspeed_spi_ast2600_calibrate,
.segment_start = aspeed_spi_segment_ast2600_start,
.segment_end = aspeed_spi_segment_ast2600_end,
.segment_reg = aspeed_spi_segment_ast2600_reg,
@@ -872,6 +1149,10 @@ static const struct aspeed_spi_data ast2600_spi_data = {
.mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xf0fff0ff,
+ .hdiv_max = 2,
+ .calibrate = aspeed_spi_ast2600_calibrate,
.segment_start = aspeed_spi_segment_ast2600_start,
.segment_end = aspeed_spi_segment_ast2600_end,
.segment_reg = aspeed_spi_segment_ast2600_reg,
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 09/10] spi: aspeed: Calibrate read timings
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
To accommodate the different response time of SPI transfers on different
boards and different SPI NOR devices, the Aspeed controllers provide a
set of Read Timing Compensation registers to tune the timing delays
depending on the frequency being used. The AST2600 SoC has one of
these registers per device. On the AST2500 and AST2400 SoCs, the
timing register is shared by all devices which is a bit problematic to
get good results other than for one device.
The algorithm first reads a golden buffer at low speed and then performs
reads with different clocks and delay cycle settings to find a breaking
point. This selects a default good frequency for the CEx control register.
The current settings are bit optimistic as we pick the first delay giving
good results. A safer approach would be to determine an interval and
choose the middle value.
Calibration is performed when the direct mapping for reads is created.
Since the underlying spi-nor object needs to be initialized to create
the spi_mem operation for direct mapping, we should be fine. Having a
specific API would clarify the requirements though.
Cc: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 281 +++++++++++++++++++++++++++++++++++
1 file changed, 281 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 8c6d7f79d97f..dce25dfe6913 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -35,6 +35,8 @@
#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
#define CTRL_IO_DUMMY_SET(dummy) \
(((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
+#define CTRL_FREQ_SEL_SHIFT 8
+#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
#define CTRL_CE_STOP_ACTIVE BIT(2)
#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
#define CTRL_IO_MODE_NORMAL 0x0
@@ -47,6 +49,9 @@
/* CEx Address Decoding Range Register */
#define CE0_SEGMENT_ADDR_REG 0x30
+/* CEx Read timing compensation register */
+#define CE0_TIMING_COMPENSATION_REG 0x94
+
enum aspeed_spi_ctl_reg_value {
ASPEED_SPI_BASE,
ASPEED_SPI_READ,
@@ -72,10 +77,15 @@ struct aspeed_spi_data {
bool hastype;
u32 mode_bits;
u32 we0;
+ u32 timing;
+ u32 hclk_mask;
+ u32 hdiv_max;
u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
+ int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf);
};
#define ASPEED_SPI_MAX_NUM_CS 5
@@ -519,6 +529,8 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
return 0;
}
+static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
+
static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
@@ -567,6 +579,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+ ret = aspeed_spi_do_calibration(chip);
+
dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
@@ -814,6 +828,249 @@ static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
((end - 1) & AST2600_SEG_ADDR_MASK);
}
+/*
+ * Read timing compensation sequences
+ */
+
+#define CALIBRATE_BUF_SIZE SZ_16K
+
+static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
+ if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
+#if defined(VERBOSE_DEBUG)
+ print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
+ test_buf, 0x100);
+#endif
+ return false;
+ }
+ }
+ return true;
+}
+
+#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
+
+/*
+ * The timing register is shared by all devices. Only update for CE0.
+ */
+static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ const struct aspeed_spi_data *data = aspi->data;
+ int i;
+ int good_pass = -1, pass_count = 0;
+ u32 shift = (hdiv - 1) << 2;
+ u32 mask = ~(0xfu << shift);
+ u32 fread_timing_val = 0;
+
+ /* Try HCLK delay 0..5, each one with/without delay and look for a
+ * good pair.
+ */
+ for (i = 0; i < 12; i++) {
+ bool pass;
+
+ if (chip->cs == 0) {
+ fread_timing_val &= mask;
+ fread_timing_val |= FREAD_TPASS(i) << shift;
+ writel(fread_timing_val, aspi->regs + data->timing);
+ }
+ pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(aspi->dev,
+ " * [%08x] %d HCLK delay, %dns DI delay : %s",
+ fread_timing_val, i / 2, (i & 1) ? 0 : 4,
+ pass ? "PASS" : "FAIL");
+ if (pass) {
+ pass_count++;
+ if (pass_count == 3) {
+ good_pass = i - 1;
+ break;
+ }
+ } else {
+ pass_count = 0;
+ }
+ }
+
+ /* No good setting for this frequency */
+ if (good_pass < 0)
+ return -1;
+
+ /* We have at least one pass of margin, let's use first pass */
+ if (chip->cs == 0) {
+ fread_timing_val &= mask;
+ fread_timing_val |= FREAD_TPASS(good_pass) << shift;
+ writel(fread_timing_val, aspi->regs + data->timing);
+ }
+ dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
+ good_pass, fread_timing_val);
+ return 0;
+}
+
+static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
+{
+ const u32 *tb32 = (const u32 *)test_buf;
+ u32 i, cnt = 0;
+
+ /* We check if we have enough words that are neither all 0
+ * nor all 1's so the calibration can be considered valid.
+ *
+ * I use an arbitrary threshold for now of 64
+ */
+ size >>= 2;
+ for (i = 0; i < size; i++) {
+ if (tb32[i] != 0 && tb32[i] != 0xffffffff)
+ cnt++;
+ }
+ return cnt >= 64;
+}
+
+static const u32 aspeed_spi_hclk_divs[] = {
+ 0xf, /* HCLK */
+ 0x7, /* HCLK/2 */
+ 0xe, /* HCLK/3 */
+ 0x6, /* HCLK/4 */
+ 0xd, /* HCLK/5 */
+};
+
+#define ASPEED_SPI_HCLK_DIV(i) \
+ (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
+
+static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ const struct aspeed_spi_data *data = aspi->data;
+ u32 ahb_freq = aspi->clk_freq;
+ u32 max_freq = chip->clk_freq;
+ u32 ctl_val;
+ u8 *golden_buf = NULL;
+ u8 *test_buf = NULL;
+ int i, rc, best_div = -1;
+
+ dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
+ ahb_freq / 1000000);
+
+ /*
+ * use the related low frequency to get check calibration data
+ * and get golden data.
+ */
+ ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
+ writel(ctl_val, chip->ctl);
+
+ test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
+ if (!test_buf)
+ return -ENOMEM;
+
+ golden_buf = test_buf + CALIBRATE_BUF_SIZE;
+
+ memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
+ if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
+ dev_info(aspi->dev, "Calibration area too uniform, using low speed");
+ goto no_calib;
+ }
+
+#if defined(VERBOSE_DEBUG)
+ print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
+ golden_buf, 0x100);
+#endif
+
+ /* Now we iterate the HCLK dividers until we find our breaking point */
+ for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
+ u32 tv, freq;
+
+ freq = ahb_freq / i;
+ if (freq > max_freq)
+ continue;
+
+ /* Set the timing */
+ tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
+ writel(tv, chip->ctl);
+ dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
+ rc = data->calibrate(chip, i, golden_buf, test_buf);
+ if (rc == 0)
+ best_div = i;
+ }
+
+ /* Nothing found ? */
+ if (best_div < 0) {
+ dev_warn(aspi->dev, "No good frequency, using dumb slow");
+ } else {
+ dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
+
+ /* Record the freq */
+ for (i = 0; i < ASPEED_SPI_MAX; i++)
+ chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
+ ASPEED_SPI_HCLK_DIV(best_div);
+ }
+
+no_calib:
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+ kfree(test_buf);
+ return 0;
+}
+
+#define TIMING_DELAY_DI BIT(3)
+#define TIMING_DELAY_HCYCLE_MAX 5
+#define TIMING_REG_AST2600(chip) \
+ ((chip)->aspi->regs + (chip)->aspi->data->timing + \
+ (chip)->cs * 4)
+
+static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ int hcycle;
+ u32 shift = (hdiv - 2) << 3;
+ u32 mask = ~(0xfu << shift);
+ u32 fread_timing_val = 0;
+
+ for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
+ int delay_ns;
+ bool pass = false;
+
+ fread_timing_val &= mask;
+ fread_timing_val |= hcycle << shift;
+
+ /* no DI input delay first */
+ writel(fread_timing_val, TIMING_REG_AST2600(chip));
+ pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(aspi->dev,
+ " * [%08x] %d HCLK delay, DI delay none : %s",
+ fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
+ if (pass)
+ return 0;
+
+ /* Add DI input delays */
+ fread_timing_val &= mask;
+ fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
+
+ for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
+ fread_timing_val &= ~(0xf << (4 + shift));
+ fread_timing_val |= delay_ns << (4 + shift);
+
+ writel(fread_timing_val, TIMING_REG_AST2600(chip));
+ pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(aspi->dev,
+ " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
+ fread_timing_val, hcycle, (delay_ns + 1) / 2,
+ (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
+ /*
+ * TODO: This is optimistic. We should look
+ * for a working interval and save the middle
+ * value in the read timing register.
+ */
+ if (pass)
+ return 0;
+ }
+ }
+
+ /* No good setting for this frequency */
+ return -1;
+}
+
/*
* Platform definitions
*/
@@ -822,6 +1079,10 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
.hastype = true,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
.segment_start = aspeed_spi_segment_start,
.segment_end = aspeed_spi_segment_end,
.segment_reg = aspeed_spi_segment_reg,
@@ -832,6 +1093,10 @@ static const struct aspeed_spi_data ast2400_spi_data = {
.hastype = false,
.we0 = 0,
.ctl0 = 0x04,
+ .timing = 0x14,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
/* No segment registers */
};
@@ -840,6 +1105,10 @@ static const struct aspeed_spi_data ast2500_fmc_data = {
.hastype = true,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
.segment_start = aspeed_spi_segment_start,
.segment_end = aspeed_spi_segment_end,
.segment_reg = aspeed_spi_segment_reg,
@@ -850,6 +1119,10 @@ static const struct aspeed_spi_data ast2500_spi_data = {
.hastype = false,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
.segment_start = aspeed_spi_segment_start,
.segment_end = aspeed_spi_segment_end,
.segment_reg = aspeed_spi_segment_reg,
@@ -861,6 +1134,10 @@ static const struct aspeed_spi_data ast2600_fmc_data = {
.mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xf0fff0ff,
+ .hdiv_max = 2,
+ .calibrate = aspeed_spi_ast2600_calibrate,
.segment_start = aspeed_spi_segment_ast2600_start,
.segment_end = aspeed_spi_segment_ast2600_end,
.segment_reg = aspeed_spi_segment_ast2600_reg,
@@ -872,6 +1149,10 @@ static const struct aspeed_spi_data ast2600_spi_data = {
.mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xf0fff0ff,
+ .hdiv_max = 2,
+ .calibrate = aspeed_spi_ast2600_calibrate,
.segment_start = aspeed_spi_segment_ast2600_start,
.segment_end = aspeed_spi_segment_ast2600_end,
.segment_reg = aspeed_spi_segment_ast2600_reg,
--
2.34.1
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 09/10] spi: aspeed: Calibrate read timings
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
To accommodate the different response time of SPI transfers on different
boards and different SPI NOR devices, the Aspeed controllers provide a
set of Read Timing Compensation registers to tune the timing delays
depending on the frequency being used. The AST2600 SoC has one of
these registers per device. On the AST2500 and AST2400 SoCs, the
timing register is shared by all devices which is a bit problematic to
get good results other than for one device.
The algorithm first reads a golden buffer at low speed and then performs
reads with different clocks and delay cycle settings to find a breaking
point. This selects a default good frequency for the CEx control register.
The current settings are bit optimistic as we pick the first delay giving
good results. A safer approach would be to determine an interval and
choose the middle value.
Calibration is performed when the direct mapping for reads is created.
Since the underlying spi-nor object needs to be initialized to create
the spi_mem operation for direct mapping, we should be fine. Having a
specific API would clarify the requirements though.
Cc: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/spi/spi-aspeed-smc.c | 281 +++++++++++++++++++++++++++++++++++
1 file changed, 281 insertions(+)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 8c6d7f79d97f..dce25dfe6913 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -35,6 +35,8 @@
#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
#define CTRL_IO_DUMMY_SET(dummy) \
(((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
+#define CTRL_FREQ_SEL_SHIFT 8
+#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
#define CTRL_CE_STOP_ACTIVE BIT(2)
#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
#define CTRL_IO_MODE_NORMAL 0x0
@@ -47,6 +49,9 @@
/* CEx Address Decoding Range Register */
#define CE0_SEGMENT_ADDR_REG 0x30
+/* CEx Read timing compensation register */
+#define CE0_TIMING_COMPENSATION_REG 0x94
+
enum aspeed_spi_ctl_reg_value {
ASPEED_SPI_BASE,
ASPEED_SPI_READ,
@@ -72,10 +77,15 @@ struct aspeed_spi_data {
bool hastype;
u32 mode_bits;
u32 we0;
+ u32 timing;
+ u32 hclk_mask;
+ u32 hdiv_max;
u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
+ int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf);
};
#define ASPEED_SPI_MAX_NUM_CS 5
@@ -519,6 +529,8 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
return 0;
}
+static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
+
static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
@@ -567,6 +579,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+ ret = aspeed_spi_do_calibration(chip);
+
dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
@@ -814,6 +828,249 @@ static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
((end - 1) & AST2600_SEG_ADDR_MASK);
}
+/*
+ * Read timing compensation sequences
+ */
+
+#define CALIBRATE_BUF_SIZE SZ_16K
+
+static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
+ if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
+#if defined(VERBOSE_DEBUG)
+ print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
+ test_buf, 0x100);
+#endif
+ return false;
+ }
+ }
+ return true;
+}
+
+#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
+
+/*
+ * The timing register is shared by all devices. Only update for CE0.
+ */
+static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ const struct aspeed_spi_data *data = aspi->data;
+ int i;
+ int good_pass = -1, pass_count = 0;
+ u32 shift = (hdiv - 1) << 2;
+ u32 mask = ~(0xfu << shift);
+ u32 fread_timing_val = 0;
+
+ /* Try HCLK delay 0..5, each one with/without delay and look for a
+ * good pair.
+ */
+ for (i = 0; i < 12; i++) {
+ bool pass;
+
+ if (chip->cs == 0) {
+ fread_timing_val &= mask;
+ fread_timing_val |= FREAD_TPASS(i) << shift;
+ writel(fread_timing_val, aspi->regs + data->timing);
+ }
+ pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(aspi->dev,
+ " * [%08x] %d HCLK delay, %dns DI delay : %s",
+ fread_timing_val, i / 2, (i & 1) ? 0 : 4,
+ pass ? "PASS" : "FAIL");
+ if (pass) {
+ pass_count++;
+ if (pass_count == 3) {
+ good_pass = i - 1;
+ break;
+ }
+ } else {
+ pass_count = 0;
+ }
+ }
+
+ /* No good setting for this frequency */
+ if (good_pass < 0)
+ return -1;
+
+ /* We have at least one pass of margin, let's use first pass */
+ if (chip->cs == 0) {
+ fread_timing_val &= mask;
+ fread_timing_val |= FREAD_TPASS(good_pass) << shift;
+ writel(fread_timing_val, aspi->regs + data->timing);
+ }
+ dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
+ good_pass, fread_timing_val);
+ return 0;
+}
+
+static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
+{
+ const u32 *tb32 = (const u32 *)test_buf;
+ u32 i, cnt = 0;
+
+ /* We check if we have enough words that are neither all 0
+ * nor all 1's so the calibration can be considered valid.
+ *
+ * I use an arbitrary threshold for now of 64
+ */
+ size >>= 2;
+ for (i = 0; i < size; i++) {
+ if (tb32[i] != 0 && tb32[i] != 0xffffffff)
+ cnt++;
+ }
+ return cnt >= 64;
+}
+
+static const u32 aspeed_spi_hclk_divs[] = {
+ 0xf, /* HCLK */
+ 0x7, /* HCLK/2 */
+ 0xe, /* HCLK/3 */
+ 0x6, /* HCLK/4 */
+ 0xd, /* HCLK/5 */
+};
+
+#define ASPEED_SPI_HCLK_DIV(i) \
+ (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
+
+static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ const struct aspeed_spi_data *data = aspi->data;
+ u32 ahb_freq = aspi->clk_freq;
+ u32 max_freq = chip->clk_freq;
+ u32 ctl_val;
+ u8 *golden_buf = NULL;
+ u8 *test_buf = NULL;
+ int i, rc, best_div = -1;
+
+ dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
+ ahb_freq / 1000000);
+
+ /*
+ * use the related low frequency to get check calibration data
+ * and get golden data.
+ */
+ ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
+ writel(ctl_val, chip->ctl);
+
+ test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
+ if (!test_buf)
+ return -ENOMEM;
+
+ golden_buf = test_buf + CALIBRATE_BUF_SIZE;
+
+ memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
+ if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
+ dev_info(aspi->dev, "Calibration area too uniform, using low speed");
+ goto no_calib;
+ }
+
+#if defined(VERBOSE_DEBUG)
+ print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
+ golden_buf, 0x100);
+#endif
+
+ /* Now we iterate the HCLK dividers until we find our breaking point */
+ for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
+ u32 tv, freq;
+
+ freq = ahb_freq / i;
+ if (freq > max_freq)
+ continue;
+
+ /* Set the timing */
+ tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
+ writel(tv, chip->ctl);
+ dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
+ rc = data->calibrate(chip, i, golden_buf, test_buf);
+ if (rc == 0)
+ best_div = i;
+ }
+
+ /* Nothing found ? */
+ if (best_div < 0) {
+ dev_warn(aspi->dev, "No good frequency, using dumb slow");
+ } else {
+ dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
+
+ /* Record the freq */
+ for (i = 0; i < ASPEED_SPI_MAX; i++)
+ chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
+ ASPEED_SPI_HCLK_DIV(best_div);
+ }
+
+no_calib:
+ writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
+ kfree(test_buf);
+ return 0;
+}
+
+#define TIMING_DELAY_DI BIT(3)
+#define TIMING_DELAY_HCYCLE_MAX 5
+#define TIMING_REG_AST2600(chip) \
+ ((chip)->aspi->regs + (chip)->aspi->data->timing + \
+ (chip)->cs * 4)
+
+static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ struct aspeed_spi *aspi = chip->aspi;
+ int hcycle;
+ u32 shift = (hdiv - 2) << 3;
+ u32 mask = ~(0xfu << shift);
+ u32 fread_timing_val = 0;
+
+ for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
+ int delay_ns;
+ bool pass = false;
+
+ fread_timing_val &= mask;
+ fread_timing_val |= hcycle << shift;
+
+ /* no DI input delay first */
+ writel(fread_timing_val, TIMING_REG_AST2600(chip));
+ pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(aspi->dev,
+ " * [%08x] %d HCLK delay, DI delay none : %s",
+ fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
+ if (pass)
+ return 0;
+
+ /* Add DI input delays */
+ fread_timing_val &= mask;
+ fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
+
+ for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
+ fread_timing_val &= ~(0xf << (4 + shift));
+ fread_timing_val |= delay_ns << (4 + shift);
+
+ writel(fread_timing_val, TIMING_REG_AST2600(chip));
+ pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(aspi->dev,
+ " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
+ fread_timing_val, hcycle, (delay_ns + 1) / 2,
+ (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
+ /*
+ * TODO: This is optimistic. We should look
+ * for a working interval and save the middle
+ * value in the read timing register.
+ */
+ if (pass)
+ return 0;
+ }
+ }
+
+ /* No good setting for this frequency */
+ return -1;
+}
+
/*
* Platform definitions
*/
@@ -822,6 +1079,10 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
.hastype = true,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
.segment_start = aspeed_spi_segment_start,
.segment_end = aspeed_spi_segment_end,
.segment_reg = aspeed_spi_segment_reg,
@@ -832,6 +1093,10 @@ static const struct aspeed_spi_data ast2400_spi_data = {
.hastype = false,
.we0 = 0,
.ctl0 = 0x04,
+ .timing = 0x14,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
/* No segment registers */
};
@@ -840,6 +1105,10 @@ static const struct aspeed_spi_data ast2500_fmc_data = {
.hastype = true,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
.segment_start = aspeed_spi_segment_start,
.segment_end = aspeed_spi_segment_end,
.segment_reg = aspeed_spi_segment_reg,
@@ -850,6 +1119,10 @@ static const struct aspeed_spi_data ast2500_spi_data = {
.hastype = false,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xfffff0ff,
+ .hdiv_max = 1,
+ .calibrate = aspeed_spi_calibrate,
.segment_start = aspeed_spi_segment_start,
.segment_end = aspeed_spi_segment_end,
.segment_reg = aspeed_spi_segment_reg,
@@ -861,6 +1134,10 @@ static const struct aspeed_spi_data ast2600_fmc_data = {
.mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xf0fff0ff,
+ .hdiv_max = 2,
+ .calibrate = aspeed_spi_ast2600_calibrate,
.segment_start = aspeed_spi_segment_ast2600_start,
.segment_end = aspeed_spi_segment_ast2600_end,
.segment_reg = aspeed_spi_segment_ast2600_reg,
@@ -872,6 +1149,10 @@ static const struct aspeed_spi_data ast2600_spi_data = {
.mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
.we0 = 16,
.ctl0 = CE0_CTRL_REG,
+ .timing = CE0_TIMING_COMPENSATION_REG,
+ .hclk_mask = 0xf0fff0ff,
+ .hdiv_max = 2,
+ .calibrate = aspeed_spi_ast2600_calibrate,
.segment_start = aspeed_spi_segment_ast2600_start,
.segment_end = aspeed_spi_segment_ast2600_end,
.segment_reg = aspeed_spi_segment_ast2600_reg,
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 17:31 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
All these controllers support at least Dual SPI. Update the DTs.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 9ae67e83cf60..31e6569db97e 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -64,27 +64,32 @@ fmc: spi@1e620000 {
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@3 {
reg = < 3 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@4 {
reg = < 4 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -100,6 +105,7 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index c3e0a8e13c8a..29bf017899b6 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -66,18 +66,21 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -93,12 +96,14 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -114,12 +119,14 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1ad05dde19d2..ce93c56a21a7 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -106,18 +106,21 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -133,12 +136,14 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -154,18 +159,21 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
All these controllers support at least Dual SPI. Update the DTs.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 9ae67e83cf60..31e6569db97e 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -64,27 +64,32 @@ fmc: spi@1e620000 {
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@3 {
reg = < 3 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@4 {
reg = < 4 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -100,6 +105,7 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index c3e0a8e13c8a..29bf017899b6 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -66,18 +66,21 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -93,12 +96,14 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -114,12 +119,14 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1ad05dde19d2..ce93c56a21a7 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -106,18 +106,21 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -133,12 +136,14 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -154,18 +159,21 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
@ 2022-03-02 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-02 17:31 UTC (permalink / raw)
To: linux-spi, linux-mtd
Cc: Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Joel Stanley, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, linux-arm-kernel, linux-kernel,
Cédric Le Goater
All these controllers support at least Dual SPI. Update the DTs.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 9ae67e83cf60..31e6569db97e 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -64,27 +64,32 @@ fmc: spi@1e620000 {
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@3 {
reg = < 3 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@4 {
reg = < 4 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -100,6 +105,7 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index c3e0a8e13c8a..29bf017899b6 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -66,18 +66,21 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -93,12 +96,14 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -114,12 +119,14 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1ad05dde19d2..ce93c56a21a7 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -106,18 +106,21 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -133,12 +136,14 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -154,18 +159,21 @@ flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 21:26 ` Rob Herring
-1 siblings, 0 replies; 79+ messages in thread
From: Rob Herring @ 2022-03-02 21:26 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Joel Stanley, Andrew Jeffery, Chin-Ting Kuo,
devicetree, linux-arm-kernel, linux-kernel
On Wed, Mar 02, 2022 at 06:31:07PM +0100, Cédric Le Goater wrote:
> The "interrupt" property is optional because it is only necessary for
> controllers supporting DMAs (Not implemented yet in the new driver).
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> .../bindings/spi/aspeed,ast2600-fmc.yaml | 90 +++++++++++++++++++
> MAINTAINERS | 9 ++
> 2 files changed, 99 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> new file mode 100644
> index 000000000000..0289a4f52196
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed SMC controllers bindings
> +
> +maintainers:
> + - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> + - Cédric Le Goater <clg@kaod.org>
> +
> +description: |
> + This binding describes the Aspeed Static Memory Controllers (FMC and
> + SPI) of the AST2400, AST2500 and AST2600 SOCs.
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2600-fmc
> + - aspeed,ast2600-spi
> + - aspeed,ast2500-fmc
> + - aspeed,ast2500-spi
> + - aspeed,ast2400-fmc
> + - aspeed,ast2400-spi
> +
> + reg:
> + items:
> + - description: registers
> + - description: memory mapping
> +
> + clocks:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "@[0-9a-f]+":
> + type: object
> +
> + properties:
> + spi-rx-bus-width:
> + enum: [1, 2, 4]
> +
> + required:
> + - reg
No need for required here, spi-controller.yaml already enforces that.
Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
> + #include <dt-bindings/clock/ast2600-clock.h>
> +
> + spi@1e620000 {
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2600-fmc";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4175103e928d..f5ab77548ef6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2925,6 +2925,15 @@ S: Maintained
> F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
> F: drivers/mmc/host/sdhci-of-aspeed*
>
> +ASPEED SMC SPI DRIVER
> +M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> +M: Cédric Le Goater <clg@kaod.org>
> +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
> +L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
> +L: linux-spi@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> +
> ASPEED VIDEO ENGINE DRIVER
> M: Eddie James <eajames@linux.ibm.com>
> L: linux-media@vger.kernel.org
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding
@ 2022-03-02 21:26 ` Rob Herring
0 siblings, 0 replies; 79+ messages in thread
From: Rob Herring @ 2022-03-02 21:26 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Joel Stanley, Andrew Jeffery, Chin-Ting Kuo,
devicetree, linux-arm-kernel, linux-kernel
On Wed, Mar 02, 2022 at 06:31:07PM +0100, Cédric Le Goater wrote:
> The "interrupt" property is optional because it is only necessary for
> controllers supporting DMAs (Not implemented yet in the new driver).
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> .../bindings/spi/aspeed,ast2600-fmc.yaml | 90 +++++++++++++++++++
> MAINTAINERS | 9 ++
> 2 files changed, 99 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> new file mode 100644
> index 000000000000..0289a4f52196
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed SMC controllers bindings
> +
> +maintainers:
> + - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> + - Cédric Le Goater <clg@kaod.org>
> +
> +description: |
> + This binding describes the Aspeed Static Memory Controllers (FMC and
> + SPI) of the AST2400, AST2500 and AST2600 SOCs.
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2600-fmc
> + - aspeed,ast2600-spi
> + - aspeed,ast2500-fmc
> + - aspeed,ast2500-spi
> + - aspeed,ast2400-fmc
> + - aspeed,ast2400-spi
> +
> + reg:
> + items:
> + - description: registers
> + - description: memory mapping
> +
> + clocks:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "@[0-9a-f]+":
> + type: object
> +
> + properties:
> + spi-rx-bus-width:
> + enum: [1, 2, 4]
> +
> + required:
> + - reg
No need for required here, spi-controller.yaml already enforces that.
Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
> + #include <dt-bindings/clock/ast2600-clock.h>
> +
> + spi@1e620000 {
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2600-fmc";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4175103e928d..f5ab77548ef6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2925,6 +2925,15 @@ S: Maintained
> F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
> F: drivers/mmc/host/sdhci-of-aspeed*
>
> +ASPEED SMC SPI DRIVER
> +M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> +M: Cédric Le Goater <clg@kaod.org>
> +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
> +L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
> +L: linux-spi@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> +
> ASPEED VIDEO ENGINE DRIVER
> M: Eddie James <eajames@linux.ibm.com>
> L: linux-media@vger.kernel.org
> --
> 2.34.1
>
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding
@ 2022-03-02 21:26 ` Rob Herring
0 siblings, 0 replies; 79+ messages in thread
From: Rob Herring @ 2022-03-02 21:26 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Joel Stanley, Andrew Jeffery, Chin-Ting Kuo,
devicetree, linux-arm-kernel, linux-kernel
On Wed, Mar 02, 2022 at 06:31:07PM +0100, Cédric Le Goater wrote:
> The "interrupt" property is optional because it is only necessary for
> controllers supporting DMAs (Not implemented yet in the new driver).
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> .../bindings/spi/aspeed,ast2600-fmc.yaml | 90 +++++++++++++++++++
> MAINTAINERS | 9 ++
> 2 files changed, 99 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> new file mode 100644
> index 000000000000..0289a4f52196
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed SMC controllers bindings
> +
> +maintainers:
> + - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> + - Cédric Le Goater <clg@kaod.org>
> +
> +description: |
> + This binding describes the Aspeed Static Memory Controllers (FMC and
> + SPI) of the AST2400, AST2500 and AST2600 SOCs.
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2600-fmc
> + - aspeed,ast2600-spi
> + - aspeed,ast2500-fmc
> + - aspeed,ast2500-spi
> + - aspeed,ast2400-fmc
> + - aspeed,ast2400-spi
> +
> + reg:
> + items:
> + - description: registers
> + - description: memory mapping
> +
> + clocks:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "@[0-9a-f]+":
> + type: object
> +
> + properties:
> + spi-rx-bus-width:
> + enum: [1, 2, 4]
> +
> + required:
> + - reg
No need for required here, spi-controller.yaml already enforces that.
Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
> + #include <dt-bindings/clock/ast2600-clock.h>
> +
> + spi@1e620000 {
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2600-fmc";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4175103e928d..f5ab77548ef6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2925,6 +2925,15 @@ S: Maintained
> F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
> F: drivers/mmc/host/sdhci-of-aspeed*
>
> +ASPEED SMC SPI DRIVER
> +M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> +M: Cédric Le Goater <clg@kaod.org>
> +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
> +L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
> +L: linux-spi@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> +
> ASPEED VIDEO ENGINE DRIVER
> M: Eddie James <eajames@linux.ibm.com>
> L: linux-media@vger.kernel.org
> --
> 2.34.1
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 01/10] mtd: spi-nor: aspeed: Rename Kconfig option
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 22:16 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:16 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> To prepare transition to the new Aspeed SMC SPI controller driver using
> the spi-mem interface, change the kernel CONFIG option of the current
> driver to reflect that the implementation uses the MTD SPI-NOR interface.
> Once the new driver is sufficiently exposed, we should remove the old one.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
As the maintianer of the aspeed systems and the openbmc kernel, I
think this makes the most sense.
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/mtd/spi-nor/controllers/Kconfig | 2 +-
> drivers/mtd/spi-nor/controllers/Makefile | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
> index 5c0e0ec2e6d1..876a47042fec 100644
> --- a/drivers/mtd/spi-nor/controllers/Kconfig
> +++ b/drivers/mtd/spi-nor/controllers/Kconfig
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> -config SPI_ASPEED_SMC
> +config SPI_ASPEED_SMC_MTD_SPI_NOR
> tristate "Aspeed flash controllers in SPI mode"
> depends on ARCH_ASPEED || COMPILE_TEST
> depends on HAS_IOMEM && OF
> diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile
> index e7abba491d98..1e28297fb1e8 100644
> --- a/drivers/mtd/spi-nor/controllers/Makefile
> +++ b/drivers/mtd/spi-nor/controllers/Makefile
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
> +obj-$(CONFIG_SPI_ASPEED_SMC_MTD_SPI_NOR) += aspeed-smc.o
> obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
> obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
> obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 01/10] mtd: spi-nor: aspeed: Rename Kconfig option
@ 2022-03-02 22:16 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:16 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> To prepare transition to the new Aspeed SMC SPI controller driver using
> the spi-mem interface, change the kernel CONFIG option of the current
> driver to reflect that the implementation uses the MTD SPI-NOR interface.
> Once the new driver is sufficiently exposed, we should remove the old one.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
As the maintianer of the aspeed systems and the openbmc kernel, I
think this makes the most sense.
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/mtd/spi-nor/controllers/Kconfig | 2 +-
> drivers/mtd/spi-nor/controllers/Makefile | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
> index 5c0e0ec2e6d1..876a47042fec 100644
> --- a/drivers/mtd/spi-nor/controllers/Kconfig
> +++ b/drivers/mtd/spi-nor/controllers/Kconfig
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> -config SPI_ASPEED_SMC
> +config SPI_ASPEED_SMC_MTD_SPI_NOR
> tristate "Aspeed flash controllers in SPI mode"
> depends on ARCH_ASPEED || COMPILE_TEST
> depends on HAS_IOMEM && OF
> diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile
> index e7abba491d98..1e28297fb1e8 100644
> --- a/drivers/mtd/spi-nor/controllers/Makefile
> +++ b/drivers/mtd/spi-nor/controllers/Makefile
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
> +obj-$(CONFIG_SPI_ASPEED_SMC_MTD_SPI_NOR) += aspeed-smc.o
> obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
> obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
> obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
> --
> 2.34.1
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 01/10] mtd: spi-nor: aspeed: Rename Kconfig option
@ 2022-03-02 22:16 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:16 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> To prepare transition to the new Aspeed SMC SPI controller driver using
> the spi-mem interface, change the kernel CONFIG option of the current
> driver to reflect that the implementation uses the MTD SPI-NOR interface.
> Once the new driver is sufficiently exposed, we should remove the old one.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
As the maintianer of the aspeed systems and the openbmc kernel, I
think this makes the most sense.
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/mtd/spi-nor/controllers/Kconfig | 2 +-
> drivers/mtd/spi-nor/controllers/Makefile | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
> index 5c0e0ec2e6d1..876a47042fec 100644
> --- a/drivers/mtd/spi-nor/controllers/Kconfig
> +++ b/drivers/mtd/spi-nor/controllers/Kconfig
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> -config SPI_ASPEED_SMC
> +config SPI_ASPEED_SMC_MTD_SPI_NOR
> tristate "Aspeed flash controllers in SPI mode"
> depends on ARCH_ASPEED || COMPILE_TEST
> depends on HAS_IOMEM && OF
> diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile
> index e7abba491d98..1e28297fb1e8 100644
> --- a/drivers/mtd/spi-nor/controllers/Makefile
> +++ b/drivers/mtd/spi-nor/controllers/Makefile
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
> +obj-$(CONFIG_SPI_ASPEED_SMC_MTD_SPI_NOR) += aspeed-smc.o
> obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
> obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
> obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 02/10] ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 22:18 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:18 UTC (permalink / raw)
To: Cédric Le Goater, Rob Herring
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:32, Cédric Le Goater <clg@kaod.org> wrote:
>
> This is compatible with the current driver and addresses issues when
> running 'make dt_binding_check'.
Hey Rob, why does the checking rule complain about this style of reg property?
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++----
> arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++------
> arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++------
> 3 files changed, 8 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index f14dace34c5a..9ae67e83cf60 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -54,8 +54,7 @@ ahb {
> ranges;
>
> fmc: spi@1e620000 {
> - reg = < 0x1e620000 0x94
> - 0x20000000 0x10000000 >;
> + reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2400-fmc";
> @@ -91,8 +90,7 @@ flash@4 {
> };
>
> spi: spi@1e630000 {
> - reg = < 0x1e630000 0x18
> - 0x30000000 0x10000000 >;
> + reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2400-spi";
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index 7495f93c5069..c3e0a8e13c8a 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -55,8 +55,7 @@ ahb {
> ranges;
>
> fmc: spi@1e620000 {
> - reg = < 0x1e620000 0xc4
> - 0x20000000 0x10000000 >;
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-fmc";
> @@ -84,8 +83,7 @@ flash@2 {
> };
>
> spi1: spi@1e630000 {
> - reg = < 0x1e630000 0xc4
> - 0x30000000 0x08000000 >;
> + reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-spi";
> @@ -106,8 +104,7 @@ flash@1 {
> };
>
> spi2: spi@1e631000 {
> - reg = < 0x1e631000 0xc4
> - 0x38000000 0x08000000 >;
> + reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-spi";
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index c32e87fad4dc..1ad05dde19d2 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -95,8 +95,7 @@ gic: interrupt-controller@40461000 {
> };
>
> fmc: spi@1e620000 {
> - reg = < 0x1e620000 0xc4
> - 0x20000000 0x10000000 >;
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2600-fmc";
> @@ -124,8 +123,7 @@ flash@2 {
> };
>
> spi1: spi@1e630000 {
> - reg = < 0x1e630000 0xc4
> - 0x30000000 0x10000000 >;
> + reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2600-spi";
> @@ -146,8 +144,7 @@ flash@1 {
> };
>
> spi2: spi@1e631000 {
> - reg = < 0x1e631000 0xc4
> - 0x50000000 0x10000000 >;
> + reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2600-spi";
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 02/10] ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
@ 2022-03-02 22:18 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:18 UTC (permalink / raw)
To: Cédric Le Goater, Rob Herring
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:32, Cédric Le Goater <clg@kaod.org> wrote:
>
> This is compatible with the current driver and addresses issues when
> running 'make dt_binding_check'.
Hey Rob, why does the checking rule complain about this style of reg property?
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++----
> arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++------
> arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++------
> 3 files changed, 8 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index f14dace34c5a..9ae67e83cf60 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -54,8 +54,7 @@ ahb {
> ranges;
>
> fmc: spi@1e620000 {
> - reg = < 0x1e620000 0x94
> - 0x20000000 0x10000000 >;
> + reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2400-fmc";
> @@ -91,8 +90,7 @@ flash@4 {
> };
>
> spi: spi@1e630000 {
> - reg = < 0x1e630000 0x18
> - 0x30000000 0x10000000 >;
> + reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2400-spi";
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index 7495f93c5069..c3e0a8e13c8a 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -55,8 +55,7 @@ ahb {
> ranges;
>
> fmc: spi@1e620000 {
> - reg = < 0x1e620000 0xc4
> - 0x20000000 0x10000000 >;
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-fmc";
> @@ -84,8 +83,7 @@ flash@2 {
> };
>
> spi1: spi@1e630000 {
> - reg = < 0x1e630000 0xc4
> - 0x30000000 0x08000000 >;
> + reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-spi";
> @@ -106,8 +104,7 @@ flash@1 {
> };
>
> spi2: spi@1e631000 {
> - reg = < 0x1e631000 0xc4
> - 0x38000000 0x08000000 >;
> + reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-spi";
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index c32e87fad4dc..1ad05dde19d2 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -95,8 +95,7 @@ gic: interrupt-controller@40461000 {
> };
>
> fmc: spi@1e620000 {
> - reg = < 0x1e620000 0xc4
> - 0x20000000 0x10000000 >;
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2600-fmc";
> @@ -124,8 +123,7 @@ flash@2 {
> };
>
> spi1: spi@1e630000 {
> - reg = < 0x1e630000 0xc4
> - 0x30000000 0x10000000 >;
> + reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2600-spi";
> @@ -146,8 +144,7 @@ flash@1 {
> };
>
> spi2: spi@1e631000 {
> - reg = < 0x1e631000 0xc4
> - 0x50000000 0x10000000 >;
> + reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2600-spi";
> --
> 2.34.1
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 02/10] ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
@ 2022-03-02 22:18 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:18 UTC (permalink / raw)
To: Cédric Le Goater, Rob Herring
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:32, Cédric Le Goater <clg@kaod.org> wrote:
>
> This is compatible with the current driver and addresses issues when
> running 'make dt_binding_check'.
Hey Rob, why does the checking rule complain about this style of reg property?
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++----
> arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++------
> arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++------
> 3 files changed, 8 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index f14dace34c5a..9ae67e83cf60 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -54,8 +54,7 @@ ahb {
> ranges;
>
> fmc: spi@1e620000 {
> - reg = < 0x1e620000 0x94
> - 0x20000000 0x10000000 >;
> + reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2400-fmc";
> @@ -91,8 +90,7 @@ flash@4 {
> };
>
> spi: spi@1e630000 {
> - reg = < 0x1e630000 0x18
> - 0x30000000 0x10000000 >;
> + reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2400-spi";
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index 7495f93c5069..c3e0a8e13c8a 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -55,8 +55,7 @@ ahb {
> ranges;
>
> fmc: spi@1e620000 {
> - reg = < 0x1e620000 0xc4
> - 0x20000000 0x10000000 >;
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-fmc";
> @@ -84,8 +83,7 @@ flash@2 {
> };
>
> spi1: spi@1e630000 {
> - reg = < 0x1e630000 0xc4
> - 0x30000000 0x08000000 >;
> + reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-spi";
> @@ -106,8 +104,7 @@ flash@1 {
> };
>
> spi2: spi@1e631000 {
> - reg = < 0x1e631000 0xc4
> - 0x38000000 0x08000000 >;
> + reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2500-spi";
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index c32e87fad4dc..1ad05dde19d2 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -95,8 +95,7 @@ gic: interrupt-controller@40461000 {
> };
>
> fmc: spi@1e620000 {
> - reg = < 0x1e620000 0xc4
> - 0x20000000 0x10000000 >;
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2600-fmc";
> @@ -124,8 +123,7 @@ flash@2 {
> };
>
> spi1: spi@1e630000 {
> - reg = < 0x1e630000 0xc4
> - 0x30000000 0x10000000 >;
> + reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2600-spi";
> @@ -146,8 +144,7 @@ flash@1 {
> };
>
> spi2: spi@1e631000 {
> - reg = < 0x1e631000 0xc4
> - 0x50000000 0x10000000 >;
> + reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "aspeed,ast2600-spi";
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 22:20 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:20 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> The "interrupt" property is optional because it is only necessary for
> controllers supporting DMAs (Not implemented yet in the new driver).
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> .../bindings/spi/aspeed,ast2600-fmc.yaml | 90 +++++++++++++++++++
> MAINTAINERS | 9 ++
> 2 files changed, 99 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> new file mode 100644
> index 000000000000..0289a4f52196
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed SMC controllers bindings
> +
> +maintainers:
> + - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> + - Cédric Le Goater <clg@kaod.org>
> +
> +description: |
> + This binding describes the Aspeed Static Memory Controllers (FMC and
> + SPI) of the AST2400, AST2500 and AST2600 SOCs.
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2600-fmc
> + - aspeed,ast2600-spi
> + - aspeed,ast2500-fmc
> + - aspeed,ast2500-spi
> + - aspeed,ast2400-fmc
> + - aspeed,ast2400-spi
> +
> + reg:
> + items:
> + - description: registers
> + - description: memory mapping
> +
> + clocks:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "@[0-9a-f]+":
> + type: object
> +
> + properties:
> + spi-rx-bus-width:
> + enum: [1, 2, 4]
> +
> + required:
> + - reg
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
> + #include <dt-bindings/clock/ast2600-clock.h>
> +
> + spi@1e620000 {
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2600-fmc";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4175103e928d..f5ab77548ef6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2925,6 +2925,15 @@ S: Maintained
> F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
> F: drivers/mmc/host/sdhci-of-aspeed*
>
> +ASPEED SMC SPI DRIVER
> +M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> +M: Cédric Le Goater <clg@kaod.org>
> +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
> +L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
> +L: linux-spi@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> +
> ASPEED VIDEO ENGINE DRIVER
> M: Eddie James <eajames@linux.ibm.com>
> L: linux-media@vger.kernel.org
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding
@ 2022-03-02 22:20 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:20 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> The "interrupt" property is optional because it is only necessary for
> controllers supporting DMAs (Not implemented yet in the new driver).
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> .../bindings/spi/aspeed,ast2600-fmc.yaml | 90 +++++++++++++++++++
> MAINTAINERS | 9 ++
> 2 files changed, 99 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> new file mode 100644
> index 000000000000..0289a4f52196
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed SMC controllers bindings
> +
> +maintainers:
> + - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> + - Cédric Le Goater <clg@kaod.org>
> +
> +description: |
> + This binding describes the Aspeed Static Memory Controllers (FMC and
> + SPI) of the AST2400, AST2500 and AST2600 SOCs.
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2600-fmc
> + - aspeed,ast2600-spi
> + - aspeed,ast2500-fmc
> + - aspeed,ast2500-spi
> + - aspeed,ast2400-fmc
> + - aspeed,ast2400-spi
> +
> + reg:
> + items:
> + - description: registers
> + - description: memory mapping
> +
> + clocks:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "@[0-9a-f]+":
> + type: object
> +
> + properties:
> + spi-rx-bus-width:
> + enum: [1, 2, 4]
> +
> + required:
> + - reg
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
> + #include <dt-bindings/clock/ast2600-clock.h>
> +
> + spi@1e620000 {
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2600-fmc";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4175103e928d..f5ab77548ef6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2925,6 +2925,15 @@ S: Maintained
> F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
> F: drivers/mmc/host/sdhci-of-aspeed*
>
> +ASPEED SMC SPI DRIVER
> +M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> +M: Cédric Le Goater <clg@kaod.org>
> +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
> +L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
> +L: linux-spi@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> +
> ASPEED VIDEO ENGINE DRIVER
> M: Eddie James <eajames@linux.ibm.com>
> L: linux-media@vger.kernel.org
> --
> 2.34.1
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding
@ 2022-03-02 22:20 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:20 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> The "interrupt" property is optional because it is only necessary for
> controllers supporting DMAs (Not implemented yet in the new driver).
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> .../bindings/spi/aspeed,ast2600-fmc.yaml | 90 +++++++++++++++++++
> MAINTAINERS | 9 ++
> 2 files changed, 99 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> new file mode 100644
> index 000000000000..0289a4f52196
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed SMC controllers bindings
> +
> +maintainers:
> + - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> + - Cédric Le Goater <clg@kaod.org>
> +
> +description: |
> + This binding describes the Aspeed Static Memory Controllers (FMC and
> + SPI) of the AST2400, AST2500 and AST2600 SOCs.
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2600-fmc
> + - aspeed,ast2600-spi
> + - aspeed,ast2500-fmc
> + - aspeed,ast2500-spi
> + - aspeed,ast2400-fmc
> + - aspeed,ast2400-spi
> +
> + reg:
> + items:
> + - description: registers
> + - description: memory mapping
> +
> + clocks:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +patternProperties:
> + "@[0-9a-f]+":
> + type: object
> +
> + properties:
> + spi-rx-bus-width:
> + enum: [1, 2, 4]
> +
> + required:
> + - reg
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
> + #include <dt-bindings/clock/ast2600-clock.h>
> +
> + spi@1e620000 {
> + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2600-fmc";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + flash@2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4175103e928d..f5ab77548ef6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2925,6 +2925,15 @@ S: Maintained
> F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
> F: drivers/mmc/host/sdhci-of-aspeed*
>
> +ASPEED SMC SPI DRIVER
> +M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> +M: Cédric Le Goater <clg@kaod.org>
> +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
> +L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
> +L: linux-spi@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
> +
> ASPEED VIDEO ENGINE DRIVER
> M: Eddie James <eajames@linux.ibm.com>
> L: linux-media@vger.kernel.org
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 07/10] spi: aspeed: Workaround AST2500 limitations
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 22:30 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:30 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> It is not possible to configure a full 128MB window for a chip of the
> same size on the AST2500 SPI controller. For his case, the maximum
typo: this
> window size is restricted to 120MB for CE0.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index 974ab215ec34..e133984d3c95 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -445,6 +445,8 @@ static int aspeed_spi_set_window(struct aspeed_spi *aspi,
> * - ioremap each window, not strictly necessary since the overall window
> * is correct.
> */
> +static const struct aspeed_spi_data ast2500_spi_data;
> +
> static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> u32 local_offset, u32 size)
> {
> @@ -453,6 +455,16 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> struct aspeed_spi_window *win = &windows[chip->cs];
> int ret;
>
> + /*
> + * Due to an HW issue on the AST2500 SPI controller, the CE0
> + * window size should be smaller than the maximum 128MB.
> + */
> + if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
> + size = 120 << 20;
> + dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
> + chip->cs, size >> 20);
> + }
> +
> aspeed_spi_get_windows(aspi, windows);
>
> /* Adjust this chip window */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 07/10] spi: aspeed: Workaround AST2500 limitations
@ 2022-03-02 22:30 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:30 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> It is not possible to configure a full 128MB window for a chip of the
> same size on the AST2500 SPI controller. For his case, the maximum
typo: this
> window size is restricted to 120MB for CE0.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index 974ab215ec34..e133984d3c95 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -445,6 +445,8 @@ static int aspeed_spi_set_window(struct aspeed_spi *aspi,
> * - ioremap each window, not strictly necessary since the overall window
> * is correct.
> */
> +static const struct aspeed_spi_data ast2500_spi_data;
> +
> static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> u32 local_offset, u32 size)
> {
> @@ -453,6 +455,16 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> struct aspeed_spi_window *win = &windows[chip->cs];
> int ret;
>
> + /*
> + * Due to an HW issue on the AST2500 SPI controller, the CE0
> + * window size should be smaller than the maximum 128MB.
> + */
> + if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
> + size = 120 << 20;
> + dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
> + chip->cs, size >> 20);
> + }
> +
> aspeed_spi_get_windows(aspi, windows);
>
> /* Adjust this chip window */
> --
> 2.34.1
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 07/10] spi: aspeed: Workaround AST2500 limitations
@ 2022-03-02 22:30 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:30 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> It is not possible to configure a full 128MB window for a chip of the
> same size on the AST2500 SPI controller. For his case, the maximum
typo: this
> window size is restricted to 120MB for CE0.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index 974ab215ec34..e133984d3c95 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -445,6 +445,8 @@ static int aspeed_spi_set_window(struct aspeed_spi *aspi,
> * - ioremap each window, not strictly necessary since the overall window
> * is correct.
> */
> +static const struct aspeed_spi_data ast2500_spi_data;
> +
> static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> u32 local_offset, u32 size)
> {
> @@ -453,6 +455,16 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> struct aspeed_spi_window *win = &windows[chip->cs];
> int ret;
>
> + /*
> + * Due to an HW issue on the AST2500 SPI controller, the CE0
> + * window size should be smaller than the maximum 128MB.
> + */
> + if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
> + size = 120 << 20;
> + dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
> + chip->cs, size >> 20);
> + }
> +
> aspeed_spi_get_windows(aspi, windows);
>
> /* Adjust this chip window */
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 06/10] spi: aspeed: Adjust direct mapping to device size
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 22:31 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:31 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> The segment registers of the FMC/SPI controllers provide a way to
> configure the mapping window of the flash device contents on the AHB
> bus. Adjust this window to the size of the spi-mem mapping.
>
> Things get more complex with multiple devices. The driver needs to
> also adjust the window of the next device to make sure that there is
> no overlap, even if there is no available device. The proposal below
> is not perfect but it is covering all the cases we have seen on
> different boards with one and two devices on the same bus.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 88 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index b4854b521477..974ab215ec34 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -405,6 +405,92 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
> return chip->ahb_window_size ? 0 : -1;
> }
>
> +static int aspeed_spi_set_window(struct aspeed_spi *aspi,
> + const struct aspeed_spi_window *win)
> +{
> + u32 start = aspi->ahb_base_phy + win->offset;
> + u32 end = start + win->size;
> + void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
> + u32 seg_val_backup = readl(seg_reg);
> + u32 seg_val = aspi->data->segment_reg(aspi, start, end);
> +
> + if (seg_val == seg_val_backup)
> + return 0;
> +
> + writel(seg_val, seg_reg);
> +
> + /*
> + * Restore initial value if something goes wrong else we could
> + * loose access to the chip.
> + */
> + if (seg_val != readl(seg_reg)) {
> + dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
> + win->cs, start, end - 1, win->size >> 20);
> + writel(seg_val_backup, seg_reg);
> + return -EIO;
> + }
> +
> + if (win->size)
> + dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
> + win->cs, start, end - 1, win->size >> 20);
> + else
> + dev_dbg(aspi->dev, "CE%d window closed", win->cs);
> +
> + return 0;
> +}
> +
> +/*
> + * Yet to be done when possible :
> + * - Align mappings on flash size (we don't have the info)
> + * - ioremap each window, not strictly necessary since the overall window
> + * is correct.
> + */
> +static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> + u32 local_offset, u32 size)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
> + struct aspeed_spi_window *win = &windows[chip->cs];
> + int ret;
> +
> + aspeed_spi_get_windows(aspi, windows);
> +
> + /* Adjust this chip window */
> + win->offset += local_offset;
> + win->size = size;
> +
> + if (win->offset + win->size > aspi->ahb_window_size) {
> + win->size = aspi->ahb_window_size - win->offset;
> + dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
> + }
> +
> + ret = aspeed_spi_set_window(aspi, win);
> + if (ret)
> + return ret;
> +
> + /* Update chip mapping info */
> + chip->ahb_base = aspi->ahb_base + win->offset;
> + chip->ahb_window_size = win->size;
> +
> + /*
> + * Also adjust next chip window to make sure that it does not
> + * overlap with the current window.
> + */
> + if (chip->cs < aspi->data->max_cs - 1) {
> + struct aspeed_spi_window *next = &windows[chip->cs + 1];
> +
> + /* Change offset and size to keep the same end address */
> + if ((next->offset + next->size) > (win->offset + win->size))
> + next->size = (next->offset + next->size) - (win->offset + win->size);
> + else
> + next->size = 0;
> + next->offset = win->offset + win->size;
> +
> + aspeed_spi_set_window(aspi, next);
> + }
> + return 0;
> +}
> +
> static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> {
> struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> @@ -419,6 +505,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> if (op->data.dir != SPI_MEM_DATA_IN)
> return -EOPNOTSUPP;
>
> + aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
> +
> if (desc->info.length > chip->ahb_window_size)
> dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
> chip->cs, chip->ahb_window_size >> 20);
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 06/10] spi: aspeed: Adjust direct mapping to device size
@ 2022-03-02 22:31 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:31 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> The segment registers of the FMC/SPI controllers provide a way to
> configure the mapping window of the flash device contents on the AHB
> bus. Adjust this window to the size of the spi-mem mapping.
>
> Things get more complex with multiple devices. The driver needs to
> also adjust the window of the next device to make sure that there is
> no overlap, even if there is no available device. The proposal below
> is not perfect but it is covering all the cases we have seen on
> different boards with one and two devices on the same bus.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 88 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index b4854b521477..974ab215ec34 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -405,6 +405,92 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
> return chip->ahb_window_size ? 0 : -1;
> }
>
> +static int aspeed_spi_set_window(struct aspeed_spi *aspi,
> + const struct aspeed_spi_window *win)
> +{
> + u32 start = aspi->ahb_base_phy + win->offset;
> + u32 end = start + win->size;
> + void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
> + u32 seg_val_backup = readl(seg_reg);
> + u32 seg_val = aspi->data->segment_reg(aspi, start, end);
> +
> + if (seg_val == seg_val_backup)
> + return 0;
> +
> + writel(seg_val, seg_reg);
> +
> + /*
> + * Restore initial value if something goes wrong else we could
> + * loose access to the chip.
> + */
> + if (seg_val != readl(seg_reg)) {
> + dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
> + win->cs, start, end - 1, win->size >> 20);
> + writel(seg_val_backup, seg_reg);
> + return -EIO;
> + }
> +
> + if (win->size)
> + dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
> + win->cs, start, end - 1, win->size >> 20);
> + else
> + dev_dbg(aspi->dev, "CE%d window closed", win->cs);
> +
> + return 0;
> +}
> +
> +/*
> + * Yet to be done when possible :
> + * - Align mappings on flash size (we don't have the info)
> + * - ioremap each window, not strictly necessary since the overall window
> + * is correct.
> + */
> +static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> + u32 local_offset, u32 size)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
> + struct aspeed_spi_window *win = &windows[chip->cs];
> + int ret;
> +
> + aspeed_spi_get_windows(aspi, windows);
> +
> + /* Adjust this chip window */
> + win->offset += local_offset;
> + win->size = size;
> +
> + if (win->offset + win->size > aspi->ahb_window_size) {
> + win->size = aspi->ahb_window_size - win->offset;
> + dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
> + }
> +
> + ret = aspeed_spi_set_window(aspi, win);
> + if (ret)
> + return ret;
> +
> + /* Update chip mapping info */
> + chip->ahb_base = aspi->ahb_base + win->offset;
> + chip->ahb_window_size = win->size;
> +
> + /*
> + * Also adjust next chip window to make sure that it does not
> + * overlap with the current window.
> + */
> + if (chip->cs < aspi->data->max_cs - 1) {
> + struct aspeed_spi_window *next = &windows[chip->cs + 1];
> +
> + /* Change offset and size to keep the same end address */
> + if ((next->offset + next->size) > (win->offset + win->size))
> + next->size = (next->offset + next->size) - (win->offset + win->size);
> + else
> + next->size = 0;
> + next->offset = win->offset + win->size;
> +
> + aspeed_spi_set_window(aspi, next);
> + }
> + return 0;
> +}
> +
> static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> {
> struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> @@ -419,6 +505,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> if (op->data.dir != SPI_MEM_DATA_IN)
> return -EOPNOTSUPP;
>
> + aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
> +
> if (desc->info.length > chip->ahb_window_size)
> dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
> chip->cs, chip->ahb_window_size >> 20);
> --
> 2.34.1
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 06/10] spi: aspeed: Adjust direct mapping to device size
@ 2022-03-02 22:31 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:31 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> The segment registers of the FMC/SPI controllers provide a way to
> configure the mapping window of the flash device contents on the AHB
> bus. Adjust this window to the size of the spi-mem mapping.
>
> Things get more complex with multiple devices. The driver needs to
> also adjust the window of the next device to make sure that there is
> no overlap, even if there is no available device. The proposal below
> is not perfect but it is covering all the cases we have seen on
> different boards with one and two devices on the same bus.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 88 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index b4854b521477..974ab215ec34 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -405,6 +405,92 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
> return chip->ahb_window_size ? 0 : -1;
> }
>
> +static int aspeed_spi_set_window(struct aspeed_spi *aspi,
> + const struct aspeed_spi_window *win)
> +{
> + u32 start = aspi->ahb_base_phy + win->offset;
> + u32 end = start + win->size;
> + void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
> + u32 seg_val_backup = readl(seg_reg);
> + u32 seg_val = aspi->data->segment_reg(aspi, start, end);
> +
> + if (seg_val == seg_val_backup)
> + return 0;
> +
> + writel(seg_val, seg_reg);
> +
> + /*
> + * Restore initial value if something goes wrong else we could
> + * loose access to the chip.
> + */
> + if (seg_val != readl(seg_reg)) {
> + dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
> + win->cs, start, end - 1, win->size >> 20);
> + writel(seg_val_backup, seg_reg);
> + return -EIO;
> + }
> +
> + if (win->size)
> + dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
> + win->cs, start, end - 1, win->size >> 20);
> + else
> + dev_dbg(aspi->dev, "CE%d window closed", win->cs);
> +
> + return 0;
> +}
> +
> +/*
> + * Yet to be done when possible :
> + * - Align mappings on flash size (we don't have the info)
> + * - ioremap each window, not strictly necessary since the overall window
> + * is correct.
> + */
> +static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> + u32 local_offset, u32 size)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
> + struct aspeed_spi_window *win = &windows[chip->cs];
> + int ret;
> +
> + aspeed_spi_get_windows(aspi, windows);
> +
> + /* Adjust this chip window */
> + win->offset += local_offset;
> + win->size = size;
> +
> + if (win->offset + win->size > aspi->ahb_window_size) {
> + win->size = aspi->ahb_window_size - win->offset;
> + dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
> + }
> +
> + ret = aspeed_spi_set_window(aspi, win);
> + if (ret)
> + return ret;
> +
> + /* Update chip mapping info */
> + chip->ahb_base = aspi->ahb_base + win->offset;
> + chip->ahb_window_size = win->size;
> +
> + /*
> + * Also adjust next chip window to make sure that it does not
> + * overlap with the current window.
> + */
> + if (chip->cs < aspi->data->max_cs - 1) {
> + struct aspeed_spi_window *next = &windows[chip->cs + 1];
> +
> + /* Change offset and size to keep the same end address */
> + if ((next->offset + next->size) > (win->offset + win->size))
> + next->size = (next->offset + next->size) - (win->offset + win->size);
> + else
> + next->size = 0;
> + next->offset = win->offset + win->size;
> +
> + aspeed_spi_set_window(aspi, next);
> + }
> + return 0;
> +}
> +
> static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> {
> struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> @@ -419,6 +505,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> if (op->data.dir != SPI_MEM_DATA_IN)
> return -EOPNOTSUPP;
>
> + aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
> +
> if (desc->info.length > chip->ahb_window_size)
> dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
> chip->cs, chip->ahb_window_size >> 20);
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 08/10] spi: aspeed: Add support for the AST2400 SPI controller
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 22:33 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:33 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> Extend the driver for the AST2400 SPI Flash Controller (SPI). This
> controller has a slightly different interface which requires
> adaptation of the 4B handling. Summary of features :
>
> . host Firmware
> . 1 chip select pin (CE0)
> . slightly different register set, between AST2500 and the legacy
> controller
> . no segment registers
> . single, dual mode.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 33 ++++++++++++++++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index e133984d3c95..8c6d7f79d97f 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -32,6 +32,7 @@
> #define CTRL_IO_DUAL_DATA BIT(29)
> #define CTRL_IO_QUAD_DATA BIT(30)
> #define CTRL_COMMAND_SHIFT 16
> +#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
> #define CTRL_IO_DUMMY_SET(dummy) \
> (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
> #define CTRL_CE_STOP_ACTIVE BIT(2)
> @@ -272,6 +273,8 @@ static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op
> return spi_mem_default_supports_op(mem, op);
> }
>
> +static const struct aspeed_spi_data ast2400_spi_data;
> +
> static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
> {
> struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
> @@ -301,6 +304,9 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
> addr_mode |= (0x11 << chip->cs);
> else
> addr_mode &= ~(0x11 << chip->cs);
> +
> + if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
> + ctl_val |= CTRL_IO_ADDRESS_4B;
> }
>
> if (op->dummy.buswidth && op->dummy.nbytes)
> @@ -392,7 +398,13 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
> struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
> struct aspeed_spi_window *win = &windows[chip->cs];
>
> - aspeed_spi_get_windows(aspi, windows);
> + /* No segment registers for the AST2400 SPI controller */
> + if (aspi->data == &ast2400_spi_data) {
> + win->offset = 0;
> + win->size = aspi->ahb_window_size;
> + } else {
> + aspeed_spi_get_windows(aspi, windows);
> + }
>
> chip->ahb_base = aspi->ahb_base + win->offset;
> chip->ahb_window_size = win->size;
> @@ -455,6 +467,10 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> struct aspeed_spi_window *win = &windows[chip->cs];
> int ret;
>
> + /* No segment registers for the AST2400 SPI controller */
> + if (aspi->data == &ast2400_spi_data)
> + return 0;
> +
> /*
> * Due to an HW issue on the AST2500 SPI controller, the CE0
> * window size should be smaller than the maximum 128MB.
> @@ -539,6 +555,12 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> else
> addr_mode &= ~(0x11 << chip->cs);
> writel(addr_mode, aspi->regs + CE_CTRL_REG);
> +
> + /* AST2400 SPI controller sets 4BYTE address mode in
> + * CE0 Control Register
> + */
> + if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
> + ctl_val |= CTRL_IO_ADDRESS_4B;
> }
>
> /* READ mode is the controller default setting */
> @@ -805,6 +827,14 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
> .segment_reg = aspeed_spi_segment_reg,
> };
>
> +static const struct aspeed_spi_data ast2400_spi_data = {
> + .max_cs = 1,
> + .hastype = false,
> + .we0 = 0,
> + .ctl0 = 0x04,
> + /* No segment registers */
> +};
> +
> static const struct aspeed_spi_data ast2500_fmc_data = {
> .max_cs = 3,
> .hastype = true,
> @@ -849,6 +879,7 @@ static const struct aspeed_spi_data ast2600_spi_data = {
>
> static const struct of_device_id aspeed_spi_matches[] = {
> { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
> + { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
> { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
> { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
> { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 08/10] spi: aspeed: Add support for the AST2400 SPI controller
@ 2022-03-02 22:33 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:33 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> Extend the driver for the AST2400 SPI Flash Controller (SPI). This
> controller has a slightly different interface which requires
> adaptation of the 4B handling. Summary of features :
>
> . host Firmware
> . 1 chip select pin (CE0)
> . slightly different register set, between AST2500 and the legacy
> controller
> . no segment registers
> . single, dual mode.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 33 ++++++++++++++++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index e133984d3c95..8c6d7f79d97f 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -32,6 +32,7 @@
> #define CTRL_IO_DUAL_DATA BIT(29)
> #define CTRL_IO_QUAD_DATA BIT(30)
> #define CTRL_COMMAND_SHIFT 16
> +#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
> #define CTRL_IO_DUMMY_SET(dummy) \
> (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
> #define CTRL_CE_STOP_ACTIVE BIT(2)
> @@ -272,6 +273,8 @@ static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op
> return spi_mem_default_supports_op(mem, op);
> }
>
> +static const struct aspeed_spi_data ast2400_spi_data;
> +
> static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
> {
> struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
> @@ -301,6 +304,9 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
> addr_mode |= (0x11 << chip->cs);
> else
> addr_mode &= ~(0x11 << chip->cs);
> +
> + if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
> + ctl_val |= CTRL_IO_ADDRESS_4B;
> }
>
> if (op->dummy.buswidth && op->dummy.nbytes)
> @@ -392,7 +398,13 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
> struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
> struct aspeed_spi_window *win = &windows[chip->cs];
>
> - aspeed_spi_get_windows(aspi, windows);
> + /* No segment registers for the AST2400 SPI controller */
> + if (aspi->data == &ast2400_spi_data) {
> + win->offset = 0;
> + win->size = aspi->ahb_window_size;
> + } else {
> + aspeed_spi_get_windows(aspi, windows);
> + }
>
> chip->ahb_base = aspi->ahb_base + win->offset;
> chip->ahb_window_size = win->size;
> @@ -455,6 +467,10 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> struct aspeed_spi_window *win = &windows[chip->cs];
> int ret;
>
> + /* No segment registers for the AST2400 SPI controller */
> + if (aspi->data == &ast2400_spi_data)
> + return 0;
> +
> /*
> * Due to an HW issue on the AST2500 SPI controller, the CE0
> * window size should be smaller than the maximum 128MB.
> @@ -539,6 +555,12 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> else
> addr_mode &= ~(0x11 << chip->cs);
> writel(addr_mode, aspi->regs + CE_CTRL_REG);
> +
> + /* AST2400 SPI controller sets 4BYTE address mode in
> + * CE0 Control Register
> + */
> + if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
> + ctl_val |= CTRL_IO_ADDRESS_4B;
> }
>
> /* READ mode is the controller default setting */
> @@ -805,6 +827,14 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
> .segment_reg = aspeed_spi_segment_reg,
> };
>
> +static const struct aspeed_spi_data ast2400_spi_data = {
> + .max_cs = 1,
> + .hastype = false,
> + .we0 = 0,
> + .ctl0 = 0x04,
> + /* No segment registers */
> +};
> +
> static const struct aspeed_spi_data ast2500_fmc_data = {
> .max_cs = 3,
> .hastype = true,
> @@ -849,6 +879,7 @@ static const struct aspeed_spi_data ast2600_spi_data = {
>
> static const struct of_device_id aspeed_spi_matches[] = {
> { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
> + { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
> { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
> { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
> { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
> --
> 2.34.1
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 08/10] spi: aspeed: Add support for the AST2400 SPI controller
@ 2022-03-02 22:33 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:33 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> Extend the driver for the AST2400 SPI Flash Controller (SPI). This
> controller has a slightly different interface which requires
> adaptation of the 4B handling. Summary of features :
>
> . host Firmware
> . 1 chip select pin (CE0)
> . slightly different register set, between AST2500 and the legacy
> controller
> . no segment registers
> . single, dual mode.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 33 ++++++++++++++++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index e133984d3c95..8c6d7f79d97f 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -32,6 +32,7 @@
> #define CTRL_IO_DUAL_DATA BIT(29)
> #define CTRL_IO_QUAD_DATA BIT(30)
> #define CTRL_COMMAND_SHIFT 16
> +#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
> #define CTRL_IO_DUMMY_SET(dummy) \
> (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
> #define CTRL_CE_STOP_ACTIVE BIT(2)
> @@ -272,6 +273,8 @@ static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op
> return spi_mem_default_supports_op(mem, op);
> }
>
> +static const struct aspeed_spi_data ast2400_spi_data;
> +
> static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
> {
> struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
> @@ -301,6 +304,9 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
> addr_mode |= (0x11 << chip->cs);
> else
> addr_mode &= ~(0x11 << chip->cs);
> +
> + if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
> + ctl_val |= CTRL_IO_ADDRESS_4B;
> }
>
> if (op->dummy.buswidth && op->dummy.nbytes)
> @@ -392,7 +398,13 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
> struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
> struct aspeed_spi_window *win = &windows[chip->cs];
>
> - aspeed_spi_get_windows(aspi, windows);
> + /* No segment registers for the AST2400 SPI controller */
> + if (aspi->data == &ast2400_spi_data) {
> + win->offset = 0;
> + win->size = aspi->ahb_window_size;
> + } else {
> + aspeed_spi_get_windows(aspi, windows);
> + }
>
> chip->ahb_base = aspi->ahb_base + win->offset;
> chip->ahb_window_size = win->size;
> @@ -455,6 +467,10 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> struct aspeed_spi_window *win = &windows[chip->cs];
> int ret;
>
> + /* No segment registers for the AST2400 SPI controller */
> + if (aspi->data == &ast2400_spi_data)
> + return 0;
> +
> /*
> * Due to an HW issue on the AST2500 SPI controller, the CE0
> * window size should be smaller than the maximum 128MB.
> @@ -539,6 +555,12 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> else
> addr_mode &= ~(0x11 << chip->cs);
> writel(addr_mode, aspi->regs + CE_CTRL_REG);
> +
> + /* AST2400 SPI controller sets 4BYTE address mode in
> + * CE0 Control Register
> + */
> + if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
> + ctl_val |= CTRL_IO_ADDRESS_4B;
> }
>
> /* READ mode is the controller default setting */
> @@ -805,6 +827,14 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
> .segment_reg = aspeed_spi_segment_reg,
> };
>
> +static const struct aspeed_spi_data ast2400_spi_data = {
> + .max_cs = 1,
> + .hastype = false,
> + .we0 = 0,
> + .ctl0 = 0x04,
> + /* No segment registers */
> +};
> +
> static const struct aspeed_spi_data ast2500_fmc_data = {
> .max_cs = 3,
> .hastype = true,
> @@ -849,6 +879,7 @@ static const struct aspeed_spi_data ast2600_spi_data = {
>
> static const struct of_device_id aspeed_spi_matches[] = {
> { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
> + { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
> { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
> { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
> { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 09/10] spi: aspeed: Calibrate read timings
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 22:44 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:44 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:32, Cédric Le Goater <clg@kaod.org> wrote:
>
> To accommodate the different response time of SPI transfers on different
> boards and different SPI NOR devices, the Aspeed controllers provide a
> set of Read Timing Compensation registers to tune the timing delays
> depending on the frequency being used. The AST2600 SoC has one of
> these registers per device. On the AST2500 and AST2400 SoCs, the
> timing register is shared by all devices which is a bit problematic to
> get good results other than for one device.
>
> The algorithm first reads a golden buffer at low speed and then performs
> reads with different clocks and delay cycle settings to find a breaking
> point. This selects a default good frequency for the CEx control register.
> The current settings are bit optimistic as we pick the first delay giving
typo: are a bit
> good results. A safer approach would be to determine an interval and
> choose the middle value.
>
> Calibration is performed when the direct mapping for reads is created.
> Since the underlying spi-nor object needs to be initialized to create
> the spi_mem operation for direct mapping, we should be fine. Having a
> specific API would clarify the requirements though.
>
> Cc: Pratyush Yadav <p.yadav@ti.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 281 +++++++++++++++++++++++++++++++++++
> 1 file changed, 281 insertions(+)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index 8c6d7f79d97f..dce25dfe6913 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -35,6 +35,8 @@
> #define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
> #define CTRL_IO_DUMMY_SET(dummy) \
> (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
> +#define CTRL_FREQ_SEL_SHIFT 8
> +#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
> #define CTRL_CE_STOP_ACTIVE BIT(2)
> #define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
> #define CTRL_IO_MODE_NORMAL 0x0
> @@ -47,6 +49,9 @@
> /* CEx Address Decoding Range Register */
> #define CE0_SEGMENT_ADDR_REG 0x30
>
> +/* CEx Read timing compensation register */
> +#define CE0_TIMING_COMPENSATION_REG 0x94
> +
> enum aspeed_spi_ctl_reg_value {
> ASPEED_SPI_BASE,
> ASPEED_SPI_READ,
> @@ -72,10 +77,15 @@ struct aspeed_spi_data {
> bool hastype;
> u32 mode_bits;
> u32 we0;
> + u32 timing;
> + u32 hclk_mask;
> + u32 hdiv_max;
>
> u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
> u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
> u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
> + int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
> + const u8 *golden_buf, u8 *test_buf);
> };
>
> #define ASPEED_SPI_MAX_NUM_CS 5
> @@ -519,6 +529,8 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> return 0;
> }
>
> +static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
> +
> static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> {
> struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> @@ -567,6 +579,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
> writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
>
> + ret = aspeed_spi_do_calibration(chip);
> +
> dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
> chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
>
> @@ -814,6 +828,249 @@ static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
> ((end - 1) & AST2600_SEG_ADDR_MASK);
> }
>
> +/*
> + * Read timing compensation sequences
> + */
> +
> +#define CALIBRATE_BUF_SIZE SZ_16K
> +
> +static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
> + const u8 *golden_buf, u8 *test_buf)
> +{
> + int i;
> +
> + for (i = 0; i < 10; i++) {
> + memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
> + if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
> +#if defined(VERBOSE_DEBUG)
> + print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
> + test_buf, 0x100);
> +#endif
> + return false;
> + }
> + }
> + return true;
> +}
> +
> +#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
> +
> +/*
> + * The timing register is shared by all devices. Only update for CE0.
> + */
> +static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
> + const u8 *golden_buf, u8 *test_buf)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + const struct aspeed_spi_data *data = aspi->data;
> + int i;
> + int good_pass = -1, pass_count = 0;
> + u32 shift = (hdiv - 1) << 2;
> + u32 mask = ~(0xfu << shift);
> + u32 fread_timing_val = 0;
> +
> + /* Try HCLK delay 0..5, each one with/without delay and look for a
> + * good pair.
> + */
> + for (i = 0; i < 12; i++) {
> + bool pass;
> +
> + if (chip->cs == 0) {
> + fread_timing_val &= mask;
> + fread_timing_val |= FREAD_TPASS(i) << shift;
> + writel(fread_timing_val, aspi->regs + data->timing);
> + }
> + pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
> + dev_dbg(aspi->dev,
> + " * [%08x] %d HCLK delay, %dns DI delay : %s",
> + fread_timing_val, i / 2, (i & 1) ? 0 : 4,
> + pass ? "PASS" : "FAIL");
> + if (pass) {
> + pass_count++;
> + if (pass_count == 3) {
> + good_pass = i - 1;
> + break;
> + }
> + } else {
> + pass_count = 0;
> + }
> + }
> +
> + /* No good setting for this frequency */
> + if (good_pass < 0)
> + return -1;
> +
> + /* We have at least one pass of margin, let's use first pass */
> + if (chip->cs == 0) {
> + fread_timing_val &= mask;
> + fread_timing_val |= FREAD_TPASS(good_pass) << shift;
> + writel(fread_timing_val, aspi->regs + data->timing);
> + }
> + dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
> + good_pass, fread_timing_val);
> + return 0;
> +}
> +
> +static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
> +{
> + const u32 *tb32 = (const u32 *)test_buf;
> + u32 i, cnt = 0;
> +
> + /* We check if we have enough words that are neither all 0
> + * nor all 1's so the calibration can be considered valid.
> + *
> + * I use an arbitrary threshold for now of 64
> + */
> + size >>= 2;
> + for (i = 0; i < size; i++) {
> + if (tb32[i] != 0 && tb32[i] != 0xffffffff)
> + cnt++;
> + }
> + return cnt >= 64;
> +}
> +
> +static const u32 aspeed_spi_hclk_divs[] = {
> + 0xf, /* HCLK */
> + 0x7, /* HCLK/2 */
> + 0xe, /* HCLK/3 */
> + 0x6, /* HCLK/4 */
> + 0xd, /* HCLK/5 */
> +};
> +
> +#define ASPEED_SPI_HCLK_DIV(i) \
> + (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
> +
> +static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + const struct aspeed_spi_data *data = aspi->data;
> + u32 ahb_freq = aspi->clk_freq;
> + u32 max_freq = chip->clk_freq;
> + u32 ctl_val;
> + u8 *golden_buf = NULL;
> + u8 *test_buf = NULL;
> + int i, rc, best_div = -1;
> +
> + dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
> + ahb_freq / 1000000);
> +
> + /*
> + * use the related low frequency to get check calibration data
> + * and get golden data.
> + */
> + ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
> + writel(ctl_val, chip->ctl);
> +
> + test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
> + if (!test_buf)
> + return -ENOMEM;
> +
> + golden_buf = test_buf + CALIBRATE_BUF_SIZE;
> +
> + memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
> + if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
> + dev_info(aspi->dev, "Calibration area too uniform, using low speed");
> + goto no_calib;
> + }
> +
> +#if defined(VERBOSE_DEBUG)
> + print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
> + golden_buf, 0x100);
> +#endif
> +
> + /* Now we iterate the HCLK dividers until we find our breaking point */
> + for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
> + u32 tv, freq;
> +
> + freq = ahb_freq / i;
> + if (freq > max_freq)
> + continue;
> +
> + /* Set the timing */
> + tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
> + writel(tv, chip->ctl);
> + dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
> + rc = data->calibrate(chip, i, golden_buf, test_buf);
> + if (rc == 0)
> + best_div = i;
> + }
> +
> + /* Nothing found ? */
> + if (best_div < 0) {
> + dev_warn(aspi->dev, "No good frequency, using dumb slow");
> + } else {
> + dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
> +
> + /* Record the freq */
> + for (i = 0; i < ASPEED_SPI_MAX; i++)
> + chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
> + ASPEED_SPI_HCLK_DIV(best_div);
> + }
> +
> +no_calib:
> + writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
> + kfree(test_buf);
> + return 0;
> +}
> +
> +#define TIMING_DELAY_DI BIT(3)
> +#define TIMING_DELAY_HCYCLE_MAX 5
> +#define TIMING_REG_AST2600(chip) \
> + ((chip)->aspi->regs + (chip)->aspi->data->timing + \
> + (chip)->cs * 4)
> +
> +static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
> + const u8 *golden_buf, u8 *test_buf)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + int hcycle;
> + u32 shift = (hdiv - 2) << 3;
> + u32 mask = ~(0xfu << shift);
> + u32 fread_timing_val = 0;
> +
> + for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
> + int delay_ns;
> + bool pass = false;
> +
> + fread_timing_val &= mask;
> + fread_timing_val |= hcycle << shift;
> +
> + /* no DI input delay first */
> + writel(fread_timing_val, TIMING_REG_AST2600(chip));
> + pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
> + dev_dbg(aspi->dev,
> + " * [%08x] %d HCLK delay, DI delay none : %s",
> + fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
> + if (pass)
> + return 0;
> +
> + /* Add DI input delays */
> + fread_timing_val &= mask;
> + fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
> +
> + for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
> + fread_timing_val &= ~(0xf << (4 + shift));
> + fread_timing_val |= delay_ns << (4 + shift);
> +
> + writel(fread_timing_val, TIMING_REG_AST2600(chip));
> + pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
> + dev_dbg(aspi->dev,
> + " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
> + fread_timing_val, hcycle, (delay_ns + 1) / 2,
> + (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
> + /*
> + * TODO: This is optimistic. We should look
> + * for a working interval and save the middle
> + * value in the read timing register.
> + */
> + if (pass)
> + return 0;
> + }
> + }
> +
> + /* No good setting for this frequency */
> + return -1;
> +}
> +
> /*
> * Platform definitions
> */
> @@ -822,6 +1079,10 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
> .hastype = true,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> .segment_start = aspeed_spi_segment_start,
> .segment_end = aspeed_spi_segment_end,
> .segment_reg = aspeed_spi_segment_reg,
> @@ -832,6 +1093,10 @@ static const struct aspeed_spi_data ast2400_spi_data = {
> .hastype = false,
> .we0 = 0,
> .ctl0 = 0x04,
> + .timing = 0x14,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> /* No segment registers */
> };
>
> @@ -840,6 +1105,10 @@ static const struct aspeed_spi_data ast2500_fmc_data = {
> .hastype = true,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> .segment_start = aspeed_spi_segment_start,
> .segment_end = aspeed_spi_segment_end,
> .segment_reg = aspeed_spi_segment_reg,
> @@ -850,6 +1119,10 @@ static const struct aspeed_spi_data ast2500_spi_data = {
> .hastype = false,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> .segment_start = aspeed_spi_segment_start,
> .segment_end = aspeed_spi_segment_end,
> .segment_reg = aspeed_spi_segment_reg,
> @@ -861,6 +1134,10 @@ static const struct aspeed_spi_data ast2600_fmc_data = {
> .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xf0fff0ff,
> + .hdiv_max = 2,
> + .calibrate = aspeed_spi_ast2600_calibrate,
> .segment_start = aspeed_spi_segment_ast2600_start,
> .segment_end = aspeed_spi_segment_ast2600_end,
> .segment_reg = aspeed_spi_segment_ast2600_reg,
> @@ -872,6 +1149,10 @@ static const struct aspeed_spi_data ast2600_spi_data = {
> .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xf0fff0ff,
> + .hdiv_max = 2,
> + .calibrate = aspeed_spi_ast2600_calibrate,
> .segment_start = aspeed_spi_segment_ast2600_start,
> .segment_end = aspeed_spi_segment_ast2600_end,
> .segment_reg = aspeed_spi_segment_ast2600_reg,
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 09/10] spi: aspeed: Calibrate read timings
@ 2022-03-02 22:44 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:44 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:32, Cédric Le Goater <clg@kaod.org> wrote:
>
> To accommodate the different response time of SPI transfers on different
> boards and different SPI NOR devices, the Aspeed controllers provide a
> set of Read Timing Compensation registers to tune the timing delays
> depending on the frequency being used. The AST2600 SoC has one of
> these registers per device. On the AST2500 and AST2400 SoCs, the
> timing register is shared by all devices which is a bit problematic to
> get good results other than for one device.
>
> The algorithm first reads a golden buffer at low speed and then performs
> reads with different clocks and delay cycle settings to find a breaking
> point. This selects a default good frequency for the CEx control register.
> The current settings are bit optimistic as we pick the first delay giving
typo: are a bit
> good results. A safer approach would be to determine an interval and
> choose the middle value.
>
> Calibration is performed when the direct mapping for reads is created.
> Since the underlying spi-nor object needs to be initialized to create
> the spi_mem operation for direct mapping, we should be fine. Having a
> specific API would clarify the requirements though.
>
> Cc: Pratyush Yadav <p.yadav@ti.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 281 +++++++++++++++++++++++++++++++++++
> 1 file changed, 281 insertions(+)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index 8c6d7f79d97f..dce25dfe6913 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -35,6 +35,8 @@
> #define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
> #define CTRL_IO_DUMMY_SET(dummy) \
> (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
> +#define CTRL_FREQ_SEL_SHIFT 8
> +#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
> #define CTRL_CE_STOP_ACTIVE BIT(2)
> #define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
> #define CTRL_IO_MODE_NORMAL 0x0
> @@ -47,6 +49,9 @@
> /* CEx Address Decoding Range Register */
> #define CE0_SEGMENT_ADDR_REG 0x30
>
> +/* CEx Read timing compensation register */
> +#define CE0_TIMING_COMPENSATION_REG 0x94
> +
> enum aspeed_spi_ctl_reg_value {
> ASPEED_SPI_BASE,
> ASPEED_SPI_READ,
> @@ -72,10 +77,15 @@ struct aspeed_spi_data {
> bool hastype;
> u32 mode_bits;
> u32 we0;
> + u32 timing;
> + u32 hclk_mask;
> + u32 hdiv_max;
>
> u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
> u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
> u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
> + int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
> + const u8 *golden_buf, u8 *test_buf);
> };
>
> #define ASPEED_SPI_MAX_NUM_CS 5
> @@ -519,6 +529,8 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> return 0;
> }
>
> +static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
> +
> static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> {
> struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> @@ -567,6 +579,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
> writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
>
> + ret = aspeed_spi_do_calibration(chip);
> +
> dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
> chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
>
> @@ -814,6 +828,249 @@ static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
> ((end - 1) & AST2600_SEG_ADDR_MASK);
> }
>
> +/*
> + * Read timing compensation sequences
> + */
> +
> +#define CALIBRATE_BUF_SIZE SZ_16K
> +
> +static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
> + const u8 *golden_buf, u8 *test_buf)
> +{
> + int i;
> +
> + for (i = 0; i < 10; i++) {
> + memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
> + if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
> +#if defined(VERBOSE_DEBUG)
> + print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
> + test_buf, 0x100);
> +#endif
> + return false;
> + }
> + }
> + return true;
> +}
> +
> +#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
> +
> +/*
> + * The timing register is shared by all devices. Only update for CE0.
> + */
> +static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
> + const u8 *golden_buf, u8 *test_buf)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + const struct aspeed_spi_data *data = aspi->data;
> + int i;
> + int good_pass = -1, pass_count = 0;
> + u32 shift = (hdiv - 1) << 2;
> + u32 mask = ~(0xfu << shift);
> + u32 fread_timing_val = 0;
> +
> + /* Try HCLK delay 0..5, each one with/without delay and look for a
> + * good pair.
> + */
> + for (i = 0; i < 12; i++) {
> + bool pass;
> +
> + if (chip->cs == 0) {
> + fread_timing_val &= mask;
> + fread_timing_val |= FREAD_TPASS(i) << shift;
> + writel(fread_timing_val, aspi->regs + data->timing);
> + }
> + pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
> + dev_dbg(aspi->dev,
> + " * [%08x] %d HCLK delay, %dns DI delay : %s",
> + fread_timing_val, i / 2, (i & 1) ? 0 : 4,
> + pass ? "PASS" : "FAIL");
> + if (pass) {
> + pass_count++;
> + if (pass_count == 3) {
> + good_pass = i - 1;
> + break;
> + }
> + } else {
> + pass_count = 0;
> + }
> + }
> +
> + /* No good setting for this frequency */
> + if (good_pass < 0)
> + return -1;
> +
> + /* We have at least one pass of margin, let's use first pass */
> + if (chip->cs == 0) {
> + fread_timing_val &= mask;
> + fread_timing_val |= FREAD_TPASS(good_pass) << shift;
> + writel(fread_timing_val, aspi->regs + data->timing);
> + }
> + dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
> + good_pass, fread_timing_val);
> + return 0;
> +}
> +
> +static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
> +{
> + const u32 *tb32 = (const u32 *)test_buf;
> + u32 i, cnt = 0;
> +
> + /* We check if we have enough words that are neither all 0
> + * nor all 1's so the calibration can be considered valid.
> + *
> + * I use an arbitrary threshold for now of 64
> + */
> + size >>= 2;
> + for (i = 0; i < size; i++) {
> + if (tb32[i] != 0 && tb32[i] != 0xffffffff)
> + cnt++;
> + }
> + return cnt >= 64;
> +}
> +
> +static const u32 aspeed_spi_hclk_divs[] = {
> + 0xf, /* HCLK */
> + 0x7, /* HCLK/2 */
> + 0xe, /* HCLK/3 */
> + 0x6, /* HCLK/4 */
> + 0xd, /* HCLK/5 */
> +};
> +
> +#define ASPEED_SPI_HCLK_DIV(i) \
> + (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
> +
> +static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + const struct aspeed_spi_data *data = aspi->data;
> + u32 ahb_freq = aspi->clk_freq;
> + u32 max_freq = chip->clk_freq;
> + u32 ctl_val;
> + u8 *golden_buf = NULL;
> + u8 *test_buf = NULL;
> + int i, rc, best_div = -1;
> +
> + dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
> + ahb_freq / 1000000);
> +
> + /*
> + * use the related low frequency to get check calibration data
> + * and get golden data.
> + */
> + ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
> + writel(ctl_val, chip->ctl);
> +
> + test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
> + if (!test_buf)
> + return -ENOMEM;
> +
> + golden_buf = test_buf + CALIBRATE_BUF_SIZE;
> +
> + memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
> + if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
> + dev_info(aspi->dev, "Calibration area too uniform, using low speed");
> + goto no_calib;
> + }
> +
> +#if defined(VERBOSE_DEBUG)
> + print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
> + golden_buf, 0x100);
> +#endif
> +
> + /* Now we iterate the HCLK dividers until we find our breaking point */
> + for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
> + u32 tv, freq;
> +
> + freq = ahb_freq / i;
> + if (freq > max_freq)
> + continue;
> +
> + /* Set the timing */
> + tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
> + writel(tv, chip->ctl);
> + dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
> + rc = data->calibrate(chip, i, golden_buf, test_buf);
> + if (rc == 0)
> + best_div = i;
> + }
> +
> + /* Nothing found ? */
> + if (best_div < 0) {
> + dev_warn(aspi->dev, "No good frequency, using dumb slow");
> + } else {
> + dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
> +
> + /* Record the freq */
> + for (i = 0; i < ASPEED_SPI_MAX; i++)
> + chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
> + ASPEED_SPI_HCLK_DIV(best_div);
> + }
> +
> +no_calib:
> + writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
> + kfree(test_buf);
> + return 0;
> +}
> +
> +#define TIMING_DELAY_DI BIT(3)
> +#define TIMING_DELAY_HCYCLE_MAX 5
> +#define TIMING_REG_AST2600(chip) \
> + ((chip)->aspi->regs + (chip)->aspi->data->timing + \
> + (chip)->cs * 4)
> +
> +static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
> + const u8 *golden_buf, u8 *test_buf)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + int hcycle;
> + u32 shift = (hdiv - 2) << 3;
> + u32 mask = ~(0xfu << shift);
> + u32 fread_timing_val = 0;
> +
> + for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
> + int delay_ns;
> + bool pass = false;
> +
> + fread_timing_val &= mask;
> + fread_timing_val |= hcycle << shift;
> +
> + /* no DI input delay first */
> + writel(fread_timing_val, TIMING_REG_AST2600(chip));
> + pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
> + dev_dbg(aspi->dev,
> + " * [%08x] %d HCLK delay, DI delay none : %s",
> + fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
> + if (pass)
> + return 0;
> +
> + /* Add DI input delays */
> + fread_timing_val &= mask;
> + fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
> +
> + for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
> + fread_timing_val &= ~(0xf << (4 + shift));
> + fread_timing_val |= delay_ns << (4 + shift);
> +
> + writel(fread_timing_val, TIMING_REG_AST2600(chip));
> + pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
> + dev_dbg(aspi->dev,
> + " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
> + fread_timing_val, hcycle, (delay_ns + 1) / 2,
> + (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
> + /*
> + * TODO: This is optimistic. We should look
> + * for a working interval and save the middle
> + * value in the read timing register.
> + */
> + if (pass)
> + return 0;
> + }
> + }
> +
> + /* No good setting for this frequency */
> + return -1;
> +}
> +
> /*
> * Platform definitions
> */
> @@ -822,6 +1079,10 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
> .hastype = true,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> .segment_start = aspeed_spi_segment_start,
> .segment_end = aspeed_spi_segment_end,
> .segment_reg = aspeed_spi_segment_reg,
> @@ -832,6 +1093,10 @@ static const struct aspeed_spi_data ast2400_spi_data = {
> .hastype = false,
> .we0 = 0,
> .ctl0 = 0x04,
> + .timing = 0x14,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> /* No segment registers */
> };
>
> @@ -840,6 +1105,10 @@ static const struct aspeed_spi_data ast2500_fmc_data = {
> .hastype = true,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> .segment_start = aspeed_spi_segment_start,
> .segment_end = aspeed_spi_segment_end,
> .segment_reg = aspeed_spi_segment_reg,
> @@ -850,6 +1119,10 @@ static const struct aspeed_spi_data ast2500_spi_data = {
> .hastype = false,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> .segment_start = aspeed_spi_segment_start,
> .segment_end = aspeed_spi_segment_end,
> .segment_reg = aspeed_spi_segment_reg,
> @@ -861,6 +1134,10 @@ static const struct aspeed_spi_data ast2600_fmc_data = {
> .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xf0fff0ff,
> + .hdiv_max = 2,
> + .calibrate = aspeed_spi_ast2600_calibrate,
> .segment_start = aspeed_spi_segment_ast2600_start,
> .segment_end = aspeed_spi_segment_ast2600_end,
> .segment_reg = aspeed_spi_segment_ast2600_reg,
> @@ -872,6 +1149,10 @@ static const struct aspeed_spi_data ast2600_spi_data = {
> .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xf0fff0ff,
> + .hdiv_max = 2,
> + .calibrate = aspeed_spi_ast2600_calibrate,
> .segment_start = aspeed_spi_segment_ast2600_start,
> .segment_end = aspeed_spi_segment_ast2600_end,
> .segment_reg = aspeed_spi_segment_ast2600_reg,
> --
> 2.34.1
>
______________________________________________________
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^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 09/10] spi: aspeed: Calibrate read timings
@ 2022-03-02 22:44 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:44 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:32, Cédric Le Goater <clg@kaod.org> wrote:
>
> To accommodate the different response time of SPI transfers on different
> boards and different SPI NOR devices, the Aspeed controllers provide a
> set of Read Timing Compensation registers to tune the timing delays
> depending on the frequency being used. The AST2600 SoC has one of
> these registers per device. On the AST2500 and AST2400 SoCs, the
> timing register is shared by all devices which is a bit problematic to
> get good results other than for one device.
>
> The algorithm first reads a golden buffer at low speed and then performs
> reads with different clocks and delay cycle settings to find a breaking
> point. This selects a default good frequency for the CEx control register.
> The current settings are bit optimistic as we pick the first delay giving
typo: are a bit
> good results. A safer approach would be to determine an interval and
> choose the middle value.
>
> Calibration is performed when the direct mapping for reads is created.
> Since the underlying spi-nor object needs to be initialized to create
> the spi_mem operation for direct mapping, we should be fine. Having a
> specific API would clarify the requirements though.
>
> Cc: Pratyush Yadav <p.yadav@ti.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 281 +++++++++++++++++++++++++++++++++++
> 1 file changed, 281 insertions(+)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index 8c6d7f79d97f..dce25dfe6913 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -35,6 +35,8 @@
> #define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
> #define CTRL_IO_DUMMY_SET(dummy) \
> (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
> +#define CTRL_FREQ_SEL_SHIFT 8
> +#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
> #define CTRL_CE_STOP_ACTIVE BIT(2)
> #define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
> #define CTRL_IO_MODE_NORMAL 0x0
> @@ -47,6 +49,9 @@
> /* CEx Address Decoding Range Register */
> #define CE0_SEGMENT_ADDR_REG 0x30
>
> +/* CEx Read timing compensation register */
> +#define CE0_TIMING_COMPENSATION_REG 0x94
> +
> enum aspeed_spi_ctl_reg_value {
> ASPEED_SPI_BASE,
> ASPEED_SPI_READ,
> @@ -72,10 +77,15 @@ struct aspeed_spi_data {
> bool hastype;
> u32 mode_bits;
> u32 we0;
> + u32 timing;
> + u32 hclk_mask;
> + u32 hdiv_max;
>
> u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
> u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
> u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
> + int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
> + const u8 *golden_buf, u8 *test_buf);
> };
>
> #define ASPEED_SPI_MAX_NUM_CS 5
> @@ -519,6 +529,8 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
> return 0;
> }
>
> +static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
> +
> static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> {
> struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> @@ -567,6 +579,8 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
> writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
>
> + ret = aspeed_spi_do_calibration(chip);
> +
> dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
> chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
>
> @@ -814,6 +828,249 @@ static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
> ((end - 1) & AST2600_SEG_ADDR_MASK);
> }
>
> +/*
> + * Read timing compensation sequences
> + */
> +
> +#define CALIBRATE_BUF_SIZE SZ_16K
> +
> +static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
> + const u8 *golden_buf, u8 *test_buf)
> +{
> + int i;
> +
> + for (i = 0; i < 10; i++) {
> + memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
> + if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
> +#if defined(VERBOSE_DEBUG)
> + print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
> + test_buf, 0x100);
> +#endif
> + return false;
> + }
> + }
> + return true;
> +}
> +
> +#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
> +
> +/*
> + * The timing register is shared by all devices. Only update for CE0.
> + */
> +static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
> + const u8 *golden_buf, u8 *test_buf)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + const struct aspeed_spi_data *data = aspi->data;
> + int i;
> + int good_pass = -1, pass_count = 0;
> + u32 shift = (hdiv - 1) << 2;
> + u32 mask = ~(0xfu << shift);
> + u32 fread_timing_val = 0;
> +
> + /* Try HCLK delay 0..5, each one with/without delay and look for a
> + * good pair.
> + */
> + for (i = 0; i < 12; i++) {
> + bool pass;
> +
> + if (chip->cs == 0) {
> + fread_timing_val &= mask;
> + fread_timing_val |= FREAD_TPASS(i) << shift;
> + writel(fread_timing_val, aspi->regs + data->timing);
> + }
> + pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
> + dev_dbg(aspi->dev,
> + " * [%08x] %d HCLK delay, %dns DI delay : %s",
> + fread_timing_val, i / 2, (i & 1) ? 0 : 4,
> + pass ? "PASS" : "FAIL");
> + if (pass) {
> + pass_count++;
> + if (pass_count == 3) {
> + good_pass = i - 1;
> + break;
> + }
> + } else {
> + pass_count = 0;
> + }
> + }
> +
> + /* No good setting for this frequency */
> + if (good_pass < 0)
> + return -1;
> +
> + /* We have at least one pass of margin, let's use first pass */
> + if (chip->cs == 0) {
> + fread_timing_val &= mask;
> + fread_timing_val |= FREAD_TPASS(good_pass) << shift;
> + writel(fread_timing_val, aspi->regs + data->timing);
> + }
> + dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
> + good_pass, fread_timing_val);
> + return 0;
> +}
> +
> +static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
> +{
> + const u32 *tb32 = (const u32 *)test_buf;
> + u32 i, cnt = 0;
> +
> + /* We check if we have enough words that are neither all 0
> + * nor all 1's so the calibration can be considered valid.
> + *
> + * I use an arbitrary threshold for now of 64
> + */
> + size >>= 2;
> + for (i = 0; i < size; i++) {
> + if (tb32[i] != 0 && tb32[i] != 0xffffffff)
> + cnt++;
> + }
> + return cnt >= 64;
> +}
> +
> +static const u32 aspeed_spi_hclk_divs[] = {
> + 0xf, /* HCLK */
> + 0x7, /* HCLK/2 */
> + 0xe, /* HCLK/3 */
> + 0x6, /* HCLK/4 */
> + 0xd, /* HCLK/5 */
> +};
> +
> +#define ASPEED_SPI_HCLK_DIV(i) \
> + (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
> +
> +static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + const struct aspeed_spi_data *data = aspi->data;
> + u32 ahb_freq = aspi->clk_freq;
> + u32 max_freq = chip->clk_freq;
> + u32 ctl_val;
> + u8 *golden_buf = NULL;
> + u8 *test_buf = NULL;
> + int i, rc, best_div = -1;
> +
> + dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
> + ahb_freq / 1000000);
> +
> + /*
> + * use the related low frequency to get check calibration data
> + * and get golden data.
> + */
> + ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
> + writel(ctl_val, chip->ctl);
> +
> + test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
> + if (!test_buf)
> + return -ENOMEM;
> +
> + golden_buf = test_buf + CALIBRATE_BUF_SIZE;
> +
> + memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
> + if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
> + dev_info(aspi->dev, "Calibration area too uniform, using low speed");
> + goto no_calib;
> + }
> +
> +#if defined(VERBOSE_DEBUG)
> + print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
> + golden_buf, 0x100);
> +#endif
> +
> + /* Now we iterate the HCLK dividers until we find our breaking point */
> + for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
> + u32 tv, freq;
> +
> + freq = ahb_freq / i;
> + if (freq > max_freq)
> + continue;
> +
> + /* Set the timing */
> + tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
> + writel(tv, chip->ctl);
> + dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
> + rc = data->calibrate(chip, i, golden_buf, test_buf);
> + if (rc == 0)
> + best_div = i;
> + }
> +
> + /* Nothing found ? */
> + if (best_div < 0) {
> + dev_warn(aspi->dev, "No good frequency, using dumb slow");
> + } else {
> + dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
> +
> + /* Record the freq */
> + for (i = 0; i < ASPEED_SPI_MAX; i++)
> + chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
> + ASPEED_SPI_HCLK_DIV(best_div);
> + }
> +
> +no_calib:
> + writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
> + kfree(test_buf);
> + return 0;
> +}
> +
> +#define TIMING_DELAY_DI BIT(3)
> +#define TIMING_DELAY_HCYCLE_MAX 5
> +#define TIMING_REG_AST2600(chip) \
> + ((chip)->aspi->regs + (chip)->aspi->data->timing + \
> + (chip)->cs * 4)
> +
> +static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
> + const u8 *golden_buf, u8 *test_buf)
> +{
> + struct aspeed_spi *aspi = chip->aspi;
> + int hcycle;
> + u32 shift = (hdiv - 2) << 3;
> + u32 mask = ~(0xfu << shift);
> + u32 fread_timing_val = 0;
> +
> + for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
> + int delay_ns;
> + bool pass = false;
> +
> + fread_timing_val &= mask;
> + fread_timing_val |= hcycle << shift;
> +
> + /* no DI input delay first */
> + writel(fread_timing_val, TIMING_REG_AST2600(chip));
> + pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
> + dev_dbg(aspi->dev,
> + " * [%08x] %d HCLK delay, DI delay none : %s",
> + fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
> + if (pass)
> + return 0;
> +
> + /* Add DI input delays */
> + fread_timing_val &= mask;
> + fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
> +
> + for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
> + fread_timing_val &= ~(0xf << (4 + shift));
> + fread_timing_val |= delay_ns << (4 + shift);
> +
> + writel(fread_timing_val, TIMING_REG_AST2600(chip));
> + pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
> + dev_dbg(aspi->dev,
> + " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
> + fread_timing_val, hcycle, (delay_ns + 1) / 2,
> + (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
> + /*
> + * TODO: This is optimistic. We should look
> + * for a working interval and save the middle
> + * value in the read timing register.
> + */
> + if (pass)
> + return 0;
> + }
> + }
> +
> + /* No good setting for this frequency */
> + return -1;
> +}
> +
> /*
> * Platform definitions
> */
> @@ -822,6 +1079,10 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
> .hastype = true,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> .segment_start = aspeed_spi_segment_start,
> .segment_end = aspeed_spi_segment_end,
> .segment_reg = aspeed_spi_segment_reg,
> @@ -832,6 +1093,10 @@ static const struct aspeed_spi_data ast2400_spi_data = {
> .hastype = false,
> .we0 = 0,
> .ctl0 = 0x04,
> + .timing = 0x14,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> /* No segment registers */
> };
>
> @@ -840,6 +1105,10 @@ static const struct aspeed_spi_data ast2500_fmc_data = {
> .hastype = true,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> .segment_start = aspeed_spi_segment_start,
> .segment_end = aspeed_spi_segment_end,
> .segment_reg = aspeed_spi_segment_reg,
> @@ -850,6 +1119,10 @@ static const struct aspeed_spi_data ast2500_spi_data = {
> .hastype = false,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xfffff0ff,
> + .hdiv_max = 1,
> + .calibrate = aspeed_spi_calibrate,
> .segment_start = aspeed_spi_segment_start,
> .segment_end = aspeed_spi_segment_end,
> .segment_reg = aspeed_spi_segment_reg,
> @@ -861,6 +1134,10 @@ static const struct aspeed_spi_data ast2600_fmc_data = {
> .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xf0fff0ff,
> + .hdiv_max = 2,
> + .calibrate = aspeed_spi_ast2600_calibrate,
> .segment_start = aspeed_spi_segment_ast2600_start,
> .segment_end = aspeed_spi_segment_ast2600_end,
> .segment_reg = aspeed_spi_segment_ast2600_reg,
> @@ -872,6 +1149,10 @@ static const struct aspeed_spi_data ast2600_spi_data = {
> .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD,
> .we0 = 16,
> .ctl0 = CE0_CTRL_REG,
> + .timing = CE0_TIMING_COMPENSATION_REG,
> + .hclk_mask = 0xf0fff0ff,
> + .hdiv_max = 2,
> + .calibrate = aspeed_spi_ast2600_calibrate,
> .segment_start = aspeed_spi_segment_ast2600_start,
> .segment_end = aspeed_spi_segment_ast2600_end,
> .segment_reg = aspeed_spi_segment_ast2600_reg,
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 22:45 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:45 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> All these controllers support at least Dual SPI. Update the DTs.
>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Thanks. I'll apply this to the aspeed tree now.
Did you also have a patch to add a second flash chip to the AST2400 FMC?
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
> arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
> arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
> 3 files changed, 21 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index 9ae67e83cf60..31e6569db97e 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -64,27 +64,32 @@ fmc: spi@1e620000 {
> flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> spi-max-frequency = <50000000>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@3 {
> reg = < 3 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@4 {
> reg = < 4 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -100,6 +105,7 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index c3e0a8e13c8a..29bf017899b6 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -66,18 +66,21 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -93,12 +96,14 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -114,12 +119,14 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index 1ad05dde19d2..ce93c56a21a7 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -106,18 +106,21 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -133,12 +136,14 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -154,18 +159,21 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
@ 2022-03-02 22:45 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:45 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> All these controllers support at least Dual SPI. Update the DTs.
>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Thanks. I'll apply this to the aspeed tree now.
Did you also have a patch to add a second flash chip to the AST2400 FMC?
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
> arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
> arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
> 3 files changed, 21 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index 9ae67e83cf60..31e6569db97e 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -64,27 +64,32 @@ fmc: spi@1e620000 {
> flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> spi-max-frequency = <50000000>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@3 {
> reg = < 3 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@4 {
> reg = < 4 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -100,6 +105,7 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index c3e0a8e13c8a..29bf017899b6 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -66,18 +66,21 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -93,12 +96,14 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -114,12 +119,14 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index 1ad05dde19d2..ce93c56a21a7 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -106,18 +106,21 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -133,12 +136,14 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -154,18 +159,21 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> --
> 2.34.1
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
@ 2022-03-02 22:45 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:45 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> All these controllers support at least Dual SPI. Update the DTs.
>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Thanks. I'll apply this to the aspeed tree now.
Did you also have a patch to add a second flash chip to the AST2400 FMC?
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
> arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
> arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
> 3 files changed, 21 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index 9ae67e83cf60..31e6569db97e 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -64,27 +64,32 @@ fmc: spi@1e620000 {
> flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> spi-max-frequency = <50000000>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@3 {
> reg = < 3 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@4 {
> reg = < 4 >;
> compatible = "jedec,spi-nor";
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -100,6 +105,7 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index c3e0a8e13c8a..29bf017899b6 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -66,18 +66,21 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -93,12 +96,14 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -114,12 +119,14 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index 1ad05dde19d2..ce93c56a21a7 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -106,18 +106,21 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -133,12 +136,14 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> @@ -154,18 +159,21 @@ flash@0 {
> reg = < 0 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@1 {
> reg = < 1 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> flash@2 {
> reg = < 2 >;
> compatible = "jedec,spi-nor";
> spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <2>;
> status = "disabled";
> };
> };
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 05/10] spi: aspeed: Add support for direct mapping
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 22:48 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:48 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> Use direct mapping to read the flash device contents. This operation
> mode is called "Command mode" on Aspeed SoC SMC controllers. It uses a
> Control Register for the settings to apply when a memory operation is
> performed on the flash device mapping window.
>
> If the window is not big enough, fall back to the "User mode" to
> perform the read.
>
> Since direct mapping now handles all reads of the flash device
> contents, also use memcpy_fromio for other address spaces, such as
> SFDP.
>
> Direct mapping for writes will come later when validated.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 67 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index 688f9472e0d7..b4854b521477 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -324,8 +324,8 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
> if (!op->addr.nbytes)
> ret = aspeed_spi_read_reg(chip, op);
> else
> - ret = aspeed_spi_read_user(chip, op, op->addr.val,
> - op->data.nbytes, op->data.buf.in);
> + memcpy_fromio(op->data.buf.in, chip->ahb_base + op->addr.val,
> + op->data.nbytes);
> } else {
> if (!op->addr.nbytes)
> ret = aspeed_spi_write_reg(chip, op);
> @@ -405,10 +405,73 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
> return chip->ahb_window_size ? 0 : -1;
> }
>
> +static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> +{
> + struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> + struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
> + struct spi_mem_op *op = &desc->info.op_tmpl;
> + u32 ctl_val;
> + int ret = 0;
> +
> + chip->clk_freq = desc->mem->spi->max_speed_hz;
> +
> + /* Only for reads */
> + if (op->data.dir != SPI_MEM_DATA_IN)
> + return -EOPNOTSUPP;
> +
> + if (desc->info.length > chip->ahb_window_size)
> + dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
> + chip->cs, chip->ahb_window_size >> 20);
> +
> + /* Define the default IO read settings */
> + ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
> + ctl_val |= aspeed_spi_get_io_mode(op) |
> + op->cmd.opcode << CTRL_COMMAND_SHIFT |
> + CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth) |
> + CTRL_IO_MODE_READ;
> +
> + /* Tune 4BYTE address mode */
> + if (op->addr.nbytes) {
> + u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
> +
> + if (op->addr.nbytes == 4)
> + addr_mode |= (0x11 << chip->cs);
> + else
> + addr_mode &= ~(0x11 << chip->cs);
> + writel(addr_mode, aspi->regs + CE_CTRL_REG);
> + }
> +
> + /* READ mode is the controller default setting */
> + chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
> + writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
> +
> + dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
> + chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
> +
> + return ret;
> +}
> +
> +static int aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
> + u64 offset, size_t len, void *buf)
> +{
> + struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> + struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
> +
> + /* Switch to USER command mode if mapping window is too small */
> + if (chip->ahb_window_size < offset + len)
> + aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
> + else
> + memcpy_fromio(buf, chip->ahb_base + offset, len);
> +
> + return len;
> +}
> +
> static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
> .supports_op = aspeed_spi_supports_op,
> .exec_op = aspeed_spi_exec_op,
> .get_name = aspeed_spi_get_name,
> + .dirmap_create = aspeed_spi_dirmap_create,
> + .dirmap_read = aspeed_spi_dirmap_read,
> };
>
> static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 05/10] spi: aspeed: Add support for direct mapping
@ 2022-03-02 22:48 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:48 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> Use direct mapping to read the flash device contents. This operation
> mode is called "Command mode" on Aspeed SoC SMC controllers. It uses a
> Control Register for the settings to apply when a memory operation is
> performed on the flash device mapping window.
>
> If the window is not big enough, fall back to the "User mode" to
> perform the read.
>
> Since direct mapping now handles all reads of the flash device
> contents, also use memcpy_fromio for other address spaces, such as
> SFDP.
>
> Direct mapping for writes will come later when validated.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 67 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index 688f9472e0d7..b4854b521477 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -324,8 +324,8 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
> if (!op->addr.nbytes)
> ret = aspeed_spi_read_reg(chip, op);
> else
> - ret = aspeed_spi_read_user(chip, op, op->addr.val,
> - op->data.nbytes, op->data.buf.in);
> + memcpy_fromio(op->data.buf.in, chip->ahb_base + op->addr.val,
> + op->data.nbytes);
> } else {
> if (!op->addr.nbytes)
> ret = aspeed_spi_write_reg(chip, op);
> @@ -405,10 +405,73 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
> return chip->ahb_window_size ? 0 : -1;
> }
>
> +static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> +{
> + struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> + struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
> + struct spi_mem_op *op = &desc->info.op_tmpl;
> + u32 ctl_val;
> + int ret = 0;
> +
> + chip->clk_freq = desc->mem->spi->max_speed_hz;
> +
> + /* Only for reads */
> + if (op->data.dir != SPI_MEM_DATA_IN)
> + return -EOPNOTSUPP;
> +
> + if (desc->info.length > chip->ahb_window_size)
> + dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
> + chip->cs, chip->ahb_window_size >> 20);
> +
> + /* Define the default IO read settings */
> + ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
> + ctl_val |= aspeed_spi_get_io_mode(op) |
> + op->cmd.opcode << CTRL_COMMAND_SHIFT |
> + CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth) |
> + CTRL_IO_MODE_READ;
> +
> + /* Tune 4BYTE address mode */
> + if (op->addr.nbytes) {
> + u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
> +
> + if (op->addr.nbytes == 4)
> + addr_mode |= (0x11 << chip->cs);
> + else
> + addr_mode &= ~(0x11 << chip->cs);
> + writel(addr_mode, aspi->regs + CE_CTRL_REG);
> + }
> +
> + /* READ mode is the controller default setting */
> + chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
> + writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
> +
> + dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
> + chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
> +
> + return ret;
> +}
> +
> +static int aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
> + u64 offset, size_t len, void *buf)
> +{
> + struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> + struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
> +
> + /* Switch to USER command mode if mapping window is too small */
> + if (chip->ahb_window_size < offset + len)
> + aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
> + else
> + memcpy_fromio(buf, chip->ahb_base + offset, len);
> +
> + return len;
> +}
> +
> static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
> .supports_op = aspeed_spi_supports_op,
> .exec_op = aspeed_spi_exec_op,
> .get_name = aspeed_spi_get_name,
> + .dirmap_create = aspeed_spi_dirmap_create,
> + .dirmap_read = aspeed_spi_dirmap_read,
> };
>
> static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
> --
> 2.34.1
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 05/10] spi: aspeed: Add support for direct mapping
@ 2022-03-02 22:48 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:48 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> Use direct mapping to read the flash device contents. This operation
> mode is called "Command mode" on Aspeed SoC SMC controllers. It uses a
> Control Register for the settings to apply when a memory operation is
> performed on the flash device mapping window.
>
> If the window is not big enough, fall back to the "User mode" to
> perform the read.
>
> Since direct mapping now handles all reads of the flash device
> contents, also use memcpy_fromio for other address spaces, such as
> SFDP.
>
> Direct mapping for writes will come later when validated.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/spi/spi-aspeed-smc.c | 67 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
> index 688f9472e0d7..b4854b521477 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -324,8 +324,8 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
> if (!op->addr.nbytes)
> ret = aspeed_spi_read_reg(chip, op);
> else
> - ret = aspeed_spi_read_user(chip, op, op->addr.val,
> - op->data.nbytes, op->data.buf.in);
> + memcpy_fromio(op->data.buf.in, chip->ahb_base + op->addr.val,
> + op->data.nbytes);
> } else {
> if (!op->addr.nbytes)
> ret = aspeed_spi_write_reg(chip, op);
> @@ -405,10 +405,73 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
> return chip->ahb_window_size ? 0 : -1;
> }
>
> +static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
> +{
> + struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> + struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
> + struct spi_mem_op *op = &desc->info.op_tmpl;
> + u32 ctl_val;
> + int ret = 0;
> +
> + chip->clk_freq = desc->mem->spi->max_speed_hz;
> +
> + /* Only for reads */
> + if (op->data.dir != SPI_MEM_DATA_IN)
> + return -EOPNOTSUPP;
> +
> + if (desc->info.length > chip->ahb_window_size)
> + dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
> + chip->cs, chip->ahb_window_size >> 20);
> +
> + /* Define the default IO read settings */
> + ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
> + ctl_val |= aspeed_spi_get_io_mode(op) |
> + op->cmd.opcode << CTRL_COMMAND_SHIFT |
> + CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth) |
> + CTRL_IO_MODE_READ;
> +
> + /* Tune 4BYTE address mode */
> + if (op->addr.nbytes) {
> + u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
> +
> + if (op->addr.nbytes == 4)
> + addr_mode |= (0x11 << chip->cs);
> + else
> + addr_mode &= ~(0x11 << chip->cs);
> + writel(addr_mode, aspi->regs + CE_CTRL_REG);
> + }
> +
> + /* READ mode is the controller default setting */
> + chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
> + writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
> +
> + dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
> + chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
> +
> + return ret;
> +}
> +
> +static int aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
> + u64 offset, size_t len, void *buf)
> +{
> + struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
> + struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
> +
> + /* Switch to USER command mode if mapping window is too small */
> + if (chip->ahb_window_size < offset + len)
> + aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
> + else
> + memcpy_fromio(buf, chip->ahb_base + offset, len);
> +
> + return len;
> +}
> +
> static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
> .supports_op = aspeed_spi_supports_op,
> .exec_op = aspeed_spi_exec_op,
> .get_name = aspeed_spi_get_name,
> + .dirmap_create = aspeed_spi_dirmap_create,
> + .dirmap_read = aspeed_spi_dirmap_read,
> };
>
> static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
2022-03-02 22:45 ` Joel Stanley
(?)
@ 2022-03-02 22:48 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:48 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 22:45, Joel Stanley <joel@jms.id.au> wrote:
>
> On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
> >
> > All these controllers support at least Dual SPI. Update the DTs.
> >
> > Reviewed-by: Joel Stanley <joel@jms.id.au>
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> Thanks. I'll apply this to the aspeed tree now.
>
> Did you also have a patch to add a second flash chip to the AST2400 FMC?
That was a reference to the discussion on the openbmc list with Tao. I
was mistaken; the flash chips are there, but they lack the
spi-max-frequency property.
>
> > ---
> > arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
> > arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
> > arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
> > 3 files changed, 21 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> > index 9ae67e83cf60..31e6569db97e 100644
> > --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> > @@ -64,27 +64,32 @@ fmc: spi@1e620000 {
> > flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > spi-max-frequency = <50000000>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@3 {
> > reg = < 3 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@4 {
> > reg = < 4 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -100,6 +105,7 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> > index c3e0a8e13c8a..29bf017899b6 100644
> > --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> > @@ -66,18 +66,21 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -93,12 +96,14 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -114,12 +119,14 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> > index 1ad05dde19d2..ce93c56a21a7 100644
> > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > @@ -106,18 +106,21 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -133,12 +136,14 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -154,18 +159,21 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
@ 2022-03-02 22:48 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:48 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 22:45, Joel Stanley <joel@jms.id.au> wrote:
>
> On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
> >
> > All these controllers support at least Dual SPI. Update the DTs.
> >
> > Reviewed-by: Joel Stanley <joel@jms.id.au>
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> Thanks. I'll apply this to the aspeed tree now.
>
> Did you also have a patch to add a second flash chip to the AST2400 FMC?
That was a reference to the discussion on the openbmc list with Tao. I
was mistaken; the flash chips are there, but they lack the
spi-max-frequency property.
>
> > ---
> > arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
> > arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
> > arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
> > 3 files changed, 21 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> > index 9ae67e83cf60..31e6569db97e 100644
> > --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> > @@ -64,27 +64,32 @@ fmc: spi@1e620000 {
> > flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > spi-max-frequency = <50000000>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@3 {
> > reg = < 3 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@4 {
> > reg = < 4 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -100,6 +105,7 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> > index c3e0a8e13c8a..29bf017899b6 100644
> > --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> > @@ -66,18 +66,21 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -93,12 +96,14 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -114,12 +119,14 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> > index 1ad05dde19d2..ce93c56a21a7 100644
> > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > @@ -106,18 +106,21 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -133,12 +136,14 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -154,18 +159,21 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > --
> > 2.34.1
> >
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
@ 2022-03-02 22:48 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 22:48 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 22:45, Joel Stanley <joel@jms.id.au> wrote:
>
> On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
> >
> > All these controllers support at least Dual SPI. Update the DTs.
> >
> > Reviewed-by: Joel Stanley <joel@jms.id.au>
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> Thanks. I'll apply this to the aspeed tree now.
>
> Did you also have a patch to add a second flash chip to the AST2400 FMC?
That was a reference to the discussion on the openbmc list with Tao. I
was mistaken; the flash chips are there, but they lack the
spi-max-frequency property.
>
> > ---
> > arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
> > arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
> > arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
> > 3 files changed, 21 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> > index 9ae67e83cf60..31e6569db97e 100644
> > --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> > @@ -64,27 +64,32 @@ fmc: spi@1e620000 {
> > flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > spi-max-frequency = <50000000>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@3 {
> > reg = < 3 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@4 {
> > reg = < 4 >;
> > compatible = "jedec,spi-nor";
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -100,6 +105,7 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> > index c3e0a8e13c8a..29bf017899b6 100644
> > --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> > @@ -66,18 +66,21 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -93,12 +96,14 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -114,12 +119,14 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> > index 1ad05dde19d2..ce93c56a21a7 100644
> > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > @@ -106,18 +106,21 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -133,12 +136,14 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > @@ -154,18 +159,21 @@ flash@0 {
> > reg = < 0 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@1 {
> > reg = < 1 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > flash@2 {
> > reg = < 2 >;
> > compatible = "jedec,spi-nor";
> > spi-max-frequency = <50000000>;
> > + spi-rx-bus-width = <2>;
> > status = "disabled";
> > };
> > };
> > --
> > 2.34.1
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 04/10] spi: spi-mem: Add driver for Aspeed SMC controllers
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-02 23:38 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 23:38 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> This SPI driver adds support for the Aspeed static memory controllers
> of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
>
> * AST2600 Firmware SPI Memory Controller (FMC)
> . BMC firmware
> . 3 chip select pins (CE0 ~ CE2)
> . Only supports SPI type flash memory
> . different segment register interface
> . single, dual and quad mode.
>
> * AST2600 SPI Flash Controller (SPI1 and SPI2)
> . host firmware
> . 2 chip select pins (CE0 ~ CE1)
> . different segment register interface
> . single, dual and quad mode.
>
> * AST2500 Firmware SPI Memory Controller (FMC)
> . BMC firmware
> . 3 chip select pins (CE0 ~ CE2)
> . supports SPI type flash memory (CE0-CE1)
> . CE2 can be of NOR type flash but this is not supported by the driver
> . single, dual mode.
>
> * AST2500 SPI Flash Controller (SPI1 and SPI2)
> . host firmware
> . 2 chip select pins (CE0 ~ CE1)
> . single, dual mode.
>
> * AST2400 New Static Memory Controller (also referred as FMC)
> . BMC firmware
> . New register set
> . 5 chip select pins (CE0 ∼ CE4)
> . supports NOR flash, NAND flash and SPI flash memory.
> . single, dual and quad mode.
>
> Each controller has a memory range on which flash devices contents are
> mapped. Each device is assigned a window that can be changed at bootime
> with the Segment Address Registers.
>
> Each SPI flash device can then be accessed in two modes: Command and
> User. When in User mode, SPI transfers are initiated with accesses to
> the memory segment of a device. When in Command mode, memory
> operations on the memory segment of a device generate SPI commands
> automatically using a Control Register for the settings.
>
> This initial patch adds support for User mode. Command mode needs a little
> more work to check that the memory window on the AHB bus fits the device
> size. It will come later when support for direct mapping is added.
>
> Single and dual mode RX transfers are supported. Other types than SPI
> are not supported.
>
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 04/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-02 23:38 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 23:38 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> This SPI driver adds support for the Aspeed static memory controllers
> of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
>
> * AST2600 Firmware SPI Memory Controller (FMC)
> . BMC firmware
> . 3 chip select pins (CE0 ~ CE2)
> . Only supports SPI type flash memory
> . different segment register interface
> . single, dual and quad mode.
>
> * AST2600 SPI Flash Controller (SPI1 and SPI2)
> . host firmware
> . 2 chip select pins (CE0 ~ CE1)
> . different segment register interface
> . single, dual and quad mode.
>
> * AST2500 Firmware SPI Memory Controller (FMC)
> . BMC firmware
> . 3 chip select pins (CE0 ~ CE2)
> . supports SPI type flash memory (CE0-CE1)
> . CE2 can be of NOR type flash but this is not supported by the driver
> . single, dual mode.
>
> * AST2500 SPI Flash Controller (SPI1 and SPI2)
> . host firmware
> . 2 chip select pins (CE0 ~ CE1)
> . single, dual mode.
>
> * AST2400 New Static Memory Controller (also referred as FMC)
> . BMC firmware
> . New register set
> . 5 chip select pins (CE0 ∼ CE4)
> . supports NOR flash, NAND flash and SPI flash memory.
> . single, dual and quad mode.
>
> Each controller has a memory range on which flash devices contents are
> mapped. Each device is assigned a window that can be changed at bootime
> with the Segment Address Registers.
>
> Each SPI flash device can then be accessed in two modes: Command and
> User. When in User mode, SPI transfers are initiated with accesses to
> the memory segment of a device. When in Command mode, memory
> operations on the memory segment of a device generate SPI commands
> automatically using a Control Register for the settings.
>
> This initial patch adds support for User mode. Command mode needs a little
> more work to check that the memory window on the AHB bus fits the device
> size. It will come later when support for direct mapping is added.
>
> Single and dual mode RX transfers are supported. Other types than SPI
> are not supported.
>
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 04/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-02 23:38 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-02 23:38 UTC (permalink / raw)
To: Cédric Le Goater
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> This SPI driver adds support for the Aspeed static memory controllers
> of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
>
> * AST2600 Firmware SPI Memory Controller (FMC)
> . BMC firmware
> . 3 chip select pins (CE0 ~ CE2)
> . Only supports SPI type flash memory
> . different segment register interface
> . single, dual and quad mode.
>
> * AST2600 SPI Flash Controller (SPI1 and SPI2)
> . host firmware
> . 2 chip select pins (CE0 ~ CE1)
> . different segment register interface
> . single, dual and quad mode.
>
> * AST2500 Firmware SPI Memory Controller (FMC)
> . BMC firmware
> . 3 chip select pins (CE0 ~ CE2)
> . supports SPI type flash memory (CE0-CE1)
> . CE2 can be of NOR type flash but this is not supported by the driver
> . single, dual mode.
>
> * AST2500 SPI Flash Controller (SPI1 and SPI2)
> . host firmware
> . 2 chip select pins (CE0 ~ CE1)
> . single, dual mode.
>
> * AST2400 New Static Memory Controller (also referred as FMC)
> . BMC firmware
> . New register set
> . 5 chip select pins (CE0 ∼ CE4)
> . supports NOR flash, NAND flash and SPI flash memory.
> . single, dual and quad mode.
>
> Each controller has a memory range on which flash devices contents are
> mapped. Each device is assigned a window that can be changed at bootime
> with the Segment Address Registers.
>
> Each SPI flash device can then be accessed in two modes: Command and
> User. When in User mode, SPI transfers are initiated with accesses to
> the memory segment of a device. When in Command mode, memory
> operations on the memory segment of a device generate SPI commands
> automatically using a Control Register for the settings.
>
> This initial patch adds support for User mode. Command mode needs a little
> more work to check that the memory window on the AHB bus fits the device
> size. It will come later when support for direct mapping is added.
>
> Single and dual mode RX transfers are supported. Other types than SPI
> are not supported.
>
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
2022-03-02 22:48 ` Joel Stanley
(?)
@ 2022-03-03 7:57 ` Cédric Le Goater
-1 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-03 7:57 UTC (permalink / raw)
To: Joel Stanley
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On 3/2/22 23:48, Joel Stanley wrote:
> On Wed, 2 Mar 2022 at 22:45, Joel Stanley <joel@jms.id.au> wrote:
>>
>> On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>>>
>>> All these controllers support at least Dual SPI. Update the DTs.
>>>
>>> Reviewed-by: Joel Stanley <joel@jms.id.au>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>
>> Thanks. I'll apply this to the aspeed tree now.
>>
>> Did you also have a patch to add a second flash chip to the AST2400 FMC?
>
> That was a reference to the discussion on the openbmc list with Tao. I
> was mistaken; the flash chips are there, but they lack the
> spi-max-frequency property.
Yes.
I will include a patch in v3 for the second flash chip of the AST2400 FMC.
Thanks,
C.
>
>>
>>> ---
>>> arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
>>> arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
>>> arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
>>> 3 files changed, 21 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
>>> index 9ae67e83cf60..31e6569db97e 100644
>>> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
>>> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
>>> @@ -64,27 +64,32 @@ fmc: spi@1e620000 {
>>> flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> spi-max-frequency = <50000000>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@3 {
>>> reg = < 3 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@4 {
>>> reg = < 4 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -100,6 +105,7 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
>>> index c3e0a8e13c8a..29bf017899b6 100644
>>> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
>>> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
>>> @@ -66,18 +66,21 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -93,12 +96,14 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -114,12 +119,14 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
>>> index 1ad05dde19d2..ce93c56a21a7 100644
>>> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
>>> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
>>> @@ -106,18 +106,21 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -133,12 +136,14 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -154,18 +159,21 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> --
>>> 2.34.1
>>>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
@ 2022-03-03 7:57 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-03 7:57 UTC (permalink / raw)
To: Joel Stanley
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On 3/2/22 23:48, Joel Stanley wrote:
> On Wed, 2 Mar 2022 at 22:45, Joel Stanley <joel@jms.id.au> wrote:
>>
>> On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>>>
>>> All these controllers support at least Dual SPI. Update the DTs.
>>>
>>> Reviewed-by: Joel Stanley <joel@jms.id.au>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>
>> Thanks. I'll apply this to the aspeed tree now.
>>
>> Did you also have a patch to add a second flash chip to the AST2400 FMC?
>
> That was a reference to the discussion on the openbmc list with Tao. I
> was mistaken; the flash chips are there, but they lack the
> spi-max-frequency property.
Yes.
I will include a patch in v3 for the second flash chip of the AST2400 FMC.
Thanks,
C.
>
>>
>>> ---
>>> arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
>>> arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
>>> arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
>>> 3 files changed, 21 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
>>> index 9ae67e83cf60..31e6569db97e 100644
>>> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
>>> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
>>> @@ -64,27 +64,32 @@ fmc: spi@1e620000 {
>>> flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> spi-max-frequency = <50000000>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@3 {
>>> reg = < 3 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@4 {
>>> reg = < 4 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -100,6 +105,7 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
>>> index c3e0a8e13c8a..29bf017899b6 100644
>>> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
>>> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
>>> @@ -66,18 +66,21 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -93,12 +96,14 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -114,12 +119,14 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
>>> index 1ad05dde19d2..ce93c56a21a7 100644
>>> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
>>> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
>>> @@ -106,18 +106,21 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -133,12 +136,14 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -154,18 +159,21 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> --
>>> 2.34.1
>>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers
@ 2022-03-03 7:57 ` Cédric Le Goater
0 siblings, 0 replies; 79+ messages in thread
From: Cédric Le Goater @ 2022-03-03 7:57 UTC (permalink / raw)
To: Joel Stanley
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On 3/2/22 23:48, Joel Stanley wrote:
> On Wed, 2 Mar 2022 at 22:45, Joel Stanley <joel@jms.id.au> wrote:
>>
>> On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>>>
>>> All these controllers support at least Dual SPI. Update the DTs.
>>>
>>> Reviewed-by: Joel Stanley <joel@jms.id.au>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>
>> Thanks. I'll apply this to the aspeed tree now.
>>
>> Did you also have a patch to add a second flash chip to the AST2400 FMC?
>
> That was a reference to the discussion on the openbmc list with Tao. I
> was mistaken; the flash chips are there, but they lack the
> spi-max-frequency property.
Yes.
I will include a patch in v3 for the second flash chip of the AST2400 FMC.
Thanks,
C.
>
>>
>>> ---
>>> arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
>>> arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
>>> arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++
>>> 3 files changed, 21 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
>>> index 9ae67e83cf60..31e6569db97e 100644
>>> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
>>> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
>>> @@ -64,27 +64,32 @@ fmc: spi@1e620000 {
>>> flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> spi-max-frequency = <50000000>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@3 {
>>> reg = < 3 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@4 {
>>> reg = < 4 >;
>>> compatible = "jedec,spi-nor";
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -100,6 +105,7 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
>>> index c3e0a8e13c8a..29bf017899b6 100644
>>> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
>>> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
>>> @@ -66,18 +66,21 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -93,12 +96,14 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -114,12 +119,14 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
>>> index 1ad05dde19d2..ce93c56a21a7 100644
>>> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
>>> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
>>> @@ -106,18 +106,21 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -133,12 +136,14 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> @@ -154,18 +159,21 @@ flash@0 {
>>> reg = < 0 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@1 {
>>> reg = < 1 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> flash@2 {
>>> reg = < 2 >;
>>> compatible = "jedec,spi-nor";
>>> spi-max-frequency = <50000000>;
>>> + spi-rx-bus-width = <2>;
>>> status = "disabled";
>>> };
>>> };
>>> --
>>> 2.34.1
>>>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers
2022-03-02 17:31 ` Cédric Le Goater
(?)
@ 2022-03-03 10:01 ` Joel Stanley
-1 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-03 10:01 UTC (permalink / raw)
To: Cédric Le Goater, Tao Ren, John Wang
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> Hi,
>
> This series adds a new SPI driver using the spi-mem interface for the
> Aspeed static memory controllers of the AST2600, AST2500 and AST2400
> SoCs.
>
> * AST2600 Firmware SPI Memory Controller (FMC)
> * AST2600 SPI Flash Controller (SPI1 and SPI2)
I've performed read and write tests on the 2600 controllers, and the
driver seems stable at the settings you have in the device tree.
Tested-by: Joel Stanley <joel@jms.id.au>
I've added Tao and John to cc as they have tested the 2400 and 2500,
and I'm sure will be able to provide some Tested-by.
Cheers,
Joel
> * AST2500 Firmware SPI Memory Controller (FMC)
> * AST2500 SPI Flash Controller (SPI1 and SPI2)
> * AST2400 New Static Memory Controller (also referred as FMC)
> * AST2400 SPI Flash Controller (SPI)
>
> It is based on the current OpenBMC kernel driver [1], using directly
> the MTD SPI-NOR interface and on a patchset [2] previously proposed
> adding support for the AST2600 only. This driver takes a slightly
> different approach to cover all 6 controllers.
>
> It does not make use of the controller register disabling Address and
> Data byte lanes because is not available on the AST2400 SoC. We could
> introduce a specific handler for new features available on recent SoCs
> if needed. As there is not much difference on performance, the driver
> chooses the common denominator: "User mode" which has been heavily
> tested in [1]. "User mode" is also used as a fall back method when
> flash device mapping window is too small.
>
> Problems to address with spi-mem were the configuration of the mapping
> windows and the calibration of the read timings. The driver handles
> them in the direct mapping handler when some knowledge on the size of
> the flash device is know. It is not perfect but not incorrect either.
> The algorithm is one from [1] because it doesn't require the DMA
> registers which are not available on all controllers.
>
> Direct mapping for writes is not supported (yet). I have seen some
> corruption with writes and I preferred to use the safer and proven
> method of the initial driver [1]. We can improve that later.
>
> The driver supports Quad SPI RX transfers on the AST2600 SoC but it
> didn't have the expected results. Therefore it is not activated yet.
> There are some issues on the pinctrl to investigate first.
>
> The series does not remove the current Aspeed SMC driver but prepares
> ground for its removal by changing its CONFIG option. This last step
> can be addressed as a followup when the new driver using the spi-mem
> interface has been sufficiently exposed.
>
> Tested on:
>
> * OpenPOWER Palmetto (AST2400)
> * Facebook Wedge 100 BMC (AST2400) by Tao Ren <rentao.bupt@gmail.com>
> * Evaluation board (AST2500)
> * Inspur FP5280G2 BMC (AST2500) by John Wang <wangzq.jn@gmail.com>
> * Facebook Backpack CMM BMC (AST2500) by Tao Ren <rentao.bupt@gmail.com>
> * OpenPOWER Witherspoon (AST2500)
> * Evaluation board (AST2600 A0 and A3)
> * Rainier board (AST2600)
>
> [1] https://github.com/openbmc/linux/blob/dev-5.15/drivers/mtd/spi-nor/controllers/aspeed-smc.c
> [2] https://patchwork.ozlabs.org/project/linux-aspeed/list/?series=212394
>
> Thanks,
>
> C.
>
> Changes in v2:
>
> - Fixed dt_binding_check warnings (Rob)
> - New entry in MAINTAINERS
> - Addressed Lukas comments regarding the SPI controller registration
> and device removal. Checked with driver bind/unbind
> - Introduced setup and cleanup handlers and removed routine looping
> on the DT children properties (Pratyush)
> - Clarified in commit log requirements for training.
> - Removed defconfig changes of patch 1 since they were reverted in
> the last patch (Joel)
>
> Cédric Le Goater (10):
> mtd: spi-nor: aspeed: Rename Kconfig option
> ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
> dt-bindings: spi: Add Aspeed SMC controllers device tree binding
> spi: spi-mem: Add driver for Aspeed SMC controllers
> spi: aspeed: Add support for direct mapping
> spi: aspeed: Adjust direct mapping to device size
> spi: aspeed: Workaround AST2500 limitations
> spi: aspeed: Add support for the AST2400 SPI controller
> spi: aspeed: Calibrate read timings
> ARM: dts: aspeed: Enable Dual SPI RX transfers
>
> drivers/spi/spi-aspeed-smc.c | 1186 +++++++++++++++++
> .../bindings/spi/aspeed,ast2600-fmc.yaml | 90 ++
> MAINTAINERS | 10 +
> arch/arm/boot/dts/aspeed-g4.dtsi | 12 +-
> arch/arm/boot/dts/aspeed-g5.dtsi | 16 +-
> arch/arm/boot/dts/aspeed-g6.dtsi | 17 +-
> drivers/mtd/spi-nor/controllers/Kconfig | 4 +-
> drivers/mtd/spi-nor/controllers/Makefile | 2 +-
> drivers/spi/Kconfig | 11 +
> drivers/spi/Makefile | 1 +
> 10 files changed, 1330 insertions(+), 19 deletions(-)
> create mode 100644 drivers/spi/spi-aspeed-smc.c
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-03 10:01 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-03 10:01 UTC (permalink / raw)
To: Cédric Le Goater, Tao Ren, John Wang
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> Hi,
>
> This series adds a new SPI driver using the spi-mem interface for the
> Aspeed static memory controllers of the AST2600, AST2500 and AST2400
> SoCs.
>
> * AST2600 Firmware SPI Memory Controller (FMC)
> * AST2600 SPI Flash Controller (SPI1 and SPI2)
I've performed read and write tests on the 2600 controllers, and the
driver seems stable at the settings you have in the device tree.
Tested-by: Joel Stanley <joel@jms.id.au>
I've added Tao and John to cc as they have tested the 2400 and 2500,
and I'm sure will be able to provide some Tested-by.
Cheers,
Joel
> * AST2500 Firmware SPI Memory Controller (FMC)
> * AST2500 SPI Flash Controller (SPI1 and SPI2)
> * AST2400 New Static Memory Controller (also referred as FMC)
> * AST2400 SPI Flash Controller (SPI)
>
> It is based on the current OpenBMC kernel driver [1], using directly
> the MTD SPI-NOR interface and on a patchset [2] previously proposed
> adding support for the AST2600 only. This driver takes a slightly
> different approach to cover all 6 controllers.
>
> It does not make use of the controller register disabling Address and
> Data byte lanes because is not available on the AST2400 SoC. We could
> introduce a specific handler for new features available on recent SoCs
> if needed. As there is not much difference on performance, the driver
> chooses the common denominator: "User mode" which has been heavily
> tested in [1]. "User mode" is also used as a fall back method when
> flash device mapping window is too small.
>
> Problems to address with spi-mem were the configuration of the mapping
> windows and the calibration of the read timings. The driver handles
> them in the direct mapping handler when some knowledge on the size of
> the flash device is know. It is not perfect but not incorrect either.
> The algorithm is one from [1] because it doesn't require the DMA
> registers which are not available on all controllers.
>
> Direct mapping for writes is not supported (yet). I have seen some
> corruption with writes and I preferred to use the safer and proven
> method of the initial driver [1]. We can improve that later.
>
> The driver supports Quad SPI RX transfers on the AST2600 SoC but it
> didn't have the expected results. Therefore it is not activated yet.
> There are some issues on the pinctrl to investigate first.
>
> The series does not remove the current Aspeed SMC driver but prepares
> ground for its removal by changing its CONFIG option. This last step
> can be addressed as a followup when the new driver using the spi-mem
> interface has been sufficiently exposed.
>
> Tested on:
>
> * OpenPOWER Palmetto (AST2400)
> * Facebook Wedge 100 BMC (AST2400) by Tao Ren <rentao.bupt@gmail.com>
> * Evaluation board (AST2500)
> * Inspur FP5280G2 BMC (AST2500) by John Wang <wangzq.jn@gmail.com>
> * Facebook Backpack CMM BMC (AST2500) by Tao Ren <rentao.bupt@gmail.com>
> * OpenPOWER Witherspoon (AST2500)
> * Evaluation board (AST2600 A0 and A3)
> * Rainier board (AST2600)
>
> [1] https://github.com/openbmc/linux/blob/dev-5.15/drivers/mtd/spi-nor/controllers/aspeed-smc.c
> [2] https://patchwork.ozlabs.org/project/linux-aspeed/list/?series=212394
>
> Thanks,
>
> C.
>
> Changes in v2:
>
> - Fixed dt_binding_check warnings (Rob)
> - New entry in MAINTAINERS
> - Addressed Lukas comments regarding the SPI controller registration
> and device removal. Checked with driver bind/unbind
> - Introduced setup and cleanup handlers and removed routine looping
> on the DT children properties (Pratyush)
> - Clarified in commit log requirements for training.
> - Removed defconfig changes of patch 1 since they were reverted in
> the last patch (Joel)
>
> Cédric Le Goater (10):
> mtd: spi-nor: aspeed: Rename Kconfig option
> ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
> dt-bindings: spi: Add Aspeed SMC controllers device tree binding
> spi: spi-mem: Add driver for Aspeed SMC controllers
> spi: aspeed: Add support for direct mapping
> spi: aspeed: Adjust direct mapping to device size
> spi: aspeed: Workaround AST2500 limitations
> spi: aspeed: Add support for the AST2400 SPI controller
> spi: aspeed: Calibrate read timings
> ARM: dts: aspeed: Enable Dual SPI RX transfers
>
> drivers/spi/spi-aspeed-smc.c | 1186 +++++++++++++++++
> .../bindings/spi/aspeed,ast2600-fmc.yaml | 90 ++
> MAINTAINERS | 10 +
> arch/arm/boot/dts/aspeed-g4.dtsi | 12 +-
> arch/arm/boot/dts/aspeed-g5.dtsi | 16 +-
> arch/arm/boot/dts/aspeed-g6.dtsi | 17 +-
> drivers/mtd/spi-nor/controllers/Kconfig | 4 +-
> drivers/mtd/spi-nor/controllers/Makefile | 2 +-
> drivers/spi/Kconfig | 11 +
> drivers/spi/Makefile | 1 +
> 10 files changed, 1330 insertions(+), 19 deletions(-)
> create mode 100644 drivers/spi/spi-aspeed-smc.c
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
>
> --
> 2.34.1
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-03 10:01 ` Joel Stanley
0 siblings, 0 replies; 79+ messages in thread
From: Joel Stanley @ 2022-03-03 10:01 UTC (permalink / raw)
To: Cédric Le Goater, Tao Ren, John Wang
Cc: linux-spi, linux-mtd, Mark Brown, Tudor Ambarus, Pratyush Yadav,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
linux-aspeed, Andrew Jeffery, Chin-Ting Kuo, devicetree,
Rob Herring, Linux ARM, Linux Kernel Mailing List
On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
>
> Hi,
>
> This series adds a new SPI driver using the spi-mem interface for the
> Aspeed static memory controllers of the AST2600, AST2500 and AST2400
> SoCs.
>
> * AST2600 Firmware SPI Memory Controller (FMC)
> * AST2600 SPI Flash Controller (SPI1 and SPI2)
I've performed read and write tests on the 2600 controllers, and the
driver seems stable at the settings you have in the device tree.
Tested-by: Joel Stanley <joel@jms.id.au>
I've added Tao and John to cc as they have tested the 2400 and 2500,
and I'm sure will be able to provide some Tested-by.
Cheers,
Joel
> * AST2500 Firmware SPI Memory Controller (FMC)
> * AST2500 SPI Flash Controller (SPI1 and SPI2)
> * AST2400 New Static Memory Controller (also referred as FMC)
> * AST2400 SPI Flash Controller (SPI)
>
> It is based on the current OpenBMC kernel driver [1], using directly
> the MTD SPI-NOR interface and on a patchset [2] previously proposed
> adding support for the AST2600 only. This driver takes a slightly
> different approach to cover all 6 controllers.
>
> It does not make use of the controller register disabling Address and
> Data byte lanes because is not available on the AST2400 SoC. We could
> introduce a specific handler for new features available on recent SoCs
> if needed. As there is not much difference on performance, the driver
> chooses the common denominator: "User mode" which has been heavily
> tested in [1]. "User mode" is also used as a fall back method when
> flash device mapping window is too small.
>
> Problems to address with spi-mem were the configuration of the mapping
> windows and the calibration of the read timings. The driver handles
> them in the direct mapping handler when some knowledge on the size of
> the flash device is know. It is not perfect but not incorrect either.
> The algorithm is one from [1] because it doesn't require the DMA
> registers which are not available on all controllers.
>
> Direct mapping for writes is not supported (yet). I have seen some
> corruption with writes and I preferred to use the safer and proven
> method of the initial driver [1]. We can improve that later.
>
> The driver supports Quad SPI RX transfers on the AST2600 SoC but it
> didn't have the expected results. Therefore it is not activated yet.
> There are some issues on the pinctrl to investigate first.
>
> The series does not remove the current Aspeed SMC driver but prepares
> ground for its removal by changing its CONFIG option. This last step
> can be addressed as a followup when the new driver using the spi-mem
> interface has been sufficiently exposed.
>
> Tested on:
>
> * OpenPOWER Palmetto (AST2400)
> * Facebook Wedge 100 BMC (AST2400) by Tao Ren <rentao.bupt@gmail.com>
> * Evaluation board (AST2500)
> * Inspur FP5280G2 BMC (AST2500) by John Wang <wangzq.jn@gmail.com>
> * Facebook Backpack CMM BMC (AST2500) by Tao Ren <rentao.bupt@gmail.com>
> * OpenPOWER Witherspoon (AST2500)
> * Evaluation board (AST2600 A0 and A3)
> * Rainier board (AST2600)
>
> [1] https://github.com/openbmc/linux/blob/dev-5.15/drivers/mtd/spi-nor/controllers/aspeed-smc.c
> [2] https://patchwork.ozlabs.org/project/linux-aspeed/list/?series=212394
>
> Thanks,
>
> C.
>
> Changes in v2:
>
> - Fixed dt_binding_check warnings (Rob)
> - New entry in MAINTAINERS
> - Addressed Lukas comments regarding the SPI controller registration
> and device removal. Checked with driver bind/unbind
> - Introduced setup and cleanup handlers and removed routine looping
> on the DT children properties (Pratyush)
> - Clarified in commit log requirements for training.
> - Removed defconfig changes of patch 1 since they were reverted in
> the last patch (Joel)
>
> Cédric Le Goater (10):
> mtd: spi-nor: aspeed: Rename Kconfig option
> ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers
> dt-bindings: spi: Add Aspeed SMC controllers device tree binding
> spi: spi-mem: Add driver for Aspeed SMC controllers
> spi: aspeed: Add support for direct mapping
> spi: aspeed: Adjust direct mapping to device size
> spi: aspeed: Workaround AST2500 limitations
> spi: aspeed: Add support for the AST2400 SPI controller
> spi: aspeed: Calibrate read timings
> ARM: dts: aspeed: Enable Dual SPI RX transfers
>
> drivers/spi/spi-aspeed-smc.c | 1186 +++++++++++++++++
> .../bindings/spi/aspeed,ast2600-fmc.yaml | 90 ++
> MAINTAINERS | 10 +
> arch/arm/boot/dts/aspeed-g4.dtsi | 12 +-
> arch/arm/boot/dts/aspeed-g5.dtsi | 16 +-
> arch/arm/boot/dts/aspeed-g6.dtsi | 17 +-
> drivers/mtd/spi-nor/controllers/Kconfig | 4 +-
> drivers/mtd/spi-nor/controllers/Makefile | 2 +-
> drivers/spi/Kconfig | 11 +
> drivers/spi/Makefile | 1 +
> 10 files changed, 1330 insertions(+), 19 deletions(-)
> create mode 100644 drivers/spi/spi-aspeed-smc.c
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
>
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 05/10] spi: aspeed: Add support for direct mapping
2022-03-02 17:31 ` Cédric Le Goater
` (2 preceding siblings ...)
(?)
@ 2022-03-03 12:02 ` kernel test robot
-1 siblings, 0 replies; 79+ messages in thread
From: kernel test robot @ 2022-03-03 12:02 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: llvm, kbuild-all
Hi "Cédric,
I love your patch! Yet something to improve:
[auto build test ERROR on mtd/spi-nor/next]
[also build test ERROR on joel-aspeed/for-next v5.17-rc6 next-20220302]
[cannot apply to broonie-spi/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/C-dric-Le-Goater/spi-spi-mem-Add-driver-for-Aspeed-SMC-controllers/20220303-013538
base: https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-nor/next
config: arm64-randconfig-r023-20220303 (https://download.01.org/0day-ci/archive/20220303/202203031902.e9vpKoAW-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project d271fc04d5b97b12e6b797c6067d3c96a8d7470e)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/0day-ci/linux/commit/a107d6ec2c4377b805efb71d3ab7921d7a7e61a2
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review C-dric-Le-Goater/spi-spi-mem-Add-driver-for-Aspeed-SMC-controllers/20220303-013538
git checkout a107d6ec2c4377b805efb71d3ab7921d7a7e61a2
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/spi/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/spi/spi-aspeed-smc.c:474:17: error: incompatible function pointer types initializing 'ssize_t (*)(struct spi_mem_dirmap_desc *, u64, size_t, void *)' (aka 'long (*)(struct spi_mem_dirmap_desc *, unsigned long long, unsigned long, void *)') with an expression of type 'int (struct spi_mem_dirmap_desc *, u64, size_t, void *)' (aka 'int (struct spi_mem_dirmap_desc *, unsigned long long, unsigned long, void *)') [-Werror,-Wincompatible-function-pointer-types]
.dirmap_read = aspeed_spi_dirmap_read,
^~~~~~~~~~~~~~~~~~~~~~
1 error generated.
vim +474 drivers/spi/spi-aspeed-smc.c
468
469 static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
470 .supports_op = aspeed_spi_supports_op,
471 .exec_op = aspeed_spi_exec_op,
472 .get_name = aspeed_spi_get_name,
473 .dirmap_create = aspeed_spi_dirmap_create,
> 474 .dirmap_read = aspeed_spi_dirmap_read,
475 };
476
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers
2022-03-03 10:01 ` Joel Stanley
(?)
@ 2022-03-04 7:57 ` Tao Ren
-1 siblings, 0 replies; 79+ messages in thread
From: Tao Ren @ 2022-03-04 7:57 UTC (permalink / raw)
To: Joel Stanley
Cc: Cédric Le Goater, John Wang, linux-spi, linux-mtd,
Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Andrew Jeffery, Chin-Ting Kuo, devicetree, Rob Herring,
Linux ARM, Linux Kernel Mailing List
On Thu, Mar 03, 2022 at 10:01:20AM +0000, Joel Stanley wrote:
> On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
> >
> > Hi,
> >
> > This series adds a new SPI driver using the spi-mem interface for the
> > Aspeed static memory controllers of the AST2600, AST2500 and AST2400
> > SoCs.
> >
> > * AST2600 Firmware SPI Memory Controller (FMC)
> > * AST2600 SPI Flash Controller (SPI1 and SPI2)
>
> I've performed read and write tests on the 2600 controllers, and the
> driver seems stable at the settings you have in the device tree.
>
> Tested-by: Joel Stanley <joel@jms.id.au>
>
> I've added Tao and John to cc as they have tested the 2400 and 2500,
> and I'm sure will be able to provide some Tested-by.
>
> Cheers,
>
> Joel
I've tested the patch series on ast2400 (wedge100) and ast2500 (cmm) by
reading/writing FMC flash0 and flash1 for several times, and no issues
observed so far.
Tested-by: Tao Ren <rentao.bupt@gmail.com>
Cheers,
Tao
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-04 7:57 ` Tao Ren
0 siblings, 0 replies; 79+ messages in thread
From: Tao Ren @ 2022-03-04 7:57 UTC (permalink / raw)
To: Joel Stanley
Cc: Cédric Le Goater, John Wang, linux-spi, linux-mtd,
Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Andrew Jeffery, Chin-Ting Kuo, devicetree, Rob Herring,
Linux ARM, Linux Kernel Mailing List
On Thu, Mar 03, 2022 at 10:01:20AM +0000, Joel Stanley wrote:
> On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
> >
> > Hi,
> >
> > This series adds a new SPI driver using the spi-mem interface for the
> > Aspeed static memory controllers of the AST2600, AST2500 and AST2400
> > SoCs.
> >
> > * AST2600 Firmware SPI Memory Controller (FMC)
> > * AST2600 SPI Flash Controller (SPI1 and SPI2)
>
> I've performed read and write tests on the 2600 controllers, and the
> driver seems stable at the settings you have in the device tree.
>
> Tested-by: Joel Stanley <joel@jms.id.au>
>
> I've added Tao and John to cc as they have tested the 2400 and 2500,
> and I'm sure will be able to provide some Tested-by.
>
> Cheers,
>
> Joel
I've tested the patch series on ast2400 (wedge100) and ast2500 (cmm) by
reading/writing FMC flash0 and flash1 for several times, and no issues
observed so far.
Tested-by: Tao Ren <rentao.bupt@gmail.com>
Cheers,
Tao
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers
@ 2022-03-04 7:57 ` Tao Ren
0 siblings, 0 replies; 79+ messages in thread
From: Tao Ren @ 2022-03-04 7:57 UTC (permalink / raw)
To: Joel Stanley
Cc: Cédric Le Goater, John Wang, linux-spi, linux-mtd,
Mark Brown, Tudor Ambarus, Pratyush Yadav, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, linux-aspeed,
Andrew Jeffery, Chin-Ting Kuo, devicetree, Rob Herring,
Linux ARM, Linux Kernel Mailing List
On Thu, Mar 03, 2022 at 10:01:20AM +0000, Joel Stanley wrote:
> On Wed, 2 Mar 2022 at 17:31, Cédric Le Goater <clg@kaod.org> wrote:
> >
> > Hi,
> >
> > This series adds a new SPI driver using the spi-mem interface for the
> > Aspeed static memory controllers of the AST2600, AST2500 and AST2400
> > SoCs.
> >
> > * AST2600 Firmware SPI Memory Controller (FMC)
> > * AST2600 SPI Flash Controller (SPI1 and SPI2)
>
> I've performed read and write tests on the 2600 controllers, and the
> driver seems stable at the settings you have in the device tree.
>
> Tested-by: Joel Stanley <joel@jms.id.au>
>
> I've added Tao and John to cc as they have tested the 2400 and 2500,
> and I'm sure will be able to provide some Tested-by.
>
> Cheers,
>
> Joel
I've tested the patch series on ast2400 (wedge100) and ast2500 (cmm) by
reading/writing FMC flash0 and flash1 for several times, and no issues
observed so far.
Tested-by: Tao Ren <rentao.bupt@gmail.com>
Cheers,
Tao
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^ permalink raw reply [flat|nested] 79+ messages in thread
end of thread, other threads:[~2022-03-04 7:59 UTC | newest]
Thread overview: 79+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-02 17:31 [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` [PATCH v2 01/10] mtd: spi-nor: aspeed: Rename Kconfig option Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 22:16 ` Joel Stanley
2022-03-02 22:16 ` Joel Stanley
2022-03-02 22:16 ` Joel Stanley
2022-03-02 17:31 ` [PATCH v2 02/10] ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 22:18 ` Joel Stanley
2022-03-02 22:18 ` Joel Stanley
2022-03-02 22:18 ` Joel Stanley
2022-03-02 17:31 ` [PATCH v2 03/10] dt-bindings: spi: Add Aspeed SMC controllers device tree binding Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 21:26 ` Rob Herring
2022-03-02 21:26 ` Rob Herring
2022-03-02 21:26 ` Rob Herring
2022-03-02 22:20 ` Joel Stanley
2022-03-02 22:20 ` Joel Stanley
2022-03-02 22:20 ` Joel Stanley
2022-03-02 17:31 ` [PATCH v2 04/10] spi: spi-mem: Add driver for Aspeed SMC controllers Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 23:38 ` Joel Stanley
2022-03-02 23:38 ` Joel Stanley
2022-03-02 23:38 ` Joel Stanley
2022-03-02 17:31 ` [PATCH v2 05/10] spi: aspeed: Add support for direct mapping Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 22:48 ` Joel Stanley
2022-03-02 22:48 ` Joel Stanley
2022-03-02 22:48 ` Joel Stanley
2022-03-03 12:02 ` kernel test robot
2022-03-02 17:31 ` [PATCH v2 06/10] spi: aspeed: Adjust direct mapping to device size Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 22:31 ` Joel Stanley
2022-03-02 22:31 ` Joel Stanley
2022-03-02 22:31 ` Joel Stanley
2022-03-02 17:31 ` [PATCH v2 07/10] spi: aspeed: Workaround AST2500 limitations Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 22:30 ` Joel Stanley
2022-03-02 22:30 ` Joel Stanley
2022-03-02 22:30 ` Joel Stanley
2022-03-02 17:31 ` [PATCH v2 08/10] spi: aspeed: Add support for the AST2400 SPI controller Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 22:33 ` Joel Stanley
2022-03-02 22:33 ` Joel Stanley
2022-03-02 22:33 ` Joel Stanley
2022-03-02 17:31 ` [PATCH v2 09/10] spi: aspeed: Calibrate read timings Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 22:44 ` Joel Stanley
2022-03-02 22:44 ` Joel Stanley
2022-03-02 22:44 ` Joel Stanley
2022-03-02 17:31 ` [PATCH v2 10/10] ARM: dts: aspeed: Enable Dual SPI RX transfers Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 17:31 ` Cédric Le Goater
2022-03-02 22:45 ` Joel Stanley
2022-03-02 22:45 ` Joel Stanley
2022-03-02 22:45 ` Joel Stanley
2022-03-02 22:48 ` Joel Stanley
2022-03-02 22:48 ` Joel Stanley
2022-03-02 22:48 ` Joel Stanley
2022-03-03 7:57 ` Cédric Le Goater
2022-03-03 7:57 ` Cédric Le Goater
2022-03-03 7:57 ` Cédric Le Goater
2022-03-03 10:01 ` [PATCH v2 00/10] spi: spi-mem: Add driver for Aspeed SMC controllers Joel Stanley
2022-03-03 10:01 ` Joel Stanley
2022-03-03 10:01 ` Joel Stanley
2022-03-04 7:57 ` Tao Ren
2022-03-04 7:57 ` Tao Ren
2022-03-04 7:57 ` Tao Ren
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