* [PATCH v2 0/3] Enhancements to AMD pinctrl and implementation of AMD pinmux
@ 2022-05-24 7:40 Basavaraj Natikar
2022-05-24 7:40 ` [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP Basavaraj Natikar
` (2 more replies)
0 siblings, 3 replies; 23+ messages in thread
From: Basavaraj Natikar @ 2022-05-24 7:40 UTC (permalink / raw)
To: Shyam-sundar.S-k, linus.walleij, linux-gpio; +Cc: Basavaraj Natikar
Changes include enhancements to pinctrl-amd and implementing
AMD pinmux functionalities.
v2:
- Fix for initializer element is not a compile-time constant
on riscv architecture reported by kernel test robot
<lkp@intel.com>.
Link: https://lore.kernel.org/all/202205240107.bryIFhOh-lkp@intel.com/
Basavaraj Natikar (3):
pinctrl: amd: Define and use PINCTRL_GRP
pinctrl: amd: Get and update IOMUX details
pinctrl: amd: Implement pinmux functionality
drivers/pinctrl/pinctrl-amd.c | 144 +++++
drivers/pinctrl/pinctrl-amd.h | 1079 ++++++++++++++++++++++++++++++++-
2 files changed, 1192 insertions(+), 31 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP 2022-05-24 7:40 [PATCH v2 0/3] Enhancements to AMD pinctrl and implementation of AMD pinmux Basavaraj Natikar @ 2022-05-24 7:40 ` Basavaraj Natikar 2022-05-24 9:36 ` Linus Walleij ` (2 more replies) 2022-05-24 7:40 ` [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details Basavaraj Natikar 2022-05-24 7:40 ` [PATCH v2 3/3] pinctrl: amd: Implement pinmux functionality Basavaraj Natikar 2 siblings, 3 replies; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-24 7:40 UTC (permalink / raw) To: Shyam-sundar.S-k, linus.walleij, linux-gpio; +Cc: Basavaraj Natikar AMD pingroup can be extended to support multi-function pins. Hence define and use PINCTRL_GRP to manage and represent larger number of pingroups inline. Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> --- drivers/pinctrl/pinctrl-amd.h | 39 ++++++++--------------------------- 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 1d4317073654..de2bc9dddc9c 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -296,37 +296,16 @@ static const unsigned i2c3_pins[] = {19, 20}; static const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; static const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; +#define PINCTRL_GRP(_name, _pins, _npins) \ + { .name = _name, .pins = _pins, .npins = _npins} + static const struct amd_pingroup kerncz_groups[] = { - { - .name = "i2c0", - .pins = i2c0_pins, - .npins = 2, - }, - { - .name = "i2c1", - .pins = i2c1_pins, - .npins = 2, - }, - { - .name = "i2c2", - .pins = i2c2_pins, - .npins = 2, - }, - { - .name = "i2c3", - .pins = i2c3_pins, - .npins = 2, - }, - { - .name = "uart0", - .pins = uart0_pins, - .npins = 5, - }, - { - .name = "uart1", - .pins = uart1_pins, - .npins = 5, - }, + PINCTRL_GRP("i2c0", i2c0_pins, 2), + PINCTRL_GRP("i2c1", i2c1_pins, 2), + PINCTRL_GRP("i2c2", i2c2_pins, 2), + PINCTRL_GRP("i2c3", i2c3_pins, 2), + PINCTRL_GRP("uart0", uart0_pins, 5), + PINCTRL_GRP("uart1", uart1_pins, 5), }; #endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP 2022-05-24 7:40 ` [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP Basavaraj Natikar @ 2022-05-24 9:36 ` Linus Walleij 2022-05-24 14:34 ` Andy Shevchenko 2022-05-24 14:38 ` Andy Shevchenko 2 siblings, 0 replies; 23+ messages in thread From: Linus Walleij @ 2022-05-24 9:36 UTC (permalink / raw) To: Basavaraj Natikar; +Cc: Shyam-sundar.S-k, linux-gpio Hi Basavaraj, thanks for your patch! On Tue, May 24, 2022 at 9:40 AM Basavaraj Natikar <Basavaraj.Natikar@amd.com> wrote: > +#define PINCTRL_GRP(_name, _pins, _npins) \ > + { .name = _name, .pins = _pins, .npins = _npins} Please prefix this macro with AMD_ so it doesn't run the risk of namespace collisions with generic macros, AMD_PINCTRL_GRP(...). Yours, Linus Walleij ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP 2022-05-24 7:40 ` [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP Basavaraj Natikar 2022-05-24 9:36 ` Linus Walleij @ 2022-05-24 14:34 ` Andy Shevchenko 2022-05-24 14:38 ` Andy Shevchenko 2 siblings, 0 replies; 23+ messages in thread From: Andy Shevchenko @ 2022-05-24 14:34 UTC (permalink / raw) To: Basavaraj Natikar Cc: Shyam Sundar S K, Linus Walleij, open list:GPIO SUBSYSTEM On Tue, May 24, 2022 at 10:13 AM Basavaraj Natikar <Basavaraj.Natikar@amd.com> wrote: > > AMD pingroup can be extended to support multi-function pins. > Hence define and use PINCTRL_GRP to manage and represent > larger number of pingroups inline. > > Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> > --- > drivers/pinctrl/pinctrl-amd.h | 39 ++++++++--------------------------- > 1 file changed, 9 insertions(+), 30 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h > index 1d4317073654..de2bc9dddc9c 100644 > --- a/drivers/pinctrl/pinctrl-amd.h > +++ b/drivers/pinctrl/pinctrl-amd.h > @@ -296,37 +296,16 @@ static const unsigned i2c3_pins[] = {19, 20}; > static const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; > static const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; > > +#define PINCTRL_GRP(_name, _pins, _npins) \ > + { .name = _name, .pins = _pins, .npins = _npins} > + > static const struct amd_pingroup kerncz_groups[] = { > - { > - .name = "i2c0", > - .pins = i2c0_pins, > - .npins = 2, > - }, > - { > - .name = "i2c1", > - .pins = i2c1_pins, > - .npins = 2, > - }, > - { > - .name = "i2c2", > - .pins = i2c2_pins, > - .npins = 2, > - }, > - { > - .name = "i2c3", > - .pins = i2c3_pins, > - .npins = 2, > - }, > - { > - .name = "uart0", > - .pins = uart0_pins, > - .npins = 5, > - }, > - { > - .name = "uart1", > - .pins = uart1_pins, > - .npins = 5, > - }, > + PINCTRL_GRP("i2c0", i2c0_pins, 2), > + PINCTRL_GRP("i2c1", i2c1_pins, 2), > + PINCTRL_GRP("i2c2", i2c2_pins, 2), > + PINCTRL_GRP("i2c3", i2c3_pins, 2), > + PINCTRL_GRP("uart0", uart0_pins, 5), > + PINCTRL_GRP("uart1", uart1_pins, 5), > }; > > #endif > -- > 2.25.1 > -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP 2022-05-24 7:40 ` [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP Basavaraj Natikar 2022-05-24 9:36 ` Linus Walleij 2022-05-24 14:34 ` Andy Shevchenko @ 2022-05-24 14:38 ` Andy Shevchenko 2022-05-25 6:05 ` Linus Walleij 2 siblings, 1 reply; 23+ messages in thread From: Andy Shevchenko @ 2022-05-24 14:38 UTC (permalink / raw) To: Basavaraj Natikar Cc: Shyam Sundar S K, Linus Walleij, open list:GPIO SUBSYSTEM On Tue, May 24, 2022 at 10:13 AM Basavaraj Natikar <Basavaraj.Natikar@amd.com> wrote: > > AMD pingroup can be extended to support multi-function pins. > Hence define and use PINCTRL_GRP to manage and represent > larger number of pingroups inline. This is good idea, but please make it available for all pin control drivers, since the data structure like pingroup { *name; *pins; npins; } is used in many drivers. That said, I think the AMD_ prefix will be misleading in this case. ... > +#define PINCTRL_GRP(_name, _pins, _npins) \ > + { .name = _name, .pins = _pins, .npins = _npins} Please, don't forget spaces and commas, also it would be better to 1) split {} on the separate lines; 2) make it compound literal, so one can use it in the code. -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP 2022-05-24 14:38 ` Andy Shevchenko @ 2022-05-25 6:05 ` Linus Walleij 2022-05-26 6:27 ` Basavaraj Natikar 0 siblings, 1 reply; 23+ messages in thread From: Linus Walleij @ 2022-05-25 6:05 UTC (permalink / raw) To: Andy Shevchenko Cc: Basavaraj Natikar, Shyam Sundar S K, open list:GPIO SUBSYSTEM On Tue, May 24, 2022 at 4:39 PM Andy Shevchenko <andy.shevchenko@gmail.com> wrote: > On Tue, May 24, 2022 at 10:13 AM Basavaraj Natikar > <Basavaraj.Natikar@amd.com> wrote: > > > > AMD pingroup can be extended to support multi-function pins. > > Hence define and use PINCTRL_GRP to manage and represent > > larger number of pingroups inline. > > This is good idea, but please make it available for all pin control > drivers, since the data structure like > > pingroup { > *name; > *pins; > npins; > } > > is used in many drivers. > > That said, I think the AMD_ prefix will be misleading in this case. Aha you mean like a utility macro? That's useful, don't know where to put it though, include/linux/pinctrl/pinmux.h? Yours, Linus Walleij ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP 2022-05-25 6:05 ` Linus Walleij @ 2022-05-26 6:27 ` Basavaraj Natikar 0 siblings, 0 replies; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-26 6:27 UTC (permalink / raw) To: Linus Walleij, Andy Shevchenko Cc: Basavaraj Natikar, Shyam Sundar S K, open list:GPIO SUBSYSTEM On 5/25/2022 11:35 AM, Linus Walleij wrote: > On Tue, May 24, 2022 at 4:39 PM Andy Shevchenko > <andy.shevchenko@gmail.com> wrote: >> On Tue, May 24, 2022 at 10:13 AM Basavaraj Natikar >> <Basavaraj.Natikar@amd.com> wrote: >>> AMD pingroup can be extended to support multi-function pins. >>> Hence define and use PINCTRL_GRP to manage and represent >>> larger number of pingroups inline. >> This is good idea, but please make it available for all pin control >> drivers, since the data structure like >> >> pingroup { >> *name; >> *pins; >> npins; >> } >> >> is used in many drivers. >> >> That said, I think the AMD_ prefix will be misleading in this case. > Aha you mean like a utility macro? That's useful, don't know where to put it > though, include/linux/pinctrl/pinmux.h? For me looks like we need to put this in include/linux/pinctrl/pinctrl.h for a generic usage. is this fine? > Yours, > Linus Walleij ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 7:40 [PATCH v2 0/3] Enhancements to AMD pinctrl and implementation of AMD pinmux Basavaraj Natikar 2022-05-24 7:40 ` [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP Basavaraj Natikar @ 2022-05-24 7:40 ` Basavaraj Natikar 2022-05-24 9:38 ` Linus Walleij 2022-05-24 13:06 ` Andy Shevchenko 2022-05-24 7:40 ` [PATCH v2 3/3] pinctrl: amd: Implement pinmux functionality Basavaraj Natikar 2 siblings, 2 replies; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-24 7:40 UTC (permalink / raw) To: Shyam-sundar.S-k, linus.walleij, linux-gpio; +Cc: Basavaraj Natikar Presently there is no way to change pinmux configuration runtime. Hence add IOMUX details which can be used to configure IOMUX gpio pins runtime to different functionalities. Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> --- drivers/pinctrl/pinctrl-amd.c | 65 +++++++++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-amd.h | 1 + 2 files changed, 66 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 1a7d686494ff..3058b6d35e47 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -32,6 +32,8 @@ #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include "../acpi/acpica/accommon.h" + #include "core.h" #include "pinctrl-utils.h" #include "pinctrl-amd.h" @@ -958,6 +960,68 @@ static struct pinctrl_desc amd_pinctrl_desc = { .owner = THIS_MODULE, }; +static acpi_status acpi_get_iomux_region(acpi_handle handle, u32 level, + void *ctx, void **return_value) +{ + struct acpi_namespace_node *node = handle; + union acpi_operand_object *region_obj; + struct amd_gpio *gpio_dev = ctx; + + /* Already mapped the IOMUX base */ + if (gpio_dev->iomux_base) + return AE_OK; + + /* Valid object */ + if (!node || !node->object) + return AE_OK; + + /* Valid operand or namespace node*/ + if ((ACPI_GET_DESCRIPTOR_TYPE(node->object) != ACPI_DESC_TYPE_OPERAND) && + (ACPI_GET_DESCRIPTOR_TYPE(node->object) != ACPI_DESC_TYPE_NAMED)) + return AE_OK; + + /* Valid object type*/ + if (node->object->common.type == ACPI_TYPE_LOCAL_DATA) + return AE_OK; + + region_obj = node->object; + if (!region_obj->region.handler) + return AE_OK; + + if (region_obj->region.space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) + return AE_OK; + + if (strncmp("IOMX", region_obj->region.node->name.ascii, strlen("IOMX"))) + return AE_OK; + + gpio_dev->iomux_base = devm_ioremap(&gpio_dev->pdev->dev, + region_obj->region.address, + region_obj->region.length); + if (!gpio_dev->iomux_base) + dev_err(&gpio_dev->pdev->dev, "failed to devm_ioremap() iomux_base\n"); + + return AE_OK; +} + +static void amd_update_iomux_info(struct amd_gpio *gpio_dev) +{ + acpi_handle sys_bus_handle; + int status = acpi_get_handle(NULL, "\\_SB", &sys_bus_handle); + + if (ACPI_FAILURE(status)) { + dev_err(&gpio_dev->pdev->dev, "Failed to get SB handle\n"); + return; + } + + status = acpi_walk_namespace(ACPI_TYPE_REGION, sys_bus_handle, ACPI_UINT32_MAX, + acpi_get_iomux_region, NULL, gpio_dev, NULL); + + if (ACPI_FAILURE(status)) { + dev_err(&gpio_dev->pdev->dev, "Failed to get acpi_get_iomux_region\n"); + return; + } +} + static int amd_gpio_probe(struct platform_device *pdev) { int ret = 0; @@ -1052,6 +1116,7 @@ static int amd_gpio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, gpio_dev); acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); + amd_update_iomux_info(gpio_dev); dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); return ret; diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index de2bc9dddc9c..8296426f4c81 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -89,6 +89,7 @@ struct amd_function { struct amd_gpio { raw_spinlock_t lock; void __iomem *base; + void __iomem *iomux_base; const struct amd_pingroup *groups; u32 ngroups; -- 2.25.1 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 7:40 ` [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details Basavaraj Natikar @ 2022-05-24 9:38 ` Linus Walleij 2022-05-24 11:18 ` Basavaraj Natikar 2022-05-24 13:06 ` Andy Shevchenko 1 sibling, 1 reply; 23+ messages in thread From: Linus Walleij @ 2022-05-24 9:38 UTC (permalink / raw) To: Basavaraj Natikar, Mika Westerberg, Andy Shevchenko Cc: Shyam-sundar.S-k, linux-gpio Hi Basavaraj, thanks for your patch! On Tue, May 24, 2022 at 9:40 AM Basavaraj Natikar <Basavaraj.Natikar@amd.com> wrote: > Presently there is no way to change pinmux configuration runtime. > Hence add IOMUX details which can be used to configure IOMUX > gpio pins runtime to different functionalities. > > Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Interesting! > +static acpi_status acpi_get_iomux_region(acpi_handle handle, u32 level, > + void *ctx, void **return_value) > +{ > + struct acpi_namespace_node *node = handle; > + union acpi_operand_object *region_obj; > + struct amd_gpio *gpio_dev = ctx; > + > + /* Already mapped the IOMUX base */ > + if (gpio_dev->iomux_base) > + return AE_OK; > + > + /* Valid object */ > + if (!node || !node->object) > + return AE_OK; > + > + /* Valid operand or namespace node*/ > + if ((ACPI_GET_DESCRIPTOR_TYPE(node->object) != ACPI_DESC_TYPE_OPERAND) && > + (ACPI_GET_DESCRIPTOR_TYPE(node->object) != ACPI_DESC_TYPE_NAMED)) > + return AE_OK; > + > + /* Valid object type*/ > + if (node->object->common.type == ACPI_TYPE_LOCAL_DATA) > + return AE_OK; > + > + region_obj = node->object; > + if (!region_obj->region.handler) > + return AE_OK; > + > + if (region_obj->region.space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) > + return AE_OK; > + > + if (strncmp("IOMX", region_obj->region.node->name.ascii, strlen("IOMX"))) > + return AE_OK; > + > + gpio_dev->iomux_base = devm_ioremap(&gpio_dev->pdev->dev, > + region_obj->region.address, > + region_obj->region.length); > + if (!gpio_dev->iomux_base) > + dev_err(&gpio_dev->pdev->dev, "failed to devm_ioremap() iomux_base\n"); > + > + return AE_OK; > +} > + > +static void amd_update_iomux_info(struct amd_gpio *gpio_dev) > +{ > + acpi_handle sys_bus_handle; > + int status = acpi_get_handle(NULL, "\\_SB", &sys_bus_handle); > + > + if (ACPI_FAILURE(status)) { > + dev_err(&gpio_dev->pdev->dev, "Failed to get SB handle\n"); > + return; > + } > + > + status = acpi_walk_namespace(ACPI_TYPE_REGION, sys_bus_handle, ACPI_UINT32_MAX, > + acpi_get_iomux_region, NULL, gpio_dev, NULL); > + > + if (ACPI_FAILURE(status)) { > + dev_err(&gpio_dev->pdev->dev, "Failed to get acpi_get_iomux_region\n"); > + return; > + } > +} Oh this looks scary to me, make sure you get the review from the GPIO ACPI experts, Andy Shevchenko and/or Mika Westerberg. (Added on the To: line) Yours, Linus Walleij ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 9:38 ` Linus Walleij @ 2022-05-24 11:18 ` Basavaraj Natikar 2022-05-24 11:37 ` Mika Westerberg 0 siblings, 1 reply; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-24 11:18 UTC (permalink / raw) To: Mika Westerberg, Andy Shevchenko Cc: Shyam-sundar.S-k, linux-gpio, Linus Walleij >> + >> + status = acpi_walk_namespace(ACPI_TYPE_REGION, sys_bus_handle, ACPI_UINT32_MAX, >> + acpi_get_iomux_region, NULL, gpio_dev, NULL); >> + >> + if (ACPI_FAILURE(status)) { >> + dev_err(&gpio_dev->pdev->dev, "Failed to get acpi_get_iomux_region\n"); >> + return; >> + } >> +} > Oh this looks scary to me, make sure you get the review from the GPIO > ACPI experts, Andy Shevchenko and/or Mika Westerberg. (Added on the > To: line) Thanks Linus for the feedback. Hi Andy/Mika, Please provide your suggestions for this patch. Thanks, Basavaraj > > Yours, > Linus Walleij ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 11:18 ` Basavaraj Natikar @ 2022-05-24 11:37 ` Mika Westerberg 2022-05-24 11:52 ` Basavaraj Natikar 0 siblings, 1 reply; 23+ messages in thread From: Mika Westerberg @ 2022-05-24 11:37 UTC (permalink / raw) To: Basavaraj Natikar Cc: Andy Shevchenko, Shyam-sundar.S-k, linux-gpio, Linus Walleij Hi, On Tue, May 24, 2022 at 04:48:03PM +0530, Basavaraj Natikar wrote: > > >> + > >> + status = acpi_walk_namespace(ACPI_TYPE_REGION, sys_bus_handle, ACPI_UINT32_MAX, > >> + acpi_get_iomux_region, NULL, gpio_dev, NULL); > >> + > >> + if (ACPI_FAILURE(status)) { > >> + dev_err(&gpio_dev->pdev->dev, "Failed to get acpi_get_iomux_region\n"); > >> + return; > >> + } > >> +} > > Oh this looks scary to me, make sure you get the review from the GPIO > > ACPI experts, Andy Shevchenko and/or Mika Westerberg. (Added on the > > To: line) > > Thanks Linus for the feedback. > > Hi Andy/Mika, > > Please provide your suggestions for this patch. If this is about muxing pins, have you looked at the ACPI PinFunction () and related descriptors? ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 11:37 ` Mika Westerberg @ 2022-05-24 11:52 ` Basavaraj Natikar 2022-05-24 12:07 ` Mika Westerberg 0 siblings, 1 reply; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-24 11:52 UTC (permalink / raw) To: Mika Westerberg Cc: Andy Shevchenko, Shyam-sundar.S-k, linux-gpio, Linus Walleij On 5/24/2022 5:07 PM, Mika Westerberg wrote: > Hi, > > On Tue, May 24, 2022 at 04:48:03PM +0530, Basavaraj Natikar wrote: >>>> + >>>> + status = acpi_walk_namespace(ACPI_TYPE_REGION, sys_bus_handle, ACPI_UINT32_MAX, >>>> + acpi_get_iomux_region, NULL, gpio_dev, NULL); >>>> + >>>> + if (ACPI_FAILURE(status)) { >>>> + dev_err(&gpio_dev->pdev->dev, "Failed to get acpi_get_iomux_region\n"); >>>> + return; >>>> + } >>>> +} >>> Oh this looks scary to me, make sure you get the review from the GPIO >>> ACPI experts, Andy Shevchenko and/or Mika Westerberg. (Added on the >>> To: line) >> Thanks Linus for the feedback. >> >> Hi Andy/Mika, >> >> Please provide your suggestions for this patch. > If this is about muxing pins, have you looked at the ACPI PinFunction () > and related descriptors? This is about finding below IOMX (pinmux region) from ACPI namespace. OperationRegion (IOMX, SystemMemory, 0xFED80D00, 0x0100) I did not find any other methods to get IOMUX system memory region. ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 11:52 ` Basavaraj Natikar @ 2022-05-24 12:07 ` Mika Westerberg 2022-05-24 12:24 ` Basavaraj Natikar 0 siblings, 1 reply; 23+ messages in thread From: Mika Westerberg @ 2022-05-24 12:07 UTC (permalink / raw) To: Basavaraj Natikar Cc: Andy Shevchenko, Shyam-sundar.S-k, linux-gpio, Linus Walleij On Tue, May 24, 2022 at 05:22:47PM +0530, Basavaraj Natikar wrote: > > On 5/24/2022 5:07 PM, Mika Westerberg wrote: > > > Hi, > > > > On Tue, May 24, 2022 at 04:48:03PM +0530, Basavaraj Natikar wrote: > >>>> + > >>>> + status = acpi_walk_namespace(ACPI_TYPE_REGION, sys_bus_handle, ACPI_UINT32_MAX, > >>>> + acpi_get_iomux_region, NULL, gpio_dev, NULL); > >>>> + > >>>> + if (ACPI_FAILURE(status)) { > >>>> + dev_err(&gpio_dev->pdev->dev, "Failed to get acpi_get_iomux_region\n"); > >>>> + return; > >>>> + } > >>>> +} > >>> Oh this looks scary to me, make sure you get the review from the GPIO > >>> ACPI experts, Andy Shevchenko and/or Mika Westerberg. (Added on the > >>> To: line) > >> Thanks Linus for the feedback. > >> > >> Hi Andy/Mika, > >> > >> Please provide your suggestions for this patch. > > If this is about muxing pins, have you looked at the ACPI PinFunction () > > and related descriptors? > > This is about finding below IOMX (pinmux region) from ACPI namespace. Yes, I know but you use it for muxing pins, no? > OperationRegion (IOMX, SystemMemory, 0xFED80D00, 0x0100) > > I did not find any other methods to get IOMUX system memory region. It seems to be standard BAR so simple memory descriptor in _CRS () probably works too and does not need any additional lines of code. ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 12:07 ` Mika Westerberg @ 2022-05-24 12:24 ` Basavaraj Natikar 2022-05-24 12:34 ` Mika Westerberg 0 siblings, 1 reply; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-24 12:24 UTC (permalink / raw) To: Mika Westerberg Cc: Andy Shevchenko, Shyam-sundar.S-k, linux-gpio, Linus Walleij On 5/24/2022 5:37 PM, Mika Westerberg wrote: > On Tue, May 24, 2022 at 05:22:47PM +0530, Basavaraj Natikar wrote: >> On 5/24/2022 5:07 PM, Mika Westerberg wrote: >> >>> Hi, >>> >>> On Tue, May 24, 2022 at 04:48:03PM +0530, Basavaraj Natikar wrote: >>>>>> + >>>>>> + status = acpi_walk_namespace(ACPI_TYPE_REGION, sys_bus_handle, ACPI_UINT32_MAX, >>>>>> + acpi_get_iomux_region, NULL, gpio_dev, NULL); >>>>>> + >>>>>> + if (ACPI_FAILURE(status)) { >>>>>> + dev_err(&gpio_dev->pdev->dev, "Failed to get acpi_get_iomux_region\n"); >>>>>> + return; >>>>>> + } >>>>>> +} >>>>> Oh this looks scary to me, make sure you get the review from the GPIO >>>>> ACPI experts, Andy Shevchenko and/or Mika Westerberg. (Added on the >>>>> To: line) >>>> Thanks Linus for the feedback. >>>> >>>> Hi Andy/Mika, >>>> >>>> Please provide your suggestions for this patch. >>> If this is about muxing pins, have you looked at the ACPI PinFunction () >>> and related descriptors? >> This is about finding below IOMX (pinmux region) from ACPI namespace. > Yes, I know but you use it for muxing pins, no? > >> OperationRegion (IOMX, SystemMemory, 0xFED80D00, 0x0100) >> >> I did not find any other methods to get IOMUX system memory region. > It seems to be standard BAR so simple memory descriptor in _CRS () > probably works too and does not need any additional lines of code. There is no CRS method defined for IOMX/0xFED80D00 in ACPI namespace // IOMX Address Base Hence I added additional code to get IOMX memory region. since _CRS method is used to get GPIO pin base for AMDI0030 in pinctrl-amd as below, same is not available for IOMX Device (GPIO) { Name (_HID, "AMDI0030") // _HID: Hardware ID Name (_CID, "AMDI0030") // _CID: Compatible ID Name (_UID, Zero) // _UID: Unique ID Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { Name (RBUF, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) { 0x00000007, } Memory32Fixed (ReadWrite, 0xFED81500, // Address Base 0x00000400, // Address Length ) }) Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ } ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 12:24 ` Basavaraj Natikar @ 2022-05-24 12:34 ` Mika Westerberg 2022-05-24 13:50 ` Basavaraj Natikar 0 siblings, 1 reply; 23+ messages in thread From: Mika Westerberg @ 2022-05-24 12:34 UTC (permalink / raw) To: Basavaraj Natikar Cc: Andy Shevchenko, Shyam-sundar.S-k, linux-gpio, Linus Walleij On Tue, May 24, 2022 at 05:54:47PM +0530, Basavaraj Natikar wrote: > There is no CRS method defined for IOMX/0xFED80D00 in ACPI namespace // IOMX Address Base > Hence I added additional code to get IOMX memory region. > > since _CRS method is used to get GPIO pin base for AMDI0030 in > pinctrl-amd as below, same is not available for IOMX > > Device (GPIO) > { > Name (_HID, "AMDI0030") // _HID: Hardware ID > Name (_CID, "AMDI0030") // _CID: Compatible ID > Name (_UID, Zero) // _UID: Unique ID > Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings > { > Name (RBUF, ResourceTemplate () > { > Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) > { > 0x00000007, > } > Memory32Fixed (ReadWrite, > 0xFED81500, // Address Base > 0x00000400, // Address Length > ) Is there something preventing you to add it here like below? Memory32Fixed (ReadWrite, 0xFED80D00 0x00000400) ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 12:34 ` Mika Westerberg @ 2022-05-24 13:50 ` Basavaraj Natikar 2022-05-24 16:39 ` Andy Shevchenko 0 siblings, 1 reply; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-24 13:50 UTC (permalink / raw) To: Mika Westerberg Cc: Andy Shevchenko, Shyam-sundar.S-k, linux-gpio, Linus Walleij On 5/24/2022 6:04 PM, Mika Westerberg wrote: > On Tue, May 24, 2022 at 05:54:47PM +0530, Basavaraj Natikar wrote: >> There is no CRS method defined for IOMX/0xFED80D00 in ACPI namespace // IOMX Address Base >> Hence I added additional code to get IOMX memory region. >> >> since _CRS method is used to get GPIO pin base for AMDI0030 in >> pinctrl-amd as below, same is not available for IOMX >> >> Device (GPIO) >> { >> Name (_HID, "AMDI0030") // _HID: Hardware ID >> Name (_CID, "AMDI0030") // _CID: Compatible ID >> Name (_UID, Zero) // _UID: Unique ID >> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings >> { >> Name (RBUF, ResourceTemplate () >> { >> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) >> { >> 0x00000007, >> } >> Memory32Fixed (ReadWrite, >> 0xFED81500, // Address Base >> 0x00000400, // Address Length >> ) > Is there something preventing you to add it here like below? > > Memory32Fixed (ReadWrite, 0xFED80D00 0x00000400) yes few system has different entries already defined like below Device (GPIO) { Name (_HID, "AMDI0030") // _HID: Hardware ID Name (_CID, "AMDI0030") // _CID: Compatible ID Name (_UID, Zero) // _UID: Unique ID Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { Name (RBUF, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) { 0x00000007, } Memory32Fixed (ReadWrite, 0xFED81500, // Address Base 0x00000400, // Address Length ) }) Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ } Device (GPIO) { Name (_HID, "AMDI0030") // _HID: Hardware ID Name (_CID, "AMDI0030") // _CID: Compatible ID Name (_UID, Zero) // _UID: Unique ID Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { Name (RBUF, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) { 0x00000007, } Memory32Fixed (ReadWrite, 0xFED81500, // Address Base 0x00000400, // Address Length ) Memory32Fixed (ReadWrite, 0xFED81200, // Address Base 0x00000100, // Address Length ) }) Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ } if we add or in future some entries added. is there way to map particular entry for IOMUX? ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 13:50 ` Basavaraj Natikar @ 2022-05-24 16:39 ` Andy Shevchenko 2022-05-25 9:42 ` Basavaraj Natikar 0 siblings, 1 reply; 23+ messages in thread From: Andy Shevchenko @ 2022-05-24 16:39 UTC (permalink / raw) To: Basavaraj Natikar Cc: Mika Westerberg, Shyam-sundar.S-k, linux-gpio, Linus Walleij On Tue, May 24, 2022 at 07:20:34PM +0530, Basavaraj Natikar wrote: > On 5/24/2022 6:04 PM, Mika Westerberg wrote: > > On Tue, May 24, 2022 at 05:54:47PM +0530, Basavaraj Natikar wrote: > >> There is no CRS method defined for IOMX/0xFED80D00 in ACPI namespace // IOMX Address Base > >> Hence I added additional code to get IOMX memory region. > >> > >> since _CRS method is used to get GPIO pin base for AMDI0030 in > >> pinctrl-amd as below, same is not available for IOMX > >> > >> Device (GPIO) > >> { > >> Name (_HID, "AMDI0030") // _HID: Hardware ID > >> Name (_CID, "AMDI0030") // _CID: Compatible ID > >> Name (_UID, Zero) // _UID: Unique ID > >> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings > >> { > >> Name (RBUF, ResourceTemplate () > >> { > >> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) > >> { > >> 0x00000007, > >> } > >> Memory32Fixed (ReadWrite, > >> 0xFED81500, // Address Base > >> 0x00000400, // Address Length > >> ) > > Is there something preventing you to add it here like below? > > > > Memory32Fixed (ReadWrite, 0xFED80D00 0x00000400) > > yes few system has different entries already defined like below > Device (GPIO) > { > Name (_HID, "AMDI0030") // _HID: Hardware ID > Name (_CID, "AMDI0030") // _CID: Compatible ID > Name (_UID, Zero) // _UID: Unique ID > Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings > { > Name (RBUF, ResourceTemplate () > { > Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) > { > 0x00000007, > } > Memory32Fixed (ReadWrite, > 0xFED81500, // Address Base > 0x00000400, // Address Length > ) > }) > Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ > } > > > Device (GPIO) > { > Name (_HID, "AMDI0030") // _HID: Hardware ID > Name (_CID, "AMDI0030") // _CID: Compatible ID > Name (_UID, Zero) // _UID: Unique ID > Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings > { > Name (RBUF, ResourceTemplate () > { > Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) > { > 0x00000007, > } > Memory32Fixed (ReadWrite, > 0xFED81500, // Address Base > 0x00000400, // Address Length > ) > Memory32Fixed (ReadWrite, > 0xFED81200, // Address Base > 0x00000100, // Address Length > ) > }) > Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ > } > > if we add or in future some entries added. > is there way to map particular entry for IOMUX? Straightforward way is to add it always to the end and add _DSD boolean property ("amd,pinctrl-iomux-present") and act accordingly. More flexible and less error prone is to name all resources with DSD property and find resource by name: "amd,pinctrl-resource-names" = "bank0", "bank1", "iomux". -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 16:39 ` Andy Shevchenko @ 2022-05-25 9:42 ` Basavaraj Natikar 2022-05-25 16:45 ` Andy Shevchenko 0 siblings, 1 reply; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-25 9:42 UTC (permalink / raw) To: Andy Shevchenko Cc: Mika Westerberg, Shyam-sundar.S-k, linux-gpio, Linus Walleij On 5/24/2022 10:09 PM, Andy Shevchenko wrote: > On Tue, May 24, 2022 at 07:20:34PM +0530, Basavaraj Natikar wrote: >> On 5/24/2022 6:04 PM, Mika Westerberg wrote: >>> On Tue, May 24, 2022 at 05:54:47PM +0530, Basavaraj Natikar wrote: >>>> There is no CRS method defined for IOMX/0xFED80D00 in ACPI namespace // IOMX Address Base >>>> Hence I added additional code to get IOMX memory region. >>>> >>>> since _CRS method is used to get GPIO pin base for AMDI0030 in >>>> pinctrl-amd as below, same is not available for IOMX >>>> >>>> Device (GPIO) >>>> { >>>> Name (_HID, "AMDI0030") // _HID: Hardware ID >>>> Name (_CID, "AMDI0030") // _CID: Compatible ID >>>> Name (_UID, Zero) // _UID: Unique ID >>>> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings >>>> { >>>> Name (RBUF, ResourceTemplate () >>>> { >>>> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) >>>> { >>>> 0x00000007, >>>> } >>>> Memory32Fixed (ReadWrite, >>>> 0xFED81500, // Address Base >>>> 0x00000400, // Address Length >>>> ) >>> Is there something preventing you to add it here like below? >>> >>> Memory32Fixed (ReadWrite, 0xFED80D00 0x00000400) >> yes few system has different entries already defined like below >> Device (GPIO) >> { >> Name (_HID, "AMDI0030") // _HID: Hardware ID >> Name (_CID, "AMDI0030") // _CID: Compatible ID >> Name (_UID, Zero) // _UID: Unique ID >> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings >> { >> Name (RBUF, ResourceTemplate () >> { >> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) >> { >> 0x00000007, >> } >> Memory32Fixed (ReadWrite, >> 0xFED81500, // Address Base >> 0x00000400, // Address Length >> ) >> }) >> Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ >> } >> >> >> Device (GPIO) >> { >> Name (_HID, "AMDI0030") // _HID: Hardware ID >> Name (_CID, "AMDI0030") // _CID: Compatible ID >> Name (_UID, Zero) // _UID: Unique ID >> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings >> { >> Name (RBUF, ResourceTemplate () >> { >> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) >> { >> 0x00000007, >> } >> Memory32Fixed (ReadWrite, >> 0xFED81500, // Address Base >> 0x00000400, // Address Length >> ) >> Memory32Fixed (ReadWrite, >> 0xFED81200, // Address Base >> 0x00000100, // Address Length >> ) >> }) >> Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ >> } >> >> if we add or in future some entries added. >> is there way to map particular entry for IOMUX? > Straightforward way is to add it always to the end and add _DSD boolean > property ("amd,pinctrl-iomux-present") and act accordingly. More flexible and > less error prone is to name all resources with DSD property and find resource > by name: "amd,pinctrl-resource-names" = "bank0", "bank1", "iomux". > Idea of adding _DSD property looks good, we can add easily _DSD "pinctrl-iomux-present" u8 property to return index or instance value directly. But systems already in use or old platforms needs BIOS update to avail this feature and it may also impact existing windows OS functionality. one more flexible way is to directly use _DSD property to get memory region as below also works, which also needs BIOS update to avail feature. Package (0x02) { "pinctrl-iomux", Package (0x2) { 0xFED80D00, 0x00000100 } } How about adding generic new function in drivers/acpi/utils.h to avoid using "../acpi/acpica/accommon.h" in pinctrl-amd.c like below. acpi_status acpi_get_sys_mem_region(acpi_handle handle, const char *nname, struct acpi_mem_space_context *res); can be used directly in acpi_get_iomux_region by calling like acpi_get_sys_mem_region(handle, "IOMX", &res) This can be generically used to get details like below Operation regions which is already present in dsdt table. OperationRegion (IOMX, SystemMemory, 0xFED80D00, 0x0100) ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-25 9:42 ` Basavaraj Natikar @ 2022-05-25 16:45 ` Andy Shevchenko 2022-05-26 6:30 ` Basavaraj Natikar 0 siblings, 1 reply; 23+ messages in thread From: Andy Shevchenko @ 2022-05-25 16:45 UTC (permalink / raw) To: Basavaraj Natikar Cc: Mika Westerberg, Shyam-sundar.S-k, linux-gpio, Linus Walleij On Wed, May 25, 2022 at 03:12:05PM +0530, Basavaraj Natikar wrote: > On 5/24/2022 10:09 PM, Andy Shevchenko wrote: > > On Tue, May 24, 2022 at 07:20:34PM +0530, Basavaraj Natikar wrote: > >> On 5/24/2022 6:04 PM, Mika Westerberg wrote: > >>> On Tue, May 24, 2022 at 05:54:47PM +0530, Basavaraj Natikar wrote: > >>>> There is no CRS method defined for IOMX/0xFED80D00 in ACPI namespace // IOMX Address Base > >>>> Hence I added additional code to get IOMX memory region. > >>>> > >>>> since _CRS method is used to get GPIO pin base for AMDI0030 in > >>>> pinctrl-amd as below, same is not available for IOMX > >>>> > >>>> Device (GPIO) > >>>> { > >>>> Name (_HID, "AMDI0030") // _HID: Hardware ID > >>>> Name (_CID, "AMDI0030") // _CID: Compatible ID > >>>> Name (_UID, Zero) // _UID: Unique ID > >>>> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings > >>>> { > >>>> Name (RBUF, ResourceTemplate () > >>>> { > >>>> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) > >>>> { > >>>> 0x00000007, > >>>> } > >>>> Memory32Fixed (ReadWrite, > >>>> 0xFED81500, // Address Base > >>>> 0x00000400, // Address Length > >>>> ) > >>> Is there something preventing you to add it here like below? > >>> > >>> Memory32Fixed (ReadWrite, 0xFED80D00 0x00000400) > >> yes few system has different entries already defined like below > >> Device (GPIO) > >> { > >> Name (_HID, "AMDI0030") // _HID: Hardware ID > >> Name (_CID, "AMDI0030") // _CID: Compatible ID > >> Name (_UID, Zero) // _UID: Unique ID > >> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings > >> { > >> Name (RBUF, ResourceTemplate () > >> { > >> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) > >> { > >> 0x00000007, > >> } > >> Memory32Fixed (ReadWrite, > >> 0xFED81500, // Address Base > >> 0x00000400, // Address Length > >> ) > >> }) > >> Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ > >> } > >> > >> > >> Device (GPIO) > >> { > >> Name (_HID, "AMDI0030") // _HID: Hardware ID > >> Name (_CID, "AMDI0030") // _CID: Compatible ID > >> Name (_UID, Zero) // _UID: Unique ID > >> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings > >> { > >> Name (RBUF, ResourceTemplate () > >> { > >> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) > >> { > >> 0x00000007, > >> } > >> Memory32Fixed (ReadWrite, > >> 0xFED81500, // Address Base > >> 0x00000400, // Address Length > >> ) > >> Memory32Fixed (ReadWrite, > >> 0xFED81200, // Address Base > >> 0x00000100, // Address Length > >> ) > >> }) > >> Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ > >> } > >> > >> if we add or in future some entries added. > >> is there way to map particular entry for IOMUX? > > Straightforward way is to add it always to the end and add _DSD boolean > > property ("amd,pinctrl-iomux-present") and act accordingly. More flexible and > > less error prone is to name all resources with DSD property and find resource > > by name: "amd,pinctrl-resource-names" = "bank0", "bank1", "iomux". > > > Idea of adding _DSD property looks good, we can add easily _DSD > "pinctrl-iomux-present" u8 property to return index or instance > value directly. Better to name them all, it will be more consistent and robust. > But systems already in use or old platforms needs BIOS update to avail > this feature and it may also impact existing windows OS functionality. I don't believe it will anyhow alter Windows, except the new part not being tested in Windows. > one more flexible way is to directly use _DSD property to get memory > region as below also works, Strongly no. We do not allow to repeat in _DSD the existing ACPI concepts. ... > How about adding generic new function in drivers/acpi/utils.h to avoid > using "../acpi/acpica/accommon.h" in pinctrl-amd.c like below. > > acpi_status acpi_get_sys_mem_region(acpi_handle handle, > const char *nname, struct acpi_mem_space_context *res); > > can be used directly in acpi_get_iomux_region by calling like > acpi_get_sys_mem_region(handle, "IOMX", &res) > This can be generically used to get details like below Operation regions > which is already present in dsdt table. > OperationRegion (IOMX, SystemMemory, 0xFED80D00, 0x0100) It seems you missed the point of OpRegions in ACPI. We have a standart way of subscribing to the OpRegion:s, if somebody in ACPI touches it, you will handle writes and reads in the driver. Using OpRegion in replace of _CRS is a huge abuse of ACPI. Fix your firmware, because it sounds like it must be fixed. -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-25 16:45 ` Andy Shevchenko @ 2022-05-26 6:30 ` Basavaraj Natikar 0 siblings, 0 replies; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-26 6:30 UTC (permalink / raw) To: Andy Shevchenko Cc: Mika Westerberg, Shyam-sundar.S-k, linux-gpio, Linus Walleij On 5/25/2022 10:15 PM, Andy Shevchenko wrote: > On Wed, May 25, 2022 at 03:12:05PM +0530, Basavaraj Natikar wrote: >> On 5/24/2022 10:09 PM, Andy Shevchenko wrote: >>> On Tue, May 24, 2022 at 07:20:34PM +0530, Basavaraj Natikar wrote: >>>> On 5/24/2022 6:04 PM, Mika Westerberg wrote: >>>>> On Tue, May 24, 2022 at 05:54:47PM +0530, Basavaraj Natikar wrote: >>>>>> There is no CRS method defined for IOMX/0xFED80D00 in ACPI namespace // IOMX Address Base >>>>>> Hence I added additional code to get IOMX memory region. >>>>>> >>>>>> since _CRS method is used to get GPIO pin base for AMDI0030 in >>>>>> pinctrl-amd as below, same is not available for IOMX >>>>>> >>>>>> Device (GPIO) >>>>>> { >>>>>> Name (_HID, "AMDI0030") // _HID: Hardware ID >>>>>> Name (_CID, "AMDI0030") // _CID: Compatible ID >>>>>> Name (_UID, Zero) // _UID: Unique ID >>>>>> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings >>>>>> { >>>>>> Name (RBUF, ResourceTemplate () >>>>>> { >>>>>> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) >>>>>> { >>>>>> 0x00000007, >>>>>> } >>>>>> Memory32Fixed (ReadWrite, >>>>>> 0xFED81500, // Address Base >>>>>> 0x00000400, // Address Length >>>>>> ) >>>>> Is there something preventing you to add it here like below? >>>>> >>>>> Memory32Fixed (ReadWrite, 0xFED80D00 0x00000400) >>>> yes few system has different entries already defined like below >>>> Device (GPIO) >>>> { >>>> Name (_HID, "AMDI0030") // _HID: Hardware ID >>>> Name (_CID, "AMDI0030") // _CID: Compatible ID >>>> Name (_UID, Zero) // _UID: Unique ID >>>> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings >>>> { >>>> Name (RBUF, ResourceTemplate () >>>> { >>>> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) >>>> { >>>> 0x00000007, >>>> } >>>> Memory32Fixed (ReadWrite, >>>> 0xFED81500, // Address Base >>>> 0x00000400, // Address Length >>>> ) >>>> }) >>>> Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ >>>> } >>>> >>>> >>>> Device (GPIO) >>>> { >>>> Name (_HID, "AMDI0030") // _HID: Hardware ID >>>> Name (_CID, "AMDI0030") // _CID: Compatible ID >>>> Name (_UID, Zero) // _UID: Unique ID >>>> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings >>>> { >>>> Name (RBUF, ResourceTemplate () >>>> { >>>> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) >>>> { >>>> 0x00000007, >>>> } >>>> Memory32Fixed (ReadWrite, >>>> 0xFED81500, // Address Base >>>> 0x00000400, // Address Length >>>> ) >>>> Memory32Fixed (ReadWrite, >>>> 0xFED81200, // Address Base >>>> 0x00000100, // Address Length >>>> ) >>>> }) >>>> Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ >>>> } >>>> >>>> if we add or in future some entries added. >>>> is there way to map particular entry for IOMUX? >>> Straightforward way is to add it always to the end and add _DSD boolean >>> property ("amd,pinctrl-iomux-present") and act accordingly. More flexible and >>> less error prone is to name all resources with DSD property and find resource >>> by name: "amd,pinctrl-resource-names" = "bank0", "bank1", "iomux". >>> >> Idea of adding _DSD property looks good, we can add easily _DSD >> "pinctrl-iomux-present" u8 property to return index or instance >> value directly. > Better to name them all, it will be more consistent and robust. Thanks. Sounds good, will make this change. Thanks, Basavaraj ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details 2022-05-24 7:40 ` [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details Basavaraj Natikar 2022-05-24 9:38 ` Linus Walleij @ 2022-05-24 13:06 ` Andy Shevchenko 1 sibling, 0 replies; 23+ messages in thread From: Andy Shevchenko @ 2022-05-24 13:06 UTC (permalink / raw) To: Basavaraj Natikar Cc: Shyam Sundar S K, Linus Walleij, open list:GPIO SUBSYSTEM On Tue, May 24, 2022 at 10:01 AM Basavaraj Natikar <Basavaraj.Natikar@amd.com> wrote: > > Presently there is no way to change pinmux configuration runtime. > Hence add IOMUX details which can be used to configure IOMUX > gpio pins runtime to different functionalities. GPIO run time ... > +#include "../acpi/acpica/accommon.h" One shoudn't ever include this except ACPICA code. ... > +static acpi_status acpi_get_iomux_region(acpi_handle handle, u32 level, > + void *ctx, void **return_value) > +{ > + struct acpi_namespace_node *node = handle; > + union acpi_operand_object *region_obj; > + struct amd_gpio *gpio_dev = ctx; > + > + /* Already mapped the IOMUX base */ > + if (gpio_dev->iomux_base) > + return AE_OK; > + > + /* Valid object */ > + if (!node || !node->object) > + return AE_OK; > + > + /* Valid operand or namespace node*/ > + if ((ACPI_GET_DESCRIPTOR_TYPE(node->object) != ACPI_DESC_TYPE_OPERAND) && > + (ACPI_GET_DESCRIPTOR_TYPE(node->object) != ACPI_DESC_TYPE_NAMED)) > + return AE_OK; > + > + /* Valid object type*/ > + if (node->object->common.type == ACPI_TYPE_LOCAL_DATA) > + return AE_OK; > + > + region_obj = node->object; > + if (!region_obj->region.handler) > + return AE_OK; > + > + if (region_obj->region.space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) > + return AE_OK; > + > + if (strncmp("IOMX", region_obj->region.node->name.ascii, strlen("IOMX"))) > + return AE_OK; > + > + gpio_dev->iomux_base = devm_ioremap(&gpio_dev->pdev->dev, > + region_obj->region.address, > + region_obj->region.length); > + if (!gpio_dev->iomux_base) > + dev_err(&gpio_dev->pdev->dev, "failed to devm_ioremap() iomux_base\n"); > + > + return AE_OK; > +} Your commit message is quite poor, can you add a lot of missed details, i.e. how it's done in ACPI (DSDT), what the version of ACPI specification have you in mind when implementing this, etc. ... > + acpi_handle sys_bus_handle; > + int status = acpi_get_handle(NULL, "\\_SB", &sys_bus_handle); > + > + if (ACPI_FAILURE(status)) { > + dev_err(&gpio_dev->pdev->dev, "Failed to get SB handle\n"); > + return; > + } Usually you don't need an \\_SB handle. Why is it here? -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 3/3] pinctrl: amd: Implement pinmux functionality 2022-05-24 7:40 [PATCH v2 0/3] Enhancements to AMD pinctrl and implementation of AMD pinmux Basavaraj Natikar 2022-05-24 7:40 ` [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP Basavaraj Natikar 2022-05-24 7:40 ` [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details Basavaraj Natikar @ 2022-05-24 7:40 ` Basavaraj Natikar 2022-05-24 9:41 ` Linus Walleij 2 siblings, 1 reply; 23+ messages in thread From: Basavaraj Natikar @ 2022-05-24 7:40 UTC (permalink / raw) To: Shyam-sundar.S-k, linus.walleij, linux-gpio; +Cc: Basavaraj Natikar Provide pinmux functionality by implementing pinmux_ops. Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> --- drivers/pinctrl/pinctrl-amd.c | 79 +++ drivers/pinctrl/pinctrl-amd.h | 1039 ++++++++++++++++++++++++++++++++- 2 files changed, 1117 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 3058b6d35e47..28698a8b2263 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -31,6 +31,7 @@ #include <linux/bitops.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> #include "../acpi/acpica/accommon.h" @@ -952,10 +953,88 @@ static const struct dev_pm_ops amd_gpio_pm_ops = { }; #endif +static int amd_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pmx_functions); +} + +static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) +{ + return pmx_functions[selector].name; +} + +static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); + + if (!gpio_dev->iomux_base) { + dev_warn(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); + return -EINVAL; + } + + *groups = pmx_functions[selector].groups; + *num_groups = pmx_functions[selector].ngroups; + return 0; +} + +static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) +{ + struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); + struct pin_desc *pd; + int ind, index; + + if (!gpio_dev->iomux_base) + return -EINVAL; + + for (index = 0; index < NSELECTS; index++) { + if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) + continue; + + if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == + FUNCTION_INVALID) { + dev_warn(&gpio_dev->pdev->dev, + "IOMUX_GPIO 0x%x not present or supported\n", + pmx_functions[function].index); + return -EINVAL; + } + + writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); + + if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & + FUNCTION_MASK)) { + dev_warn(&gpio_dev->pdev->dev, + "IOMUX_GPIO 0x%x not present or supported\n", + pmx_functions[function].index); + return -EINVAL; + } + + for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { + if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) + continue; + + pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); + pd->mux_owner = gpio_dev->groups[group].name; + } + break; + } + + return 0; +} + +static const struct pinmux_ops amd_pmxops = { + .get_functions_count = amd_get_functions_count, + .get_function_name = amd_get_fname, + .get_function_groups = amd_get_groups, + .set_mux = amd_set_mux, +}; + static struct pinctrl_desc amd_pinctrl_desc = { .pins = kerncz_pins, .npins = ARRAY_SIZE(kerncz_pins), .pctlops = &amd_pinctrl_ops, + .pmxops = &amd_pmxops, .confops = &amd_pinconf_ops, .owner = THIS_MODULE, }; diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 8296426f4c81..5de11eefbfbe 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -74,6 +74,11 @@ #define CLR_INTR_STAT 0x1UL +#define NSELECTS 0x4 + +#define FUNCTION_MASK GENMASK(1, 0) +#define FUNCTION_INVALID GENMASK(7, 0) + struct amd_pingroup { const char *name; const unsigned *pins; @@ -82,8 +87,9 @@ struct amd_pingroup { struct amd_function { const char *name; - const char * const *groups; + const char * const groups[NSELECTS]; unsigned ngroups; + int index; }; struct amd_gpio { @@ -297,10 +303,887 @@ static const unsigned i2c3_pins[] = {19, 20}; static const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; static const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; +#define DEFINE_GPIO(_number) static const unsigned int gpio##_number[] = {_number} + +DEFINE_GPIO(0); +DEFINE_GPIO(1); +DEFINE_GPIO(2); +DEFINE_GPIO(3); +DEFINE_GPIO(4); +DEFINE_GPIO(5); +DEFINE_GPIO(6); +DEFINE_GPIO(7); +DEFINE_GPIO(8); +DEFINE_GPIO(9); +DEFINE_GPIO(10); +DEFINE_GPIO(11); +DEFINE_GPIO(12); +DEFINE_GPIO(13); +DEFINE_GPIO(14); +DEFINE_GPIO(15); +DEFINE_GPIO(16); +DEFINE_GPIO(17); +DEFINE_GPIO(18); +DEFINE_GPIO(19); +DEFINE_GPIO(20); +DEFINE_GPIO(21); +DEFINE_GPIO(22); +DEFINE_GPIO(23); +DEFINE_GPIO(24); +DEFINE_GPIO(25); +DEFINE_GPIO(26); +DEFINE_GPIO(27); +DEFINE_GPIO(28); +DEFINE_GPIO(29); +DEFINE_GPIO(30); +DEFINE_GPIO(31); +DEFINE_GPIO(32); +DEFINE_GPIO(33); +DEFINE_GPIO(34); +DEFINE_GPIO(35); +DEFINE_GPIO(36); +DEFINE_GPIO(37); +DEFINE_GPIO(38); +DEFINE_GPIO(39); +DEFINE_GPIO(40); +DEFINE_GPIO(41); +DEFINE_GPIO(42); +DEFINE_GPIO(43); +DEFINE_GPIO(44); +DEFINE_GPIO(45); +DEFINE_GPIO(46); +DEFINE_GPIO(47); +DEFINE_GPIO(48); +DEFINE_GPIO(49); +DEFINE_GPIO(50); +DEFINE_GPIO(51); +DEFINE_GPIO(52); +DEFINE_GPIO(53); +DEFINE_GPIO(54); +DEFINE_GPIO(55); +DEFINE_GPIO(56); +DEFINE_GPIO(57); +DEFINE_GPIO(58); +DEFINE_GPIO(59); +DEFINE_GPIO(60); +DEFINE_GPIO(61); +DEFINE_GPIO(62); +DEFINE_GPIO(64); +DEFINE_GPIO(65); +DEFINE_GPIO(66); +DEFINE_GPIO(67); +DEFINE_GPIO(68); +DEFINE_GPIO(69); +DEFINE_GPIO(70); +DEFINE_GPIO(71); +DEFINE_GPIO(72); +DEFINE_GPIO(73); +DEFINE_GPIO(74); +DEFINE_GPIO(75); +DEFINE_GPIO(76); +DEFINE_GPIO(77); +DEFINE_GPIO(78); +DEFINE_GPIO(79); +DEFINE_GPIO(80); +DEFINE_GPIO(81); +DEFINE_GPIO(82); +DEFINE_GPIO(83); +DEFINE_GPIO(84); +DEFINE_GPIO(85); +DEFINE_GPIO(86); +DEFINE_GPIO(87); +DEFINE_GPIO(88); +DEFINE_GPIO(89); +DEFINE_GPIO(90); +DEFINE_GPIO(91); +DEFINE_GPIO(92); +DEFINE_GPIO(93); +DEFINE_GPIO(94); +DEFINE_GPIO(95); +DEFINE_GPIO(96); +DEFINE_GPIO(97); +DEFINE_GPIO(98); +DEFINE_GPIO(99); +DEFINE_GPIO(100); +DEFINE_GPIO(101); +DEFINE_GPIO(102); +DEFINE_GPIO(103); +DEFINE_GPIO(104); +DEFINE_GPIO(105); +DEFINE_GPIO(106); +DEFINE_GPIO(107); +DEFINE_GPIO(108); +DEFINE_GPIO(109); +DEFINE_GPIO(110); +DEFINE_GPIO(111); +DEFINE_GPIO(112); +DEFINE_GPIO(113); +DEFINE_GPIO(114); +DEFINE_GPIO(115); +DEFINE_GPIO(116); +DEFINE_GPIO(117); +DEFINE_GPIO(118); +DEFINE_GPIO(119); +DEFINE_GPIO(120); +DEFINE_GPIO(121); +DEFINE_GPIO(122); +DEFINE_GPIO(123); +DEFINE_GPIO(124); +DEFINE_GPIO(125); +DEFINE_GPIO(126); +DEFINE_GPIO(127); +DEFINE_GPIO(128); +DEFINE_GPIO(129); +DEFINE_GPIO(130); +DEFINE_GPIO(131); +DEFINE_GPIO(132); +DEFINE_GPIO(133); +DEFINE_GPIO(134); +DEFINE_GPIO(135); +DEFINE_GPIO(136); +DEFINE_GPIO(137); +DEFINE_GPIO(138); +DEFINE_GPIO(139); +DEFINE_GPIO(140); +DEFINE_GPIO(141); +DEFINE_GPIO(142); +DEFINE_GPIO(143); +DEFINE_GPIO(144); + #define PINCTRL_GRP(_name, _pins, _npins) \ { .name = _name, .pins = _pins, .npins = _npins} +enum amd_functions { + IMX_F0_GPIO0, + IMX_F1_GPIO0, + IMX_F2_GPIO0, + IMX_F3_GPIO0, + IMX_F0_GPIO1, + IMX_F1_GPIO1, + IMX_F2_GPIO1, + IMX_F3_GPIO1, + IMX_F0_GPIO2, + IMX_F1_GPIO2, + IMX_F2_GPIO2, + IMX_F3_GPIO2, + IMX_F0_GPIO3, + IMX_F1_GPIO3, + IMX_F2_GPIO3, + IMX_F3_GPIO3, + IMX_F0_GPIO4, + IMX_F1_GPIO4, + IMX_F2_GPIO4, + IMX_F3_GPIO4, + IMX_F0_GPIO5, + IMX_F1_GPIO5, + IMX_F2_GPIO5, + IMX_F3_GPIO5, + IMX_F0_GPIO6, + IMX_F1_GPIO6, + IMX_F2_GPIO6, + IMX_F3_GPIO6, + IMX_F0_GPIO7, + IMX_F1_GPIO7, + IMX_F2_GPIO7, + IMX_F3_GPIO7, + IMX_F0_GPIO8, + IMX_F1_GPIO8, + IMX_F2_GPIO8, + IMX_F3_GPIO8, + IMX_F0_GPIO9, + IMX_F1_GPIO9, + IMX_F2_GPIO9, + IMX_F3_GPIO9, + IMX_F0_GPIO10, + IMX_F1_GPIO10, + IMX_F2_GPIO10, + IMX_F3_GPIO10, + IMX_F0_GPIO11, + IMX_F1_GPIO11, + IMX_F2_GPIO11, + IMX_F3_GPIO11, + IMX_F0_GPIO12, + IMX_F1_GPIO12, + IMX_F2_GPIO12, + IMX_F3_GPIO12, + IMX_F0_GPIO13, + IMX_F1_GPIO13, + IMX_F2_GPIO13, + IMX_F3_GPIO13, + IMX_F0_GPIO14, + IMX_F1_GPIO14, + IMX_F2_GPIO14, + IMX_F3_GPIO14, + IMX_F0_GPIO15, + IMX_F1_GPIO15, + IMX_F2_GPIO15, + IMX_F3_GPIO15, + IMX_F0_GPIO16, + IMX_F1_GPIO16, + IMX_F2_GPIO16, + IMX_F3_GPIO16, + IMX_F0_GPIO17, + IMX_F1_GPIO17, + IMX_F2_GPIO17, + IMX_F3_GPIO17, + IMX_F0_GPIO18, + IMX_F1_GPIO18, + IMX_F2_GPIO18, + IMX_F3_GPIO18, + IMX_F0_GPIO19, + IMX_F1_GPIO19, + IMX_F2_GPIO19, + IMX_F3_GPIO19, + IMX_F0_GPIO20, + IMX_F1_GPIO20, + IMX_F2_GPIO20, + IMX_F3_GPIO20, + IMX_F0_GPIO21, + IMX_F1_GPIO21, + IMX_F2_GPIO21, + IMX_F3_GPIO21, + IMX_F0_GPIO22, + IMX_F1_GPIO22, + IMX_F2_GPIO22, + IMX_F3_GPIO22, + IMX_F0_GPIO23, + IMX_F1_GPIO23, + IMX_F2_GPIO23, + IMX_F3_GPIO23, + IMX_F0_GPIO24, + IMX_F1_GPIO24, + IMX_F2_GPIO24, + IMX_F3_GPIO24, + IMX_F0_GPIO25, + IMX_F1_GPIO25, + IMX_F2_GPIO25, + IMX_F3_GPIO25, + IMX_F0_GPIO26, + IMX_F1_GPIO26, + IMX_F2_GPIO26, + IMX_F3_GPIO26, + IMX_F0_GPIO27, + IMX_F1_GPIO27, + IMX_F2_GPIO27, + IMX_F3_GPIO27, + IMX_F0_GPIO28, + IMX_F1_GPIO28, + IMX_F2_GPIO28, + IMX_F3_GPIO28, + IMX_F0_GPIO29, + IMX_F1_GPIO29, + IMX_F2_GPIO29, + IMX_F3_GPIO29, + IMX_F0_GPIO30, + IMX_F1_GPIO30, + IMX_F2_GPIO30, + IMX_F3_GPIO30, + IMX_F0_GPIO31, + IMX_F1_GPIO31, + IMX_F2_GPIO31, + IMX_F3_GPIO31, + IMX_F0_GPIO32, + IMX_F1_GPIO32, + IMX_F2_GPIO32, + IMX_F3_GPIO32, + IMX_F0_GPIO33, + IMX_F1_GPIO33, + IMX_F2_GPIO33, + IMX_F3_GPIO33, + IMX_F0_GPIO34, + IMX_F1_GPIO34, + IMX_F2_GPIO34, + IMX_F3_GPIO34, + IMX_F0_GPIO35, + IMX_F1_GPIO35, + IMX_F2_GPIO35, + IMX_F3_GPIO35, + IMX_F0_GPIO36, + IMX_F1_GPIO36, + IMX_F2_GPIO36, + IMX_F3_GPIO36, + IMX_F0_GPIO37, + IMX_F1_GPIO37, + IMX_F2_GPIO37, + IMX_F3_GPIO37, + IMX_F0_GPIO38, + IMX_F1_GPIO38, + IMX_F2_GPIO38, + IMX_F3_GPIO38, + IMX_F0_GPIO39, + IMX_F1_GPIO39, + IMX_F2_GPIO39, + IMX_F3_GPIO39, + IMX_F0_GPIO40, + IMX_F1_GPIO40, + IMX_F2_GPIO40, + IMX_F3_GPIO40, + IMX_F0_GPIO41, + IMX_F1_GPIO41, + IMX_F2_GPIO41, + IMX_F3_GPIO41, + IMX_F0_GPIO42, + IMX_F1_GPIO42, + IMX_F2_GPIO42, + IMX_F3_GPIO42, + IMX_F0_GPIO43, + IMX_F1_GPIO43, + IMX_F2_GPIO43, + IMX_F3_GPIO43, + IMX_F0_GPIO44, + IMX_F1_GPIO44, + IMX_F2_GPIO44, + IMX_F3_GPIO44, + IMX_F0_GPIO45, + IMX_F1_GPIO45, + IMX_F2_GPIO45, + IMX_F3_GPIO45, + IMX_F0_GPIO46, + IMX_F1_GPIO46, + IMX_F2_GPIO46, + IMX_F3_GPIO46, + IMX_F0_GPIO47, + IMX_F1_GPIO47, + IMX_F2_GPIO47, + IMX_F3_GPIO47, + IMX_F0_GPIO48, + IMX_F1_GPIO48, + IMX_F2_GPIO48, + IMX_F3_GPIO48, + IMX_F0_GPIO49, + IMX_F1_GPIO49, + IMX_F2_GPIO49, + IMX_F3_GPIO49, + IMX_F0_GPIO50, + IMX_F1_GPIO50, + IMX_F2_GPIO50, + IMX_F3_GPIO50, + IMX_F0_GPIO51, + IMX_F1_GPIO51, + IMX_F2_GPIO51, + IMX_F3_GPIO51, + IMX_F0_GPIO52, + IMX_F1_GPIO52, + IMX_F2_GPIO52, + IMX_F3_GPIO52, + IMX_F0_GPIO53, + IMX_F1_GPIO53, + IMX_F2_GPIO53, + IMX_F3_GPIO53, + IMX_F0_GPIO54, + IMX_F1_GPIO54, + IMX_F2_GPIO54, + IMX_F3_GPIO54, + IMX_F0_GPIO55, + IMX_F1_GPIO55, + IMX_F2_GPIO55, + IMX_F3_GPIO55, + IMX_F0_GPIO56, + IMX_F1_GPIO56, + IMX_F2_GPIO56, + IMX_F3_GPIO56, + IMX_F0_GPIO57, + IMX_F1_GPIO57, + IMX_F2_GPIO57, + IMX_F3_GPIO57, + IMX_F0_GPIO58, + IMX_F1_GPIO58, + IMX_F2_GPIO58, + IMX_F3_GPIO58, + IMX_F0_GPIO59, + IMX_F1_GPIO59, + IMX_F2_GPIO59, + IMX_F3_GPIO59, + IMX_F0_GPIO60, + IMX_F1_GPIO60, + IMX_F2_GPIO60, + IMX_F3_GPIO60, + IMX_F0_GPIO61, + IMX_F1_GPIO61, + IMX_F2_GPIO61, + IMX_F3_GPIO61, + IMX_F0_GPIO62, + IMX_F1_GPIO62, + IMX_F2_GPIO62, + IMX_F3_GPIO62, + IMX_F0_GPIO64, + IMX_F1_GPIO64, + IMX_F2_GPIO64, + IMX_F3_GPIO64, + IMX_F0_GPIO65, + IMX_F1_GPIO65, + IMX_F2_GPIO65, + IMX_F3_GPIO65, + IMX_F0_GPIO66, + IMX_F1_GPIO66, + IMX_F2_GPIO66, + IMX_F3_GPIO66, + IMX_F0_GPIO67, + IMX_F1_GPIO67, + IMX_F2_GPIO67, + IMX_F3_GPIO67, + IMX_F0_GPIO68, + IMX_F1_GPIO68, + IMX_F2_GPIO68, + IMX_F3_GPIO68, + IMX_F0_GPIO69, + IMX_F1_GPIO69, + IMX_F2_GPIO69, + IMX_F3_GPIO69, + IMX_F0_GPIO70, + IMX_F1_GPIO70, + IMX_F2_GPIO70, + IMX_F3_GPIO70, + IMX_F0_GPIO71, + IMX_F1_GPIO71, + IMX_F2_GPIO71, + IMX_F3_GPIO71, + IMX_F0_GPIO72, + IMX_F1_GPIO72, + IMX_F2_GPIO72, + IMX_F3_GPIO72, + IMX_F0_GPIO73, + IMX_F1_GPIO73, + IMX_F2_GPIO73, + IMX_F3_GPIO73, + IMX_F0_GPIO74, + IMX_F1_GPIO74, + IMX_F2_GPIO74, + IMX_F3_GPIO74, + IMX_F0_GPIO75, + IMX_F1_GPIO75, + IMX_F2_GPIO75, + IMX_F3_GPIO75, + IMX_F0_GPIO76, + IMX_F1_GPIO76, + IMX_F2_GPIO76, + IMX_F3_GPIO76, + IMX_F0_GPIO77, + IMX_F1_GPIO77, + IMX_F2_GPIO77, + IMX_F3_GPIO77, + IMX_F0_GPIO78, + IMX_F1_GPIO78, + IMX_F2_GPIO78, + IMX_F3_GPIO78, + IMX_F0_GPIO79, + IMX_F1_GPIO79, + IMX_F2_GPIO79, + IMX_F3_GPIO79, + IMX_F0_GPIO80, + IMX_F1_GPIO80, + IMX_F2_GPIO80, + IMX_F3_GPIO80, + IMX_F0_GPIO81, + IMX_F1_GPIO81, + IMX_F2_GPIO81, + IMX_F3_GPIO81, + IMX_F0_GPIO82, + IMX_F1_GPIO82, + IMX_F2_GPIO82, + IMX_F3_GPIO82, + IMX_F0_GPIO83, + IMX_F1_GPIO83, + IMX_F2_GPIO83, + IMX_F3_GPIO83, + IMX_F0_GPIO84, + IMX_F1_GPIO84, + IMX_F2_GPIO84, + IMX_F3_GPIO84, + IMX_F0_GPIO85, + IMX_F1_GPIO85, + IMX_F2_GPIO85, + IMX_F3_GPIO85, + IMX_F0_GPIO86, + IMX_F1_GPIO86, + IMX_F2_GPIO86, + IMX_F3_GPIO86, + IMX_F0_GPIO87, + IMX_F1_GPIO87, + IMX_F2_GPIO87, + IMX_F3_GPIO87, + IMX_F0_GPIO88, + IMX_F1_GPIO88, + IMX_F2_GPIO88, + IMX_F3_GPIO88, + IMX_F0_GPIO89, + IMX_F1_GPIO89, + IMX_F2_GPIO89, + IMX_F3_GPIO89, + IMX_F0_GPIO90, + IMX_F1_GPIO90, + IMX_F2_GPIO90, + IMX_F3_GPIO90, + IMX_F0_GPIO91, + IMX_F1_GPIO91, + IMX_F2_GPIO91, + IMX_F3_GPIO91, + IMX_F0_GPIO92, + IMX_F1_GPIO92, + IMX_F2_GPIO92, + IMX_F3_GPIO92, + IMX_F0_GPIO93, + IMX_F1_GPIO93, + IMX_F2_GPIO93, + IMX_F3_GPIO93, + IMX_F0_GPIO94, + IMX_F1_GPIO94, + IMX_F2_GPIO94, + IMX_F3_GPIO94, + IMX_F0_GPIO95, + IMX_F1_GPIO95, + IMX_F2_GPIO95, + IMX_F3_GPIO95, + IMX_F0_GPIO96, + IMX_F1_GPIO96, + IMX_F2_GPIO96, + IMX_F3_GPIO96, + IMX_F0_GPIO97, + IMX_F1_GPIO97, + IMX_F2_GPIO97, + IMX_F3_GPIO97, + IMX_F0_GPIO98, + IMX_F1_GPIO98, + IMX_F2_GPIO98, + IMX_F3_GPIO98, + IMX_F0_GPIO99, + IMX_F1_GPIO99, + IMX_F2_GPIO99, + IMX_F3_GPIO99, + IMX_F0_GPIO100, + IMX_F1_GPIO100, + IMX_F2_GPIO100, + IMX_F3_GPIO100, + IMX_F0_GPIO101, + IMX_F1_GPIO101, + IMX_F2_GPIO101, + IMX_F3_GPIO101, + IMX_F0_GPIO102, + IMX_F1_GPIO102, + IMX_F2_GPIO102, + IMX_F3_GPIO102, + IMX_F0_GPIO103, + IMX_F1_GPIO103, + IMX_F2_GPIO103, + IMX_F3_GPIO103, + IMX_F0_GPIO104, + IMX_F1_GPIO104, + IMX_F2_GPIO104, + IMX_F3_GPIO104, + IMX_F0_GPIO105, + IMX_F1_GPIO105, + IMX_F2_GPIO105, + IMX_F3_GPIO105, + IMX_F0_GPIO106, + IMX_F1_GPIO106, + IMX_F2_GPIO106, + IMX_F3_GPIO106, + IMX_F0_GPIO107, + IMX_F1_GPIO107, + IMX_F2_GPIO107, + IMX_F3_GPIO107, + IMX_F0_GPIO108, + IMX_F1_GPIO108, + IMX_F2_GPIO108, + IMX_F3_GPIO108, + IMX_F0_GPIO109, + IMX_F1_GPIO109, + IMX_F2_GPIO109, + IMX_F3_GPIO109, + IMX_F0_GPIO110, + IMX_F1_GPIO110, + IMX_F2_GPIO110, + IMX_F3_GPIO110, + IMX_F0_GPIO111, + IMX_F1_GPIO111, + IMX_F2_GPIO111, + IMX_F3_GPIO111, + IMX_F0_GPIO112, + IMX_F1_GPIO112, + IMX_F2_GPIO112, + IMX_F3_GPIO112, + IMX_F0_GPIO113, + IMX_F1_GPIO113, + IMX_F2_GPIO113, + IMX_F3_GPIO113, + IMX_F0_GPIO114, + IMX_F1_GPIO114, + IMX_F2_GPIO114, + IMX_F3_GPIO114, + IMX_F0_GPIO115, + IMX_F1_GPIO115, + IMX_F2_GPIO115, + IMX_F3_GPIO115, + IMX_F0_GPIO116, + IMX_F1_GPIO116, + IMX_F2_GPIO116, + IMX_F3_GPIO116, + IMX_F0_GPIO117, + IMX_F1_GPIO117, + IMX_F2_GPIO117, + IMX_F3_GPIO117, + IMX_F0_GPIO118, + IMX_F1_GPIO118, + IMX_F2_GPIO118, + IMX_F3_GPIO118, + IMX_F0_GPIO119, + IMX_F1_GPIO119, + IMX_F2_GPIO119, + IMX_F3_GPIO119, + IMX_F0_GPIO120, + IMX_F1_GPIO120, + IMX_F2_GPIO120, + IMX_F3_GPIO120, + IMX_F0_GPIO121, + IMX_F1_GPIO121, + IMX_F2_GPIO121, + IMX_F3_GPIO121, + IMX_F0_GPIO122, + IMX_F1_GPIO122, + IMX_F2_GPIO122, + IMX_F3_GPIO122, + IMX_F0_GPIO123, + IMX_F1_GPIO123, + IMX_F2_GPIO123, + IMX_F3_GPIO123, + IMX_F0_GPIO124, + IMX_F1_GPIO124, + IMX_F2_GPIO124, + IMX_F3_GPIO124, + IMX_F0_GPIO125, + IMX_F1_GPIO125, + IMX_F2_GPIO125, + IMX_F3_GPIO125, + IMX_F0_GPIO126, + IMX_F1_GPIO126, + IMX_F2_GPIO126, + IMX_F3_GPIO126, + IMX_F0_GPIO127, + IMX_F1_GPIO127, + IMX_F2_GPIO127, + IMX_F3_GPIO127, + IMX_F0_GPIO128, + IMX_F1_GPIO128, + IMX_F2_GPIO128, + IMX_F3_GPIO128, + IMX_F0_GPIO129, + IMX_F1_GPIO129, + IMX_F2_GPIO129, + IMX_F3_GPIO129, + IMX_F0_GPIO130, + IMX_F1_GPIO130, + IMX_F2_GPIO130, + IMX_F3_GPIO130, + IMX_F0_GPIO131, + IMX_F1_GPIO131, + IMX_F2_GPIO131, + IMX_F3_GPIO131, + IMX_F0_GPIO132, + IMX_F1_GPIO132, + IMX_F2_GPIO132, + IMX_F3_GPIO132, + IMX_F0_GPIO133, + IMX_F1_GPIO133, + IMX_F2_GPIO133, + IMX_F3_GPIO133, + IMX_F0_GPIO134, + IMX_F1_GPIO134, + IMX_F2_GPIO134, + IMX_F3_GPIO134, + IMX_F0_GPIO135, + IMX_F1_GPIO135, + IMX_F2_GPIO135, + IMX_F3_GPIO135, + IMX_F0_GPIO136, + IMX_F1_GPIO136, + IMX_F2_GPIO136, + IMX_F3_GPIO136, + IMX_F0_GPIO137, + IMX_F1_GPIO137, + IMX_F2_GPIO137, + IMX_F3_GPIO137, + IMX_F0_GPIO138, + IMX_F1_GPIO138, + IMX_F2_GPIO138, + IMX_F3_GPIO138, + IMX_F0_GPIO139, + IMX_F1_GPIO139, + IMX_F2_GPIO139, + IMX_F3_GPIO139, + IMX_F0_GPIO140, + IMX_F1_GPIO140, + IMX_F2_GPIO140, + IMX_F3_GPIO140, + IMX_F0_GPIO141, + IMX_F1_GPIO141, + IMX_F2_GPIO141, + IMX_F3_GPIO141, + IMX_F0_GPIO142, + IMX_F1_GPIO142, + IMX_F2_GPIO142, + IMX_F3_GPIO142, + IMX_F0_GPIO143, + IMX_F1_GPIO143, + IMX_F2_GPIO143, + IMX_F3_GPIO143, + IMX_F0_GPIO144, + IMX_F1_GPIO144, + IMX_F2_GPIO144, + IMX_F3_GPIO144, +}; + +#define PINCTRL_FUNC_GRP(_number) \ + [IMX_F0_GPIO##_number] = PINCTRL_GRP("IMX_F0_GPIO"#_number, gpio##_number, 1),\ + [IMX_F1_GPIO##_number] = PINCTRL_GRP("IMX_F1_GPIO"#_number, gpio##_number, 1),\ + [IMX_F2_GPIO##_number] = PINCTRL_GRP("IMX_F2_GPIO"#_number, gpio##_number, 1),\ + [IMX_F3_GPIO##_number] = PINCTRL_GRP("IMX_F3_GPIO"#_number, gpio##_number, 1) + static const struct amd_pingroup kerncz_groups[] = { + PINCTRL_FUNC_GRP(0), + PINCTRL_FUNC_GRP(1), + PINCTRL_FUNC_GRP(2), + PINCTRL_FUNC_GRP(3), + PINCTRL_FUNC_GRP(4), + PINCTRL_FUNC_GRP(5), + PINCTRL_FUNC_GRP(6), + PINCTRL_FUNC_GRP(7), + PINCTRL_FUNC_GRP(8), + PINCTRL_FUNC_GRP(9), + PINCTRL_FUNC_GRP(10), + PINCTRL_FUNC_GRP(11), + PINCTRL_FUNC_GRP(12), + PINCTRL_FUNC_GRP(13), + PINCTRL_FUNC_GRP(14), + PINCTRL_FUNC_GRP(15), + PINCTRL_FUNC_GRP(16), + PINCTRL_FUNC_GRP(17), + PINCTRL_FUNC_GRP(18), + PINCTRL_FUNC_GRP(19), + PINCTRL_FUNC_GRP(20), + PINCTRL_FUNC_GRP(21), + PINCTRL_FUNC_GRP(22), + PINCTRL_FUNC_GRP(23), + PINCTRL_FUNC_GRP(24), + PINCTRL_FUNC_GRP(25), + PINCTRL_FUNC_GRP(26), + PINCTRL_FUNC_GRP(27), + PINCTRL_FUNC_GRP(28), + PINCTRL_FUNC_GRP(29), + PINCTRL_FUNC_GRP(30), + PINCTRL_FUNC_GRP(31), + PINCTRL_FUNC_GRP(32), + PINCTRL_FUNC_GRP(33), + PINCTRL_FUNC_GRP(34), + PINCTRL_FUNC_GRP(35), + PINCTRL_FUNC_GRP(36), + PINCTRL_FUNC_GRP(37), + PINCTRL_FUNC_GRP(38), + PINCTRL_FUNC_GRP(39), + PINCTRL_FUNC_GRP(40), + PINCTRL_FUNC_GRP(41), + PINCTRL_FUNC_GRP(42), + PINCTRL_FUNC_GRP(43), + PINCTRL_FUNC_GRP(44), + PINCTRL_FUNC_GRP(45), + PINCTRL_FUNC_GRP(46), + PINCTRL_FUNC_GRP(47), + PINCTRL_FUNC_GRP(48), + PINCTRL_FUNC_GRP(49), + PINCTRL_FUNC_GRP(50), + PINCTRL_FUNC_GRP(51), + PINCTRL_FUNC_GRP(52), + PINCTRL_FUNC_GRP(53), + PINCTRL_FUNC_GRP(54), + PINCTRL_FUNC_GRP(55), + PINCTRL_FUNC_GRP(56), + PINCTRL_FUNC_GRP(57), + PINCTRL_FUNC_GRP(58), + PINCTRL_FUNC_GRP(59), + PINCTRL_FUNC_GRP(60), + PINCTRL_FUNC_GRP(61), + PINCTRL_FUNC_GRP(62), + PINCTRL_FUNC_GRP(64), + PINCTRL_FUNC_GRP(65), + PINCTRL_FUNC_GRP(66), + PINCTRL_FUNC_GRP(67), + PINCTRL_FUNC_GRP(68), + PINCTRL_FUNC_GRP(69), + PINCTRL_FUNC_GRP(70), + PINCTRL_FUNC_GRP(71), + PINCTRL_FUNC_GRP(72), + PINCTRL_FUNC_GRP(73), + PINCTRL_FUNC_GRP(74), + PINCTRL_FUNC_GRP(75), + PINCTRL_FUNC_GRP(76), + PINCTRL_FUNC_GRP(77), + PINCTRL_FUNC_GRP(78), + PINCTRL_FUNC_GRP(79), + PINCTRL_FUNC_GRP(80), + PINCTRL_FUNC_GRP(81), + PINCTRL_FUNC_GRP(82), + PINCTRL_FUNC_GRP(83), + PINCTRL_FUNC_GRP(84), + PINCTRL_FUNC_GRP(85), + PINCTRL_FUNC_GRP(86), + PINCTRL_FUNC_GRP(87), + PINCTRL_FUNC_GRP(88), + PINCTRL_FUNC_GRP(89), + PINCTRL_FUNC_GRP(90), + PINCTRL_FUNC_GRP(91), + PINCTRL_FUNC_GRP(92), + PINCTRL_FUNC_GRP(93), + PINCTRL_FUNC_GRP(94), + PINCTRL_FUNC_GRP(95), + PINCTRL_FUNC_GRP(96), + PINCTRL_FUNC_GRP(97), + PINCTRL_FUNC_GRP(98), + PINCTRL_FUNC_GRP(99), + PINCTRL_FUNC_GRP(100), + PINCTRL_FUNC_GRP(101), + PINCTRL_FUNC_GRP(102), + PINCTRL_FUNC_GRP(103), + PINCTRL_FUNC_GRP(104), + PINCTRL_FUNC_GRP(105), + PINCTRL_FUNC_GRP(106), + PINCTRL_FUNC_GRP(107), + PINCTRL_FUNC_GRP(108), + PINCTRL_FUNC_GRP(109), + PINCTRL_FUNC_GRP(110), + PINCTRL_FUNC_GRP(111), + PINCTRL_FUNC_GRP(112), + PINCTRL_FUNC_GRP(113), + PINCTRL_FUNC_GRP(114), + PINCTRL_FUNC_GRP(115), + PINCTRL_FUNC_GRP(116), + PINCTRL_FUNC_GRP(117), + PINCTRL_FUNC_GRP(118), + PINCTRL_FUNC_GRP(119), + PINCTRL_FUNC_GRP(120), + PINCTRL_FUNC_GRP(121), + PINCTRL_FUNC_GRP(122), + PINCTRL_FUNC_GRP(123), + PINCTRL_FUNC_GRP(124), + PINCTRL_FUNC_GRP(125), + PINCTRL_FUNC_GRP(126), + PINCTRL_FUNC_GRP(127), + PINCTRL_FUNC_GRP(128), + PINCTRL_FUNC_GRP(129), + PINCTRL_FUNC_GRP(130), + PINCTRL_FUNC_GRP(131), + PINCTRL_FUNC_GRP(132), + PINCTRL_FUNC_GRP(133), + PINCTRL_FUNC_GRP(134), + PINCTRL_FUNC_GRP(135), + PINCTRL_FUNC_GRP(136), + PINCTRL_FUNC_GRP(137), + PINCTRL_FUNC_GRP(138), + PINCTRL_FUNC_GRP(139), + PINCTRL_FUNC_GRP(140), + PINCTRL_FUNC_GRP(141), + PINCTRL_FUNC_GRP(142), + PINCTRL_FUNC_GRP(143), + PINCTRL_FUNC_GRP(144), + PINCTRL_GRP("i2c0", i2c0_pins, 2), PINCTRL_GRP("i2c1", i2c1_pins, 2), PINCTRL_GRP("i2c2", i2c2_pins, 2), @@ -309,4 +1192,158 @@ static const struct amd_pingroup kerncz_groups[] = { PINCTRL_GRP("uart1", uart1_pins, 5), }; +#define PMUX_FUNC(_number, _gname1, _gname2, _gname3, _gname4) {\ + .name = "iomux_gpio_"#_number,\ + .groups = {"IMX_F0_GPIO"#_number, "IMX_F1_GPIO"#_number,\ + "IMX_F2_GPIO"#_number, "IMX_F3_GPIO"#_number},\ + .index = _number,\ + .ngroups = NSELECTS } + +static const struct amd_function pmx_functions[] = { + PMUX_FUNC(0, IMX_F0_GPIO0, IMX_F1_GPIO0, IMX_F2_GPIO0, IMX_F3_GPIO0), + PMUX_FUNC(1, IMX_F0_GPIO1, IMX_F1_GPIO1, IMX_F2_GPIO1, IMX_F3_GPIO1), + PMUX_FUNC(2, IMX_F0_GPIO2, IMX_F1_GPIO2, IMX_F2_GPIO2, IMX_F3_GPIO2), + PMUX_FUNC(3, IMX_F0_GPIO3, IMX_F1_GPIO3, IMX_F2_GPIO3, IMX_F3_GPIO3), + PMUX_FUNC(4, IMX_F0_GPIO4, IMX_F1_GPIO4, IMX_F2_GPIO4, IMX_F3_GPIO4), + PMUX_FUNC(5, IMX_F0_GPIO5, IMX_F1_GPIO5, IMX_F2_GPIO5, IMX_F3_GPIO5), + PMUX_FUNC(6, IMX_F0_GPIO6, IMX_F1_GPIO6, IMX_F2_GPIO6, IMX_F3_GPIO6), + PMUX_FUNC(7, IMX_F0_GPIO7, IMX_F1_GPIO7, IMX_F2_GPIO7, IMX_F3_GPIO7), + PMUX_FUNC(8, IMX_F0_GPIO8, IMX_F1_GPIO8, IMX_F2_GPIO8, IMX_F3_GPIO8), + PMUX_FUNC(9, IMX_F0_GPIO9, IMX_F1_GPIO9, IMX_F2_GPIO9, IMX_F3_GPIO9), + PMUX_FUNC(10, IMX_F0_GPIO10, IMX_F1_GPIO10, IMX_F2_GPIO10, IMX_F3_GPIO10), + PMUX_FUNC(11, IMX_F0_GPIO11, IMX_F1_GPIO11, IMX_F2_GPIO11, IMX_F3_GPIO11), + PMUX_FUNC(12, IMX_F0_GPIO12, IMX_F1_GPIO12, IMX_F2_GPIO12, IMX_F3_GPIO12), + PMUX_FUNC(13, IMX_F0_GPIO13, IMX_F1_GPIO13, IMX_F2_GPIO13, IMX_F3_GPIO13), + PMUX_FUNC(14, IMX_F0_GPIO14, IMX_F1_GPIO14, IMX_F2_GPIO14, IMX_F3_GPIO14), + PMUX_FUNC(15, IMX_F0_GPIO15, IMX_F1_GPIO15, IMX_F2_GPIO15, IMX_F3_GPIO15), + PMUX_FUNC(16, IMX_F0_GPIO16, IMX_F1_GPIO16, IMX_F2_GPIO16, IMX_F3_GPIO16), + PMUX_FUNC(17, IMX_F0_GPIO17, IMX_F1_GPIO17, IMX_F2_GPIO17, IMX_F3_GPIO17), + PMUX_FUNC(18, IMX_F0_GPIO18, IMX_F1_GPIO18, IMX_F2_GPIO18, IMX_F3_GPIO18), + PMUX_FUNC(19, IMX_F0_GPIO19, IMX_F1_GPIO19, IMX_F2_GPIO19, IMX_F3_GPIO19), + PMUX_FUNC(20, IMX_F0_GPIO20, IMX_F1_GPIO20, IMX_F2_GPIO20, IMX_F3_GPIO20), + PMUX_FUNC(21, IMX_F0_GPIO21, IMX_F1_GPIO21, IMX_F2_GPIO21, IMX_F3_GPIO21), + PMUX_FUNC(22, IMX_F0_GPIO22, IMX_F1_GPIO22, IMX_F2_GPIO22, IMX_F3_GPIO22), + PMUX_FUNC(23, IMX_F0_GPIO23, IMX_F1_GPIO23, IMX_F2_GPIO23, IMX_F3_GPIO23), + PMUX_FUNC(24, IMX_F0_GPIO24, IMX_F1_GPIO24, IMX_F2_GPIO24, IMX_F3_GPIO24), + PMUX_FUNC(25, IMX_F0_GPIO25, IMX_F1_GPIO25, IMX_F2_GPIO25, IMX_F3_GPIO25), + PMUX_FUNC(26, IMX_F0_GPIO26, IMX_F1_GPIO26, IMX_F2_GPIO26, IMX_F3_GPIO26), + PMUX_FUNC(27, IMX_F0_GPIO27, IMX_F1_GPIO27, IMX_F2_GPIO27, IMX_F3_GPIO27), + PMUX_FUNC(28, IMX_F0_GPIO28, IMX_F1_GPIO28, IMX_F2_GPIO28, IMX_F3_GPIO28), + PMUX_FUNC(29, IMX_F0_GPIO29, IMX_F1_GPIO29, IMX_F2_GPIO29, IMX_F3_GPIO29), + PMUX_FUNC(30, IMX_F0_GPIO30, IMX_F1_GPIO30, IMX_F2_GPIO30, IMX_F3_GPIO30), + PMUX_FUNC(31, IMX_F0_GPIO31, IMX_F1_GPIO31, IMX_F2_GPIO31, IMX_F3_GPIO31), + PMUX_FUNC(32, IMX_F0_GPIO32, IMX_F1_GPIO32, IMX_F2_GPIO32, IMX_F3_GPIO32), + PMUX_FUNC(33, IMX_F0_GPIO33, IMX_F1_GPIO33, IMX_F2_GPIO33, IMX_F3_GPIO33), + PMUX_FUNC(34, IMX_F0_GPIO34, IMX_F1_GPIO34, IMX_F2_GPIO34, IMX_F3_GPIO34), + PMUX_FUNC(35, IMX_F0_GPIO35, IMX_F1_GPIO35, IMX_F2_GPIO35, IMX_F3_GPIO35), + PMUX_FUNC(36, IMX_F0_GPIO36, IMX_F1_GPIO36, IMX_F2_GPIO36, IMX_F3_GPIO36), + PMUX_FUNC(37, IMX_F0_GPIO37, IMX_F1_GPIO37, IMX_F2_GPIO37, IMX_F3_GPIO37), + PMUX_FUNC(38, IMX_F0_GPIO38, IMX_F1_GPIO38, IMX_F2_GPIO38, IMX_F3_GPIO38), + PMUX_FUNC(39, IMX_F0_GPIO39, IMX_F1_GPIO39, IMX_F2_GPIO39, IMX_F3_GPIO39), + PMUX_FUNC(40, IMX_F0_GPIO40, IMX_F1_GPIO40, IMX_F2_GPIO40, IMX_F3_GPIO40), + PMUX_FUNC(41, IMX_F0_GPIO41, IMX_F1_GPIO41, IMX_F2_GPIO41, IMX_F3_GPIO41), + PMUX_FUNC(42, IMX_F0_GPIO42, IMX_F1_GPIO42, IMX_F2_GPIO42, IMX_F3_GPIO42), + PMUX_FUNC(43, IMX_F0_GPIO43, IMX_F1_GPIO43, IMX_F2_GPIO43, IMX_F3_GPIO43), + PMUX_FUNC(44, IMX_F0_GPIO44, IMX_F1_GPIO44, IMX_F2_GPIO44, IMX_F3_GPIO44), + PMUX_FUNC(45, IMX_F0_GPIO45, IMX_F1_GPIO45, IMX_F2_GPIO45, IMX_F3_GPIO45), + PMUX_FUNC(46, IMX_F0_GPIO46, IMX_F1_GPIO46, IMX_F2_GPIO46, IMX_F3_GPIO46), + PMUX_FUNC(47, IMX_F0_GPIO47, IMX_F1_GPIO47, IMX_F2_GPIO47, IMX_F3_GPIO47), + PMUX_FUNC(48, IMX_F0_GPIO48, IMX_F1_GPIO48, IMX_F2_GPIO48, IMX_F3_GPIO48), + PMUX_FUNC(49, IMX_F0_GPIO49, IMX_F1_GPIO49, IMX_F2_GPIO49, IMX_F3_GPIO49), + PMUX_FUNC(50, IMX_F0_GPIO50, IMX_F1_GPIO50, IMX_F2_GPIO50, IMX_F3_GPIO50), + PMUX_FUNC(51, IMX_F0_GPIO51, IMX_F1_GPIO51, IMX_F2_GPIO51, IMX_F3_GPIO41), + PMUX_FUNC(52, IMX_F0_GPIO52, IMX_F1_GPIO52, IMX_F2_GPIO52, IMX_F3_GPIO52), + PMUX_FUNC(53, IMX_F0_GPIO53, IMX_F1_GPIO53, IMX_F2_GPIO53, IMX_F3_GPIO53), + PMUX_FUNC(54, IMX_F0_GPIO54, IMX_F1_GPIO54, IMX_F2_GPIO54, IMX_F3_GPIO54), + PMUX_FUNC(55, IMX_F0_GPIO55, IMX_F1_GPIO55, IMX_F2_GPIO55, IMX_F3_GPIO55), + PMUX_FUNC(56, IMX_F0_GPIO56, IMX_F1_GPIO56, IMX_F2_GPIO56, IMX_F3_GPIO56), + PMUX_FUNC(57, IMX_F0_GPIO57, IMX_F1_GPIO57, IMX_F2_GPIO57, IMX_F3_GPIO57), + PMUX_FUNC(58, IMX_F0_GPIO58, IMX_F1_GPIO58, IMX_F2_GPIO58, IMX_F3_GPIO58), + PMUX_FUNC(59, IMX_F0_GPIO59, IMX_F1_GPIO59, IMX_F2_GPIO59, IMX_F3_GPIO59), + PMUX_FUNC(60, IMX_F0_GPIO60, IMX_F1_GPIO60, IMX_F2_GPIO60, IMX_F3_GPIO60), + PMUX_FUNC(61, IMX_F0_GPIO61, IMX_F1_GPIO61, IMX_F2_GPIO61, IMX_F3_GPIO61), + PMUX_FUNC(62, IMX_F0_GPIO62, IMX_F1_GPIO62, IMX_F2_GPIO62, IMX_F3_GPIO62), + PMUX_FUNC(64, IMX_F0_GPIO64, IMX_F1_GPIO64, IMX_F2_GPIO64, IMX_F3_GPIO64), + PMUX_FUNC(65, IMX_F0_GPIO65, IMX_F1_GPIO65, IMX_F2_GPIO65, IMX_F3_GPIO65), + PMUX_FUNC(66, IMX_F0_GPIO66, IMX_F1_GPIO66, IMX_F2_GPIO66, IMX_F3_GPIO66), + PMUX_FUNC(67, IMX_F0_GPIO67, IMX_F1_GPIO67, IMX_F2_GPIO67, IMX_F3_GPIO67), + PMUX_FUNC(68, IMX_F0_GPIO68, IMX_F1_GPIO68, IMX_F2_GPIO68, IMX_F3_GPIO68), + PMUX_FUNC(69, IMX_F0_GPIO69, IMX_F1_GPIO69, IMX_F2_GPIO69, IMX_F3_GPIO69), + PMUX_FUNC(70, IMX_F0_GPIO70, IMX_F1_GPIO70, IMX_F2_GPIO70, IMX_F3_GPIO70), + PMUX_FUNC(71, IMX_F0_GPIO71, IMX_F1_GPIO71, IMX_F2_GPIO71, IMX_F3_GPIO71), + PMUX_FUNC(72, IMX_F0_GPIO72, IMX_F1_GPIO72, IMX_F2_GPIO72, IMX_F3_GPIO72), + PMUX_FUNC(73, IMX_F0_GPIO73, IMX_F1_GPIO73, IMX_F2_GPIO73, IMX_F3_GPIO73), + PMUX_FUNC(74, IMX_F0_GPIO74, IMX_F1_GPIO74, IMX_F2_GPIO74, IMX_F3_GPIO74), + PMUX_FUNC(75, IMX_F0_GPIO75, IMX_F1_GPIO75, IMX_F2_GPIO75, IMX_F3_GPIO75), + PMUX_FUNC(76, IMX_F0_GPIO76, IMX_F1_GPIO76, IMX_F2_GPIO76, IMX_F3_GPIO76), + PMUX_FUNC(77, IMX_F0_GPIO77, IMX_F1_GPIO77, IMX_F2_GPIO77, IMX_F3_GPIO77), + PMUX_FUNC(78, IMX_F0_GPIO78, IMX_F1_GPIO78, IMX_F2_GPIO78, IMX_F3_GPIO78), + PMUX_FUNC(79, IMX_F0_GPIO79, IMX_F1_GPIO79, IMX_F2_GPIO79, IMX_F3_GPIO79), + PMUX_FUNC(80, IMX_F0_GPIO80, IMX_F1_GPIO80, IMX_F2_GPIO80, IMX_F3_GPIO80), + PMUX_FUNC(81, IMX_F0_GPIO81, IMX_F1_GPIO81, IMX_F2_GPIO81, IMX_F3_GPIO81), + PMUX_FUNC(82, IMX_F0_GPIO82, IMX_F1_GPIO82, IMX_F2_GPIO82, IMX_F3_GPIO82), + PMUX_FUNC(83, IMX_F0_GPIO83, IMX_F1_GPIO83, IMX_F2_GPIO83, IMX_F3_GPIO83), + PMUX_FUNC(84, IMX_F0_GPIO84, IMX_F1_GPIO84, IMX_F2_GPIO84, IMX_F3_GPIO84), + PMUX_FUNC(85, IMX_F0_GPIO85, IMX_F1_GPIO85, IMX_F2_GPIO85, IMX_F3_GPIO85), + PMUX_FUNC(86, IMX_F0_GPIO86, IMX_F1_GPIO86, IMX_F2_GPIO86, IMX_F3_GPIO86), + PMUX_FUNC(87, IMX_F0_GPIO87, IMX_F1_GPIO87, IMX_F2_GPIO87, IMX_F3_GPIO87), + PMUX_FUNC(88, IMX_F0_GPIO88, IMX_F1_GPIO88, IMX_F2_GPIO88, IMX_F3_GPIO88), + PMUX_FUNC(89, IMX_F0_GPIO89, IMX_F1_GPIO89, IMX_F2_GPIO89, IMX_F3_GPIO89), + PMUX_FUNC(90, IMX_F0_GPIO90, IMX_F1_GPIO90, IMX_F2_GPIO90, IMX_F3_GPIO90), + PMUX_FUNC(91, IMX_F0_GPIO91, IMX_F1_GPIO91, IMX_F2_GPIO91, IMX_F3_GPIO91), + PMUX_FUNC(92, IMX_F0_GPIO92, IMX_F1_GPIO92, IMX_F2_GPIO92, IMX_F3_GPIO92), + PMUX_FUNC(93, IMX_F0_GPIO93, IMX_F1_GPIO93, IMX_F2_GPIO93, IMX_F3_GPIO93), + PMUX_FUNC(94, IMX_F0_GPIO94, IMX_F1_GPIO94, IMX_F2_GPIO94, IMX_F3_GPIO94), + PMUX_FUNC(95, IMX_F0_GPIO95, IMX_F1_GPIO95, IMX_F2_GPIO95, IMX_F3_GPIO95), + PMUX_FUNC(96, IMX_F0_GPIO96, IMX_F1_GPIO96, IMX_F2_GPIO96, IMX_F3_GPIO96), + PMUX_FUNC(97, IMX_F0_GPIO97, IMX_F1_GPIO97, IMX_F2_GPIO97, IMX_F3_GPIO97), + PMUX_FUNC(98, IMX_F0_GPIO98, IMX_F1_GPIO98, IMX_F2_GPIO98, IMX_F3_GPIO98), + PMUX_FUNC(99, IMX_F0_GPIO99, IMX_F1_GPIO99, IMX_F2_GPIO99, IMX_F3_GPIO99), + PMUX_FUNC(100, IMX_F0_GPIO100, IMX_F1_GPIO100, IMX_F2_GPIO100, IMX_F3_GPIO100), + PMUX_FUNC(101, IMX_F0_GPIO101, IMX_F1_GPIO101, IMX_F2_GPIO101, IMX_F3_GPIO101), + PMUX_FUNC(102, IMX_F0_GPIO102, IMX_F1_GPIO102, IMX_F2_GPIO102, IMX_F3_GPIO102), + PMUX_FUNC(103, IMX_F0_GPIO103, IMX_F1_GPIO103, IMX_F2_GPIO103, IMX_F3_GPIO103), + PMUX_FUNC(104, IMX_F0_GPIO104, IMX_F1_GPIO104, IMX_F2_GPIO104, IMX_F3_GPIO104), + PMUX_FUNC(105, IMX_F0_GPIO105, IMX_F1_GPIO105, IMX_F2_GPIO105, IMX_F3_GPIO105), + PMUX_FUNC(106, IMX_F0_GPIO106, IMX_F1_GPIO106, IMX_F2_GPIO106, IMX_F3_GPIO106), + PMUX_FUNC(107, IMX_F0_GPIO107, IMX_F1_GPIO107, IMX_F2_GPIO107, IMX_F3_GPIO107), + PMUX_FUNC(108, IMX_F0_GPIO108, IMX_F1_GPIO108, IMX_F2_GPIO108, IMX_F3_GPIO108), + PMUX_FUNC(109, IMX_F0_GPIO109, IMX_F1_GPIO109, IMX_F2_GPIO109, IMX_F3_GPIO109), + PMUX_FUNC(110, IMX_F0_GPIO110, IMX_F1_GPIO110, IMX_F2_GPIO110, IMX_F3_GPIO110), + PMUX_FUNC(111, IMX_F0_GPIO111, IMX_F1_GPIO111, IMX_F2_GPIO111, IMX_F3_GPIO111), + PMUX_FUNC(112, IMX_F0_GPIO112, IMX_F1_GPIO112, IMX_F2_GPIO112, IMX_F3_GPIO112), + PMUX_FUNC(113, IMX_F0_GPIO113, IMX_F1_GPIO113, IMX_F2_GPIO113, IMX_F3_GPIO113), + PMUX_FUNC(114, IMX_F0_GPIO114, IMX_F1_GPIO114, IMX_F2_GPIO114, IMX_F3_GPIO114), + PMUX_FUNC(115, IMX_F0_GPIO115, IMX_F1_GPIO115, IMX_F2_GPIO115, IMX_F3_GPIO115), + PMUX_FUNC(116, IMX_F0_GPIO116, IMX_F1_GPIO116, IMX_F2_GPIO116, IMX_F3_GPIO116), + PMUX_FUNC(117, IMX_F0_GPIO117, IMX_F1_GPIO117, IMX_F2_GPIO117, IMX_F3_GPIO117), + PMUX_FUNC(118, IMX_F0_GPIO118, IMX_F1_GPIO118, IMX_F2_GPIO118, IMX_F3_GPIO118), + PMUX_FUNC(119, IMX_F0_GPIO119, IMX_F1_GPIO119, IMX_F2_GPIO119, IMX_F3_GPIO119), + PMUX_FUNC(120, IMX_F0_GPIO120, IMX_F1_GPIO120, IMX_F2_GPIO120, IMX_F3_GPIO120), + PMUX_FUNC(121, IMX_F0_GPIO121, IMX_F1_GPIO121, IMX_F2_GPIO121, IMX_F3_GPIO121), + PMUX_FUNC(122, IMX_F0_GPIO122, IMX_F1_GPIO122, IMX_F2_GPIO122, IMX_F3_GPIO122), + PMUX_FUNC(123, IMX_F0_GPIO123, IMX_F1_GPIO123, IMX_F2_GPIO123, IMX_F3_GPIO123), + PMUX_FUNC(124, IMX_F0_GPIO124, IMX_F1_GPIO124, IMX_F2_GPIO124, IMX_F3_GPIO124), + PMUX_FUNC(125, IMX_F0_GPIO125, IMX_F1_GPIO125, IMX_F2_GPIO125, IMX_F3_GPIO125), + PMUX_FUNC(126, IMX_F0_GPIO126, IMX_F1_GPIO126, IMX_F2_GPIO126, IMX_F3_GPIO126), + PMUX_FUNC(127, IMX_F0_GPIO127, IMX_F1_GPIO127, IMX_F2_GPIO127, IMX_F3_GPIO127), + PMUX_FUNC(128, IMX_F0_GPIO128, IMX_F1_GPIO128, IMX_F2_GPIO128, IMX_F3_GPIO128), + PMUX_FUNC(129, IMX_F0_GPIO129, IMX_F1_GPIO129, IMX_F2_GPIO129, IMX_F3_GPIO129), + PMUX_FUNC(130, IMX_F0_GPIO130, IMX_F1_GPIO130, IMX_F2_GPIO130, IMX_F3_GPIO130), + PMUX_FUNC(131, IMX_F0_GPIO131, IMX_F1_GPIO131, IMX_F2_GPIO131, IMX_F3_GPIO131), + PMUX_FUNC(132, IMX_F0_GPIO132, IMX_F1_GPIO132, IMX_F2_GPIO132, IMX_F3_GPIO132), + PMUX_FUNC(133, IMX_F0_GPIO133, IMX_F1_GPIO133, IMX_F2_GPIO133, IMX_F3_GPIO133), + PMUX_FUNC(134, IMX_F0_GPIO134, IMX_F1_GPIO134, IMX_F2_GPIO134, IMX_F3_GPIO134), + PMUX_FUNC(135, IMX_F0_GPIO135, IMX_F1_GPIO135, IMX_F2_GPIO135, IMX_F3_GPIO135), + PMUX_FUNC(136, IMX_F0_GPIO136, IMX_F1_GPIO136, IMX_F2_GPIO136, IMX_F3_GPIO136), + PMUX_FUNC(137, IMX_F0_GPIO137, IMX_F1_GPIO137, IMX_F2_GPIO137, IMX_F3_GPIO137), + PMUX_FUNC(138, IMX_F0_GPIO138, IMX_F1_GPIO138, IMX_F2_GPIO138, IMX_F3_GPIO138), + PMUX_FUNC(139, IMX_F0_GPIO139, IMX_F1_GPIO139, IMX_F2_GPIO139, IMX_F3_GPIO139), + PMUX_FUNC(140, IMX_F0_GPIO140, IMX_F1_GPIO140, IMX_F2_GPIO140, IMX_F3_GPIO140), + PMUX_FUNC(141, IMX_F0_GPIO141, IMX_F1_GPIO141, IMX_F2_GPIO141, IMX_F3_GPIO141), + PMUX_FUNC(142, IMX_F0_GPIO142, IMX_F1_GPIO142, IMX_F2_GPIO142, IMX_F3_GPIO142), + PMUX_FUNC(143, IMX_F0_GPIO143, IMX_F1_GPIO143, IMX_F2_GPIO143, IMX_F3_GPIO143), + PMUX_FUNC(144, IMX_F0_GPIO144, IMX_F1_GPIO144, IMX_F2_GPIO144, IMX_F3_GPIO144), +}; + #endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 3/3] pinctrl: amd: Implement pinmux functionality 2022-05-24 7:40 ` [PATCH v2 3/3] pinctrl: amd: Implement pinmux functionality Basavaraj Natikar @ 2022-05-24 9:41 ` Linus Walleij 0 siblings, 0 replies; 23+ messages in thread From: Linus Walleij @ 2022-05-24 9:41 UTC (permalink / raw) To: Basavaraj Natikar; +Cc: Shyam-sundar.S-k, linux-gpio Hi Basavaraj, thanks for your patch! On Tue, May 24, 2022 at 9:40 AM Basavaraj Natikar <Basavaraj.Natikar@amd.com> wrote: > > Provide pinmux functionality by implementing pinmux_ops. > > Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> This has the same request as patch 1, prefix macros with AMD_* (...) > +#define DEFINE_GPIO(_number) static const unsigned int gpio##_number[] = {_number} Like this > #define PINCTRL_GRP(_name, _pins, _npins) \ > { .name = _name, .pins = _pins, .npins = _npins} Hm this one was in patch 1, already commented > +#define PINCTRL_FUNC_GRP(_number) \ > + [IMX_F0_GPIO##_number] = PINCTRL_GRP("IMX_F0_GPIO"#_number, gpio##_number, 1),\ > + [IMX_F1_GPIO##_number] = PINCTRL_GRP("IMX_F1_GPIO"#_number, gpio##_number, 1),\ > + [IMX_F2_GPIO##_number] = PINCTRL_GRP("IMX_F2_GPIO"#_number, gpio##_number, 1),\ > + [IMX_F3_GPIO##_number] = PINCTRL_GRP("IMX_F3_GPIO"#_number, gpio##_number, 1) Prefix this one > +#define PMUX_FUNC(_number, _gname1, _gname2, _gname3, _gname4) {\ > + .name = "iomux_gpio_"#_number,\ > + .groups = {"IMX_F0_GPIO"#_number, "IMX_F1_GPIO"#_number,\ > + "IMX_F2_GPIO"#_number, "IMX_F3_GPIO"#_number},\ > + .index = _number,\ > + .ngroups = NSELECTS } And this Apart from that it all looks reasonable to me. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2022-05-26 6:31 UTC | newest] Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-05-24 7:40 [PATCH v2 0/3] Enhancements to AMD pinctrl and implementation of AMD pinmux Basavaraj Natikar 2022-05-24 7:40 ` [PATCH v2 1/3] pinctrl: amd: Define and use PINCTRL_GRP Basavaraj Natikar 2022-05-24 9:36 ` Linus Walleij 2022-05-24 14:34 ` Andy Shevchenko 2022-05-24 14:38 ` Andy Shevchenko 2022-05-25 6:05 ` Linus Walleij 2022-05-26 6:27 ` Basavaraj Natikar 2022-05-24 7:40 ` [PATCH v2 2/3] pinctrl: amd: Get and update IOMUX details Basavaraj Natikar 2022-05-24 9:38 ` Linus Walleij 2022-05-24 11:18 ` Basavaraj Natikar 2022-05-24 11:37 ` Mika Westerberg 2022-05-24 11:52 ` Basavaraj Natikar 2022-05-24 12:07 ` Mika Westerberg 2022-05-24 12:24 ` Basavaraj Natikar 2022-05-24 12:34 ` Mika Westerberg 2022-05-24 13:50 ` Basavaraj Natikar 2022-05-24 16:39 ` Andy Shevchenko 2022-05-25 9:42 ` Basavaraj Natikar 2022-05-25 16:45 ` Andy Shevchenko 2022-05-26 6:30 ` Basavaraj Natikar 2022-05-24 13:06 ` Andy Shevchenko 2022-05-24 7:40 ` [PATCH v2 3/3] pinctrl: amd: Implement pinmux functionality Basavaraj Natikar 2022-05-24 9:41 ` Linus Walleij
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