* [U-Boot] [PATCH v6 02/10] mips: add base support for QCA/Atheros ath79 SOCs
[not found] <1451906101-9801-2-git-send-email-wills.wang@live.com>
@ 2016-01-04 11:14 ` Wills Wang
2016-01-04 11:14 ` [U-Boot] [PATCH v6 03/10] mips: ath79: add support for AR933x SOCs Wills Wang
` (7 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-04 11:14 UTC (permalink / raw)
To: u-boot
Signed-off-by: Wills Wang <wills.wang@live.com>
---
Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early
Changes in v5:
- Add independent Kconfig
- Use SRAM for initial stack
- Move DDR initialization into board_early_init_f
- Convert DDR tap tunning code to C
- Save SOC's version into arch_global_data
Changes in v4:
- Use global_data to save CPU/DDR/AHB clock
- Use arch_global_data to save SOC's type, revison and id
Changes in v3:
- Move SoC specific header files into arch/mips/mach-ath79/include/mach
- Optimize assembly code
- Same code style convertion
Changes in v2:
- Move all SoC specific header files into arch/mips/include/asm/arch-ath79
- Check SOC type and extract common code into arch/mips/mach-ath79
arch/mips/Kconfig | 6 +
arch/mips/Makefile | 1 +
arch/mips/include/asm/global_data.h | 6 +
arch/mips/mach-ath79/Kconfig | 10 +
arch/mips/mach-ath79/Makefile | 7 +
arch/mips/mach-ath79/cpu.c | 204 ++++
arch/mips/mach-ath79/dram.c | 17 +
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1187 +++++++++++++++++++++++
arch/mips/mach-ath79/include/mach/ath79.h | 143 +++
arch/mips/mach-ath79/include/mach/ddr.h | 14 +
arch/mips/mach-ath79/include/mach/reset.h | 15 +
arch/mips/mach-ath79/reset.c | 75 ++
12 files changed, 1685 insertions(+)
create mode 100644 arch/mips/mach-ath79/Kconfig
create mode 100644 arch/mips/mach-ath79/Makefile
create mode 100644 arch/mips/mach-ath79/cpu.c
create mode 100644 arch/mips/mach-ath79/dram.c
create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h
create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h
create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h
create mode 100644 arch/mips/mach-ath79/include/mach/reset.h
create mode 100644 arch/mips/mach-ath79/reset.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 388e4c0..c9c6aae 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -53,6 +53,11 @@ config TARGET_PB1X00
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select MIPS_TUNE_4KC
+config ARCH_ATH79
+ bool "Support ath79"
+ select OF_CONTROL
+ select DM
+
endchoice
source "board/dbau1x00/Kconfig"
@@ -60,6 +65,7 @@ source "board/imgtec/malta/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-ath79/Kconfig"
if MIPS
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 90cd590..93c461c 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_ARCH_ATH79) += ath79
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
libs-y += $(machdirs)
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 2d9a0c9..3799e98 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -20,6 +20,12 @@ struct arch_global_data {
unsigned long tbl;
unsigned long lastinc;
#endif
+#ifdef CONFIG_ARCH_ATH79
+ unsigned long id;
+ unsigned long soc;
+ unsigned long rev;
+ unsigned long ver;
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
new file mode 100644
index 0000000..df84876
--- /dev/null
+++ b/arch/mips/mach-ath79/Kconfig
@@ -0,0 +1,10 @@
+menu "QCA/Athroes 7xxx/9xxx platforms"
+ depends on ARCH_ATH79
+
+config SYS_VENDOR
+ default "ath79"
+
+config SYS_SOC
+ default "ath79"
+
+endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
new file mode 100644
index 0000000..6203cf0
--- /dev/null
+++ b/arch/mips/mach-ath79/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o
diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
new file mode 100644
index 0000000..2952679
--- /dev/null
+++ b/arch/mips/mach-ath79/cpu.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <asm/arch/ar71xx_regs.h>
+
+struct ath79_soc_desc {
+ enum ath79_soc_type soc;
+ const char *chip;
+};
+
+static struct ath79_soc_desc desc[] = {
+ {ATH79_SOC_AR7130, "7130"},
+ {ATH79_SOC_AR7141, "7141"},
+ {ATH79_SOC_AR7161, "7161"},
+ {ATH79_SOC_AR7240, "7240"},
+ {ATH79_SOC_AR7242, "7242"},
+ {ATH79_SOC_AR9130, "9130"},
+ {ATH79_SOC_AR9132, "9132"},
+ {ATH79_SOC_AR9330, "9330"},
+ {ATH79_SOC_AR9331, "9331"},
+ {ATH79_SOC_AR9341, "9341"},
+ {ATH79_SOC_AR9342, "9342"},
+ {ATH79_SOC_AR9344, "9344"},
+ {ATH79_SOC_QCA9533, "9533"},
+ {ATH79_SOC_QCA9556, "9556"},
+ {ATH79_SOC_QCA9558, "9558"},
+ {ATH79_SOC_TP9343, "9343"},
+ {ATH79_SOC_QCA9561, "9561"},
+};
+
+int arch_cpu_init(void)
+{
+ const void __iomem *base;
+ enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+ u32 id, major, minor;
+ u32 rev = 0;
+ u32 ver = 1;
+
+ base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+
+ id = readl(base + AR71XX_RESET_REG_REV_ID);
+ major = id & REV_ID_MAJOR_MASK;
+
+ switch (major) {
+ case REV_ID_MAJOR_AR71XX:
+ minor = id & AR71XX_REV_ID_MINOR_MASK;
+ rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+ rev &= AR71XX_REV_ID_REVISION_MASK;
+ switch (minor) {
+ case AR71XX_REV_ID_MINOR_AR7130:
+ soc = ATH79_SOC_AR7130;
+ break;
+
+ case AR71XX_REV_ID_MINOR_AR7141:
+ soc = ATH79_SOC_AR7141;
+ break;
+
+ case AR71XX_REV_ID_MINOR_AR7161:
+ soc = ATH79_SOC_AR7161;
+ break;
+ }
+ break;
+
+ case REV_ID_MAJOR_AR7240:
+ soc = ATH79_SOC_AR7240;
+ rev = id & AR71XX_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR7241:
+ soc = ATH79_SOC_AR7241;
+ rev = id & AR71XX_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR7242:
+ soc = ATH79_SOC_AR7242;
+ rev = id & AR71XX_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR913X:
+ minor = id & AR71XX_REV_ID_MINOR_MASK;
+ rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+ rev &= AR71XX_REV_ID_REVISION_MASK;
+ switch (minor) {
+ case AR913X_REV_ID_MINOR_AR9130:
+ soc = ATH79_SOC_AR9130;
+ break;
+
+ case AR913X_REV_ID_MINOR_AR9132:
+ soc = ATH79_SOC_AR9132;
+ break;
+ }
+ break;
+
+ case REV_ID_MAJOR_AR9330:
+ soc = ATH79_SOC_AR9330;
+ rev = id & AR71XX_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR9331:
+ soc = ATH79_SOC_AR9331;
+ rev = id & AR71XX_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR9341:
+ soc = ATH79_SOC_AR9341;
+ rev = id & AR934X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR9342:
+ soc = ATH79_SOC_AR9342;
+ rev = id & AR934X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR9344:
+ soc = ATH79_SOC_AR9344;
+ rev = id & AR934X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_QCA9533_V2:
+ ver = 2;
+ /* drop through */
+
+ case REV_ID_MAJOR_QCA9533:
+ soc = ATH79_SOC_QCA9533;
+ rev = id & QCA953X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_QCA9556:
+ soc = ATH79_SOC_QCA9556;
+ rev = id & QCA955X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_QCA9558:
+ soc = ATH79_SOC_QCA9558;
+ rev = id & QCA955X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_TP9343:
+ soc = ATH79_SOC_TP9343;
+ rev = id & QCA956X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_QCA9561:
+ soc = ATH79_SOC_QCA9561;
+ rev = id & QCA956X_REV_ID_REVISION_MASK;
+ break;
+ }
+
+ gd->arch.id = id;
+ gd->arch.soc = soc;
+ gd->arch.rev = rev;
+ gd->arch.ver = ver;
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+ const char *chip = "????";
+ u32 id, rev, ver;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(desc); i++) {
+ if (desc[i].soc == gd->arch.soc) {
+ chip = desc[i].chip;
+ soc = desc[i].soc;
+ break;
+ }
+ }
+
+ id = gd->arch.id;
+ rev = gd->arch.rev;
+ ver = gd->arch.ver;
+
+ switch (soc) {
+ case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9556:
+ case ATH79_SOC_QCA9558:
+ case ATH79_SOC_QCA9561:
+ printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip,
+ ver, rev);
+ break;
+ case ATH79_SOC_TP9343:
+ printf("Qualcomm Atheros TP%s rev %u\n", chip, rev);
+ break;
+ case ATH79_SOC_UNKNOWN:
+ printf("ATH79: unknown SoC, id:0x%08x", id);
+ break;
+ default:
+ printf("Atheros AR%s rev %u\n", chip, rev);
+ }
+
+ return 0;
+}
diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c
new file mode 100644
index 0000000..53810d5
--- /dev/null
+++ b/arch/mips/mach-ath79/dram.c
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/addrspace.h>
+#include <mach/ddr.h>
+
+phys_size_t initdram(int board_type)
+{
+ ddr_tap_tuning();
+ return get_ram_size((void *)KSEG1, SZ_256M);
+}
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
new file mode 100644
index 0000000..c2b7463
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -0,0 +1,1187 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015 Wills Wang, <wills.wang@live.com>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+#endif
+
+#define AR71XX_APB_BASE 0x18000000
+#define AR71XX_GE0_BASE 0x19000000
+#define AR71XX_GE0_SIZE 0x10000
+#define AR71XX_GE1_BASE 0x1a000000
+#define AR71XX_GE1_SIZE 0x10000
+#define AR71XX_EHCI_BASE 0x1b000000
+#define AR71XX_EHCI_SIZE 0x1000
+#define AR71XX_OHCI_BASE 0x1c000000
+#define AR71XX_OHCI_SIZE 0x1000
+#define AR71XX_SPI_BASE 0x1f000000
+#define AR71XX_SPI_SIZE 0x01000000
+
+#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE 0x100
+#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE 0x100
+#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE 0x100
+#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE 0x100
+#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE 0x100
+#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE 0x100
+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE 0x100
+
+#define AR71XX_PCI_MEM_BASE 0x10000000
+#define AR71XX_PCI_MEM_SIZE 0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS 0x10000000
+#define AR71XX_PCI_WIN1_OFFS 0x11000000
+#define AR71XX_PCI_WIN2_OFFS 0x12000000
+#define AR71XX_PCI_WIN3_OFFS 0x13000000
+#define AR71XX_PCI_WIN4_OFFS 0x14000000
+#define AR71XX_PCI_WIN5_OFFS 0x15000000
+#define AR71XX_PCI_WIN6_OFFS 0x16000000
+#define AR71XX_PCI_WIN7_OFFS 0x07000000
+
+#define AR71XX_PCI_CFG_BASE \
+ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE 0x100
+
+#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE 0x100
+#define AR7240_OHCI_BASE 0x1b000000
+#define AR7240_OHCI_SIZE 0x1000
+
+#define AR724X_PCI_MEM_BASE 0x10000000
+#define AR724X_PCI_MEM_SIZE 0x04000000
+
+#define AR724X_PCI_CFG_BASE 0x14000000
+#define AR724X_PCI_CFG_SIZE 0x1000
+#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE 0x1000
+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE 0x100
+
+#define AR724X_EHCI_BASE 0x1b000000
+#define AR724X_EHCI_SIZE 0x1000
+
+#define AR913X_EHCI_BASE 0x1b000000
+#define AR913X_EHCI_SIZE 0x1000
+#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_SIZE 0x30000
+
+#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE 0x14
+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE 0x04
+#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE 0x20000
+#define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000)
+#define AR933X_RTC_SIZE 0x1000
+#define AR933X_EHCI_BASE 0x1b000000
+#define AR933X_EHCI_SIZE 0x1000
+#define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
+#define AR933X_SRIF_SIZE 0x1000
+
+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE 0x14
+#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE 0x20000
+#define AR934X_EHCI_BASE 0x1b000000
+#define AR934X_EHCI_SIZE 0x200
+#define AR934X_NFC_BASE 0x1b000200
+#define AR934X_NFC_SIZE 0xb8
+#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE 0x1000
+
+#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA953X_GMAC_SIZE 0x14
+#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_SIZE 0x20000
+#define QCA953X_RTC_BASE (AR71XX_APB_BASE + 0x00107000)
+#define QCA953X_RTC_SIZE 0x1000
+#define QCA953X_EHCI_BASE 0x1b000000
+#define QCA953X_EHCI_SIZE 0x200
+#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
+#define QCA953X_SRIF_SIZE 0x1000
+
+#define QCA953X_PCI_CFG_BASE0 0x14000000
+#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
+#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
+#define QCA953X_PCI_MEM_BASE0 0x10000000
+#define QCA953X_PCI_MEM_SIZE 0x02000000
+
+#define QCA955X_PCI_MEM_BASE0 0x10000000
+#define QCA955X_PCI_MEM_BASE1 0x12000000
+#define QCA955X_PCI_MEM_SIZE 0x02000000
+#define QCA955X_PCI_CFG_BASE0 0x14000000
+#define QCA955X_PCI_CFG_BASE1 0x16000000
+#define QCA955X_PCI_CFG_SIZE 0x1000
+#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE 0x1000
+#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE 0x100
+
+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE 0x40
+#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE 0x20000
+#define QCA955X_EHCI0_BASE 0x1b000000
+#define QCA955X_EHCI1_BASE 0x1b400000
+#define QCA955X_EHCI_SIZE 0x1000
+#define QCA955X_NFC_BASE 0x1b800200
+#define QCA955X_NFC_SIZE 0xb8
+
+#define QCA956X_PCI_MEM_BASE1 0x12000000
+#define QCA956X_PCI_MEM_SIZE 0x02000000
+#define QCA956X_PCI_CFG_BASE1 0x16000000
+#define QCA956X_PCI_CFG_SIZE 0x1000
+#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
+#define QCA956X_PCI_CRP_SIZE 0x1000
+#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
+#define QCA956X_PCI_CTRL_SIZE 0x100
+
+#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define QCA956X_WMAC_SIZE 0x20000
+#define QCA956X_EHCI0_BASE 0x1b000000
+#define QCA956X_EHCI1_BASE 0x1b400000
+#define QCA956X_EHCI_SIZE 0x200
+#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SIZE 0x64
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_CONFIG 0x00
+#define AR71XX_DDR_REG_CONFIG2 0x04
+#define AR71XX_DDR_REG_MODE 0x08
+#define AR71XX_DDR_REG_EMR 0x0c
+#define AR71XX_DDR_REG_CONTROL 0x10
+#define AR71XX_DDR_REG_REFRESH 0x14
+#define AR71XX_DDR_REG_RD_CYCLE 0x18
+#define AR71XX_DDR_REG_TAP_CTRL0 0x1c
+#define AR71XX_DDR_REG_TAP_CTRL1 0x20
+
+#define AR71XX_DDR_REG_PCI_WIN0 0x7c
+#define AR71XX_DDR_REG_PCI_WIN1 0x80
+#define AR71XX_DDR_REG_PCI_WIN2 0x84
+#define AR71XX_DDR_REG_PCI_WIN3 0x88
+#define AR71XX_DDR_REG_PCI_WIN4 0x8c
+#define AR71XX_DDR_REG_PCI_WIN5 0x90
+#define AR71XX_DDR_REG_PCI_WIN6 0x94
+#define AR71XX_DDR_REG_PCI_WIN7 0x98
+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
+#define AR71XX_DDR_REG_FLUSH_USB 0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0 0x7c
+#define AR724X_DDR_REG_FLUSH_GE1 0x80
+#define AR724X_DDR_REG_FLUSH_USB 0x84
+#define AR724X_DDR_REG_FLUSH_PCIE 0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0 0x7c
+#define AR913X_DDR_REG_FLUSH_GE1 0x80
+#define AR913X_DDR_REG_FLUSH_USB 0x84
+#define AR913X_DDR_REG_FLUSH_WMAC 0x88
+
+#define AR933X_DDR_REG_FLUSH_GE0 0x7c
+#define AR933X_DDR_REG_FLUSH_GE1 0x80
+#define AR933X_DDR_REG_FLUSH_USB 0x84
+#define AR933X_DDR_REG_FLUSH_WMAC 0x88
+#define AR933X_DDR_REG_DDR2_CONFIG 0x8c
+#define AR933X_DDR_REG_EMR2 0x90
+#define AR933X_DDR_REG_EMR3 0x94
+#define AR933X_DDR_REG_BURST 0x98
+#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c
+#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c
+#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c
+
+#define AR934X_DDR_REG_FLUSH_GE0 0x9c
+#define AR934X_DDR_REG_FLUSH_GE1 0xa0
+#define AR934X_DDR_REG_FLUSH_USB 0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC 0xac
+
+#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
+#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
+#define QCA953X_DDR_REG_FLUSH_USB 0xa4
+#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
+#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
+#define QCA953X_DDR_REG_DDR2_CONFIG 0xb8
+#define QCA953X_DDR_REG_BURST 0xc4
+#define QCA953X_DDR_REG_BURST2 0xc8
+#define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc
+#define QCA953X_DDR_REG_CTL_CONF 0x108
+#define QCA953X_DDR_REG_CONFIG3 0x15c
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG 0x00
+#define AR71XX_PLL_REG_SEC_CONFIG 0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
+
+#define AR71XX_PLL_DIV_SHIFT 3
+#define AR71XX_PLL_DIV_MASK 0x1f
+#define AR71XX_CPU_DIV_SHIFT 16
+#define AR71XX_CPU_DIV_MASK 0x3
+#define AR71XX_DDR_DIV_SHIFT 18
+#define AR71XX_DDR_DIV_MASK 0x3
+#define AR71XX_AHB_DIV_SHIFT 20
+#define AR71XX_AHB_DIV_MASK 0x7
+
+#define AR71XX_ETH0_PLL_SHIFT 17
+#define AR71XX_ETH1_PLL_SHIFT 19
+
+#define AR724X_PLL_REG_CPU_CONFIG 0x00
+#define AR724X_PLL_REG_PCIE_CONFIG 0x18
+
+#define AR724X_PLL_DIV_SHIFT 0
+#define AR724X_PLL_DIV_MASK 0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT 10
+#define AR724X_PLL_REF_DIV_MASK 0xf
+#define AR724X_AHB_DIV_SHIFT 19
+#define AR724X_AHB_DIV_MASK 0x1
+#define AR724X_DDR_DIV_SHIFT 22
+#define AR724X_DDR_DIV_MASK 0x3
+
+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
+
+#define AR913X_PLL_REG_CPU_CONFIG 0x00
+#define AR913X_PLL_REG_ETH_CONFIG 0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
+
+#define AR913X_PLL_DIV_SHIFT 0
+#define AR913X_PLL_DIV_MASK 0x3ff
+#define AR913X_DDR_DIV_SHIFT 22
+#define AR913X_DDR_DIV_MASK 0x3
+#define AR913X_AHB_DIV_SHIFT 19
+#define AR913X_AHB_DIV_MASK 0x1
+
+#define AR913X_ETH0_PLL_SHIFT 20
+#define AR913X_ETH1_PLL_SHIFT 22
+
+#define AR933X_PLL_CPU_CONFIG_REG 0x00
+#define AR933X_PLL_CLK_CTRL_REG 0x08
+#define AR933X_PLL_DITHER_FRAC_REG 0x10
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7
+
+#define AR934X_PLL_CPU_CONFIG_REG 0x00
+#define AR934X_PLL_DDR_CONFIG_REG 0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6)
+
+#define QCA953X_PLL_CPU_CONFIG_REG 0x00
+#define QCA953X_PLL_DDR_CONFIG_REG 0x04
+#define QCA953X_PLL_CLK_CTRL_REG 0x08
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
+#define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44
+#define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48
+
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA953X_PLL_CONFIG_PWD BIT(30)
+
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f
+
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f
+
+#define QCA953X_PLL_DIT_FRAC_EN BIT(31)
+
+#define QCA955X_PLL_CPU_CONFIG_REG 0x00
+#define QCA955X_PLL_DDR_CONFIG_REG 0x04
+#define QCA955X_PLL_CLK_CTRL_REG 0x08
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+#define QCA956X_PLL_CPU_CONFIG_REG 0x00
+#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
+#define QCA956X_PLL_DDR_CONFIG_REG 0x08
+#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
+#define QCA956X_PLL_CLK_CTRL_REG 0x10
+
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff
+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
+
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff
+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
+
+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ 0x00
+#define AR71XX_USB_CTRL_REG_CONFIG 0x04
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER 0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
+#define AR71XX_RESET_REG_WDOG_CTRL 0x08
+#define AR71XX_RESET_REG_WDOG 0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
+#define AR71XX_RESET_REG_RESET_MODULE 0x24
+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
+#define AR71XX_RESET_REG_PERFC0 0x30
+#define AR71XX_RESET_REG_PERFC1 0x34
+#define AR71XX_RESET_REG_REV_ID 0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
+#define AR913X_RESET_REG_RESET_MODULE 0x1c
+#define AR913X_RESET_REG_PERF_CTRL 0x20
+#define AR913X_RESET_REG_PERFC0 0x24
+#define AR913X_RESET_REG_PERFC1 0x28
+
+#define AR724X_RESET_REG_RESET_MODULE 0x1c
+
+#define AR933X_RESET_REG_RESET_MODULE 0x1c
+#define AR933X_RESET_REG_BOOTSTRAP 0xac
+
+#define AR934X_RESET_REG_RESET_MODULE 0x1c
+#define AR934X_RESET_REG_BOOTSTRAP 0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+
+#define QCA953X_RESET_REG_RESET_MODULE 0x1c
+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+
+#define QCA955X_RESET_REG_RESET_MODULE 0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
+
+#define QCA956X_RESET_REG_RESET_MODULE 0x1c
+#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
+#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
+
+#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
+#define MISC_INT_ETHSW BIT(12)
+#define MISC_INT_TIMER4 BIT(10)
+#define MISC_INT_TIMER3 BIT(9)
+#define MISC_INT_TIMER2 BIT(8)
+#define MISC_INT_DMA BIT(7)
+#define MISC_INT_OHCI BIT(6)
+#define MISC_INT_PERFC BIT(5)
+#define MISC_INT_WDOG BIT(4)
+#define MISC_INT_UART BIT(3)
+#define MISC_INT_GPIO BIT(2)
+#define MISC_INT_ERROR BIT(1)
+#define MISC_INT_TIMER BIT(0)
+
+#define AR71XX_RESET_EXTERNAL BIT(28)
+#define AR71XX_RESET_FULL_CHIP BIT(24)
+#define AR71XX_RESET_CPU_NMI BIT(21)
+#define AR71XX_RESET_CPU_COLD BIT(20)
+#define AR71XX_RESET_DMA BIT(19)
+#define AR71XX_RESET_SLIC BIT(18)
+#define AR71XX_RESET_STEREO BIT(17)
+#define AR71XX_RESET_DDR BIT(16)
+#define AR71XX_RESET_GE1_MAC BIT(13)
+#define AR71XX_RESET_GE1_PHY BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
+#define AR71XX_RESET_GE0_MAC BIT(9)
+#define AR71XX_RESET_GE0_PHY BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
+#define AR71XX_RESET_USB_HOST BIT(5)
+#define AR71XX_RESET_USB_PHY BIT(4)
+#define AR71XX_RESET_PCI_BUS BIT(1)
+#define AR71XX_RESET_PCI_CORE BIT(0)
+
+#define AR7240_RESET_USB_HOST BIT(5)
+#define AR7240_RESET_OHCI_DLL BIT(3)
+
+#define AR724X_RESET_GE1_MDIO BIT(23)
+#define AR724X_RESET_GE0_MDIO BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
+#define AR724X_RESET_PCIE_PHY BIT(7)
+#define AR724X_RESET_PCIE BIT(6)
+#define AR724X_RESET_USB_HOST BIT(5)
+#define AR724X_RESET_USB_PHY BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
+#define AR913X_RESET_USB_HOST BIT(5)
+#define AR913X_RESET_USB_PHY BIT(4)
+
+#define AR933X_RESET_GE1_MDIO BIT(23)
+#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_GE1_MAC BIT(13)
+#define AR933X_RESET_WMAC BIT(11)
+#define AR933X_RESET_GE0_MAC BIT(9)
+#define AR933X_RESET_USB_HOST BIT(5)
+#define AR933X_RESET_USB_PHY BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define AR934X_RESET_HOST BIT(31)
+#define AR934X_RESET_SLIC BIT(30)
+#define AR934X_RESET_HDMA BIT(29)
+#define AR934X_RESET_EXTERNAL BIT(28)
+#define AR934X_RESET_RTC BIT(27)
+#define AR934X_RESET_PCIE_EP_INT BIT(26)
+#define AR934X_RESET_CHKSUM_ACC BIT(25)
+#define AR934X_RESET_FULL_CHIP BIT(24)
+#define AR934X_RESET_GE1_MDIO BIT(23)
+#define AR934X_RESET_GE0_MDIO BIT(22)
+#define AR934X_RESET_CPU_NMI BIT(21)
+#define AR934X_RESET_CPU_COLD BIT(20)
+#define AR934X_RESET_HOST_RESET_INT BIT(19)
+#define AR934X_RESET_PCIE_EP BIT(18)
+#define AR934X_RESET_UART1 BIT(17)
+#define AR934X_RESET_DDR BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF BIT(14)
+#define AR934X_RESET_GE1_MAC BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
+#define AR934X_RESET_HOST_DMA_INT BIT(10)
+#define AR934X_RESET_GE0_MAC BIT(9)
+#define AR934X_RESET_ETH_SWITCH BIT(8)
+#define AR934X_RESET_PCIE_PHY BIT(7)
+#define AR934X_RESET_PCIE BIT(6)
+#define AR934X_RESET_USB_HOST BIT(5)
+#define AR934X_RESET_USB_PHY BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
+#define AR934X_RESET_LUT BIT(2)
+#define AR934X_RESET_MBOX BIT(1)
+#define AR934X_RESET_I2S BIT(0)
+
+#define QCA953X_RESET_USB_EXT_PWR BIT(29)
+#define QCA953X_RESET_EXTERNAL BIT(28)
+#define QCA953X_RESET_RTC BIT(27)
+#define QCA953X_RESET_FULL_CHIP BIT(24)
+#define QCA953X_RESET_GE1_MDIO BIT(23)
+#define QCA953X_RESET_GE0_MDIO BIT(22)
+#define QCA953X_RESET_CPU_NMI BIT(21)
+#define QCA953X_RESET_CPU_COLD BIT(20)
+#define QCA953X_RESET_DDR BIT(16)
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA953X_RESET_GE1_MAC BIT(13)
+#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
+#define QCA953X_RESET_GE0_MAC BIT(9)
+#define QCA953X_RESET_ETH_SWITCH BIT(8)
+#define QCA953X_RESET_PCIE_PHY BIT(7)
+#define QCA953X_RESET_PCIE BIT(6)
+#define QCA953X_RESET_USB_HOST BIT(5)
+#define QCA953X_RESET_USB_PHY BIT(4)
+#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define QCA955X_RESET_HOST BIT(31)
+#define QCA955X_RESET_SLIC BIT(30)
+#define QCA955X_RESET_HDMA BIT(29)
+#define QCA955X_RESET_EXTERNAL BIT(28)
+#define QCA955X_RESET_RTC BIT(27)
+#define QCA955X_RESET_PCIE_EP_INT BIT(26)
+#define QCA955X_RESET_CHKSUM_ACC BIT(25)
+#define QCA955X_RESET_FULL_CHIP BIT(24)
+#define QCA955X_RESET_GE1_MDIO BIT(23)
+#define QCA955X_RESET_GE0_MDIO BIT(22)
+#define QCA955X_RESET_CPU_NMI BIT(21)
+#define QCA955X_RESET_CPU_COLD BIT(20)
+#define QCA955X_RESET_HOST_RESET_INT BIT(19)
+#define QCA955X_RESET_PCIE_EP BIT(18)
+#define QCA955X_RESET_UART1 BIT(17)
+#define QCA955X_RESET_DDR BIT(16)
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA955X_RESET_NANDF BIT(14)
+#define QCA955X_RESET_GE1_MAC BIT(13)
+#define QCA955X_RESET_SGMII_ANALOG BIT(12)
+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
+#define QCA955X_RESET_HOST_DMA_INT BIT(10)
+#define QCA955X_RESET_GE0_MAC BIT(9)
+#define QCA955X_RESET_SGMII BIT(8)
+#define QCA955X_RESET_PCIE_PHY BIT(7)
+#define QCA955X_RESET_PCIE BIT(6)
+#define QCA955X_RESET_USB_HOST BIT(5)
+#define QCA955X_RESET_USB_PHY BIT(4)
+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
+#define QCA955X_RESET_LUT BIT(2)
+#define QCA955X_RESET_MBOX BIT(1)
+#define QCA955X_RESET_I2S BIT(0)
+
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
+#define AR933X_BOOTSTRAP_DDR2 BIT(13)
+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
+#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define AR934X_BOOTSTRAP_DDR1 BIT(0)
+
+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
+
+#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
+
+#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+ AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
+ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
+ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
+ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
+ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
+ QCA953X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
+#define QCA955X_EXT_INT_USB1 BIT(24)
+#define QCA955X_EXT_INT_USB2 BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+ QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+ (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+ QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+ QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+ (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+ QCA955X_EXT_INT_PCIE_RC2_INT3)
+
+#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
+#define QCA956X_EXT_INT_WMAC_TX BIT(1)
+#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
+#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
+#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
+#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
+#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
+#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
+#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
+#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
+#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
+#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
+#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
+#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
+#define QCA956X_EXT_INT_USB1 BIT(24)
+#define QCA956X_EXT_INT_USB2 BIT(28)
+
+#define QCA956X_EXT_INT_WMAC_ALL \
+ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
+ QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
+
+#define QCA956X_EXT_INT_PCIE_RC1_ALL \
+ (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
+ QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
+ QCA956X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA956X_EXT_INT_PCIE_RC2_ALL \
+ (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
+ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
+ QCA956X_EXT_INT_PCIE_RC2_INT3)
+
+#define REV_ID_MAJOR_MASK 0xfff0
+#define REV_ID_MAJOR_AR71XX 0x00a0
+#define REV_ID_MAJOR_AR913X 0x00b0
+#define REV_ID_MAJOR_AR7240 0x00c0
+#define REV_ID_MAJOR_AR7241 0x0100
+#define REV_ID_MAJOR_AR7242 0x1100
+#define REV_ID_MAJOR_AR9330 0x0110
+#define REV_ID_MAJOR_AR9331 0x1110
+#define REV_ID_MAJOR_AR9341 0x0120
+#define REV_ID_MAJOR_AR9342 0x1120
+#define REV_ID_MAJOR_AR9344 0x2120
+#define REV_ID_MAJOR_QCA9533 0x0140
+#define REV_ID_MAJOR_QCA9533_V2 0x0160
+#define REV_ID_MAJOR_QCA9556 0x0130
+#define REV_ID_MAJOR_QCA9558 0x1130
+#define REV_ID_MAJOR_TP9343 0x0150
+#define REV_ID_MAJOR_QCA9561 0x1150
+
+#define AR71XX_REV_ID_MINOR_MASK 0x3
+#define AR71XX_REV_ID_MINOR_AR7130 0x0
+#define AR71XX_REV_ID_MINOR_AR7141 0x1
+#define AR71XX_REV_ID_MINOR_AR7161 0x2
+#define AR71XX_REV_ID_REVISION_MASK 0x3
+#define AR71XX_REV_ID_REVISION_SHIFT 2
+
+#define AR913X_REV_ID_MINOR_AR9130 0x0
+#define AR913X_REV_ID_MINOR_AR9132 0x1
+
+#define AR934X_REV_ID_REVISION_MASK 0xf
+#define QCA953X_REV_ID_REVISION_MASK 0xf
+#define QCA955X_REV_ID_REVISION_MASK 0xf
+#define QCA956X_REV_ID_REVISION_MASK 0xf
+
+/*
+ * RTC block
+ */
+#define AR933X_RTC_REG_RESET 0x40
+#define AR933X_RTC_REG_STATUS 0x44
+#define AR933X_RTC_REG_DERIVED 0x48
+#define AR933X_RTC_REG_FORCE_WAKE 0x4c
+#define AR933X_RTC_REG_INT_CAUSE 0x50
+#define AR933X_RTC_REG_CAUSE_CLR 0x50
+#define AR933X_RTC_REG_INT_ENABLE 0x54
+#define AR933X_RTC_REG_INT_MASKE 0x58
+
+#define QCA953X_RTC_REG_SYNC_RESET 0x40
+#define QCA953X_RTC_REG_SYNC_STATUS 0x44
+
+/*
+ * SPI block
+ */
+#define AR71XX_SPI_REG_FS 0x00
+#define AR71XX_SPI_REG_CTRL 0x04
+#define AR71XX_SPI_REG_IOC 0x08
+#define AR71XX_SPI_REG_RDS 0x0c
+
+#define AR71XX_SPI_FS_GPIO BIT(0)
+
+#define AR71XX_SPI_CTRL_RD BIT(6)
+#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
+
+#define AR71XX_SPI_IOC_DO BIT(0)
+#define AR71XX_SPI_IOC_CLK BIT(8)
+#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_IOC_CS_ALL \
+ (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2)
+
+/*
+ * GPIO block
+ */
+#define AR71XX_GPIO_REG_OE 0x00
+#define AR71XX_GPIO_REG_IN 0x04
+#define AR71XX_GPIO_REG_OUT 0x08
+#define AR71XX_GPIO_REG_SET 0x0c
+#define AR71XX_GPIO_REG_CLEAR 0x10
+#define AR71XX_GPIO_REG_INT_MODE 0x14
+#define AR71XX_GPIO_REG_INT_TYPE 0x18
+#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
+#define AR71XX_GPIO_REG_INT_PENDING 0x20
+#define AR71XX_GPIO_REG_INT_ENABLE 0x24
+#define AR71XX_GPIO_REG_FUNC 0x28
+#define AR933X_GPIO_REG_FUNC 0x30
+
+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
+#define AR934X_GPIO_REG_FUNC 0x6c
+
+#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
+#define QCA953X_GPIO_REG_FUNC 0x6c
+
+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
+#define QCA955X_GPIO_REG_FUNC 0x6c
+
+#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
+#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
+#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
+#define QCA956X_GPIO_REG_FUNC 0x6c
+
+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
+
+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
+
+#define AR933X_GPIO(x) BIT(x)
+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
+#define AR933X_GPIO_FUNC_RES_TRUE BIT(15)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
+#define AR933X_GPIO_FUNC_XLNA_EN BIT(12)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
+
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
+#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
+
+#define AR934X_GPIO_OUT_GPIO 0
+#define AR934X_GPIO_OUT_SPI_CS1 7
+#define AR934X_GPIO_OUT_LED_LINK0 41
+#define AR934X_GPIO_OUT_LED_LINK1 42
+#define AR934X_GPIO_OUT_LED_LINK2 43
+#define AR934X_GPIO_OUT_LED_LINK3 44
+#define AR934X_GPIO_OUT_LED_LINK4 45
+#define AR934X_GPIO_OUT_EXT_LNA0 46
+#define AR934X_GPIO_OUT_EXT_LNA1 47
+
+#define QCA953X_GPIO(x) BIT(x)
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
+#define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
+#define QCA953X_GPIO_OUT_MUX_MASK(x) (0xff << (x))
+
+#define QCA953X_GPIO_IN_MUX_UART0_SIN 9
+
+#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
+#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
+
+#define AR71XX_GPIO_COUNT 16
+#define AR7240_GPIO_COUNT 18
+#define AR7241_GPIO_COUNT 20
+#define AR913X_GPIO_COUNT 22
+#define AR933X_GPIO_COUNT 30
+#define AR934X_GPIO_COUNT 23
+#define QCA953X_GPIO_COUNT 18
+#define QCA955X_GPIO_COUNT 24
+#define QCA956X_GPIO_COUNT 23
+
+/*
+ * SRIF block
+ */
+#define AR933X_SRIF_DDR_DPLL1_REG 0x240
+#define AR933X_SRIF_DDR_DPLL2_REG 0x244
+#define AR933X_SRIF_DDR_DPLL3_REG 0x248
+#define AR933X_SRIF_DDR_DPLL4_REG 0x24c
+
+#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
+
+#define AR934X_SRIF_DDR_DPLL1_REG 0x240
+#define AR934X_SRIF_DDR_DPLL2_REG 0x244
+#define AR934X_SRIF_DDR_DPLL3_REG 0x248
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
+#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+
+#define QCA953X_SRIF_BB_DPLL1_REG 0x180
+#define QCA953X_SRIF_BB_DPLL2_REG 0x184
+#define QCA953X_SRIF_BB_DPLL3_REG 0x188
+
+#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
+#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
+#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
+
+#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
+#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
+#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
+
+#define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00
+#define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04
+#define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08
+
+#define QCA953X_SRIF_PMU1_REG 0xc40
+#define QCA953X_SRIF_PMU2_REG 0xc44
+
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
+
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
+#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
+
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
+
+#define QCA953X_SRIF_DPLL2_KI_SHIFT 29
+#define QCA953X_SRIF_DPLL2_KI_MASK 0x3
+
+#define QCA953X_SRIF_DPLL2_KD_SHIFT 25
+#define QCA953X_SRIF_DPLL2_KD_MASK 0xf
+
+#define QCA953X_SRIF_DPLL2_PWD BIT(22)
+
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
+
+/*
+ * MII_CTRL block
+ */
+#define AR71XX_MII_REG_MII0_CTRL 0x00
+#define AR71XX_MII_REG_MII1_CTRL 0x04
+
+#define AR71XX_MII_CTRL_IF_MASK 3
+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
+#define AR71XX_MII_CTRL_SPEED_MASK 3
+#define AR71XX_MII_CTRL_SPEED_10 0
+#define AR71XX_MII_CTRL_SPEED_100 1
+#define AR71XX_MII_CTRL_SPEED_1000 2
+
+#define AR71XX_MII0_CTRL_IF_GMII 0
+#define AR71XX_MII0_CTRL_IF_MII 1
+#define AR71XX_MII0_CTRL_IF_RGMII 2
+#define AR71XX_MII0_CTRL_IF_RMII 3
+
+#define AR71XX_MII1_CTRL_IF_RGMII 0
+#define AR71XX_MII1_CTRL_IF_RMII 1
+
+/*
+ * AR933X GMAC interface
+ */
+#define AR933X_GMAC_REG_ETH_CFG 0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
+
+/*
+ * AR934X GMAC Interface
+ */
+#define AR934X_GMAC_REG_ETH_CFG 0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
+#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
+
+/*
+ * QCA953X GMAC Interface
+ */
+#define QCA953X_GMAC_REG_ETH_CFG 0x00
+
+#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
+#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+
+/*
+ * QCA955X GMAC Interface
+ */
+
+#define QCA955X_GMAC_REG_ETH_CFG 0x00
+
+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
+
+#endif /* __ASM_AR71XX_H */
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
new file mode 100644
index 0000000..58c8224
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -0,0 +1,143 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X common definitions
+ *
+ * Copyright (C) 2015 Wills Wang, <wills.wang@live.com>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_ATH79_H
+#define __ASM_MACH_ATH79_H
+
+#include <linux/types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ath79_soc_type {
+ ATH79_SOC_UNKNOWN,
+ ATH79_SOC_AR7130,
+ ATH79_SOC_AR7141,
+ ATH79_SOC_AR7161,
+ ATH79_SOC_AR7240,
+ ATH79_SOC_AR7241,
+ ATH79_SOC_AR7242,
+ ATH79_SOC_AR9130,
+ ATH79_SOC_AR9132,
+ ATH79_SOC_AR9330,
+ ATH79_SOC_AR9331,
+ ATH79_SOC_AR9341,
+ ATH79_SOC_AR9342,
+ ATH79_SOC_AR9344,
+ ATH79_SOC_QCA9533,
+ ATH79_SOC_QCA9556,
+ ATH79_SOC_QCA9558,
+ ATH79_SOC_TP9343,
+ ATH79_SOC_QCA9561,
+};
+
+static inline int soc_is_ar71xx(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7130 ||
+ gd->arch.soc == ATH79_SOC_AR7141 ||
+ gd->arch.soc == ATH79_SOC_AR7161;
+}
+
+static inline int soc_is_ar724x(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7240 ||
+ gd->arch.soc == ATH79_SOC_AR7241 ||
+ gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar7240(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7240;
+}
+
+static inline int soc_is_ar7241(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7241;
+}
+
+static inline int soc_is_ar7242(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar913x(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9130 ||
+ gd->arch.soc == ATH79_SOC_AR9132;
+}
+
+static inline int soc_is_ar933x(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9330 ||
+ gd->arch.soc == ATH79_SOC_AR9331;
+}
+
+static inline int soc_is_ar9341(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9341;
+}
+
+static inline int soc_is_ar9342(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9342;
+}
+
+static inline int soc_is_ar9344(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9344;
+}
+
+static inline int soc_is_ar934x(void)
+{
+ return soc_is_ar9341() ||
+ soc_is_ar9342() ||
+ soc_is_ar9344();
+}
+
+static inline int soc_is_qca9533(void)
+{
+ return gd->arch.soc == ATH79_SOC_QCA9533;
+}
+
+static inline int soc_is_qca953x(void)
+{
+ return soc_is_qca9533();
+}
+
+static inline int soc_is_qca9556(void)
+{
+ return gd->arch.soc == ATH79_SOC_QCA9556;
+}
+
+static inline int soc_is_qca9558(void)
+{
+ return gd->arch.soc == ATH79_SOC_QCA9558;
+}
+
+static inline int soc_is_qca955x(void)
+{
+ return soc_is_qca9556() || soc_is_qca9558();
+}
+
+static inline int soc_is_tp9343(void)
+{
+ return gd->arch.soc == ATH79_SOC_TP9343;
+}
+
+static inline int soc_is_qca9561(void)
+{
+ return gd->arch.soc == ATH79_SOC_QCA9561;
+}
+
+static inline int soc_is_qca956x(void)
+{
+ return soc_is_tp9343() || soc_is_qca9561();
+}
+
+#endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/mach-ath79/include/mach/ddr.h b/arch/mips/mach-ath79/include/mach/ddr.h
new file mode 100644
index 0000000..95e7971
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ddr.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_DDR_H
+#define __ASM_MACH_DDR_H
+
+void ddr_init(void);
+void ddr_tap_tuning(void);
+
+#endif /* __ASM_MACH_DDR_H */
diff --git a/arch/mips/mach-ath79/include/mach/reset.h b/arch/mips/mach-ath79/include/mach/reset.h
new file mode 100644
index 0000000..3e7519d
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/reset.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_RESET_H
+#define __ASM_MACH_RESET_H
+
+#include <linux/types.h>
+
+u32 get_bootstrap(void);
+
+#endif /* __ASM_MACH_RESET_H */
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
new file mode 100644
index 0000000..410b900
--- /dev/null
+++ b/arch/mips/mach-ath79/reset.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+void _machine_restart(void)
+{
+ const void __iomem *base;
+ u32 val, reg = 0;
+
+ base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+ if (soc_is_ar71xx())
+ reg = AR71XX_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar724x())
+ reg = AR724X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar913x())
+ reg = AR913X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar933x())
+ reg = AR933X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar934x())
+ reg = AR934X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca953x())
+ reg = QCA953X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca955x())
+ reg = QCA955X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca956x())
+ reg = QCA956X_RESET_REG_RESET_MODULE;
+ else
+ puts("Reset register not defined for this SOC\n");
+
+ if (reg) {
+ val = readl(base + reg);
+ val |= AR71XX_RESET_FULL_CHIP;
+ writel(val, base + reg);
+ }
+
+ while (1)
+ /* NOP */;
+}
+
+u32 get_bootstrap(void)
+{
+ const void __iomem *base;
+ u32 reg = 0;
+
+ base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+ if (soc_is_ar933x())
+ reg = AR933X_RESET_REG_BOOTSTRAP;
+ else if (soc_is_ar934x())
+ reg = AR934X_RESET_REG_BOOTSTRAP;
+ else if (soc_is_qca953x())
+ reg = QCA953X_RESET_REG_BOOTSTRAP;
+ else if (soc_is_qca955x())
+ reg = QCA955X_RESET_REG_BOOTSTRAP;
+ else if (soc_is_qca956x())
+ reg = QCA956X_RESET_REG_BOOTSTRAP;
+ else
+ puts("Bootstrap register not defined for this SOC\n");
+
+ if (reg)
+ return readl(base + reg);
+
+ return 0;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 03/10] mips: ath79: add support for AR933x SOCs
[not found] <1451906101-9801-2-git-send-email-wills.wang@live.com>
2016-01-04 11:14 ` [U-Boot] [PATCH v6 02/10] mips: add base support for QCA/Atheros ath79 SOCs Wills Wang
@ 2016-01-04 11:14 ` Wills Wang
2016-01-04 11:14 ` [U-Boot] [PATCH v6 04/10] mips: ath79: add support for QCA953x SOCs Wills Wang
` (6 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-04 11:14 UTC (permalink / raw)
To: u-boot
This patch enable work for ar933x SOC.
Signed-off-by: Wills Wang <wills.wang@live.com>
---
Changes in v6:
- Remove board.c
- Define magic value in ddr.c
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/mips/mach-ath79/Kconfig | 10 +
arch/mips/mach-ath79/Makefile | 2 +
arch/mips/mach-ath79/ar933x/Makefile | 7 +
arch/mips/mach-ath79/ar933x/clk.c | 90 ++++++++
arch/mips/mach-ath79/ar933x/ddr.c | 317 ++++++++++++++++++++++++++++
arch/mips/mach-ath79/ar933x/lowlevel_init.S | 280 ++++++++++++++++++++++++
6 files changed, 706 insertions(+)
create mode 100644 arch/mips/mach-ath79/ar933x/Makefile
create mode 100644 arch/mips/mach-ath79/ar933x/clk.c
create mode 100644 arch/mips/mach-ath79/ar933x/ddr.c
create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index df84876..ff2c491 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -7,4 +7,14 @@ config SYS_VENDOR
config SYS_SOC
default "ath79"
+config SOC_AR933X
+ bool
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select MIPS_TUNE_24KC
+ help
+ This supports QCA/Atheros ar933x family SOCs.
+
endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
index 6203cf0..9b9447e 100644
--- a/arch/mips/mach-ath79/Makefile
+++ b/arch/mips/mach-ath79/Makefile
@@ -5,3 +5,5 @@
obj-y += reset.o
obj-y += cpu.o
obj-y += dram.o
+
+obj-$(CONFIG_SOC_AR933X) += ar933x/
\ No newline at end of file
diff --git a/arch/mips/mach-ath79/ar933x/Makefile b/arch/mips/mach-ath79/ar933x/Makefile
new file mode 100644
index 0000000..fd74f0c
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c
new file mode 100644
index 0000000..ae7ccbc
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/clk.c
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 ar933x_get_xtal(void)
+{
+ u32 val;
+
+ val = get_bootstrap();
+ if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+ return 40000000;
+ else
+ return 25000000;
+}
+
+int get_serial_clock(void)
+{
+ return ar933x_get_xtal();
+}
+
+int get_clocks(void)
+{
+ void __iomem *regs;
+ u32 val, xtal, pll, div;
+
+ regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+ MAP_NOCACHE);
+ xtal = ar933x_get_xtal();
+ val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
+
+ /* VCOOUT = XTAL * DIV_INT */
+ div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+ & AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+ pll = xtal / div;
+
+ /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+ div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
+ & AR933X_PLL_CPU_CONFIG_NINT_MASK;
+ pll *= div;
+ div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+ & AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ if (!div)
+ div = 1;
+ pll >>= div;
+
+ val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
+
+ /* CPU_CLK = PLLOUT / CPU_POST_DIV */
+ div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+ & AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+ gd->cpu_clk = pll / div;
+
+ /* DDR_CLK = PLLOUT / DDR_POST_DIV */
+ div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+ & AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+ gd->mem_clk = pll / div;
+
+ /* AHB_CLK = PLLOUT / AHB_POST_DIV */
+ div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+ & AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
+ gd->bus_clk = pll / div;
+
+ return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+ if (!gd->bus_clk)
+ get_clocks();
+ return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+ if (!gd->mem_clk)
+ get_clocks();
+ return gd->mem_clk;
+}
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
new file mode 100644
index 0000000..675d922
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -0,0 +1,317 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_CTRL_UPD_EMR3S BIT(5)
+#define DDR_CTRL_UPD_EMR2S BIT(4)
+#define DDR_CTRL_PRECHARGE BIT(3)
+#define DDR_CTRL_AUTO_REFRESH BIT(2)
+#define DDR_CTRL_UPD_EMRS BIT(1)
+#define DDR_CTRL_UPD_MRS BIT(0)
+
+#define DDR_REFRESH_EN (1 << 14)
+#define DDR_REFRESH_M 0x3ff
+#define DDR_REFRESH(x) ((x) & 0x3ff)
+#define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390))
+#define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624))
+
+#define DDR_TRAS_S 0
+#define DDR_TRAS_M 0x1f
+#define DDR_TRAS(x) ((x) << DDR_TRAS_S)
+#define DDR_TRCD_M 0xf
+#define DDR_TRCD_S 5
+#define DDR_TRCD(x) ((x) << DDR_TRCD_S)
+#define DDR_TRP_M 0xf
+#define DDR_TRP_S 9
+#define DDR_TRP(x) ((x) << DDR_TRP_S)
+#define DDR_TRRD_M 0xf
+#define DDR_TRRD_S 13
+#define DDR_TRRD(x) ((x) << DDR_TRRD_S)
+#define DDR_TRFC_M 0x7f
+#define DDR_TRFC_S 17
+#define DDR_TRFC(x) ((x) << DDR_TRFC_S)
+#define DDR_TMRD_M 0xf
+#define DDR_TMRD_S 23
+#define DDR_TMRD(x) ((x) << DDR_TMRD_S)
+#define DDR_CAS_L_M 0x17
+#define DDR_CAS_L_S 27
+#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
+#define DDR_OPEN (1 << 30)
+#define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \
+ DDR_TRP(6) | DDR_TRRD(4) | \
+ DDR_TRFC(30) | DDR_TMRD(15) | \
+ DDR_CAS_L(7) | DDR_OPEN)
+
+#define DDR_BURST_LEN_S 0
+#define DDR_BURST_LEN_M 0xf
+#define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S)
+#define DDR_BURST_TYPE (1 << 4)
+#define DDR_CNTL_OE_EN (1 << 5)
+#define DDR_PHASE_SEL (1 << 6)
+#define DDR_CKE (1 << 7)
+#define DDR_TWR_S 8
+#define DDR_TWR_M 0xf
+#define DDR_TWR(x) ((x) << DDR_TWR_S)
+#define DDR_TRTW_S 12
+#define DDR_TRTW_M 0x1f
+#define DDR_TRTW(x) ((x) << DDR_TRTW_S)
+#define DDR_TRTP_S 17
+#define DDR_TRTP_M 0xf
+#define DDR_TRTP(x) ((x) << DDR_TRTP_S)
+#define DDR_TWTR_S 21
+#define DDR_TWTR_M 0x1f
+#define DDR_TWTR(x) ((x) << DDR_TWTR_S)
+#define DDR_G_OPEN_L_S 26
+#define DDR_G_OPEN_L_M 0xf
+#define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S)
+#define DDR_HALF_WIDTH_LOW (1 << 31)
+#define DDR_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+ DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
+ DDR_TRTP(8) | DDR_TWTR(14) | \
+ DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW)
+
+#define DDR2_CONF_TWL_S 10
+#define DDR2_CONF_TWL_M 0xf
+#define DDR2_CONF_TWL(x) (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
+#define DDR2_CONF_ODT BIT(9)
+#define DDR2_CONF_TFAW_S 2
+#define DDR2_CONF_TFAW_M 0x3f
+#define DDR2_CONF_TFAW(x) (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
+#define DDR2_CONF_EN BIT(0)
+#define DDR2_CONF_VAL (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \
+ DDR2_CONF_TFAW(22) | DDR2_CONF_EN)
+
+#define DDR1_EXT_MODE_VAL 0x02
+#define DDR2_EXT_MODE_VAL 0x402
+#define DDR2_EXT_MODE_OCD_VAL 0x382
+#define DDR1_MODE_DLL_VAL 0x133
+#define DDR2_MODE_DLL_VAL 0x100
+#define DDR1_MODE_VAL 0x33
+#define DDR2_MODE_VAL 0xa33
+#define DDR_TAP_VAL0 0x08
+#define DDR_TAP_VAL1 0x09
+
+void ddr_init(void)
+{
+ void __iomem *regs;
+ u32 val;
+
+ regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+ MAP_NOCACHE);
+
+ writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+ writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+
+ val = get_bootstrap();
+ if (val & AR933X_BOOTSTRAP_DDR2) {
+ /* AHB maximum timeout */
+ writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+ /* Enable DDR2 */
+ writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Disable High Temperature Self-Refresh, Full Array */
+ writel(0x00, regs + AR933X_DDR_REG_EMR2);
+ /* Extended Mode Register 2 Set (EMR2S) */
+ writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+
+ writel(0x00, regs + AR933X_DDR_REG_EMR3);
+ /* Extended Mode Register 3 Set (EMR3S) */
+ writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Enable DLL, Full strength, ODT Disabled */
+ writel(0x00, regs + AR71XX_DDR_REG_EMR);
+ /* Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Reset DLL */
+ writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+ /* Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Auto Refresh */
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Write recovery (WR) 6 clock, CAS Latency 3,
+ * Burst Length 8 */
+ writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+ /* Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Enable OCD defaults, Enable DLL,
+ * Reduced Drive Strength */
+ writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+ /* Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* OCD exit, Enable DLL, Enable /DQS,
+ * Reduced Drive Strength */
+ writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+ /* Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Refresh time control */
+ if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+ writel(DDR_REFRESH_VAL_40M, regs +
+ AR71XX_DDR_REG_REFRESH);
+ else
+ writel(DDR_REFRESH_VAL_25M, regs +
+ AR71XX_DDR_REG_REFRESH);
+
+ /* DQS 0 Tap Control */
+ writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ /* DQS 1 Tap Control */
+ writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+ /* For 16-bit DDR */
+ writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
+ } else {
+ /* AHB maximum timeout */
+ writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Reset DLL, Burst Length 8, CAS Latency 3 */
+ writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+ /* Forces an MRS update cycle in DDR */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Enable DLL, Full strength */
+ writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+ /* Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Normal DLL, Burst Length 8, CAS Latency 3 */
+ writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+ /* Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Refresh time control */
+ if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+ writel(DDR_REFRESH_VAL_40M, regs +
+ AR71XX_DDR_REG_REFRESH);
+ else
+ writel(DDR_REFRESH_VAL_25M, regs +
+ AR71XX_DDR_REG_REFRESH);
+
+ /* DQS 0 Tap Control */
+ writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ /* DQS 1 Tap Control */
+ writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+ /* For 16-bit DDR */
+ writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
+ }
+}
+
+void ddr_tap_tuning(void)
+{
+ void __iomem *regs;
+ u32 *addr_k0, *addr_k1, *addr;
+ u32 val, tap, upper, lower;
+ int i, j, dir, err, done;
+
+ regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+ MAP_NOCACHE);
+
+ addr = (void *)KSEG0ADDR(0x2000);
+ for (i = 0; i < 256; i++) {
+ val = 0;
+ for (j = 0; j < 8; j++) {
+ if (i & (1 << j)) {
+ if (j % 2)
+ val |= 0xffff0000;
+ else
+ val |= 0x0000ffff;
+ }
+
+ if (j % 2) {
+ *addr++ = val;
+ val = 0;
+ }
+ }
+ }
+
+ err = 0;
+ done = 0;
+ dir = 1;
+ tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+ val = tap;
+ while (!done) {
+ err = 0;
+ writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+ for (i = 0; i < 2; i++) {
+ addr_k1 = (void *)KSEG1ADDR(0x2000);
+ addr_k0 = (void *)KSEG0ADDR(0x2000);
+ addr = (void *)KSEG0ADDR(0x3000);
+
+ while (addr_k0 < addr) {
+ if (*addr_k1++ != *addr_k0++) {
+ err = 1;
+ break;
+ }
+ }
+
+ if (err)
+ break;
+ }
+
+ if (err) {
+ if (dir) {
+ dir = 0;
+ val--;
+ upper = val;
+ val = tap;
+ } else {
+ val++;
+ lower = val;
+ done = 1;
+ }
+ } else {
+ if (dir) {
+ if (val < 0x20) {
+ val++;
+ } else {
+ dir = 0;
+ upper = val;
+ val = tap;
+ }
+ } else {
+ if (!val) {
+ lower = val;
+ done = 1;
+ } else {
+ val--;
+ }
+ }
+ }
+ }
+ val = (upper + lower) / 2;
+ writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ val++;
+ writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}
diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S
new file mode 100644
index 0000000..ac4c364
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define SET_BIT(val, bit) ((val) | (1 << (bit)))
+#define SET_PLL_PD(val) SET_BIT(val, 30)
+#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16)
+#define PLL_BYPASS(val) SET_BIT(val, 2)
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+ (((0x3F & divint) << 10) | \
+ ((0x1F & refdiv) << 16) | \
+ ((0x1 & range) << 21) | \
+ ((0x7 & outdiv) << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+ (((0x3 & (cpudiv - 1)) << 5) | \
+ ((0x3 & (ddrdiv - 1)) << 10) | \
+ ((0x3 & (ahbdiv - 1)) << 15) )
+
+/*
+ * PLL_CPU_CONFIG_VAL
+ *
+ * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
+ *
+ * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL)
+ * => 32 (0x20) VCOOUT = XTAL * DIV_INT
+ * bits 16..20 (5bit) REFDIV (Reference clock divider)
+ * => 1 (0x1) [Must start at values 1]
+ * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL)
+ * => 0 (0x0) [Doesn't impact clock values]
+ * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output)
+ * => 1 (0x1) [0 is illegal!]
+ * PLLOUT = VCOOUT * (1/2^OUTDIV)
+ */
+/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1)
+/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1)
+
+/*
+ * PLL_CLK_CONTROL_VAL
+ *
+ * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU Clock Control Register CLOCK_CONTROL
+ *
+ * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test.
+ * Software must enable the CPU PLL for normal and
+ * then set this bit to 0)
+ * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)
+ * CPU_CLK = PLLOUT / CPU_POST_DIV
+ * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)
+ * DDR_CLK = PLLOUT / DDR_POST_DIV
+ * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)
+ * AHB_CLK = PLLOUT / AHB_POST_DIV
+ *
+ */
+#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
+
+ .text
+ .set noreorder
+
+LEAF(lowlevel_init)
+ /* These three WLAN_RESET will avoid original issue */
+ li t3, 0x03
+1:
+ li t0, KSEG1ADDR(AR71XX_RESET_BASE)
+ lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
+ ori t1, t1, 0x0800
+ sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
+ nop
+ lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
+ li t2, 0xfffff7ff
+ and t1, t1, t2
+ sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
+ nop
+ addi t3, t3, -1
+ bnez t3, 1b
+ nop
+
+ li t2, 0x20
+2:
+ beqz t2, 1b
+ nop
+ addi t2, t2, -1
+ lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
+ andi t1, t5, 0x10
+ bnez t1, 2b
+ nop
+
+ li t1, 0x02110E
+ sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
+ nop
+
+ /* RTC Force Wake */
+ li t0, KSEG1ADDR(AR933X_RTC_BASE)
+ li t1, 0x03
+ sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
+ nop
+ nop
+
+ /* RTC Reset */
+ li t1, 0x00
+ sw t1, AR933X_RTC_REG_RESET(t0)
+ nop
+ nop
+
+ li t1, 0x01
+ sw t1, AR933X_RTC_REG_RESET(t0)
+ nop
+ nop
+
+ /* Wait for RTC in on state */
+1:
+ lw t1, AR933X_RTC_REG_STATUS(t0)
+ andi t1, t1, 0x02
+ beqz t1, 1b
+ nop
+
+ /* Program ki/kd */
+ li t0, KSEG1ADDR(AR933X_SRIF_BASE)
+ andi t1, t5, 0x01 # t5 BOOT_STRAP
+ bnez t1, 1f
+ nop
+ li t1, 0x19e82f01
+ b 2f
+ nop
+1:
+ li t1, 0x18e82f01
+2:
+ sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
+
+ /* Program phase shift */
+ lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ li t2, 0xc07fffff
+ and t1, t1, t2
+ li t2, 0x800000
+ or t1, t1, t2
+ sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ nop
+
+ /* in some cases, the SoC doesn't start with higher clock on AHB */
+ li t0, KSEG1ADDR(AR71XX_PLL_BASE)
+ li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
+ sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ /* Set SETTLE_TIME in CPU PLL */
+ andi t1, t5, 0x01 # t5 BOOT_STRAP
+ bnez t1, 1f
+ nop
+ li t1, 0x0352
+ b 2f
+ nop
+1:
+ li t1, 0x0550
+2:
+ sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
+ nop
+
+ /* Set nint, frac, refdiv, outdiv, range according to xtal */
+0:
+ andi t1, t5, 0x01 # t5 BOOT_STRAP
+ bnez t1, 1f
+ nop
+ li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
+ b 2f
+ nop
+1:
+ li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
+2:
+ sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+ nop
+1:
+ lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+ li t2, 0x80000000
+ and t1, t1, t2
+ bnez t1, 1b
+ nop
+
+ /* Put frac bit19:10 configuration */
+ li t1, 0x1003E8
+ sw t1, AR933X_PLL_DITHER_FRAC_REG(t0)
+ nop
+
+ /* Clear PLL power down bit in CPU PLL configuration */
+ andi t1, t5, 0x01 # t5 BOOT_STRAP
+ bnez t1, 1f
+ nop
+ li t1, PLL_CPU_CONFIG_VAL_25M
+ b 2f
+ nop
+1:
+ li t1, PLL_CPU_CONFIG_VAL_40M
+2:
+ sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+ nop
+
+ /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
+1:
+ lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+ li t2, 0x80000000
+ and t1, t1, t2
+ bnez t1, 1b
+ nop
+
+ /* Confirm DDR PLL lock */
+ li t3, 100
+ li t4, 0
+
+2:
+ addi t4, t4, 1
+ bgt t4, t3, 0b
+ nop
+
+ li t3, 5
+3:
+ /* Clear do_meas */
+ li t0, KSEG1ADDR(AR933X_SRIF_BASE)
+ lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ li t2, 0xBFFFFFFF
+ and t1, t1, t2
+ sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ nop
+
+ li t2, 10
+1:
+ subu t2, t2, 1
+ bnez t2, 1b
+ nop
+
+ /* Set do_meas */
+ li t2, 0x40000000
+ or t1, t1, t2
+ sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ nop
+
+ /* Check meas_done */
+1:
+ lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
+ andi t1, t1, 0x8
+ beqz t1, 1b
+ nop
+
+ lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ li t2, 0x007FFFF8
+ and t1, t1, t2
+ srl t1, t1, 3
+ li t2, 0x4000
+ bgt t1, t2, 2b
+ nop
+ addi t3, t3, -1
+ bnez t3, 3b
+ nop
+
+ /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
+ li t0, KSEG1ADDR(AR71XX_PLL_BASE)
+ li t1, PLL_CLK_CONTROL_VAL
+ sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ nop
+ jr ra
+ nop
+ END(lowlevel_init)
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 04/10] mips: ath79: add support for QCA953x SOCs
[not found] <1451906101-9801-2-git-send-email-wills.wang@live.com>
2016-01-04 11:14 ` [U-Boot] [PATCH v6 02/10] mips: add base support for QCA/Atheros ath79 SOCs Wills Wang
2016-01-04 11:14 ` [U-Boot] [PATCH v6 03/10] mips: ath79: add support for AR933x SOCs Wills Wang
@ 2016-01-04 11:14 ` Wills Wang
2016-01-04 11:14 ` [U-Boot] [PATCH v6 05/10] mips: ath79: add serial driver for ar933x SOC Wills Wang
` (5 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-04 11:14 UTC (permalink / raw)
To: u-boot
This patch enable work for qca953x SOC.
Signed-off-by: Wills Wang <wills.wang@live.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/mips/mach-ath79/Kconfig | 10 +
arch/mips/mach-ath79/Makefile | 3 +-
arch/mips/mach-ath79/qca953x/Makefile | 7 +
arch/mips/mach-ath79/qca953x/clk.c | 112 +++++++
arch/mips/mach-ath79/qca953x/ddr.c | 463 +++++++++++++++++++++++++++
arch/mips/mach-ath79/qca953x/lowlevel_init.S | 186 +++++++++++
6 files changed, 780 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/mach-ath79/qca953x/Makefile
create mode 100644 arch/mips/mach-ath79/qca953x/clk.c
create mode 100644 arch/mips/mach-ath79/qca953x/ddr.c
create mode 100644 arch/mips/mach-ath79/qca953x/lowlevel_init.S
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index ff2c491..f7801e4 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -17,4 +17,14 @@ config SOC_AR933X
help
This supports QCA/Atheros ar933x family SOCs.
+config SOC_QCA953X
+ bool
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select MIPS_TUNE_24KC
+ help
+ This supports QCA/Atheros qca953x family SOCs.
+
endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
index 9b9447e..160dfaa 100644
--- a/arch/mips/mach-ath79/Makefile
+++ b/arch/mips/mach-ath79/Makefile
@@ -6,4 +6,5 @@ obj-y += reset.o
obj-y += cpu.o
obj-y += dram.o
-obj-$(CONFIG_SOC_AR933X) += ar933x/
\ No newline at end of file
+obj-$(CONFIG_SOC_AR933X) += ar933x/
+obj-$(CONFIG_SOC_QCA953X) += qca953x/
\ No newline at end of file
diff --git a/arch/mips/mach-ath79/qca953x/Makefile b/arch/mips/mach-ath79/qca953x/Makefile
new file mode 100644
index 0000000..fd74f0c
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c
new file mode 100644
index 0000000..2c0dbbb
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/clk.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 qca953x_get_xtal(void)
+{
+ u32 val;
+
+ val = get_bootstrap();
+ if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
+ return 40000000;
+ else
+ return 25000000;
+}
+
+int get_serial_clock(void)
+{
+ return qca953x_get_xtal();
+}
+
+int get_clocks(void)
+{
+ void __iomem *regs;
+ u32 val, ctrl, xtal, pll, div;
+
+ regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+ MAP_NOCACHE);
+
+ xtal = qca953x_get_xtal();
+ ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
+ val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
+
+ /* VCOOUT = XTAL * DIV_INT */
+ div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+ & QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
+ pll = xtal / div;
+
+ /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+ div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT)
+ & QCA953X_PLL_CPU_CONFIG_NINT_MASK;
+ pll *= div;
+ div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+ & QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ if (!div)
+ div = 1;
+ pll >>= div;
+
+ /* CPU_CLK = PLLOUT / CPU_POST_DIV */
+ div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+ & QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+ gd->cpu_clk = pll / div;
+
+
+ val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
+ /* VCOOUT = XTAL * DIV_INT */
+ div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
+ & QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
+ pll = xtal / div;
+
+ /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+ div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT)
+ & QCA953X_PLL_DDR_CONFIG_NINT_MASK;
+ pll *= div;
+ div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT)
+ & QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ if (!div)
+ div = 1;
+ pll >>= div;
+
+ /* DDR_CLK = PLLOUT / DDR_POST_DIV */
+ div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+ & QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+ gd->mem_clk = pll / div;
+
+ div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+ & QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
+ if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) {
+ /* AHB_CLK = DDR_CLK / AHB_POST_DIV */
+ gd->bus_clk = gd->mem_clk / (div + 1);
+ } else {
+ /* AHB_CLK = CPU_CLK / AHB_POST_DIV */
+ gd->bus_clk = gd->cpu_clk / (div + 1);
+ }
+
+ return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+ if (!gd->bus_clk)
+ get_clocks();
+ return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+ if (!gd->mem_clk)
+ get_clocks();
+ return gd->mem_clk;
+}
diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c
new file mode 100644
index 0000000..520af07
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/ddr.c
@@ -0,0 +1,463 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_CTRL_UPD_EMR3S BIT(5)
+#define DDR_CTRL_UPD_EMR2S BIT(4)
+#define DDR_CTRL_PRECHARGE BIT(3)
+#define DDR_CTRL_AUTO_REFRESH BIT(2)
+#define DDR_CTRL_UPD_EMRS BIT(1)
+#define DDR_CTRL_UPD_MRS BIT(0)
+
+#define DDR_REFRESH_EN BIT(14)
+#define DDR_REFRESH_M 0x3ff
+#define DDR_REFRESH(x) ((x) & DDR_REFRESH_M)
+#define DDR_REFRESH_VAL (DDR_REFRESH_EN | DDR_REFRESH(312))
+
+#define DDR_TRAS_S 0
+#define DDR_TRAS_M 0x1f
+#define DDR_TRAS(x) (((x) & DDR_TRAS_M) << DDR_TRAS_S)
+#define DDR_TRCD_M 0xf
+#define DDR_TRCD_S 5
+#define DDR_TRCD(x) (((x) & DDR_TRCD_M) << DDR_TRCD_S)
+#define DDR_TRP_M 0xf
+#define DDR_TRP_S 9
+#define DDR_TRP(x) (((x) & DDR_TRP_M) << DDR_TRP_S)
+#define DDR_TRRD_M 0xf
+#define DDR_TRRD_S 13
+#define DDR_TRRD(x) (((x) & DDR_TRRD_M) << DDR_TRRD_S)
+#define DDR_TRFC_M 0x7f
+#define DDR_TRFC_S 17
+#define DDR_TRFC(x) (((x) & DDR_TRFC_M) << DDR_TRFC_S)
+#define DDR_TMRD_M 0xf
+#define DDR_TMRD_S 23
+#define DDR_TMRD(x) (((x) & DDR_TMRD_M) << DDR_TMRD_S)
+#define DDR_CAS_L_M 0x17
+#define DDR_CAS_L_S 27
+#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
+#define DDR_OPEN BIT(30)
+#define DDR1_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \
+ DDR_TRP(6) | DDR_TRRD(4) | \
+ DDR_TRFC(7) | DDR_TMRD(5) | \
+ DDR_CAS_L(7) | DDR_OPEN)
+#define DDR2_CONF_REG_VAL (DDR_TRAS(27) | DDR_TRCD(9) | \
+ DDR_TRP(9) | DDR_TRRD(7) | \
+ DDR_TRFC(21) | DDR_TMRD(15) | \
+ DDR_CAS_L(17) | DDR_OPEN)
+
+#define DDR_BURST_LEN_S 0
+#define DDR_BURST_LEN_M 0xf
+#define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S)
+#define DDR_BURST_TYPE BIT(4)
+#define DDR_CNTL_OE_EN BIT(5)
+#define DDR_PHASE_SEL BIT(6)
+#define DDR_CKE BIT(7)
+#define DDR_TWR_S 8
+#define DDR_TWR_M 0xf
+#define DDR_TWR(x) (((x) & DDR_TWR_M) << DDR_TWR_S)
+#define DDR_TRTW_S 12
+#define DDR_TRTW_M 0x1f
+#define DDR_TRTW(x) (((x) & DDR_TRTW_M) << DDR_TRTW_S)
+#define DDR_TRTP_S 17
+#define DDR_TRTP_M 0xf
+#define DDR_TRTP(x) (((x) & DDR_TRTP_M) << DDR_TRTP_S)
+#define DDR_TWTR_S 21
+#define DDR_TWTR_M 0x1f
+#define DDR_TWTR(x) (((x) & DDR_TWTR_M) << DDR_TWTR_S)
+#define DDR_G_OPEN_L_S 26
+#define DDR_G_OPEN_L_M 0xf
+#define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S)
+#define DDR_HALF_WIDTH_LOW BIT(31)
+#define DDR1_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+ DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \
+ DDR_TRTP(8) | DDR_TWTR(14) | \
+ DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW)
+#define DDR2_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+ DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \
+ DDR_TRTP(9) | DDR_TWTR(21) | \
+ DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW)
+
+#define DDR_TWR_MSB BIT(3)
+#define DDR_TRAS_MSB BIT(2)
+#define DDR_TRFC_MSB_M 0x3
+#define DDR_TRFC_MSB(x) (x)
+#define DDR1_CONF3_REG_VAL 0
+#define DDR2_CONF3_REG_VAL (DDR_TWR_MSB | DDR_TRFC_MSB(2))
+
+#define DDR_CTL_SRAM_TSEL BIT(30)
+#define DDR_CTL_SRAM_GE0_SYNC BIT(20)
+#define DDR_CTL_SRAM_GE1_SYNC BIT(19)
+#define DDR_CTL_SRAM_USB_SYNC BIT(18)
+#define DDR_CTL_SRAM_PCIE_SYNC BIT(17)
+#define DDR_CTL_SRAM_WMAC_SYNC BIT(16)
+#define DDR_CTL_SRAM_MISC1_SYNC BIT(15)
+#define DDR_CTL_SRAM_MISC2_SYNC BIT(14)
+#define DDR_CTL_PAD_DDR2_SEL BIT(6)
+#define DDR_CTL_HALF_WIDTH BIT(1)
+#define DDR_CTL_CONFIG_VAL (DDR_CTL_SRAM_TSEL | \
+ DDR_CTL_SRAM_GE0_SYNC | \
+ DDR_CTL_SRAM_GE1_SYNC | \
+ DDR_CTL_SRAM_USB_SYNC | \
+ DDR_CTL_SRAM_PCIE_SYNC | \
+ DDR_CTL_SRAM_WMAC_SYNC | \
+ DDR_CTL_HALF_WIDTH)
+
+#define DDR_BURST_GE0_MAX_BL_S 0
+#define DDR_BURST_GE0_MAX_BL_M 0xf
+#define DDR_BURST_GE0_MAX_BL(x) \
+ (((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S)
+#define DDR_BURST_GE1_MAX_BL_S 4
+#define DDR_BURST_GE1_MAX_BL_M 0xf
+#define DDR_BURST_GE1_MAX_BL(x) \
+ (((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S)
+#define DDR_BURST_PCIE_MAX_BL_S 8
+#define DDR_BURST_PCIE_MAX_BL_M 0xf
+#define DDR_BURST_PCIE_MAX_BL(x) \
+ (((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S)
+#define DDR_BURST_USB_MAX_BL_S 12
+#define DDR_BURST_USB_MAX_BL_M 0xf
+#define DDR_BURST_USB_MAX_BL(x) \
+ (((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S)
+#define DDR_BURST_CPU_MAX_BL_S 16
+#define DDR_BURST_CPU_MAX_BL_M 0xf
+#define DDR_BURST_CPU_MAX_BL(x) \
+ (((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S)
+#define DDR_BURST_RD_MAX_BL_S 20
+#define DDR_BURST_RD_MAX_BL_M 0xf
+#define DDR_BURST_RD_MAX_BL(x) \
+ (((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S)
+#define DDR_BURST_WR_MAX_BL_S 24
+#define DDR_BURST_WR_MAX_BL_M 0xf
+#define DDR_BURST_WR_MAX_BL(x) \
+ (((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S)
+#define DDR_BURST_RWP_MASK_EN_S 28
+#define DDR_BURST_RWP_MASK_EN_M 0x3
+#define DDR_BURST_RWP_MASK_EN(x) \
+ (((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S)
+#define DDR_BURST_CPU_PRI_BE BIT(30)
+#define DDR_BURST_CPU_PRI BIT(31)
+#define DDR_BURST_VAL (DDR_BURST_CPU_PRI_BE | \
+ DDR_BURST_RWP_MASK_EN(3) | \
+ DDR_BURST_WR_MAX_BL(4) | \
+ DDR_BURST_RD_MAX_BL(4) | \
+ DDR_BURST_CPU_MAX_BL(4) | \
+ DDR_BURST_USB_MAX_BL(4) | \
+ DDR_BURST_PCIE_MAX_BL(4) | \
+ DDR_BURST_GE1_MAX_BL(4) | \
+ DDR_BURST_GE0_MAX_BL(4))
+
+#define DDR_BURST_WMAC_MAX_BL_S 0
+#define DDR_BURST_WMAC_MAX_BL_M 0xf
+#define DDR_BURST_WMAC_MAX_BL(x) \
+ (((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S)
+#define DDR_BURST2_VAL DDR_BURST_WMAC_MAX_BL(4)
+
+#define DDR2_CONF_TWL_S 10
+#define DDR2_CONF_TWL_M 0xf
+#define DDR2_CONF_TWL(x) \
+ (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
+#define DDR2_CONF_ODT BIT(9)
+#define DDR2_CONF_TFAW_S 2
+#define DDR2_CONF_TFAW_M 0x3f
+#define DDR2_CONF_TFAW(x) \
+ (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
+#define DDR2_CONF_EN BIT(0)
+#define DDR2_CONF_VAL (DDR2_CONF_TWL(5) | \
+ DDR2_CONF_TFAW(31) | \
+ DDR2_CONF_ODT | \
+ DDR2_CONF_EN)
+
+#define DDR1_EXT_MODE_VAL 0
+#define DDR2_EXT_MODE_VAL 0x402
+#define DDR2_EXT_MODE_OCD_VAL 0x782
+#define DDR1_MODE_DLL_VAL 0x133
+#define DDR2_MODE_DLL_VAL 0x143
+#define DDR1_MODE_VAL 0x33
+#define DDR2_MODE_VAL 0x43
+#define DDR1_TAP_VAL 0x20
+#define DDR2_TAP_VAL 0x10
+
+#define DDR_REG_BIST_MASK_ADDR_0 0x2c
+#define DDR_REG_BIST_MASK_ADDR_1 0x30
+#define DDR_REG_BIST_MASK_AHB_GE0_0 0x34
+#define DDR_REG_BIST_COMP_AHB_GE0_0 0x38
+#define DDR_REG_BIST_MASK_AHB_GE1_0 0x3c
+#define DDR_REG_BIST_COMP_AHB_GE1_0 0x40
+#define DDR_REG_BIST_COMP_ADDR_0 0x64
+#define DDR_REG_BIST_COMP_ADDR_1 0x68
+#define DDR_REG_BIST_MASK_AHB_GE0_1 0x6c
+#define DDR_REG_BIST_COMP_AHB_GE0_1 0x70
+#define DDR_REG_BIST_MASK_AHB_GE1_1 0x74
+#define DDR_REG_BIST_COMP_AHB_GE1_1 0x78
+#define DDR_REG_BIST 0x11c
+#define DDR_REG_BIST_STATUS 0x120
+
+#define DDR_BIST_COMP_CNT_S 1
+#define DDR_BIST_COMP_CNT_M 0xff
+#define DDR_BIST_COMP_CNT(x) \
+ (((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S)
+#define DDR_BIST_COMP_CNT_MASK \
+ (DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S)
+#define DDR_BIST_TEST_START BIT(0)
+#define DDR_BIST_STATUS_DONE BIT(0)
+
+/* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
+#define DDR_BIST_MASK_ADDR_VAL 0xfa5de83f
+
+#define DDR_TAP_MAGIC_VAL 0xaa55aa55
+#define DDR_TAP_MAX_VAL 0x40
+
+void ddr_init(void)
+{
+ void __iomem *regs;
+ u32 val;
+
+ regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+ MAP_NOCACHE);
+ val = get_bootstrap();
+ if (val & QCA953X_BOOTSTRAP_DDR1) {
+ writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
+ udelay(10);
+
+ /* For 16-bit DDR */
+ writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+ udelay(100);
+
+ /* Burst size */
+ writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+ udelay(100);
+ writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+ udelay(100);
+
+ /* AHB maximum timeout */
+ writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+ udelay(100);
+
+ /* DRAM timing */
+ writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+ udelay(100);
+ writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+ udelay(100);
+ writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+ udelay(100);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* ODT disable, Full strength, Enable DLL */
+ writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+ udelay(100);
+ /* Update Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Reset DLL, CAS Latency 3, Burst Length 8 */
+ writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+ udelay(100);
+ /* Update Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Auto Refresh */
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Normal DLL, CAS Latency 3, Burst Length 8 */
+ writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+ udelay(100);
+ /* Update Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Refresh time control */
+ writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
+ udelay(100);
+
+ /* DQS 0 Tap Control */
+ writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ /* DQS 1 Tap Control */
+ writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
+ } else {
+ writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+ writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+ writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL,
+ regs + QCA953X_DDR_REG_CTL_CONF);
+ udelay(10);
+
+ /* For 16-bit DDR */
+ writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+ udelay(100);
+
+ /* Burst size */
+ writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+ udelay(100);
+ writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+ udelay(100);
+
+ /* AHB maximum timeout */
+ writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+ udelay(100);
+
+ /* DRAM timing */
+ writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+ udelay(100);
+ writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+ udelay(100);
+ writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+ udelay(100);
+
+ /* Enable DDR2 */
+ writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG);
+ udelay(100);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Update Extended Mode Register 2 Set (EMR2S) */
+ writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Update Extended Mode Register 3 Set (EMR3S) */
+ writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* 150 ohm, Reduced strength, Enable DLL */
+ writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+ udelay(100);
+ /* Update Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Reset DLL, CAS Latency 4, Burst Length 8 */
+ writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+ udelay(100);
+
+ /* Update Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Auto Refresh */
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Normal DLL, CAS Latency 4, Burst Length 8 */
+ writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+ udelay(100);
+ /* Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Enable OCD, Enable DLL, Reduced Drive Strength */
+ writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+ udelay(100);
+ /* Update Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* OCD diable, Enable DLL, Reduced Drive Strength */
+ writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+ udelay(100);
+ /* Update Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Refresh time control */
+ writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
+ udelay(100);
+
+ /* DQS 0 Tap Control */
+ writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ /* DQS 1 Tap Control */
+ writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
+ }
+}
+
+void ddr_tap_tuning(void)
+{
+ void __iomem *regs;
+ u32 val, pass, tap, cnt, tap_val, last, first;
+
+ regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+ MAP_NOCACHE);
+
+ tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+ first = DDR_TAP_MAGIC_VAL;
+ last = 0;
+ cnt = 0;
+ tap = 0;
+
+ do {
+ writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+ writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1);
+ writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0);
+ writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1);
+ writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0);
+ writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1);
+ writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0);
+ writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1);
+ writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0);
+ writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1);
+ writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0);
+
+ /* Start BIST test */
+ writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST);
+
+ do {
+ val = readl(regs + DDR_REG_BIST_STATUS);
+ } while (!(val & DDR_BIST_STATUS_DONE));
+
+ /* Stop BIST test */
+ writel(0, regs + DDR_REG_BIST);
+
+ pass = val & DDR_BIST_COMP_CNT_MASK;
+ pass ^= DDR_BIST_COMP_CNT(8);
+ if (!pass) {
+ if (first != DDR_TAP_MAGIC_VAL) {
+ last = tap;
+ } else {
+ first = tap;
+ last = tap;
+ }
+ cnt++;
+ }
+ tap++;
+ } while (tap < DDR_TAP_MAX_VAL);
+
+ if (cnt) {
+ tap_val = (first + last) / 2;
+ tap_val %= DDR_TAP_MAX_VAL;
+ }
+
+ writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}
diff --git a/arch/mips/mach-ath79/qca953x/lowlevel_init.S b/arch/mips/mach-ath79/qca953x/lowlevel_init.S
new file mode 100644
index 0000000..06b6720
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/lowlevel_init.S
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+ (((0x3F & divint) << 10) | \
+ ((0x1F & refdiv) << 16) | \
+ ((0x1 & range) << 21) | \
+ ((0x7 & outdiv) << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+ (((0x3 & (cpudiv - 1)) << 5) | \
+ ((0x3 & (ddrdiv - 1)) << 10) | \
+ ((0x3 & (ahbdiv - 1)) << 15) )
+
+#define SET_FIELD(name, v) (((v) & QCA953X_##name##_MASK) << \
+ QCA953X_##name##_SHIFT)
+
+#define DPLL2_KI(v) SET_FIELD(SRIF_DPLL2_KI, v)
+#define DPLL2_KD(v) SET_FIELD(SRIF_DPLL2_KD, v)
+#define DPLL2_PWD QCA953X_SRIF_DPLL2_PWD
+#define MK_DPLL2(ki, kd) (DPLL2_KI(ki) | DPLL2_KD(kd) | DPLL2_PWD)
+
+#define PLL_CPU_NFRAC(v) SET_FIELD(PLL_CPU_CONFIG_NFRAC, v)
+#define PLL_CPU_NINT(v) SET_FIELD(PLL_CPU_CONFIG_NINT, v)
+#define PLL_CPU_REFDIV(v) SET_FIELD(PLL_CPU_CONFIG_REFDIV, v)
+#define PLL_CPU_OUTDIV(v) SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v)
+#define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \
+ (PLL_CPU_NFRAC(frac) | \
+ PLL_CPU_NINT(nint) | \
+ PLL_CPU_REFDIV(ref) | \
+ PLL_CPU_OUTDIV(outdiv))
+
+#define PLL_DDR_NFRAC(v) SET_FIELD(PLL_DDR_CONFIG_NFRAC, v)
+#define PLL_DDR_NINT(v) SET_FIELD(PLL_DDR_CONFIG_NINT, v)
+#define PLL_DDR_REFDIV(v) SET_FIELD(PLL_DDR_CONFIG_REFDIV, v)
+#define PLL_DDR_OUTDIV(v) SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v)
+#define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \
+ (PLL_DDR_NFRAC(frac) | \
+ PLL_DDR_REFDIV(ref) | \
+ PLL_DDR_NINT(nint) | \
+ PLL_DDR_OUTDIV(outdiv) | \
+ QCA953X_PLL_CONFIG_PWD)
+
+#define PLL_CPU_CONF_VAL MK_PLL_CPU_CONF(0, 26, 1, 0)
+#define PLL_DDR_CONF_VAL MK_PLL_DDR_CONF(0, 15, 1, 0)
+
+#define PLL_CLK_CTRL_PLL_BYPASS (QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS | \
+ QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS | \
+ QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+
+#define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v)
+#define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v)
+#define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v)
+#define MK_PLL_CLK_CTRL(cpu, ddr, ahb) \
+ (PLL_CLK_CTRL_CPU_DIV(cpu) | \
+ PLL_CLK_CTRL_DDR_DIV(ddr) | \
+ PLL_CLK_CTRL_AHB_DIV(ahb))
+#define PLL_CLK_CTRL_VAL (MK_PLL_CLK_CTRL(0, 0, 2) | \
+ PLL_CLK_CTRL_PLL_BYPASS | \
+ QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | \
+ QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+
+#define PLL_DDR_DIT_FRAC_MAX(v) SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v)
+#define PLL_DDR_DIT_FRAC_MIN(v) SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v)
+#define PLL_DDR_DIT_FRAC_STEP(v) SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v)
+#define PLL_DDR_DIT_UPD_CNT(v) SET_FIELD(PLL_DDR_DIT_UPD_CNT, v)
+#define PLL_CPU_DIT_FRAC_MAX(v) SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v)
+#define PLL_CPU_DIT_FRAC_MIN(v) SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v)
+#define PLL_CPU_DIT_FRAC_STEP(v) SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v)
+#define PLL_CPU_DIT_UPD_CNT(v) SET_FIELD(PLL_CPU_DIT_UPD_CNT, v)
+#define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \
+ (QCA953X_PLL_DIT_FRAC_EN | \
+ PLL_DDR_DIT_FRAC_MAX(max) | \
+ PLL_DDR_DIT_FRAC_MIN(min) | \
+ PLL_DDR_DIT_FRAC_STEP(step) | \
+ PLL_DDR_DIT_UPD_CNT(cnt))
+#define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \
+ (QCA953X_PLL_DIT_FRAC_EN | \
+ PLL_CPU_DIT_FRAC_MAX(max) | \
+ PLL_CPU_DIT_FRAC_MIN(min) | \
+ PLL_CPU_DIT_FRAC_STEP(step) | \
+ PLL_CPU_DIT_UPD_CNT(cnt))
+#define PLL_CPU_DIT_FRAC_VAL MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15)
+#define PLL_DDR_DIT_FRAC_VAL MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15)
+
+ .text
+ .set noreorder
+
+LEAF(lowlevel_init)
+ /* RTC Reset */
+ li t0, KSEG1ADDR(AR71XX_RESET_BASE)
+ lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+ li t2, 0x08000000
+ or t1, t1, t2
+ sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+ nop
+ lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+ li t2, 0xf7ffffff
+ and t1, t1, t2
+ sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+ nop
+
+ /* RTC Force Wake */
+ li t0, KSEG1ADDR(QCA953X_RTC_BASE)
+ li t1, 0x01
+ sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
+ nop
+ nop
+
+ /* Wait for RTC in on state */
+1:
+ lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
+ andi t1, t1, 0x02
+ beqz t1, 1b
+ nop
+
+ li t0, KSEG1ADDR(QCA953X_SRIF_BASE)
+ li t1, MK_DPLL2(2, 16)
+ sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
+ sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
+ sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
+ sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
+
+ li t0, KSEG1ADDR(AR71XX_PLL_BASE)
+ lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ ori t1, PLL_CLK_CTRL_PLL_BYPASS
+ sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ li t1, PLL_CPU_CONF_VAL
+ sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+ nop
+
+ li t1, PLL_DDR_CONF_VAL
+ sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+ nop
+
+ li t1, PLL_CLK_CTRL_VAL
+ sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+ li t2, ~QCA953X_PLL_CONFIG_PWD
+ and t1, t1, t2
+ sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+ nop
+
+ lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+ li t2, ~QCA953X_PLL_CONFIG_PWD
+ and t1, t1, t2
+ sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+ nop
+
+ lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ li t2, ~PLL_CLK_CTRL_PLL_BYPASS
+ and t1, t1, t2
+ sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ li t1, PLL_DDR_DIT_FRAC_VAL
+ sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
+ nop
+
+ li t1, PLL_CPU_DIT_FRAC_VAL
+ sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
+ nop
+
+ li t0, KSEG1ADDR(AR71XX_RESET_BASE)
+ lui t1, 0x03fc
+ sw t1, 0xb4(t0)
+
+ nop
+ jr ra
+ nop
+ END(lowlevel_init)
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 05/10] mips: ath79: add serial driver for ar933x SOC
[not found] <1451906101-9801-2-git-send-email-wills.wang@live.com>
` (2 preceding siblings ...)
2016-01-04 11:14 ` [U-Boot] [PATCH v6 04/10] mips: ath79: add support for QCA953x SOCs Wills Wang
@ 2016-01-04 11:14 ` Wills Wang
2016-01-04 12:52 ` Thomas Chou
2016-01-04 11:14 ` [U-Boot] [PATCH v6 06/10] ns16550: add support for mips Wills Wang
` (4 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Wills Wang @ 2016-01-04 11:14 UTC (permalink / raw)
To: u-boot
Signed-off-by: Wills Wang <wills.wang@live.com>
---
Changes in v6:
- Remove wait loop in putc and getc
- Use map_physmem instead of KSEG1ADDR
Changes in v5:
- remove ar933x_serial_platdata
- Import document "qca,ar9330-uart.txt" from kernel
- Add support for debug UART
Changes in v4:
- Auto calculate baudrate for serial driver
- Move pinctrl code in serial driver into arch/mips/mach-ath79
- Use get_serial_clock to serial clock source
Changes in v3:
- Convert serial driver to driver model
- Same code style convertion
Changes in v2:
- Move serial driver code into drivers/serial
.../serial/qca,ar9330-uart.txt | 24 ++
drivers/serial/Kconfig | 17 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_ar933x.c | 264 +++++++++++++++++++++
4 files changed, 306 insertions(+)
create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt
create mode 100644 drivers/serial/serial_ar933x.c
diff --git a/doc/device-tree-bindings/serial/qca,ar9330-uart.txt b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
new file mode 100644
index 0000000..ec576a1
--- /dev/null
+++ b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
@@ -0,0 +1,24 @@
+* Qualcomm Atheros AR9330 High-Speed UART
+
+Required properties:
+
+- compatible: Must be "qca,ar9330-uart"
+
+- reg: Specifies the physical base address of the controller and
+ the length of the memory mapped region.
+
+Additional requirements:
+
+ Each UART port must have an alias correctly numbered in "aliases"
+ node.
+
+Example:
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ uart0: uart at 18020000 {
+ compatible = "qca,ar9330-uart";
+ reg = <0x18020000 0x14>;
+ };
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fc287e..f147379 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -69,6 +69,14 @@ config DEBUG_UART_ALTERA_UART
You will need to provide parameters to make this work. The driver will
be available until the real driver model serial is running.
+config DEBUG_UART_AR933X
+ bool "QCA/Atheros ar933x"
+ help
+ Select this to enable a debug UART using the ar933x uart driver.
+ You will need to provide parameters to make this work. The
+ driver will be available until the real driver model serial is
+ running.
+
config DEBUG_UART_NS16550
bool "ns16550"
help
@@ -186,6 +194,15 @@ config ALTERA_UART
Select this to enable an UART for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
+config AR933X_UART
+ bool "QCA/Atheros ar933x UART support"
+ depends on DM_SERIAL
+ help
+ Select this to enable UART support for QCA/Atheros ar933x
+ devices. This driver uses driver model and requires a device
+ tree binding to operate, please refer to the document at
+ doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
+
config SYS_NS16550
bool "NS16550 UART or compatible"
help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index dd87147..b7b82ae 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -17,6 +17,7 @@ endif
obj-$(CONFIG_ALTERA_UART) += altera_uart.o
obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
new file mode 100644
index 0000000..38d34c2
--- /dev/null
+++ b/drivers/serial/serial_ar933x.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+
+#define AR933X_UART_DATA_REG 0x00
+#define AR933X_UART_CS_REG 0x04
+#define AR933X_UART_CLK_REG 0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK 0xff
+#define AR933X_UART_DATA_RX_CSR BIT(8)
+#define AR933X_UART_DATA_TX_CSR BIT(9)
+#define AR933X_UART_CS_IF_MODE_S 2
+#define AR933X_UART_CS_IF_MODE_M 0x3
+#define AR933X_UART_CS_IF_MODE_DTE 1
+#define AR933X_UART_CS_IF_MODE_DCE 2
+#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7)
+#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8)
+#define AR933X_UART_CLK_STEP_M 0xffff
+#define AR933X_UART_CLK_SCALE_M 0xfff
+#define AR933X_UART_CLK_SCALE_S 16
+#define AR933X_UART_CLK_STEP_S 0
+
+struct ar933x_serial_priv {
+ void __iomem *regs;
+};
+
+static inline u32 ar933x_serial_read(struct udevice *dev, u32 offset)
+{
+ struct ar933x_serial_priv *priv = dev_get_priv(dev);
+
+ return readl(priv->regs + offset);
+}
+
+static inline void ar933x_serial_write(struct udevice *dev,
+ u32 val, u32 offset)
+{
+ struct ar933x_serial_priv *priv = dev_get_priv(dev);
+
+ writel(val, priv->regs + offset);
+}
+
+/*
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ */
+static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
+{
+ u64 t;
+ u32 div;
+
+ div = (2 << 16) * (scale + 1);
+ t = clk;
+ t *= step;
+ t += (div / 2);
+ do_div(t, div);
+
+ return t;
+}
+
+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+ u32 *scale, u32 *step)
+{
+ u32 tscale, baudrate;
+ long min_diff;
+
+ *scale = 0;
+ *step = 0;
+
+ min_diff = baud;
+ for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
+ u64 tstep;
+ int diff;
+
+ tstep = baud * (tscale + 1);
+ tstep *= (2 << 16);
+ do_div(tstep, clk);
+
+ if (tstep > AR933X_UART_CLK_STEP_M)
+ break;
+
+ baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
+ diff = abs(baudrate - baud);
+ if (diff < min_diff) {
+ min_diff = diff;
+ *scale = tscale;
+ *step = tstep;
+ }
+ }
+}
+
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ u32 val, scale, step;
+
+ val = get_serial_clock();
+ ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
+
+ val = (scale & AR933X_UART_CLK_SCALE_M)
+ << AR933X_UART_CLK_SCALE_S;
+ val |= (step & AR933X_UART_CLK_STEP_M)
+ << AR933X_UART_CLK_STEP_S;
+ ar933x_serial_write(dev, val, AR933X_UART_CLK_REG);
+
+ return 0;
+}
+
+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+ u32 data;
+
+ data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+ if (!(data & AR933X_UART_DATA_TX_CSR))
+ return -EAGAIN;
+
+ data = (u32)c | AR933X_UART_DATA_TX_CSR;
+ ar933x_serial_write(dev, data, AR933X_UART_DATA_REG);
+
+ return 0;
+}
+
+static int ar933x_serial_getc(struct udevice *dev)
+{
+ u32 data;
+
+ data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+ if (!(data & AR933X_UART_DATA_RX_CSR))
+ return -EAGAIN;
+
+ data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+ ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR,
+ AR933X_UART_DATA_REG);
+ return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+ u32 data;
+
+ data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+ if (input)
+ return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+ else
+ return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+ struct ar933x_serial_priv *priv = dev_get_priv(dev);
+ u32 val;
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = map_physmem(addr,
+ AR933X_UART_SIZE,
+ MAP_NOCACHE);
+
+ /*
+ * UART controller configuration:
+ * - no DMA
+ * - no interrupt
+ * - DCE mode
+ * - no flow control
+ * - set RX ready oride
+ * - set TX ready oride
+ */
+ val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+ AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+ ar933x_serial_write(dev, val, AR933X_UART_CS_REG);
+ return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+ .putc = ar933x_serial_putc,
+ .pending = ar933x_serial_pending,
+ .getc = ar933x_serial_getc,
+ .setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+ { .compatible = "qca,ar9330-uart" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_ar933x) = {
+ .name = "serial_ar933x",
+ .id = UCLASS_SERIAL,
+ .of_match = ar933x_serial_ids,
+ .priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+ .probe = ar933x_serial_probe,
+ .ops = &ar933x_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_AR933X
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+ void __iomem *regs;
+ u32 val, scale, step;
+
+ regs = map_physmem(CONFIG_DEBUG_UART_BASE,
+ AR933X_UART_SIZE,
+ MAP_NOCACHE);
+
+ /*
+ * UART controller configuration:
+ * - no DMA
+ * - no interrupt
+ * - DCE mode
+ * - no flow control
+ * - set RX ready oride
+ * - set TX ready oride
+ */
+ val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+ AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+ writel(val, regs + AR933X_UART_CS_REG);
+
+ ar933x_serial_get_scale_step(CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE, &scale, &step);
+
+ val = (scale & AR933X_UART_CLK_SCALE_M)
+ << AR933X_UART_CLK_SCALE_S;
+ val |= (step & AR933X_UART_CLK_STEP_M)
+ << AR933X_UART_CLK_STEP_S;
+ writel(val, regs + AR933X_UART_CLK_REG);
+}
+
+static inline void _debug_uart_putc(int c)
+{
+ void __iomem *regs;
+ u32 data;
+
+ regs = map_physmem(CONFIG_DEBUG_UART_BASE,
+ AR933X_UART_SIZE,
+ MAP_NOCACHE);
+
+ do {
+ data = readl(regs + AR933X_UART_DATA_REG);
+ } while (!(data & AR933X_UART_DATA_TX_CSR));
+
+ data = (u32)c | AR933X_UART_DATA_TX_CSR;
+ writel(data, regs + AR933X_UART_DATA_REG);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 05/10] mips: ath79: add serial driver for ar933x SOC
2016-01-04 11:14 ` [U-Boot] [PATCH v6 05/10] mips: ath79: add serial driver for ar933x SOC Wills Wang
@ 2016-01-04 12:52 ` Thomas Chou
0 siblings, 0 replies; 25+ messages in thread
From: Thomas Chou @ 2016-01-04 12:52 UTC (permalink / raw)
To: u-boot
Hi Wills,
On 2016?01?04? 19:14, Wills Wang wrote:
> Signed-off-by: Wills Wang <wills.wang@live.com>
> ---
>
> Changes in v6:
> - Remove wait loop in putc and getc
> - Use map_physmem instead of KSEG1ADDR
>
> Changes in v5:
> - remove ar933x_serial_platdata
> - Import document "qca,ar9330-uart.txt" from kernel
> - Add support for debug UART
>
> Changes in v4:
> - Auto calculate baudrate for serial driver
> - Move pinctrl code in serial driver into arch/mips/mach-ath79
> - Use get_serial_clock to serial clock source
>
> Changes in v3:
> - Convert serial driver to driver model
> - Same code style convertion
>
> Changes in v2:
> - Move serial driver code into drivers/serial
>
> .../serial/qca,ar9330-uart.txt | 24 ++
> drivers/serial/Kconfig | 17 ++
> drivers/serial/Makefile | 1 +
> drivers/serial/serial_ar933x.c | 264 +++++++++++++++++++++
> 4 files changed, 306 insertions(+)
> create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt
> create mode 100644 drivers/serial/serial_ar933x.c
>
> diff --git a/doc/device-tree-bindings/serial/qca,ar9330-uart.txt b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
> new file mode 100644
> index 0000000..ec576a1
> --- /dev/null
> +++ b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
> @@ -0,0 +1,24 @@
> +* Qualcomm Atheros AR9330 High-Speed UART
> +
> +Required properties:
> +
> +- compatible: Must be "qca,ar9330-uart"
> +
> +- reg: Specifies the physical base address of the controller and
> + the length of the memory mapped region.
> +
> +Additional requirements:
> +
> + Each UART port must have an alias correctly numbered in "aliases"
> + node.
> +
> +Example:
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + uart0: uart at 18020000 {
> + compatible = "qca,ar9330-uart";
> + reg = <0x18020000 0x14>;
> + };
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 1fc287e..f147379 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -69,6 +69,14 @@ config DEBUG_UART_ALTERA_UART
> You will need to provide parameters to make this work. The driver will
> be available until the real driver model serial is running.
>
> +config DEBUG_UART_AR933X
> + bool "QCA/Atheros ar933x"
> + help
> + Select this to enable a debug UART using the ar933x uart driver.
> + You will need to provide parameters to make this work. The
> + driver will be available until the real driver model serial is
> + running.
> +
> config DEBUG_UART_NS16550
> bool "ns16550"
> help
> @@ -186,6 +194,15 @@ config ALTERA_UART
> Select this to enable an UART for Altera devices. Please find
> details on the "Embedded Peripherals IP User Guide" of Altera.
>
> +config AR933X_UART
> + bool "QCA/Atheros ar933x UART support"
> + depends on DM_SERIAL
> + help
> + Select this to enable UART support for QCA/Atheros ar933x
> + devices. This driver uses driver model and requires a device
> + tree binding to operate, please refer to the document at
> + doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
> +
> config SYS_NS16550
> bool "NS16550 UART or compatible"
> help
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index dd87147..b7b82ae 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -17,6 +17,7 @@ endif
>
> obj-$(CONFIG_ALTERA_UART) += altera_uart.o
> obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
> +obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
> obj-$(CONFIG_ARM_DCC) += arm_dcc.o
> obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
> obj-$(CONFIG_EFI_APP) += serial_efi.o
> diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
> new file mode 100644
> index 0000000..38d34c2
> --- /dev/null
> +++ b/drivers/serial/serial_ar933x.c
> @@ -0,0 +1,264 @@
> +/*
> + * (C) Copyright 2015
> + * Wills Wang, <wills.wang@live.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <div64.h>
> +#include <errno.h>
> +#include <serial.h>
> +#include <asm/io.h>
> +#include <asm/addrspace.h>
> +#include <asm/types.h>
> +#include <mach/ar71xx_regs.h>
> +
> +#define AR933X_UART_DATA_REG 0x00
> +#define AR933X_UART_CS_REG 0x04
> +#define AR933X_UART_CLK_REG 0x08
> +
> +#define AR933X_UART_DATA_TX_RX_MASK 0xff
> +#define AR933X_UART_DATA_RX_CSR BIT(8)
> +#define AR933X_UART_DATA_TX_CSR BIT(9)
> +#define AR933X_UART_CS_IF_MODE_S 2
> +#define AR933X_UART_CS_IF_MODE_M 0x3
> +#define AR933X_UART_CS_IF_MODE_DTE 1
> +#define AR933X_UART_CS_IF_MODE_DCE 2
> +#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7)
> +#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8)
> +#define AR933X_UART_CLK_STEP_M 0xffff
> +#define AR933X_UART_CLK_SCALE_M 0xfff
> +#define AR933X_UART_CLK_SCALE_S 16
> +#define AR933X_UART_CLK_STEP_S 0
> +
> +struct ar933x_serial_priv {
> + void __iomem *regs;
> +};
> +
> +static inline u32 ar933x_serial_read(struct udevice *dev, u32 offset)
> +{
> + struct ar933x_serial_priv *priv = dev_get_priv(dev);
> +
> + return readl(priv->regs + offset);
> +}
> +
> +static inline void ar933x_serial_write(struct udevice *dev,
> + u32 val, u32 offset)
> +{
> + struct ar933x_serial_priv *priv = dev_get_priv(dev);
> +
> + writel(val, priv->regs + offset);
> +}
> +
> +/*
> + * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
> + */
> +static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
> +{
> + u64 t;
> + u32 div;
> +
> + div = (2 << 16) * (scale + 1);
> + t = clk;
> + t *= step;
> + t += (div / 2);
> + do_div(t, div);
> +
> + return t;
> +}
> +
> +static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
> + u32 *scale, u32 *step)
> +{
> + u32 tscale, baudrate;
> + long min_diff;
> +
> + *scale = 0;
> + *step = 0;
> +
> + min_diff = baud;
> + for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
> + u64 tstep;
> + int diff;
> +
> + tstep = baud * (tscale + 1);
> + tstep *= (2 << 16);
> + do_div(tstep, clk);
> +
> + if (tstep > AR933X_UART_CLK_STEP_M)
> + break;
> +
> + baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
> + diff = abs(baudrate - baud);
> + if (diff < min_diff) {
> + min_diff = diff;
> + *scale = tscale;
> + *step = tstep;
> + }
> + }
> +}
> +
> +static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
> +{
> + u32 val, scale, step;
> +
> + val = get_serial_clock();
> + ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
> +
> + val = (scale & AR933X_UART_CLK_SCALE_M)
> + << AR933X_UART_CLK_SCALE_S;
> + val |= (step & AR933X_UART_CLK_STEP_M)
> + << AR933X_UART_CLK_STEP_S;
> + ar933x_serial_write(dev, val, AR933X_UART_CLK_REG);
> +
> + return 0;
> +}
> +
> +static int ar933x_serial_putc(struct udevice *dev, const char c)
> +{
> + u32 data;
> +
> + data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
> + if (!(data & AR933X_UART_DATA_TX_CSR))
> + return -EAGAIN;
> +
> + data = (u32)c | AR933X_UART_DATA_TX_CSR;
> + ar933x_serial_write(dev, data, AR933X_UART_DATA_REG);
> +
> + return 0;
> +}
> +
> +static int ar933x_serial_getc(struct udevice *dev)
> +{
> + u32 data;
> +
> + data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
> + if (!(data & AR933X_UART_DATA_RX_CSR))
> + return -EAGAIN;
> +
> + data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
Can we use the data from previous read and remove this read?
> + ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR,
> + AR933X_UART_DATA_REG);
> + return data & AR933X_UART_DATA_TX_RX_MASK;
> +}
> +
> +static int ar933x_serial_pending(struct udevice *dev, bool input)
> +{
> + u32 data;
> +
> + data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
> + if (input)
> + return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
> + else
> + return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
> +}
> +
> +static int ar933x_serial_probe(struct udevice *dev)
> +{
> + struct ar933x_serial_priv *priv = dev_get_priv(dev);
> + u32 val;
> + fdt_addr_t addr;
> +
> + addr = dev_get_addr(dev);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + priv->regs = map_physmem(addr,
> + AR933X_UART_SIZE,
> + MAP_NOCACHE);
> +
> + /*
> + * UART controller configuration:
> + * - no DMA
> + * - no interrupt
> + * - DCE mode
> + * - no flow control
> + * - set RX ready oride
> + * - set TX ready oride
> + */
> + val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
> + AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
> + ar933x_serial_write(dev, val, AR933X_UART_CS_REG);
> + return 0;
> +}
> +
> +static const struct dm_serial_ops ar933x_serial_ops = {
> + .putc = ar933x_serial_putc,
> + .pending = ar933x_serial_pending,
> + .getc = ar933x_serial_getc,
> + .setbrg = ar933x_serial_setbrg,
> +};
> +
> +static const struct udevice_id ar933x_serial_ids[] = {
> + { .compatible = "qca,ar9330-uart" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(serial_ar933x) = {
> + .name = "serial_ar933x",
> + .id = UCLASS_SERIAL,
> + .of_match = ar933x_serial_ids,
> + .priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
> + .probe = ar933x_serial_probe,
> + .ops = &ar933x_serial_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +#ifdef CONFIG_DEBUG_UART_AR933X
> +
> +#include <debug_uart.h>
> +
> +static inline void _debug_uart_init(void)
> +{
> + void __iomem *regs;
> + u32 val, scale, step;
> +
> + regs = map_physmem(CONFIG_DEBUG_UART_BASE,
> + AR933X_UART_SIZE,
> + MAP_NOCACHE);
> +
Please see my comment on your patch v6 07/10.
> + /*
> + * UART controller configuration:
> + * - no DMA
> + * - no interrupt
> + * - DCE mode
> + * - no flow control
> + * - set RX ready oride
> + * - set TX ready oride
> + */
> + val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
> + AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
> + writel(val, regs + AR933X_UART_CS_REG);
> +
> + ar933x_serial_get_scale_step(CONFIG_DEBUG_UART_CLOCK,
> + CONFIG_BAUDRATE, &scale, &step);
> +
> + val = (scale & AR933X_UART_CLK_SCALE_M)
> + << AR933X_UART_CLK_SCALE_S;
> + val |= (step & AR933X_UART_CLK_STEP_M)
> + << AR933X_UART_CLK_STEP_S;
> + writel(val, regs + AR933X_UART_CLK_REG);
> +}
> +
> +static inline void _debug_uart_putc(int c)
> +{
> + void __iomem *regs;
> + u32 data;
> +
> + regs = map_physmem(CONFIG_DEBUG_UART_BASE,
> + AR933X_UART_SIZE,
> + MAP_NOCACHE);
> +
> + do {
> + data = readl(regs + AR933X_UART_DATA_REG);
> + } while (!(data & AR933X_UART_DATA_TX_CSR));
> +
> + data = (u32)c | AR933X_UART_DATA_TX_CSR;
> + writel(data, regs + AR933X_UART_DATA_REG);
> +}
> +
> +DEBUG_UART_FUNCS
> +
> +#endif
>
Otherwise,
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
Best regards,
Thomas
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v6 06/10] ns16550: add support for mips
[not found] <1451906101-9801-2-git-send-email-wills.wang@live.com>
` (3 preceding siblings ...)
2016-01-04 11:14 ` [U-Boot] [PATCH v6 05/10] mips: ath79: add serial driver for ar933x SOC Wills Wang
@ 2016-01-04 11:14 ` Wills Wang
2016-01-04 13:12 ` Thomas Chou
2016-01-08 16:23 ` Daniel Schwierzeck
2016-01-04 11:14 ` [U-Boot] [PATCH v6 07/10] ns16550: map register base address for debug UART Wills Wang
` (3 subsequent siblings)
8 siblings, 2 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-04 11:14 UTC (permalink / raw)
To: u-boot
MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32" macro,
but usually define CONFIG_SYS_BIG_ENDIAN, this patch use readl/writel
for register operation in mips when define CONFIG_SYS_NS16550_MEM32.
Signed-off-by: Wills Wang <wills.wang@live.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/serial/ns16550.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3fab3f1..3b24af0 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -64,12 +64,16 @@ static inline void serial_out_shift(void *addr, int shift, int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
outb(value, (ulong)addr);
-#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
- out_le32(addr, value);
-#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
- out_be32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32)
+#ifdef CONFIG_MIPS
writel(value, addr);
+#else
+#ifndef CONFIG_SYS_BIG_ENDIAN
+ out_le32(addr, value);
+#else
+ out_be32(addr, value);
+#endif
+#endif
#elif defined(CONFIG_SYS_BIG_ENDIAN)
writeb(value, addr + (1 << shift) - 1);
#else
@@ -81,12 +85,16 @@ static inline int serial_in_shift(void *addr, int shift)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
return inb((ulong)addr);
-#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
- return in_le32(addr);
-#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
- return in_be32(addr);
#elif defined(CONFIG_SYS_NS16550_MEM32)
+#ifdef CONFIG_MIPS
return readl(addr);
+#else
+#ifndef CONFIG_SYS_BIG_ENDIAN
+ return in_le32(addr);
+#else
+ return in_be32(addr);
+#endif
+#endif
#elif defined(CONFIG_SYS_BIG_ENDIAN)
return readb(addr + (1 << shift) - 1);
#else
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 06/10] ns16550: add support for mips
2016-01-04 11:14 ` [U-Boot] [PATCH v6 06/10] ns16550: add support for mips Wills Wang
@ 2016-01-04 13:12 ` Thomas Chou
2016-01-04 13:25 ` Marek Vasut
2016-01-08 16:23 ` Daniel Schwierzeck
1 sibling, 1 reply; 25+ messages in thread
From: Thomas Chou @ 2016-01-04 13:12 UTC (permalink / raw)
To: u-boot
Hi Wills,
On 2016?01?04? 19:14, Wills Wang wrote:
> MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32" macro,
> but usually define CONFIG_SYS_BIG_ENDIAN, this patch use readl/writel
> for register operation in mips when define CONFIG_SYS_NS16550_MEM32.
>
> Signed-off-by: Wills Wang <wills.wang@live.com>
> ---
As Marek might have suggested, you should consider add these macro first.
Best regards,
Thomas
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v6 06/10] ns16550: add support for mips
2016-01-04 13:12 ` Thomas Chou
@ 2016-01-04 13:25 ` Marek Vasut
2016-01-04 13:56 ` Wills Wang
0 siblings, 1 reply; 25+ messages in thread
From: Marek Vasut @ 2016-01-04 13:25 UTC (permalink / raw)
To: u-boot
On Monday, January 04, 2016 at 02:12:08 PM, Thomas Chou wrote:
> Hi Wills,
>
> On 2016?01?04? 19:14, Wills Wang wrote:
> > MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32" macro,
> > but usually define CONFIG_SYS_BIG_ENDIAN, this patch use readl/writel
> > for register operation in mips when define CONFIG_SYS_NS16550_MEM32.
> >
> > Signed-off-by: Wills Wang <wills.wang@live.com>
> > ---
>
> As Marek might have suggested, you should consider add these macro first.
I think Marek's suggestions are being ignored :-)
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v6 06/10] ns16550: add support for mips
2016-01-04 13:25 ` Marek Vasut
@ 2016-01-04 13:56 ` Wills Wang
0 siblings, 0 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-04 13:56 UTC (permalink / raw)
To: u-boot
On 01/04/2016 09:25 PM, Marek Vasut wrote:
> On Monday, January 04, 2016 at 02:12:08 PM, Thomas Chou wrote:
>> Hi Wills,
>>
>> On 2016?01?04? 19:14, Wills Wang wrote:
>>> MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32" macro,
>>> but usually define CONFIG_SYS_BIG_ENDIAN, this patch use readl/writel
>>> for register operation in mips when define CONFIG_SYS_NS16550_MEM32.
>>>
>>> Signed-off-by: Wills Wang <wills.wang@live.com>
>>> ---
>> As Marek might have suggested, you should consider add these macro first.
> I think Marek's suggestions are being ignored :-)
I don't really know why u-boot and kernel don't both support these macros.
In addition, should it be considered in the scope of these patch series?
>
> Best regards,
> Marek Vasut
--
Best Regards
Wills
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v6 06/10] ns16550: add support for mips
2016-01-04 11:14 ` [U-Boot] [PATCH v6 06/10] ns16550: add support for mips Wills Wang
2016-01-04 13:12 ` Thomas Chou
@ 2016-01-08 16:23 ` Daniel Schwierzeck
2016-01-09 10:46 ` Wills Wang
1 sibling, 1 reply; 25+ messages in thread
From: Daniel Schwierzeck @ 2016-01-08 16:23 UTC (permalink / raw)
To: u-boot
Am Montag, den 04.01.2016, 19:14 +0800 schrieb Wills Wang:
> MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32" macro,
> but usually define CONFIG_SYS_BIG_ENDIAN, this patch use readl/writel
> for register operation in mips when define CONFIG_SYS_NS16550_MEM32.
>
> Signed-off-by: Wills Wang <wills.wang@live.com>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> drivers/serial/ns16550.c | 24 ++++++++++++++++--------
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 3fab3f1..3b24af0 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -64,12 +64,16 @@ static inline void serial_out_shift(void *addr,
> int shift, int value)
> {
> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> outb(value, (ulong)addr);
> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> !defined(CONFIG_SYS_BIG_ENDIAN)
> - out_le32(addr, value);
> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> defined(CONFIG_SYS_BIG_ENDIAN)
> - out_be32(addr, value);
> #elif defined(CONFIG_SYS_NS16550_MEM32)
> +#ifdef CONFIG_MIPS
> writel(value, addr);
> +#else
> +#ifndef CONFIG_SYS_BIG_ENDIAN
> + out_le32(addr, value);
> +#else
> + out_be32(addr, value);
> +#endif
> +#endif
> #elif defined(CONFIG_SYS_BIG_ENDIAN)
> writeb(value, addr + (1 << shift) - 1);
> #else
> @@ -81,12 +85,16 @@ static inline int serial_in_shift(void *addr, int
> shift)
> {
> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> return inb((ulong)addr);
> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> !defined(CONFIG_SYS_BIG_ENDIAN)
> - return in_le32(addr);
> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> defined(CONFIG_SYS_BIG_ENDIAN)
> - return in_be32(addr);
> #elif defined(CONFIG_SYS_NS16550_MEM32)
> +#ifdef CONFIG_MIPS
> return readl(addr);
> +#else
> +#ifndef CONFIG_SYS_BIG_ENDIAN
> + return in_le32(addr);
> +#else
> + return in_be32(addr);
> +#endif
> +#endif
> #elif defined(CONFIG_SYS_BIG_ENDIAN)
> return readb(addr + (1 << shift) - 1);
> #else
Could you tell us, if you need port IO or MMIO. In case of MMIO do you
need 8 bit or 32 bit I/O access?
Becasue your CPU is running in Big Endian and the NS16550 is Little
Endian, you need endianess conversion in the 32 bit case.
The 8 bit access should already work without changing anything. The
MIPS Malta board also uses NS16550 and already works in Bit Endian
mode.
To make the 32 bit case working, you need to select
CONFIG_SWAP_IO_SPACE in your SoC Kconfig code. Then all readl/writel
accessors do an endianess conversion to Little Endian if the CPU is
running in Big Endian.
Anyway I think the current implementation is wrong:
static inline void serial_out_shift(void *addr, int shift, int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
outb(value, (ulong)addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) &&
!defined(CONFIG_SYS_BIG_ENDIAN)
out_le32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32) &&
defined(CONFIG_SYS_BIG_ENDIAN)
out_be32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32)
writel(value, addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
writeb(value, addr + (1 << shift) - 1);
#else
writeb(value, addr);
#endif
}
The branch with writel() will never be taken because the two preceding
branches already catch all conditions for CONFIG_SYS_NS16550_MEM32.
Also if the NS16550 is Little Endian, the branch with out_be32 makes no
sense. All IO accessors must convert from CPU endianess to NS16550's
Little Endian, but out_be32 converts from CPU endianess to Big Endian.
To handle port IO, 32 Bit MMIO and 8 Bit MMIO, following code should be
enough:
static inline void serial_out_shift(void *addr, int shift, int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
outb(value, (ulong)addr);
#elif defined(CONFIG_SYS_NS16550_MEM32)
writel(value, addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
writeb(value, addr + (1 << shift) - 1);
#else
writeb(value, addr);
#endif
}
The arch-specific implementation of readl/writel should be responsible
for the endianess conversion and not the driver. What do you think?
--
- Daniel
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 06/10] ns16550: add support for mips
2016-01-08 16:23 ` Daniel Schwierzeck
@ 2016-01-09 10:46 ` Wills Wang
2016-01-09 14:30 ` Daniel Schwierzeck
0 siblings, 1 reply; 25+ messages in thread
From: Wills Wang @ 2016-01-09 10:46 UTC (permalink / raw)
To: u-boot
On 01/09/2016 12:23 AM, Daniel Schwierzeck wrote:
> Am Montag, den 04.01.2016, 19:14 +0800 schrieb Wills Wang:
>> MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32" macro,
>> but usually define CONFIG_SYS_BIG_ENDIAN, this patch use readl/writel
>> for register operation in mips when define CONFIG_SYS_NS16550_MEM32.
>>
>> Signed-off-by: Wills Wang <wills.wang@live.com>
>> ---
>>
>> Changes in v6: None
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>> drivers/serial/ns16550.c | 24 ++++++++++++++++--------
>> 1 file changed, 16 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>> index 3fab3f1..3b24af0 100644
>> --- a/drivers/serial/ns16550.c
>> +++ b/drivers/serial/ns16550.c
>> @@ -64,12 +64,16 @@ static inline void serial_out_shift(void *addr,
>> int shift, int value)
>> {
>> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
>> outb(value, (ulong)addr);
>> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
>> !defined(CONFIG_SYS_BIG_ENDIAN)
>> - out_le32(addr, value);
>> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
>> defined(CONFIG_SYS_BIG_ENDIAN)
>> - out_be32(addr, value);
>> #elif defined(CONFIG_SYS_NS16550_MEM32)
>> +#ifdef CONFIG_MIPS
>> writel(value, addr);
>> +#else
>> +#ifndef CONFIG_SYS_BIG_ENDIAN
>> + out_le32(addr, value);
>> +#else
>> + out_be32(addr, value);
>> +#endif
>> +#endif
>> #elif defined(CONFIG_SYS_BIG_ENDIAN)
>> writeb(value, addr + (1 << shift) - 1);
>> #else
>> @@ -81,12 +85,16 @@ static inline int serial_in_shift(void *addr, int
>> shift)
>> {
>> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
>> return inb((ulong)addr);
>> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
>> !defined(CONFIG_SYS_BIG_ENDIAN)
>> - return in_le32(addr);
>> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
>> defined(CONFIG_SYS_BIG_ENDIAN)
>> - return in_be32(addr);
>> #elif defined(CONFIG_SYS_NS16550_MEM32)
>> +#ifdef CONFIG_MIPS
>> return readl(addr);
>> +#else
>> +#ifndef CONFIG_SYS_BIG_ENDIAN
>> + return in_le32(addr);
>> +#else
>> + return in_be32(addr);
>> +#endif
>> +#endif
>> #elif defined(CONFIG_SYS_BIG_ENDIAN)
>> return readb(addr + (1 << shift) - 1);
>> #else
> Could you tell us, if you need port IO or MMIO. In case of MMIO do you
> need 8 bit or 32 bit I/O access?
>
> Becasue your CPU is running in Big Endian and the NS16550 is Little
> Endian, you need endianess conversion in the 32 bit case.
>
> The 8 bit access should already work without changing anything. The
> MIPS Malta board also uses NS16550 and already works in Bit Endian
> mode.
>
> To make the 32 bit case working, you need to select
> CONFIG_SWAP_IO_SPACE in your SoC Kconfig code. Then all readl/writel
> accessors do an endianess conversion to Little Endian if the CPU is
> running in Big Endian.
>
> Anyway I think the current implementation is wrong:
>
> static inline void serial_out_shift(void *addr, int shift, int value)
> {
> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> outb(value, (ulong)addr);
> #elif defined(CONFIG_SYS_NS16550_MEM32) &&
> !defined(CONFIG_SYS_BIG_ENDIAN)
> out_le32(addr, value);
> #elif defined(CONFIG_SYS_NS16550_MEM32) &&
> defined(CONFIG_SYS_BIG_ENDIAN)
> out_be32(addr, value);
> #elif defined(CONFIG_SYS_NS16550_MEM32)
> writel(value, addr);
> #elif defined(CONFIG_SYS_BIG_ENDIAN)
> writeb(value, addr + (1 << shift) - 1);
> #else
> writeb(value, addr);
> #endif
> }
>
> The branch with writel() will never be taken because the two preceding
> branches already catch all conditions for CONFIG_SYS_NS16550_MEM32.
> Also if the NS16550 is Little Endian, the branch with out_be32 makes no
> sense. All IO accessors must convert from CPU endianess to NS16550's
> Little Endian, but out_be32 converts from CPU endianess to Big Endian.
>
> To handle port IO, 32 Bit MMIO and 8 Bit MMIO, following code should be
> enough:
>
> static inline void serial_out_shift(void *addr, int shift, int value)
> {
> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> outb(value, (ulong)addr);
> #elif defined(CONFIG_SYS_NS16550_MEM32)
> writel(value, addr);
> #elif defined(CONFIG_SYS_BIG_ENDIAN)
> writeb(value, addr + (1 << shift) - 1);
> #else
> writeb(value, addr);
> #endif
> }
>
> The arch-specific implementation of readl/writel should be responsible
> for the endianess conversion and not the driver. What do you think?
>
I wholly agree with Daniel, driver should not care the endianness, we
need a general mechanism to deal with this situation, no matter the
endianness of CPU and peripheral IP Core.
But CONFIG_SWAP_IO_SPACE don't resolve this issue, NS16550 is just
one of many peripherals for CPU.
NS16550 use only 8bit register field even if in 32 bit MMIO. In actual,
driver may just concern the register offset beause the bit field of
register in chip datasheet is coincident with CPU endianness, even
though hardware support both big-endian and little-endian, so the
optimal code should be the following:
static inline void serial_out_shift(void *addr, int shift, int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
outb(value, (ulong)addr);
#elif defined(CONFIG_SYS_NS16550_MEM32)
writel(value, addr);
#else
writeb(value, addr);
#endif
}
I use 32bit MMIO to access uart currently, i think that 8 Bit MMIO
should work fine if adjust the register offset.
--
Best Regards
Wills
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 06/10] ns16550: add support for mips
2016-01-09 10:46 ` Wills Wang
@ 2016-01-09 14:30 ` Daniel Schwierzeck
2016-01-16 16:15 ` Wills Wang
0 siblings, 1 reply; 25+ messages in thread
From: Daniel Schwierzeck @ 2016-01-09 14:30 UTC (permalink / raw)
To: u-boot
Am Samstag, den 09.01.2016, 18:46 +0800 schrieb Wills Wang:
>
> On 01/09/2016 12:23 AM, Daniel Schwierzeck wrote:
> > Am Montag, den 04.01.2016, 19:14 +0800 schrieb Wills Wang:
> > > MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32"
> > > macro,
> > > but usually define CONFIG_SYS_BIG_ENDIAN, this patch use
> > > readl/writel
> > > for register operation in mips when define
> > > CONFIG_SYS_NS16550_MEM32.
> > >
> > > Signed-off-by: Wills Wang <wills.wang@live.com>
> > > ---
> > >
> > > Changes in v6: None
> > > Changes in v5: None
> > > Changes in v4: None
> > > Changes in v3: None
> > > Changes in v2: None
> > >
> > > drivers/serial/ns16550.c | 24 ++++++++++++++++--------
> > > 1 file changed, 16 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> > > index 3fab3f1..3b24af0 100644
> > > --- a/drivers/serial/ns16550.c
> > > +++ b/drivers/serial/ns16550.c
> > > @@ -64,12 +64,16 @@ static inline void serial_out_shift(void
> > > *addr,
> > > int shift, int value)
> > > {
> > > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > outb(value, (ulong)addr);
> > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > !defined(CONFIG_SYS_BIG_ENDIAN)
> > > - out_le32(addr, value);
> > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > defined(CONFIG_SYS_BIG_ENDIAN)
> > > - out_be32(addr, value);
> > > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > > +#ifdef CONFIG_MIPS
> > > writel(value, addr);
> > > +#else
> > > +#ifndef CONFIG_SYS_BIG_ENDIAN
> > > + out_le32(addr, value);
> > > +#else
> > > + out_be32(addr, value);
> > > +#endif
> > > +#endif
> > > #elif defined(CONFIG_SYS_BIG_ENDIAN)
> > > writeb(value, addr + (1 << shift) - 1);
> > > #else
> > > @@ -81,12 +85,16 @@ static inline int serial_in_shift(void *addr,
> > > int
> > > shift)
> > > {
> > > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > return inb((ulong)addr);
> > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > !defined(CONFIG_SYS_BIG_ENDIAN)
> > > - return in_le32(addr);
> > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > defined(CONFIG_SYS_BIG_ENDIAN)
> > > - return in_be32(addr);
> > > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > > +#ifdef CONFIG_MIPS
> > > return readl(addr);
> > > +#else
> > > +#ifndef CONFIG_SYS_BIG_ENDIAN
> > > + return in_le32(addr);
> > > +#else
> > > + return in_be32(addr);
> > > +#endif
> > > +#endif
> > > #elif defined(CONFIG_SYS_BIG_ENDIAN)
> > > return readb(addr + (1 << shift) - 1);
> > > #else
> > Could you tell us, if you need port IO or MMIO. In case of MMIO do
> > you
> > need 8 bit or 32 bit I/O access?
> >
> > Becasue your CPU is running in Big Endian and the NS16550 is Little
> > Endian, you need endianess conversion in the 32 bit case.
> >
> > The 8 bit access should already work without changing anything. The
> > MIPS Malta board also uses NS16550 and already works in Bit Endian
> > mode.
> >
> > To make the 32 bit case working, you need to select
> > CONFIG_SWAP_IO_SPACE in your SoC Kconfig code. Then all
> > readl/writel
> > accessors do an endianess conversion to Little Endian if the CPU is
> > running in Big Endian.
> >
> > Anyway I think the current implementation is wrong:
> >
> > static inline void serial_out_shift(void *addr, int shift, int
> > value)
> > {
> > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > outb(value, (ulong)addr);
> > #elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > !defined(CONFIG_SYS_BIG_ENDIAN)
> > out_le32(addr, value);
> > #elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > defined(CONFIG_SYS_BIG_ENDIAN)
> > out_be32(addr, value);
> > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > writel(value, addr);
> > #elif defined(CONFIG_SYS_BIG_ENDIAN)
> > writeb(value, addr + (1 << shift) - 1);
> > #else
> > writeb(value, addr);
> > #endif
> > }
> >
> > The branch with writel() will never be taken because the two
> > preceding
> > branches already catch all conditions for CONFIG_SYS_NS16550_MEM32.
> > Also if the NS16550 is Little Endian, the branch with out_be32
> > makes no
> > sense. All IO accessors must convert from CPU endianess to
> > NS16550's
> > Little Endian, but out_be32 converts from CPU endianess to Big
> > Endian.
> >
> > To handle port IO, 32 Bit MMIO and 8 Bit MMIO, following code
> > should be
> > enough:
> >
> > static inline void serial_out_shift(void *addr, int shift, int
> > value)
> > {
> > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > outb(value, (ulong)addr);
> > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > writel(value, addr);
> > #elif defined(CONFIG_SYS_BIG_ENDIAN)
> > writeb(value, addr + (1 << shift) - 1);
> > #else
> > writeb(value, addr);
> > #endif
> > }
> >
> > The arch-specific implementation of readl/writel should be
> > responsible
> > for the endianess conversion and not the driver. What do you think?
> >
> I wholly agree with Daniel, driver should not care the endianness, we
> need a general mechanism to deal with this situation, no matter the
> endianness of CPU and peripheral IP Core.
> But CONFIG_SWAP_IO_SPACE don't resolve this issue, NS16550 is just
> one of many peripherals for CPU.
> NS16550 use only 8bit register field even if in 32 bit MMIO. In
> actual,
> driver may just concern the register offset beause the bit field of
> register in chip datasheet is coincident with CPU endianness, even
> though hardware support both big-endian and little-endian, so the
> optimal code should be the following:
> static inline void serial_out_shift(void *addr, int shift, int value)
> {
> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> outb(value, (ulong)addr);
> #elif defined(CONFIG_SYS_NS16550_MEM32)
> writel(value, addr);
> #else
> writeb(value, addr);
> #endif
> }
> I use 32bit MMIO to access uart currently, i think that 8 Bit MMIO
> should work fine if adjust the register offset.
>
then try to use 8 bit access and find the correct register offset. You
can configure that offset with the DT property "reg-shift".
--
- Daniel
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 06/10] ns16550: add support for mips
2016-01-09 14:30 ` Daniel Schwierzeck
@ 2016-01-16 16:15 ` Wills Wang
2016-01-16 16:26 ` Daniel Schwierzeck
0 siblings, 1 reply; 25+ messages in thread
From: Wills Wang @ 2016-01-16 16:15 UTC (permalink / raw)
To: u-boot
On Saturday, January 09, 2016 10:30 PM, Daniel Schwierzeck wrote:
> Am Samstag, den 09.01.2016, 18:46 +0800 schrieb Wills Wang:
>> On 01/09/2016 12:23 AM, Daniel Schwierzeck wrote:
>>> Am Montag, den 04.01.2016, 19:14 +0800 schrieb Wills Wang:
>>>> MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32"
>>>> macro,
>>>> but usually define CONFIG_SYS_BIG_ENDIAN, this patch use
>>>> readl/writel
>>>> for register operation in mips when define
>>>> CONFIG_SYS_NS16550_MEM32.
>>>>
>>>> Signed-off-by: Wills Wang <wills.wang@live.com>
>>>> ---
>>>>
>>>> Changes in v6: None
>>>> Changes in v5: None
>>>> Changes in v4: None
>>>> Changes in v3: None
>>>> Changes in v2: None
>>>>
>>>> drivers/serial/ns16550.c | 24 ++++++++++++++++--------
>>>> 1 file changed, 16 insertions(+), 8 deletions(-)
>>>>
>>>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>>>> index 3fab3f1..3b24af0 100644
>>>> --- a/drivers/serial/ns16550.c
>>>> +++ b/drivers/serial/ns16550.c
>>>> @@ -64,12 +64,16 @@ static inline void serial_out_shift(void
>>>> *addr,
>>>> int shift, int value)
>>>> {
>>>> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
>>>> outb(value, (ulong)addr);
>>>> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
>>>> !defined(CONFIG_SYS_BIG_ENDIAN)
>>>> - out_le32(addr, value);
>>>> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
>>>> defined(CONFIG_SYS_BIG_ENDIAN)
>>>> - out_be32(addr, value);
>>>> #elif defined(CONFIG_SYS_NS16550_MEM32)
>>>> +#ifdef CONFIG_MIPS
>>>> writel(value, addr);
>>>> +#else
>>>> +#ifndef CONFIG_SYS_BIG_ENDIAN
>>>> + out_le32(addr, value);
>>>> +#else
>>>> + out_be32(addr, value);
>>>> +#endif
>>>> +#endif
>>>> #elif defined(CONFIG_SYS_BIG_ENDIAN)
>>>> writeb(value, addr + (1 << shift) - 1);
>>>> #else
>>>> @@ -81,12 +85,16 @@ static inline int serial_in_shift(void *addr,
>>>> int
>>>> shift)
>>>> {
>>>> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
>>>> return inb((ulong)addr);
>>>> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
>>>> !defined(CONFIG_SYS_BIG_ENDIAN)
>>>> - return in_le32(addr);
>>>> -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
>>>> defined(CONFIG_SYS_BIG_ENDIAN)
>>>> - return in_be32(addr);
>>>> #elif defined(CONFIG_SYS_NS16550_MEM32)
>>>> +#ifdef CONFIG_MIPS
>>>> return readl(addr);
>>>> +#else
>>>> +#ifndef CONFIG_SYS_BIG_ENDIAN
>>>> + return in_le32(addr);
>>>> +#else
>>>> + return in_be32(addr);
>>>> +#endif
>>>> +#endif
>>>> #elif defined(CONFIG_SYS_BIG_ENDIAN)
>>>> return readb(addr + (1 << shift) - 1);
>>>> #else
>>> Could you tell us, if you need port IO or MMIO. In case of MMIO do
>>> you
>>> need 8 bit or 32 bit I/O access?
>>>
>>> Becasue your CPU is running in Big Endian and the NS16550 is Little
>>> Endian, you need endianess conversion in the 32 bit case.
>>>
>>> The 8 bit access should already work without changing anything. The
>>> MIPS Malta board also uses NS16550 and already works in Bit Endian
>>> mode.
>>>
>>> To make the 32 bit case working, you need to select
>>> CONFIG_SWAP_IO_SPACE in your SoC Kconfig code. Then all
>>> readl/writel
>>> accessors do an endianess conversion to Little Endian if the CPU is
>>> running in Big Endian.
>>>
>>> Anyway I think the current implementation is wrong:
>>>
>>> static inline void serial_out_shift(void *addr, int shift, int
>>> value)
>>> {
>>> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
>>> outb(value, (ulong)addr);
>>> #elif defined(CONFIG_SYS_NS16550_MEM32) &&
>>> !defined(CONFIG_SYS_BIG_ENDIAN)
>>> out_le32(addr, value);
>>> #elif defined(CONFIG_SYS_NS16550_MEM32) &&
>>> defined(CONFIG_SYS_BIG_ENDIAN)
>>> out_be32(addr, value);
>>> #elif defined(CONFIG_SYS_NS16550_MEM32)
>>> writel(value, addr);
>>> #elif defined(CONFIG_SYS_BIG_ENDIAN)
>>> writeb(value, addr + (1 << shift) - 1);
>>> #else
>>> writeb(value, addr);
>>> #endif
>>> }
>>>
>>> The branch with writel() will never be taken because the two
>>> preceding
>>> branches already catch all conditions for CONFIG_SYS_NS16550_MEM32.
>>> Also if the NS16550 is Little Endian, the branch with out_be32
>>> makes no
>>> sense. All IO accessors must convert from CPU endianess to
>>> NS16550's
>>> Little Endian, but out_be32 converts from CPU endianess to Big
>>> Endian.
>>>
>>> To handle port IO, 32 Bit MMIO and 8 Bit MMIO, following code
>>> should be
>>> enough:
>>>
>>> static inline void serial_out_shift(void *addr, int shift, int
>>> value)
>>> {
>>> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
>>> outb(value, (ulong)addr);
>>> #elif defined(CONFIG_SYS_NS16550_MEM32)
>>> writel(value, addr);
>>> #elif defined(CONFIG_SYS_BIG_ENDIAN)
>>> writeb(value, addr + (1 << shift) - 1);
>>> #else
>>> writeb(value, addr);
>>> #endif
>>> }
>>>
>>> The arch-specific implementation of readl/writel should be
>>> responsible
>>> for the endianess conversion and not the driver. What do you think?
>>>
>> I wholly agree with Daniel, driver should not care the endianness, we
>> need a general mechanism to deal with this situation, no matter the
>> endianness of CPU and peripheral IP Core.
>> But CONFIG_SWAP_IO_SPACE don't resolve this issue, NS16550 is just
>> one of many peripherals for CPU.
>> NS16550 use only 8bit register field even if in 32 bit MMIO. In
>> actual,
>> driver may just concern the register offset beause the bit field of
>> register in chip datasheet is coincident with CPU endianness, even
>> though hardware support both big-endian and little-endian, so the
>> optimal code should be the following:
>> static inline void serial_out_shift(void *addr, int shift, int value)
>> {
>> #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
>> outb(value, (ulong)addr);
>> #elif defined(CONFIG_SYS_NS16550_MEM32)
>> writel(value, addr);
>> #else
>> writeb(value, addr);
>> #endif
>> }
>> I use 32bit MMIO to access uart currently, i think that 8 Bit MMIO
>> should work fine if adjust the register offset.
>>
> then try to use 8 bit access and find the correct register offset. You
> can configure that offset with the DT property "reg-shift".
>
CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN are used
just for MIPS in u-boot?
--
Best Regards
Wills
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 06/10] ns16550: add support for mips
2016-01-16 16:15 ` Wills Wang
@ 2016-01-16 16:26 ` Daniel Schwierzeck
0 siblings, 0 replies; 25+ messages in thread
From: Daniel Schwierzeck @ 2016-01-16 16:26 UTC (permalink / raw)
To: u-boot
Am Sonntag, den 17.01.2016, 00:15 +0800 schrieb Wills Wang:
>
> On Saturday, January 09, 2016 10:30 PM, Daniel Schwierzeck wrote:
> > Am Samstag, den 09.01.2016, 18:46 +0800 schrieb Wills Wang:
> > > On 01/09/2016 12:23 AM, Daniel Schwierzeck wrote:
> > > > Am Montag, den 04.01.2016, 19:14 +0800 schrieb Wills Wang:
> > > > > MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32"
> > > > > macro,
> > > > > but usually define CONFIG_SYS_BIG_ENDIAN, this patch use
> > > > > readl/writel
> > > > > for register operation in mips when define
> > > > > CONFIG_SYS_NS16550_MEM32.
> > > > >
> > > > > Signed-off-by: Wills Wang <wills.wang@live.com>
> > > > > ---
> > > > >
> > > > > Changes in v6: None
> > > > > Changes in v5: None
> > > > > Changes in v4: None
> > > > > Changes in v3: None
> > > > > Changes in v2: None
> > > > >
> > > > > drivers/serial/ns16550.c | 24 ++++++++++++++++--------
> > > > > 1 file changed, 16 insertions(+), 8 deletions(-)
> > > > >
> > > > > diff --git a/drivers/serial/ns16550.c
> > > > > b/drivers/serial/ns16550.c
> > > > > index 3fab3f1..3b24af0 100644
> > > > > --- a/drivers/serial/ns16550.c
> > > > > +++ b/drivers/serial/ns16550.c
> > > > > @@ -64,12 +64,16 @@ static inline void serial_out_shift(void
> > > > > *addr,
> > > > > int shift, int value)
> > > > > {
> > > > > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > > > outb(value, (ulong)addr);
> > > > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > > !defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > - out_le32(addr, value);
> > > > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > > defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > - out_be32(addr, value);
> > > > > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > > > > +#ifdef CONFIG_MIPS
> > > > > writel(value, addr);
> > > > > +#else
> > > > > +#ifndef CONFIG_SYS_BIG_ENDIAN
> > > > > + out_le32(addr, value);
> > > > > +#else
> > > > > + out_be32(addr, value);
> > > > > +#endif
> > > > > +#endif
> > > > > #elif defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > writeb(value, addr + (1 << shift) - 1);
> > > > > #else
> > > > > @@ -81,12 +85,16 @@ static inline int serial_in_shift(void
> > > > > *addr,
> > > > > int
> > > > > shift)
> > > > > {
> > > > > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > > > return inb((ulong)addr);
> > > > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > > !defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > - return in_le32(addr);
> > > > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > > defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > - return in_be32(addr);
> > > > > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > > > > +#ifdef CONFIG_MIPS
> > > > > return readl(addr);
> > > > > +#else
> > > > > +#ifndef CONFIG_SYS_BIG_ENDIAN
> > > > > + return in_le32(addr);
> > > > > +#else
> > > > > + return in_be32(addr);
> > > > > +#endif
> > > > > +#endif
> > > > > #elif defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > return readb(addr + (1 << shift) - 1);
> > > > > #else
> > > > Could you tell us, if you need port IO or MMIO. In case of MMIO
> > > > do
> > > > you
> > > > need 8 bit or 32 bit I/O access?
> > > >
> > > > Becasue your CPU is running in Big Endian and the NS16550 is
> > > > Little
> > > > Endian, you need endianess conversion in the 32 bit case.
> > > >
> > > > The 8 bit access should already work without changing anything.
> > > > The
> > > > MIPS Malta board also uses NS16550 and already works in Bit
> > > > Endian
> > > > mode.
> > > >
> > > > To make the 32 bit case working, you need to select
> > > > CONFIG_SWAP_IO_SPACE in your SoC Kconfig code. Then all
> > > > readl/writel
> > > > accessors do an endianess conversion to Little Endian if the
> > > > CPU is
> > > > running in Big Endian.
> > > >
> > > > Anyway I think the current implementation is wrong:
> > > >
> > > > static inline void serial_out_shift(void *addr, int shift, int
> > > > value)
> > > > {
> > > > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > > outb(value, (ulong)addr);
> > > > #elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > !defined(CONFIG_SYS_BIG_ENDIAN)
> > > > out_le32(addr, value);
> > > > #elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > defined(CONFIG_SYS_BIG_ENDIAN)
> > > > out_be32(addr, value);
> > > > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > > > writel(value, addr);
> > > > #elif defined(CONFIG_SYS_BIG_ENDIAN)
> > > > writeb(value, addr + (1 << shift) - 1);
> > > > #else
> > > > writeb(value, addr);
> > > > #endif
> > > > }
> > > >
> > > > The branch with writel() will never be taken because the two
> > > > preceding
> > > > branches already catch all conditions for
> > > > CONFIG_SYS_NS16550_MEM32.
> > > > Also if the NS16550 is Little Endian, the branch with out_be32
> > > > makes no
> > > > sense. All IO accessors must convert from CPU endianess to
> > > > NS16550's
> > > > Little Endian, but out_be32 converts from CPU endianess to Big
> > > > Endian.
> > > >
> > > > To handle port IO, 32 Bit MMIO and 8 Bit MMIO, following code
> > > > should be
> > > > enough:
> > > >
> > > > static inline void serial_out_shift(void *addr, int shift, int
> > > > value)
> > > > {
> > > > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > > outb(value, (ulong)addr);
> > > > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > > > writel(value, addr);
> > > > #elif defined(CONFIG_SYS_BIG_ENDIAN)
> > > > writeb(value, addr + (1 << shift) - 1);
> > > > #else
> > > > writeb(value, addr);
> > > > #endif
> > > > }
> > > >
> > > > The arch-specific implementation of readl/writel should be
> > > > responsible
> > > > for the endianess conversion and not the driver. What do you
> > > > think?
> > > >
> > > I wholly agree with Daniel, driver should not care the
> > > endianness, we
> > > need a general mechanism to deal with this situation, no matter
> > > the
> > > endianness of CPU and peripheral IP Core.
> > > But CONFIG_SWAP_IO_SPACE don't resolve this issue, NS16550 is
> > > just
> > > one of many peripherals for CPU.
> > > NS16550 use only 8bit register field even if in 32 bit MMIO. In
> > > actual,
> > > driver may just concern the register offset beause the bit field
> > > of
> > > register in chip datasheet is coincident with CPU endianness,
> > > even
> > > though hardware support both big-endian and little-endian, so the
> > > optimal code should be the following:
> > > static inline void serial_out_shift(void *addr, int shift, int
> > > value)
> > > {
> > > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > outb(value, (ulong)addr);
> > > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > > writel(value, addr);
> > > #else
> > > writeb(value, addr);
> > > #endif
> > > }
> > > I use 32bit MMIO to access uart currently, i think that 8 Bit
> > > MMIO
> > > should work fine if adjust the register offset.
> > >
> > then try to use 8 bit access and find the correct register offset.
> > You
> > can configure that offset with the DT property "reg-shift".
> >
> CONFIG_SYS_BIG_ENDIAN and CONFIG_SYS_LITTLE_ENDIAN are used
> just for MIPS in u-boot?
no, that is a generic config option. E.g. PowerPC also has BE, most
other archs have LE, MIPS supports both variants.
--
- Daniel
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v6 07/10] ns16550: map register base address for debug UART
[not found] <1451906101-9801-2-git-send-email-wills.wang@live.com>
` (4 preceding siblings ...)
2016-01-04 11:14 ` [U-Boot] [PATCH v6 06/10] ns16550: add support for mips Wills Wang
@ 2016-01-04 11:14 ` Wills Wang
2016-01-04 13:07 ` Thomas Chou
2016-01-04 11:14 ` [U-Boot] [PATCH v6 08/10] mips: ath79: add spi driver Wills Wang
` (2 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Wills Wang @ 2016-01-04 11:14 UTC (permalink / raw)
To: u-boot
MIPS need to use KSEG1 address for register operation, this patch
add map_physmem to convert CONFIG_DEBUG_UART_BASE for debug UART.
Signed-off-by: Wills Wang <wills.wang@live.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/serial/ns16550.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3b24af0..1e2538e 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -270,7 +270,8 @@ int NS16550_tstc(NS16550_t com_port)
static inline void _debug_uart_init(void)
{
- struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
+ struct NS16550 *com_port = (struct NS16550 *)map_physmem(
+ CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
int baud_divisor;
/*
@@ -293,7 +294,8 @@ static inline void _debug_uart_init(void)
static inline void _debug_uart_putc(int ch)
{
- struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
+ struct NS16550 *com_port = (struct NS16550 *)map_physmem(
+ CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
;
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 07/10] ns16550: map register base address for debug UART
2016-01-04 11:14 ` [U-Boot] [PATCH v6 07/10] ns16550: map register base address for debug UART Wills Wang
@ 2016-01-04 13:07 ` Thomas Chou
2016-01-04 14:10 ` Wills Wang
2016-01-05 21:18 ` Daniel Schwierzeck
0 siblings, 2 replies; 25+ messages in thread
From: Thomas Chou @ 2016-01-04 13:07 UTC (permalink / raw)
To: u-boot
Hi Wills,
On 2016?01?04? 19:14, Wills Wang wrote:
> MIPS need to use KSEG1 address for register operation, this patch
> add map_physmem to convert CONFIG_DEBUG_UART_BASE for debug UART.
>
> Signed-off-by: Wills Wang <wills.wang@live.com>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> drivers/serial/ns16550.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 3b24af0..1e2538e 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -270,7 +270,8 @@ int NS16550_tstc(NS16550_t com_port)
>
> static inline void _debug_uart_init(void)
> {
> - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
> + struct NS16550 *com_port = (struct NS16550 *)map_physmem(
> + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
> int baud_divisor;
>
> /*
> @@ -293,7 +294,8 @@ static inline void _debug_uart_init(void)
>
> static inline void _debug_uart_putc(int ch)
> {
> - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
> + struct NS16550 *com_port = (struct NS16550 *)map_physmem(
> + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
>
> while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
> ;
>
As debug uart may be used in very early stage and SPL, I would suggest
the CONFIG_DEBUG_UART_BASE here is mapped to uncached space already. So
that we can keep the code and stack usage minimal.
My concern is that the uncache mapping in nios2 arch is different
between NOMMU and MMU core, which will be decoded from device tree. So
it won't work for nios2 until DM initialized.
Naked-by: Thomas Chou <thomas@wytron.com.tw>
Best regards,
Thomas
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 07/10] ns16550: map register base address for debug UART
2016-01-04 13:07 ` Thomas Chou
@ 2016-01-04 14:10 ` Wills Wang
2016-01-05 21:18 ` Daniel Schwierzeck
1 sibling, 0 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-04 14:10 UTC (permalink / raw)
To: u-boot
On 01/04/2016 09:07 PM, Thomas Chou wrote:
> Hi Wills,
>
> On 2016?01?04? 19:14, Wills Wang wrote:
>> MIPS need to use KSEG1 address for register operation, this patch
>> add map_physmem to convert CONFIG_DEBUG_UART_BASE for debug UART.
>>
>> Signed-off-by: Wills Wang <wills.wang@live.com>
>> ---
>>
>> Changes in v6: None
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>> drivers/serial/ns16550.c | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>> index 3b24af0..1e2538e 100644
>> --- a/drivers/serial/ns16550.c
>> +++ b/drivers/serial/ns16550.c
>> @@ -270,7 +270,8 @@ int NS16550_tstc(NS16550_t com_port)
>>
>> static inline void _debug_uart_init(void)
>> {
>> - struct NS16550 *com_port = (struct NS16550
>> *)CONFIG_DEBUG_UART_BASE;
>> + struct NS16550 *com_port = (struct NS16550 *)map_physmem(
>> + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
>> int baud_divisor;
>>
>> /*
>> @@ -293,7 +294,8 @@ static inline void _debug_uart_init(void)
>>
>> static inline void _debug_uart_putc(int ch)
>> {
>> - struct NS16550 *com_port = (struct NS16550
>> *)CONFIG_DEBUG_UART_BASE;
>> + struct NS16550 *com_port = (struct NS16550 *)map_physmem(
>> + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
>>
>> while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
>> ;
>>
>
> As debug uart may be used in very early stage and SPL, I would suggest
> the CONFIG_DEBUG_UART_BASE here is mapped to uncached space already.
> So that we can keep the code and stack usage minimal.
>
> My concern is that the uncache mapping in nios2 arch is different
> between NOMMU and MMU core, which will be decoded from device tree. So
> it won't work for nios2 until DM initialized.
>
Ok, i see. CONFIG_DEBUG_UART_BASE is different from the address from
device tree if not map.
> Naked-by: Thomas Chou <thomas@wytron.com.tw>
>
> Best regards,
> Thomas
--
Best Regards
Wills
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 07/10] ns16550: map register base address for debug UART
2016-01-04 13:07 ` Thomas Chou
2016-01-04 14:10 ` Wills Wang
@ 2016-01-05 21:18 ` Daniel Schwierzeck
2016-01-06 2:50 ` Wills Wang
1 sibling, 1 reply; 25+ messages in thread
From: Daniel Schwierzeck @ 2016-01-05 21:18 UTC (permalink / raw)
To: u-boot
2016-01-04 14:07 GMT+01:00 Thomas Chou <thomas@wytron.com.tw>:
> Hi Wills,
>
>
> On 2016?01?04? 19:14, Wills Wang wrote:
>>
>> MIPS need to use KSEG1 address for register operation, this patch
>> add map_physmem to convert CONFIG_DEBUG_UART_BASE for debug UART.
>>
>> Signed-off-by: Wills Wang <wills.wang@live.com>
>> ---
>>
>> Changes in v6: None
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>> drivers/serial/ns16550.c | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>> index 3b24af0..1e2538e 100644
>> --- a/drivers/serial/ns16550.c
>> +++ b/drivers/serial/ns16550.c
>> @@ -270,7 +270,8 @@ int NS16550_tstc(NS16550_t com_port)
>>
>> static inline void _debug_uart_init(void)
>> {
>> - struct NS16550 *com_port = (struct NS16550
>> *)CONFIG_DEBUG_UART_BASE;
>> + struct NS16550 *com_port = (struct NS16550 *)map_physmem(
>> + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
>> int baud_divisor;
>>
>> /*
>> @@ -293,7 +294,8 @@ static inline void _debug_uart_init(void)
>>
>> static inline void _debug_uart_putc(int ch)
>> {
>> - struct NS16550 *com_port = (struct NS16550
>> *)CONFIG_DEBUG_UART_BASE;
>> + struct NS16550 *com_port = (struct NS16550 *)map_physmem(
>> + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
>>
>> while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
>> ;
>>
>
> As debug uart may be used in very early stage and SPL, I would suggest the
> CONFIG_DEBUG_UART_BASE here is mapped to uncached space already. So that we
> can keep the code and stack usage minimal.
>
> My concern is that the uncache mapping in nios2 arch is different between
> NOMMU and MMU core, which will be decoded from device tree. So it won't work
> for nios2 until DM initialized.
>
> Naked-by: Thomas Chou <thomas@wytron.com.tw>
>
I agree with Thomas. Please set CONFIG_DEBUG_UART_BASE to a KSEG1
address and discard this patch.
--
- Daniel
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 07/10] ns16550: map register base address for debug UART
2016-01-05 21:18 ` Daniel Schwierzeck
@ 2016-01-06 2:50 ` Wills Wang
0 siblings, 0 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-06 2:50 UTC (permalink / raw)
To: u-boot
On 01/06/2016 05:18 AM, Daniel Schwierzeck wrote:
> 2016-01-04 14:07 GMT+01:00 Thomas Chou <thomas@wytron.com.tw>:
>> Hi Wills,
>>
>>
>> On 2016?01?04? 19:14, Wills Wang wrote:
>>> MIPS need to use KSEG1 address for register operation, this patch
>>> add map_physmem to convert CONFIG_DEBUG_UART_BASE for debug UART.
>>>
>>> Signed-off-by: Wills Wang <wills.wang@live.com>
>>> ---
>>>
>>> Changes in v6: None
>>> Changes in v5: None
>>> Changes in v4: None
>>> Changes in v3: None
>>> Changes in v2: None
>>>
>>> drivers/serial/ns16550.c | 6 ++++--
>>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>>> index 3b24af0..1e2538e 100644
>>> --- a/drivers/serial/ns16550.c
>>> +++ b/drivers/serial/ns16550.c
>>> @@ -270,7 +270,8 @@ int NS16550_tstc(NS16550_t com_port)
>>>
>>> static inline void _debug_uart_init(void)
>>> {
>>> - struct NS16550 *com_port = (struct NS16550
>>> *)CONFIG_DEBUG_UART_BASE;
>>> + struct NS16550 *com_port = (struct NS16550 *)map_physmem(
>>> + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
>>> int baud_divisor;
>>>
>>> /*
>>> @@ -293,7 +294,8 @@ static inline void _debug_uart_init(void)
>>>
>>> static inline void _debug_uart_putc(int ch)
>>> {
>>> - struct NS16550 *com_port = (struct NS16550
>>> *)CONFIG_DEBUG_UART_BASE;
>>> + struct NS16550 *com_port = (struct NS16550 *)map_physmem(
>>> + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE);
>>>
>>> while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
>>> ;
>>>
>> As debug uart may be used in very early stage and SPL, I would suggest the
>> CONFIG_DEBUG_UART_BASE here is mapped to uncached space already. So that we
>> can keep the code and stack usage minimal.
>>
>> My concern is that the uncache mapping in nios2 arch is different between
>> NOMMU and MMU core, which will be decoded from device tree. So it won't work
>> for nios2 until DM initialized.
>>
>> Naked-by: Thomas Chou <thomas@wytron.com.tw>
>>
> I agree with Thomas. Please set CONFIG_DEBUG_UART_BASE to a KSEG1
> address and discard this patch.
>
Ok.
I will correct this in the next patch.
--
Best Regards
Wills
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v6 08/10] mips: ath79: add spi driver
[not found] <1451906101-9801-2-git-send-email-wills.wang@live.com>
` (5 preceding siblings ...)
2016-01-04 11:14 ` [U-Boot] [PATCH v6 07/10] ns16550: map register base address for debug UART Wills Wang
@ 2016-01-04 11:14 ` Wills Wang
2016-01-05 2:51 ` Thomas Chou
2016-01-06 12:16 ` Jagan Teki
2016-01-04 11:15 ` [U-Boot] [PATCH v6 09/10] mips: ath79: add AP121 reference board Wills Wang
2016-01-04 11:15 ` [U-Boot] [PATCH v6 10/10] mips: ath79: add AP143 " Wills Wang
8 siblings, 2 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-04 11:14 UTC (permalink / raw)
To: u-boot
Signed-off-by: Wills Wang <wills.wang@live.com>
---
Changes in v6:
- Add rrw_delay in ath79_spi_priv for more accurate timing
- Remove ath79_spi_delay
- Calculate delay in ath79_spi_set_speed
Changes in v5:
- remove ar933x_spi_platdata
- Import document "spi-ath79.txt" from kernel
- Add delay for bitbang operation
Changes in v4:
- Use get_bus_freq instead of hardcode in SPI driver
Changes in v3:
- Convert spi driver to driver model
- Same code style convertion
Changes in v2:
- Add a compatible spi driver
doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/ath79_spi.c | 230 +++++++++++++++++++++++++++++
4 files changed, 258 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt
create mode 100644 drivers/spi/ath79_spi.c
diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt
new file mode 100644
index 0000000..3fd9d67
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-ath79.txt
@@ -0,0 +1,19 @@
+Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
+
+Required properties:
+- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
+- reg: Base address and size of the controllers memory area
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+ spi at 1f000000 {
+ compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+ reg = <0x1f000000 0x10>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2cdb110..0ab2741 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -23,6 +23,14 @@ config ALTERA_SPI
IP core. Please find details on the "Embedded Peripherals IP
User Guide" of Altera.
+config ATH79_SPI
+ bool "Atheros SPI driver"
+ help
+ Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
+ to access SPI NOR flash and other SPI peripherals. This driver
+ uses driver model and requires a device tree binding to operate.
+ please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+
config CADENCE_QSPI
bool "Cadence QSPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3eca745..7fb2926 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,6 +17,7 @@ endif
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
new file mode 100644
index 0000000..3912332
--- /dev/null
+++ b/drivers/spi/ath79_spi.c
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+
+/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
+#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1)
+#define ATH79_SPI_RRW_DELAY_FACTOR 12000
+#define MHZ (1000 * 1000)
+
+struct ath79_spi_priv {
+ void __iomem *regs;
+ u32 rrw_delay;
+};
+
+static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
+{
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ return readl(priv->regs + offset);
+}
+
+static inline void ath79_spi_write(struct udevice *bus,
+ u32 val, u32 offset)
+{
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ writel(val, priv->regs + offset);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ u8 *rx = din;
+ const u8 *tx = dout;
+ u8 curbyte, curbitlen, restbits;
+ u32 bytes = bitlen / 8;
+ u32 out, in;
+ u64 tick;
+
+
+ if (flags & SPI_XFER_BEGIN) {
+ ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+ ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+ }
+
+ restbits = (bitlen % 8);
+ if (restbits)
+ bytes++;
+
+ out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
+ while (bytes > 0) {
+ bytes--;
+ curbyte = 0;
+ if (tx)
+ curbyte = *tx++;
+
+ if (restbits && !bytes) {
+ curbitlen = restbits;
+ curbyte <<= 8 - restbits;
+ } else {
+ curbitlen = 8;
+ }
+
+ for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
+ if (curbyte & 0x80)
+ out |= AR71XX_SPI_IOC_DO;
+ else
+ out &= ~(AR71XX_SPI_IOC_DO);
+
+ ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
+
+ /* delay for low level */
+ if (priv->rrw_delay) {
+ tick = get_ticks() + priv->rrw_delay;
+ while (get_ticks() < tick)
+ /*NOP*/;
+ }
+
+ ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK,
+ AR71XX_SPI_REG_IOC);
+
+ /* delay for high level */
+ if (priv->rrw_delay) {
+ tick = get_ticks() + priv->rrw_delay;
+ while (get_ticks() < tick)
+ /*NOP*/;
+ }
+
+ curbyte <<= 1;
+ }
+
+ if (!bytes)
+ ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
+
+ in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
+ if (rx) {
+ if (restbits && !bytes)
+ *rx++ = (in << (8 - restbits));
+ else
+ *rx++ = in;
+ }
+ }
+
+ if (flags & SPI_XFER_END) {
+ ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs),
+ AR71XX_SPI_REG_IOC);
+ ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+ ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+ }
+
+ return 0;
+}
+
+
+static int ath79_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ u32 val, div = 0;
+ u64 time;
+
+ if (speed)
+ div = get_bus_freq(0) / speed;
+
+ if (div > 63)
+ div = 63;
+
+ if (div < 5)
+ div = 5;
+
+ /* calculate delay */
+ time = get_tbclk();
+ do_div(time, speed / 2);
+ val = ATH79_SPI_RRW_DELAY_FACTOR / (get_bus_freq(0) / MHZ);
+ if (time > val)
+ priv->rrw_delay = time - val + 1;
+ else
+ priv->rrw_delay = 0;
+
+ ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+ val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL);
+ val &= ~AR71XX_SPI_CTRL_DIV_MASK;
+ val |= ATH79_SPI_CLK_DIV(div);
+ ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL);
+ ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+ return 0;
+}
+
+static int ath79_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static int ath79_spi_probe(struct udevice *bus)
+{
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(bus);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = map_physmem(addr,
+ AR71XX_SPI_SIZE,
+ MAP_NOCACHE);
+
+ /* Init SPI Hardware, disable remap, set clock */
+ ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+ ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
+ AR71XX_SPI_REG_CTRL);
+ ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+
+ return 0;
+}
+
+static int ath79_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+{
+ /* Always allow activity on CS 0/1/2 */
+ if (cs >= 3)
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct dm_spi_ops ath79_spi_ops = {
+ .claim_bus = ath79_spi_claim_bus,
+ .release_bus = ath79_spi_release_bus,
+ .xfer = ath79_spi_xfer,
+ .set_speed = ath79_spi_set_speed,
+ .set_mode = ath79_spi_set_mode,
+ .cs_info = ath79_cs_info,
+};
+
+static const struct udevice_id ath79_spi_ids[] = {
+ { .compatible = "qca,ar7100-spi" },
+ {}
+};
+
+U_BOOT_DRIVER(ath79_spi) = {
+ .name = "ath79_spi",
+ .id = UCLASS_SPI,
+ .of_match = ath79_spi_ids,
+ .ops = &ath79_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
+ .probe = ath79_spi_probe,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 08/10] mips: ath79: add spi driver
2016-01-04 11:14 ` [U-Boot] [PATCH v6 08/10] mips: ath79: add spi driver Wills Wang
@ 2016-01-05 2:51 ` Thomas Chou
2016-01-06 12:16 ` Jagan Teki
1 sibling, 0 replies; 25+ messages in thread
From: Thomas Chou @ 2016-01-05 2:51 UTC (permalink / raw)
To: u-boot
Hi Wills,
On 2016?01?04? 19:14, Wills Wang wrote:
> Signed-off-by: Wills Wang <wills.wang@live.com>
> ---
>
> Changes in v6:
> - Add rrw_delay in ath79_spi_priv for more accurate timing
> - Remove ath79_spi_delay
> - Calculate delay in ath79_spi_set_speed
>
> Changes in v5:
> - remove ar933x_spi_platdata
> - Import document "spi-ath79.txt" from kernel
> - Add delay for bitbang operation
>
> Changes in v4:
> - Use get_bus_freq instead of hardcode in SPI driver
>
> Changes in v3:
> - Convert spi driver to driver model
> - Same code style convertion
>
> Changes in v2:
> - Add a compatible spi driver
>
> doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/ath79_spi.c | 230 +++++++++++++++++++++++++++++
> 4 files changed, 258 insertions(+)
> create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt
> create mode 100644 drivers/spi/ath79_spi.c
>
> diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt
> new file mode 100644
> index 0000000..3fd9d67
> --- /dev/null
> +++ b/doc/device-tree-bindings/spi/spi-ath79.txt
> @@ -0,0 +1,19 @@
> +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
> +
> +Required properties:
> +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
> +- reg: Base address and size of the controllers memory area
> +- #address-cells: <1>, as required by generic SPI binding.
> +- #size-cells: <0>, also as required by generic SPI binding.
> +
> +Child nodes as per the generic SPI binding.
> +
> +Example:
> +
> + spi at 1f000000 {
> + compatible = "qca,ar9132-spi", "qca,ar7100-spi";
> + reg = <0x1f000000 0x10>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 2cdb110..0ab2741 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -23,6 +23,14 @@ config ALTERA_SPI
> IP core. Please find details on the "Embedded Peripherals IP
> User Guide" of Altera.
>
> +config ATH79_SPI
> + bool "Atheros SPI driver"
> + help
> + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
> + to access SPI NOR flash and other SPI peripherals. This driver
> + uses driver model and requires a device tree binding to operate.
> + please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
> +
> config CADENCE_QSPI
> bool "Cadence QSPI driver"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 3eca745..7fb2926 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -17,6 +17,7 @@ endif
>
> obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
> obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
> +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
> obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
> obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
> obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
> diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
> new file mode 100644
> index 0000000..3912332
> --- /dev/null
> +++ b/drivers/spi/ath79_spi.c
> @@ -0,0 +1,230 @@
> +/*
> + * (C) Copyright 2015
> + * Wills Wang, <wills.wang@live.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <spi.h>
> +#include <dm.h>
> +#include <div64.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <asm/addrspace.h>
> +#include <asm/types.h>
> +#include <mach/ar71xx_regs.h>
> +
> +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
> +#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1)
> +#define ATH79_SPI_RRW_DELAY_FACTOR 12000
> +#define MHZ (1000 * 1000)
> +
> +struct ath79_spi_priv {
> + void __iomem *regs;
> + u32 rrw_delay;
> +};
> +
> +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + return readl(priv->regs + offset);
> +}
> +
> +static inline void ath79_spi_write(struct udevice *bus,
> + u32 val, u32 offset)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + writel(val, priv->regs + offset);
> +}
> +
> +static int ath79_spi_claim_bus(struct udevice *dev)
> +{
> + return 0;
> +}
> +
> +static int ath79_spi_release_bus(struct udevice *dev)
> +{
> + return 0;
> +}
> +
> +static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
> + const void *dout, void *din, unsigned long flags)
> +{
> + struct udevice *bus = dev->parent;
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
> + u8 *rx = din;
> + const u8 *tx = dout;
> + u8 curbyte, curbitlen, restbits;
> + u32 bytes = bitlen / 8;
> + u32 out, in;
> + u64 tick;
> +
> +
> + if (flags & SPI_XFER_BEGIN) {
> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
> + }
> +
> + restbits = (bitlen % 8);
> + if (restbits)
> + bytes++;
> +
> + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
> + while (bytes > 0) {
> + bytes--;
> + curbyte = 0;
> + if (tx)
> + curbyte = *tx++;
> +
> + if (restbits && !bytes) {
> + curbitlen = restbits;
> + curbyte <<= 8 - restbits;
> + } else {
> + curbitlen = 8;
> + }
> +
> + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
> + if (curbyte & 0x80)
> + out |= AR71XX_SPI_IOC_DO;
> + else
> + out &= ~(AR71XX_SPI_IOC_DO);
> +
> + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
> +
> + /* delay for low level */
> + if (priv->rrw_delay) {
> + tick = get_ticks() + priv->rrw_delay;
> + while (get_ticks() < tick)
> + /*NOP*/;
> + }
> +
> + ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK,
> + AR71XX_SPI_REG_IOC);
> +
> + /* delay for high level */
> + if (priv->rrw_delay) {
> + tick = get_ticks() + priv->rrw_delay;
> + while (get_ticks() < tick)
> + /*NOP*/;
> + }
> +
> + curbyte <<= 1;
> + }
> +
> + if (!bytes)
> + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
> +
> + in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
> + if (rx) {
> + if (restbits && !bytes)
> + *rx++ = (in << (8 - restbits));
> + else
> + *rx++ = in;
> + }
> + }
> +
> + if (flags & SPI_XFER_END) {
> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs),
> + AR71XX_SPI_REG_IOC);
> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
> + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
> + }
> +
> + return 0;
> +}
> +
> +
> +static int ath79_spi_set_speed(struct udevice *bus, uint speed)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + u32 val, div = 0;
> + u64 time;
> +
> + if (speed)
> + div = get_bus_freq(0) / speed;
> +
> + if (div > 63)
> + div = 63;
> +
> + if (div < 5)
> + div = 5;
> +
> + /* calculate delay */
> + time = get_tbclk();
> + do_div(time, speed / 2);
> + val = ATH79_SPI_RRW_DELAY_FACTOR / (get_bus_freq(0) / MHZ);
> + if (time > val)
> + priv->rrw_delay = time - val + 1;
> + else
> + priv->rrw_delay = 0;
> +
> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
> + val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL);
> + val &= ~AR71XX_SPI_CTRL_DIV_MASK;
> + val |= ATH79_SPI_CLK_DIV(div);
> + ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL);
> + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
> + return 0;
> +}
> +
> +static int ath79_spi_set_mode(struct udevice *bus, uint mode)
> +{
> + return 0;
> +}
> +
> +static int ath79_spi_probe(struct udevice *bus)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + fdt_addr_t addr;
> +
> + addr = dev_get_addr(bus);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + priv->regs = map_physmem(addr,
> + AR71XX_SPI_SIZE,
> + MAP_NOCACHE);
> +
> + /* Init SPI Hardware, disable remap, set clock */
> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
> + ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
> + AR71XX_SPI_REG_CTRL);
> + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
> +
> + return 0;
> +}
> +
> +static int ath79_cs_info(struct udevice *bus, uint cs,
> + struct spi_cs_info *info)
> +{
> + /* Always allow activity on CS 0/1/2 */
> + if (cs >= 3)
> + return -ENODEV;
> +
> + return 0;
> +}
> +
> +static const struct dm_spi_ops ath79_spi_ops = {
> + .claim_bus = ath79_spi_claim_bus,
> + .release_bus = ath79_spi_release_bus,
> + .xfer = ath79_spi_xfer,
> + .set_speed = ath79_spi_set_speed,
> + .set_mode = ath79_spi_set_mode,
> + .cs_info = ath79_cs_info,
> +};
> +
> +static const struct udevice_id ath79_spi_ids[] = {
> + { .compatible = "qca,ar7100-spi" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(ath79_spi) = {
> + .name = "ath79_spi",
> + .id = UCLASS_SPI,
> + .of_match = ath79_spi_ids,
> + .ops = &ath79_spi_ops,
> + .priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
> + .probe = ath79_spi_probe,
> +};
>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
Best regards,
Thomas
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 08/10] mips: ath79: add spi driver
2016-01-04 11:14 ` [U-Boot] [PATCH v6 08/10] mips: ath79: add spi driver Wills Wang
2016-01-05 2:51 ` Thomas Chou
@ 2016-01-06 12:16 ` Jagan Teki
2016-01-09 17:51 ` Wills Wang
1 sibling, 1 reply; 25+ messages in thread
From: Jagan Teki @ 2016-01-06 12:16 UTC (permalink / raw)
To: u-boot
On 4 January 2016 at 16:44, Wills Wang <wills.wang@live.com> wrote:
> Signed-off-by: Wills Wang <wills.wang@live.com>
> ---
>
> Changes in v6:
> - Add rrw_delay in ath79_spi_priv for more accurate timing
> - Remove ath79_spi_delay
> - Calculate delay in ath79_spi_set_speed
>
> Changes in v5:
> - remove ar933x_spi_platdata
> - Import document "spi-ath79.txt" from kernel
> - Add delay for bitbang operation
>
> Changes in v4:
> - Use get_bus_freq instead of hardcode in SPI driver
>
> Changes in v3:
> - Convert spi driver to driver model
> - Same code style convertion
>
> Changes in v2:
> - Add a compatible spi driver
>
> doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/ath79_spi.c | 230 +++++++++++++++++++++++++++++
> 4 files changed, 258 insertions(+)
> create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt
> create mode 100644 drivers/spi/ath79_spi.c
>
> diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt
> new file mode 100644
> index 0000000..3fd9d67
> --- /dev/null
> +++ b/doc/device-tree-bindings/spi/spi-ath79.txt
> @@ -0,0 +1,19 @@
> +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
> +
> +Required properties:
> +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
> +- reg: Base address and size of the controllers memory area
> +- #address-cells: <1>, as required by generic SPI binding.
> +- #size-cells: <0>, also as required by generic SPI binding.
> +
> +Child nodes as per the generic SPI binding.
> +
> +Example:
> +
> + spi at 1f000000 {
> + compatible = "qca,ar9132-spi", "qca,ar7100-spi";
> + reg = <0x1f000000 0x10>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 2cdb110..0ab2741 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -23,6 +23,14 @@ config ALTERA_SPI
> IP core. Please find details on the "Embedded Peripherals IP
> User Guide" of Altera.
>
> +config ATH79_SPI
> + bool "Atheros SPI driver"
> + help
> + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
> + to access SPI NOR flash and other SPI peripherals. This driver
> + uses driver model and requires a device tree binding to operate.
> + please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
> +
> config CADENCE_QSPI
> bool "Cadence QSPI driver"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 3eca745..7fb2926 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -17,6 +17,7 @@ endif
>
> obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
> obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
> +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
> obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
> obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
> obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
> diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
> new file mode 100644
> index 0000000..3912332
> --- /dev/null
> +++ b/drivers/spi/ath79_spi.c
> @@ -0,0 +1,230 @@
> +/*
> + * (C) Copyright 2015
> + * Wills Wang, <wills.wang@live.com>
Append this above the line with space.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <spi.h>
> +#include <dm.h>
> +#include <div64.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <asm/addrspace.h>
> +#include <asm/types.h>
> +#include <mach/ar71xx_regs.h>
Does this regs common for ar71xx or for spi?
> +
> +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
> +#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1)
> +#define ATH79_SPI_RRW_DELAY_FACTOR 12000
> +#define MHZ (1000 * 1000)
Rename MHZ to ATH79_SPI_MHZ or similar
> +
> +struct ath79_spi_priv {
> + void __iomem *regs;
> + u32 rrw_delay;
> +};
> +
> +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + return readl(priv->regs + offset);
> +}
> +
> +static inline void ath79_spi_write(struct udevice *bus,
> + u32 val, u32 offset)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + writel(val, priv->regs + offset);
> +}
Instead of adding these new read|write calls, use readl and writel
directly since we can get bus any where using dev
> +
> +static int ath79_spi_claim_bus(struct udevice *dev)
> +{
> + return 0;
> +}
> +
> +static int ath79_spi_release_bus(struct udevice *dev)
> +{
> + return 0;
> +}
> +
> +static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
> + const void *dout, void *din, unsigned long flags)
> +{
> + struct udevice *bus = dev->parent;
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
> + u8 *rx = din;
> + const u8 *tx = dout;
> + u8 curbyte, curbitlen, restbits;
> + u32 bytes = bitlen / 8;
> + u32 out, in;
> + u64 tick;
> +
> +
> + if (flags & SPI_XFER_BEGIN) {
> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
Move this code to local spi_cs_activate and use clrbits_xxx or
setbits_xxxx if required for just to activate or deactivate specific
bits.
> + }
> +
> + restbits = (bitlen % 8);
> + if (restbits)
> + bytes++;
> +
> + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
> + while (bytes > 0) {
> + bytes--;
> + curbyte = 0;
> + if (tx)
> + curbyte = *tx++;
> +
> + if (restbits && !bytes) {
> + curbitlen = restbits;
> + curbyte <<= 8 - restbits;
> + } else {
> + curbitlen = 8;
> + }
> +
> + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
> + if (curbyte & 0x80)
> + out |= AR71XX_SPI_IOC_DO;
> + else
> + out &= ~(AR71XX_SPI_IOC_DO);
> +
> + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
> +
> + /* delay for low level */
> + if (priv->rrw_delay) {
> + tick = get_ticks() + priv->rrw_delay;
> + while (get_ticks() < tick)
> + /*NOP*/;
> + }
> +
> + ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK,
> + AR71XX_SPI_REG_IOC);
> +
> + /* delay for high level */
> + if (priv->rrw_delay) {
> + tick = get_ticks() + priv->rrw_delay;
> + while (get_ticks() < tick)
> + /*NOP*/;
Better to do timeout check instead of infinite while.
> + }
> +
> + curbyte <<= 1;
> + }
> +
> + if (!bytes)
> + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
> +
> + in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
> + if (rx) {
> + if (restbits && !bytes)
> + *rx++ = (in << (8 - restbits));
> + else
> + *rx++ = in;
> + }
> + }
> +
> + if (flags & SPI_XFER_END) {
> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs),
> + AR71XX_SPI_REG_IOC);
> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
> + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
Same as above use spi_cs_deactivate
> + }
> +
> + return 0;
> +}
> +
> +
> +static int ath79_spi_set_speed(struct udevice *bus, uint speed)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + u32 val, div = 0;
> + u64 time;
> +
> + if (speed)
> + div = get_bus_freq(0) / speed;
> +
> + if (div > 63)
> + div = 63;
> +
> + if (div < 5)
> + div = 5;
Where are these div comparisons? please add clear short comment.
> +
> + /* calculate delay */
> + time = get_tbclk();
> + do_div(time, speed / 2);
> + val = ATH79_SPI_RRW_DELAY_FACTOR / (get_bus_freq(0) / MHZ);
> + if (time > val)
> + priv->rrw_delay = time - val + 1;
> + else
> + priv->rrw_delay = 0;
> +
> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
> + val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL);
> + val &= ~AR71XX_SPI_CTRL_DIV_MASK;
> + val |= ATH79_SPI_CLK_DIV(div);
> + ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL);
> + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
This write also for speed setting, does this function doing other than
speed_setup?
> + return 0;
> +}
> +
> +static int ath79_spi_set_mode(struct udevice *bus, uint mode)
> +{
> + return 0;
> +}
> +
> +static int ath79_spi_probe(struct udevice *bus)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + fdt_addr_t addr;
> +
> + addr = dev_get_addr(bus);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + priv->regs = map_physmem(addr,
> + AR71XX_SPI_SIZE,
> + MAP_NOCACHE);
> +
> + /* Init SPI Hardware, disable remap, set clock */
> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
> + ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
> + AR71XX_SPI_REG_CTRL);
> + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
> +
> + return 0;
> +}
> +
> +static int ath79_cs_info(struct udevice *bus, uint cs,
> + struct spi_cs_info *info)
> +{
> + /* Always allow activity on CS 0/1/2 */
> + if (cs >= 3)
> + return -ENODEV;
> +
> + return 0;
> +}
> +
> +static const struct dm_spi_ops ath79_spi_ops = {
> + .claim_bus = ath79_spi_claim_bus,
> + .release_bus = ath79_spi_release_bus,
> + .xfer = ath79_spi_xfer,
> + .set_speed = ath79_spi_set_speed,
> + .set_mode = ath79_spi_set_mode,
> + .cs_info = ath79_cs_info,
> +};
> +
> +static const struct udevice_id ath79_spi_ids[] = {
> + { .compatible = "qca,ar7100-spi" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(ath79_spi) = {
> + .name = "ath79_spi",
> + .id = UCLASS_SPI,
> + .of_match = ath79_spi_ids,
> + .ops = &ath79_spi_ops,
> + .priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
> + .probe = ath79_spi_probe,
> +};
> --
thanks!
--
Jagan.
^ permalink raw reply [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 08/10] mips: ath79: add spi driver
2016-01-06 12:16 ` Jagan Teki
@ 2016-01-09 17:51 ` Wills Wang
0 siblings, 0 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-09 17:51 UTC (permalink / raw)
To: u-boot
On 01/06/2016 08:16 PM, Jagan Teki wrote:
> On 4 January 2016 at 16:44, Wills Wang <wills.wang@live.com> wrote:
>> Signed-off-by: Wills Wang <wills.wang@live.com>
>> ---
>>
>> Changes in v6:
>> - Add rrw_delay in ath79_spi_priv for more accurate timing
>> - Remove ath79_spi_delay
>> - Calculate delay in ath79_spi_set_speed
>>
>> Changes in v5:
>> - remove ar933x_spi_platdata
>> - Import document "spi-ath79.txt" from kernel
>> - Add delay for bitbang operation
>>
>> Changes in v4:
>> - Use get_bus_freq instead of hardcode in SPI driver
>>
>> Changes in v3:
>> - Convert spi driver to driver model
>> - Same code style convertion
>>
>> Changes in v2:
>> - Add a compatible spi driver
>>
>> doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++
>> drivers/spi/Kconfig | 8 +
>> drivers/spi/Makefile | 1 +
>> drivers/spi/ath79_spi.c | 230 +++++++++++++++++++++++++++++
>> 4 files changed, 258 insertions(+)
>> create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt
>> create mode 100644 drivers/spi/ath79_spi.c
>>
>> diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt
>> new file mode 100644
>> index 0000000..3fd9d67
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/spi/spi-ath79.txt
>> @@ -0,0 +1,19 @@
>> +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
>> +
>> +Required properties:
>> +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
>> +- reg: Base address and size of the controllers memory area
>> +- #address-cells: <1>, as required by generic SPI binding.
>> +- #size-cells: <0>, also as required by generic SPI binding.
>> +
>> +Child nodes as per the generic SPI binding.
>> +
>> +Example:
>> +
>> + spi at 1f000000 {
>> + compatible = "qca,ar9132-spi", "qca,ar7100-spi";
>> + reg = <0x1f000000 0x10>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> index 2cdb110..0ab2741 100644
>> --- a/drivers/spi/Kconfig
>> +++ b/drivers/spi/Kconfig
>> @@ -23,6 +23,14 @@ config ALTERA_SPI
>> IP core. Please find details on the "Embedded Peripherals IP
>> User Guide" of Altera.
>>
>> +config ATH79_SPI
>> + bool "Atheros SPI driver"
>> + help
>> + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
>> + to access SPI NOR flash and other SPI peripherals. This driver
>> + uses driver model and requires a device tree binding to operate.
>> + please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
>> +
>> config CADENCE_QSPI
>> bool "Cadence QSPI driver"
>> help
>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>> index 3eca745..7fb2926 100644
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>> @@ -17,6 +17,7 @@ endif
>>
>> obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
>> obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
>> +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
>> obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>> obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
>> obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
>> diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
>> new file mode 100644
>> index 0000000..3912332
>> --- /dev/null
>> +++ b/drivers/spi/ath79_spi.c
>> @@ -0,0 +1,230 @@
>> +/*
>> + * (C) Copyright 2015
>> + * Wills Wang, <wills.wang@live.com>
> Append this above the line with space.
Where?
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <spi.h>
>> +#include <dm.h>
>> +#include <div64.h>
>> +#include <errno.h>
>> +#include <asm/io.h>
>> +#include <asm/addrspace.h>
>> +#include <asm/types.h>
>> +#include <mach/ar71xx_regs.h>
> Does this regs common for ar71xx or for spi?
Yes
>> +
>> +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
>> +#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1)
>> +#define ATH79_SPI_RRW_DELAY_FACTOR 12000
>> +#define MHZ (1000 * 1000)
> Rename MHZ to ATH79_SPI_MHZ or similar
Ok.
>> +
>> +struct ath79_spi_priv {
>> + void __iomem *regs;
>> + u32 rrw_delay;
>> +};
>> +
>> +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
>> +{
>> + struct ath79_spi_priv *priv = dev_get_priv(bus);
>> + return readl(priv->regs + offset);
>> +}
>> +
>> +static inline void ath79_spi_write(struct udevice *bus,
>> + u32 val, u32 offset)
>> +{
>> + struct ath79_spi_priv *priv = dev_get_priv(bus);
>> + writel(val, priv->regs + offset);
>> +}
> Instead of adding these new read|write calls, use readl and writel
> directly since we can get bus any where using dev
>
There is an inline function.
>> +
>> +static int ath79_spi_claim_bus(struct udevice *dev)
>> +{
>> + return 0;
>> +}
>> +
>> +static int ath79_spi_release_bus(struct udevice *dev)
>> +{
>> + return 0;
>> +}
>> +
>> +static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
>> + const void *dout, void *din, unsigned long flags)
>> +{
>> + struct udevice *bus = dev->parent;
>> + struct ath79_spi_priv *priv = dev_get_priv(bus);
>> + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
>> + u8 *rx = din;
>> + const u8 *tx = dout;
>> + u8 curbyte, curbitlen, restbits;
>> + u32 bytes = bitlen / 8;
>> + u32 out, in;
>> + u64 tick;
>> +
>> +
>> + if (flags & SPI_XFER_BEGIN) {
>> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
>> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
> Move this code to local spi_cs_activate and use clrbits_xxx or
> setbits_xxxx if required for just to activate or deactivate specific
> bits.
Ok.
>> + }
>> +
>> + restbits = (bitlen % 8);
>> + if (restbits)
>> + bytes++;
>> +
>> + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
>> + while (bytes > 0) {
>> + bytes--;
>> + curbyte = 0;
>> + if (tx)
>> + curbyte = *tx++;
>> +
>> + if (restbits && !bytes) {
>> + curbitlen = restbits;
>> + curbyte <<= 8 - restbits;
>> + } else {
>> + curbitlen = 8;
>> + }
>> +
>> + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
>> + if (curbyte & 0x80)
>> + out |= AR71XX_SPI_IOC_DO;
>> + else
>> + out &= ~(AR71XX_SPI_IOC_DO);
>> +
>> + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
>> +
>> + /* delay for low level */
>> + if (priv->rrw_delay) {
>> + tick = get_ticks() + priv->rrw_delay;
>> + while (get_ticks() < tick)
>> + /*NOP*/;
>> + }
>> +
>> + ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK,
>> + AR71XX_SPI_REG_IOC);
>> +
>> + /* delay for high level */
>> + if (priv->rrw_delay) {
>> + tick = get_ticks() + priv->rrw_delay;
>> + while (get_ticks() < tick)
>> + /*NOP*/;
> Better to do timeout check instead of infinite while.
I think it is a timeout check.
>> + }
>> +
>> + curbyte <<= 1;
>> + }
>> +
>> + if (!bytes)
>> + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
>> +
>> + in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
>> + if (rx) {
>> + if (restbits && !bytes)
>> + *rx++ = (in << (8 - restbits));
>> + else
>> + *rx++ = in;
>> + }
>> + }
>> +
>> + if (flags & SPI_XFER_END) {
>> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs),
>> + AR71XX_SPI_REG_IOC);
>> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
>> + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
> Same as above use spi_cs_deactivate
>
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +
>> +static int ath79_spi_set_speed(struct udevice *bus, uint speed)
>> +{
>> + struct ath79_spi_priv *priv = dev_get_priv(bus);
>> + u32 val, div = 0;
>> + u64 time;
>> +
>> + if (speed)
>> + div = get_bus_freq(0) / speed;
>> +
>> + if (div > 63)
>> + div = 63;
>> +
>> + if (div < 5)
>> + div = 5;
> Where are these div comparisons? please add clear short comment.
The lower limitation is an empirical value, upper limitation is the
maximum value for register filed.
>> +
>> + /* calculate delay */
>> + time = get_tbclk();
>> + do_div(time, speed / 2);
>> + val = ATH79_SPI_RRW_DELAY_FACTOR / (get_bus_freq(0) / MHZ);
>> + if (time > val)
>> + priv->rrw_delay = time - val + 1;
>> + else
>> + priv->rrw_delay = 0;
>> +
>> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
>> + val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL);
>> + val &= ~AR71XX_SPI_CTRL_DIV_MASK;
>> + val |= ATH79_SPI_CLK_DIV(div);
>> + ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL);
>> + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
> This write also for speed setting, does this function doing other than
> speed_setup?
>
Calculate SPI bitbang delay according to speed.
>> + return 0;
>> +}
>> +
>> +static int ath79_spi_set_mode(struct udevice *bus, uint mode)
>> +{
>> + return 0;
>> +}
>> +
>> +static int ath79_spi_probe(struct udevice *bus)
>> +{
>> + struct ath79_spi_priv *priv = dev_get_priv(bus);
>> + fdt_addr_t addr;
>> +
>> + addr = dev_get_addr(bus);
>> + if (addr == FDT_ADDR_T_NONE)
>> + return -EINVAL;
>> +
>> + priv->regs = map_physmem(addr,
>> + AR71XX_SPI_SIZE,
>> + MAP_NOCACHE);
>> +
>> + /* Init SPI Hardware, disable remap, set clock */
>> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
>> + ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
>> + AR71XX_SPI_REG_CTRL);
>> + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
>> +
>> + return 0;
>> +}
>> +
>> +static int ath79_cs_info(struct udevice *bus, uint cs,
>> + struct spi_cs_info *info)
>> +{
>> + /* Always allow activity on CS 0/1/2 */
>> + if (cs >= 3)
>> + return -ENODEV;
>> +
>> + return 0;
>> +}
>> +
>> +static const struct dm_spi_ops ath79_spi_ops = {
>> + .claim_bus = ath79_spi_claim_bus,
>> + .release_bus = ath79_spi_release_bus,
>> + .xfer = ath79_spi_xfer,
>> + .set_speed = ath79_spi_set_speed,
>> + .set_mode = ath79_spi_set_mode,
>> + .cs_info = ath79_cs_info,
>> +};
>> +
>> +static const struct udevice_id ath79_spi_ids[] = {
>> + { .compatible = "qca,ar7100-spi" },
>> + {}
>> +};
>> +
>> +U_BOOT_DRIVER(ath79_spi) = {
>> + .name = "ath79_spi",
>> + .id = UCLASS_SPI,
>> + .of_match = ath79_spi_ids,
>> + .ops = &ath79_spi_ops,
>> + .priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
>> + .probe = ath79_spi_probe,
>> +};
>> --
> thanks!
--
Best Regards
Wills
^ permalink raw reply [flat|nested] 25+ messages in thread
* [U-Boot] [PATCH v6 09/10] mips: ath79: add AP121 reference board
[not found] <1451906101-9801-2-git-send-email-wills.wang@live.com>
` (6 preceding siblings ...)
2016-01-04 11:14 ` [U-Boot] [PATCH v6 08/10] mips: ath79: add spi driver Wills Wang
@ 2016-01-04 11:15 ` Wills Wang
2016-01-04 11:15 ` [U-Boot] [PATCH v6 10/10] mips: ath79: add AP143 " Wills Wang
8 siblings, 0 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-04 11:15 UTC (permalink / raw)
To: u-boot
Signed-off-by: Wills Wang <wills.wang@live.com>
---
Changes in v6:
- Convert SZ_XXX into hex in ap121.h
- Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
- Add board_early_init_f for DDR and pin initialization
- Select UART and SPI in ap121_defconfig
Changes in v5:
- Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk
- Remove useless README file
- Remove useless checkboard function
Changes in v4: None
Changes in v3:
- Add support for device tree
Changes in v2:
- Add a reference board implemention
arch/mips/dts/Makefile | 2 +-
arch/mips/dts/ap121.dts | 37 ++++++++++++++++++++
arch/mips/dts/ar933x.dtsi | 64 ++++++++++++++++++++++++++++++++++
arch/mips/mach-ath79/Kconfig | 11 ++++++
board/ath79/ap121/Kconfig | 9 +++++
board/ath79/ap121/MAINTAINERS | 6 ++++
board/ath79/ap121/Makefile | 5 +++
board/ath79/ap121/ap121.c | 48 +++++++++++++++++++++++++
configs/ap121_defconfig | 42 ++++++++++++++++++++++
include/configs/ap121.h | 81 +++++++++++++++++++++++++++++++++++++++++++
10 files changed, 304 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/dts/ap121.dts
create mode 100644 arch/mips/dts/ar933x.dtsi
create mode 100644 board/ath79/ap121/Kconfig
create mode 100644 board/ath79/ap121/MAINTAINERS
create mode 100644 board/ath79/ap121/Makefile
create mode 100644 board/ath79/ap121/ap121.c
create mode 100644 configs/ap121_defconfig
create mode 100644 include/configs/ap121.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 47b6eb5..3fd49eb 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-dtb-y +=
+dtb-$(CONFIG_BOARD_AP121) += ap121.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
new file mode 100644
index 0000000..f7c3a1a
--- /dev/null
+++ b/arch/mips/dts/ap121.dts
@@ -0,0 +1,37 @@
+/dts-v1/;
+#include "ar933x.dtsi"
+
+/ {
+ model = "AP121 Reference Board";
+ compatible = "qca,ap121", "qca,ar933x";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&xtal {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ spi-max-frequency = <25000000>;
+ status = "okay";
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ memory-map = <0x9f000000 0x00800000>;
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
new file mode 100644
index 0000000..05cc165
--- /dev/null
+++ b/arch/mips/dts/ar933x.dtsi
@@ -0,0 +1,64 @@
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "qca,ar933x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "mips,mips24Kc";
+ reg = <0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ apb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at 18020000 {
+ compatible = "qca,ar9330-uart";
+ reg = <0x18020000 0x20>;
+
+ status = "disabled";
+ };
+ };
+
+ spi0: spi at 1f000000 {
+ compatible = "qca,ar7100-spi";
+ reg = <0x1f000000 0x10>;
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index f7801e4..0fcd96a 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -27,4 +27,15 @@ config SOC_QCA953X
help
This supports QCA/Atheros qca953x family SOCs.
+choice
+ prompt "Board select"
+
+config BOARD_AP121
+ bool "AP121 Reference Board"
+ select SOC_AR933X
+
+endchoice
+
+source "board/ath79/ap121/Kconfig"
+
endmenu
diff --git a/board/ath79/ap121/Kconfig b/board/ath79/ap121/Kconfig
new file mode 100644
index 0000000..ec72914
--- /dev/null
+++ b/board/ath79/ap121/Kconfig
@@ -0,0 +1,9 @@
+if BOARD_AP121
+
+config SYS_BOARD
+ default "ap121"
+
+config SYS_CONFIG_NAME
+ default "ap121"
+
+endif
diff --git a/board/ath79/ap121/MAINTAINERS b/board/ath79/ap121/MAINTAINERS
new file mode 100644
index 0000000..319b521
--- /dev/null
+++ b/board/ath79/ap121/MAINTAINERS
@@ -0,0 +1,6 @@
+AP121 BOARD
+M: Wills Wang <wills.wang@live.com>
+S: Maintained
+F: board/ath79/ap121/
+F: include/configs/ap121.h
+F: configs/ap121_defconfig
diff --git a/board/ath79/ap121/Makefile b/board/ath79/ap121/Makefile
new file mode 100644
index 0000000..ced5432
--- /dev/null
+++ b/board/ath79/ap121/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ap121.o
diff --git a/board/ath79/ap121/ap121.c b/board/ath79/ap121/ap121.c
new file mode 100644
index 0000000..901b09a
--- /dev/null
+++ b/board/ath79/ap121/ap121.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ void __iomem *regs;
+ u32 val;
+
+ regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+ MAP_NOCACHE);
+
+ /*
+ * GPIO9 as input, GPIO10 as output
+ */
+ val = readl(regs + AR71XX_GPIO_REG_OE);
+ val &= ~AR933X_GPIO(9);
+ val |= AR933X_GPIO(10);
+ writel(val, regs + AR71XX_GPIO_REG_OE);
+
+ /*
+ * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
+ */
+ val = readl(regs + AR71XX_GPIO_REG_FUNC);
+ val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
+ writel(val, regs + AR71XX_GPIO_REG_FUNC);
+
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ ddr_init();
+ return 0;
+}
+#endif
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
new file mode 100644
index 0000000..d928ba8
--- /dev/null
+++ b/configs/ap121_defconfig
@@ -0,0 +1,42 @@
+CONFIG_MIPS=y
+CONFIG_ARCH_ATH79=y
+CONFIG_BOARD_AP121=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_AR933X_UART=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATH79_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="ap121"
+CONFIG_SYS_PROMPT="ap121 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_AR933X=y
+CONFIG_DEBUG_UART_BASE=0x18020000
+CONFIG_DEBUG_UART_CLOCK=25000000
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
new file mode 100644
index 0000000..04a80e7
--- /dev/null
+++ b/include/configs/ap121.h
@@ -0,0 +1,81 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x9f000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_MHZ 200
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE 0x8000
+#define CONFIG_SYS_ICACHE_SIZE 0x10000
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN 0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_LOAD_ADDR 0x81000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock2 " \
+ "rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND "sf probe;" \
+ "mtdparts default;" \
+ "bootm 0x9f300000"
+#define CONFIG_LZMA
+#define CONFIG_OF_LIBFDT
+
+#define MTDIDS_DEFAULT "nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
+ "256k(u-boot),64k(u-boot-env)," \
+ "2752k(rootfs),896k(uImage)," \
+ "64k(NVRAM),64k(ART)"
+
+#define CONFIG_ENV_SPI_MAX_HZ 25000000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_SIZE 0x10000
+
+/*
+ * Command
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [U-Boot] [PATCH v6 10/10] mips: ath79: add AP143 reference board
[not found] <1451906101-9801-2-git-send-email-wills.wang@live.com>
` (7 preceding siblings ...)
2016-01-04 11:15 ` [U-Boot] [PATCH v6 09/10] mips: ath79: add AP121 reference board Wills Wang
@ 2016-01-04 11:15 ` Wills Wang
8 siblings, 0 replies; 25+ messages in thread
From: Wills Wang @ 2016-01-04 11:15 UTC (permalink / raw)
To: u-boot
Signed-off-by: Wills Wang <wills.wang@live.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/mips/dts/Makefile | 1 +
arch/mips/dts/ap143.dts | 37 +++++++++++++++++++
arch/mips/dts/qca953x.dtsi | 66 +++++++++++++++++++++++++++++++++
arch/mips/mach-ath79/Kconfig | 5 +++
board/ath79/ap143/Kconfig | 9 +++++
board/ath79/ap143/MAINTAINERS | 6 +++
board/ath79/ap143/Makefile | 5 +++
board/ath79/ap143/ap143.c | 64 ++++++++++++++++++++++++++++++++
configs/ap143_defconfig | 43 ++++++++++++++++++++++
include/configs/ap143.h | 86 +++++++++++++++++++++++++++++++++++++++++++
10 files changed, 322 insertions(+)
create mode 100644 arch/mips/dts/ap143.dts
create mode 100644 arch/mips/dts/qca953x.dtsi
create mode 100644 board/ath79/ap143/Kconfig
create mode 100644 board/ath79/ap143/MAINTAINERS
create mode 100644 board/ath79/ap143/Makefile
create mode 100644 board/ath79/ap143/ap143.c
create mode 100644 configs/ap143_defconfig
create mode 100644 include/configs/ap143.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 3fd49eb..7da06c5 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -3,6 +3,7 @@
#
dtb-$(CONFIG_BOARD_AP121) += ap121.dtb
+dtb-$(CONFIG_BOARD_AP143) += ap143.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts
new file mode 100644
index 0000000..2133232
--- /dev/null
+++ b/arch/mips/dts/ap143.dts
@@ -0,0 +1,37 @@
+/dts-v1/;
+#include "qca953x.dtsi"
+
+/ {
+ model = "AP143 Reference Board";
+ compatible = "qca,ap143", "qca,qca953x";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&xtal {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ spi-max-frequency = <25000000>;
+ status = "okay";
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ memory-map = <0x9f000000 0x00800000>;
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi
new file mode 100644
index 0000000..9cec6be
--- /dev/null
+++ b/arch/mips/dts/qca953x.dtsi
@@ -0,0 +1,66 @@
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "qca,qca953x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "mips,mips24Kc";
+ reg = <0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ apb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at 18020000 {
+ compatible = "ns16550";
+ reg = <0x18020000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+
+ status = "disabled";
+ };
+ };
+
+ spi0: spi at 1f000000 {
+ compatible = "qca,ar7100-spi";
+ reg = <0x1f000000 0x10>;
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 0fcd96a..f61efd2 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -34,8 +34,13 @@ config BOARD_AP121
bool "AP121 Reference Board"
select SOC_AR933X
+config BOARD_AP143
+ bool "AP143 Reference Board"
+ select SOC_QCA953X
+
endchoice
source "board/ath79/ap121/Kconfig"
+source "board/ath79/ap143/Kconfig"
endmenu
diff --git a/board/ath79/ap143/Kconfig b/board/ath79/ap143/Kconfig
new file mode 100644
index 0000000..118b9b5
--- /dev/null
+++ b/board/ath79/ap143/Kconfig
@@ -0,0 +1,9 @@
+if BOARD_AP143
+
+config SYS_BOARD
+ default "ap143"
+
+config SYS_CONFIG_NAME
+ default "ap143"
+
+endif
diff --git a/board/ath79/ap143/MAINTAINERS b/board/ath79/ap143/MAINTAINERS
new file mode 100644
index 0000000..d373cf8
--- /dev/null
+++ b/board/ath79/ap143/MAINTAINERS
@@ -0,0 +1,6 @@
+AP143 BOARD
+M: Wills Wang <wills.wang@live.com>
+S: Maintained
+F: board/ath79/ap143/
+F: include/configs/ap143.h
+F: configs/ap143_defconfig
diff --git a/board/ath79/ap143/Makefile b/board/ath79/ap143/Makefile
new file mode 100644
index 0000000..00f7837
--- /dev/null
+++ b/board/ath79/ap143/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ap143.o
diff --git a/board/ath79/ap143/ap143.c b/board/ath79/ap143/ap143.c
new file mode 100644
index 0000000..d1dd2eb
--- /dev/null
+++ b/board/ath79/ap143/ap143.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ void __iomem *regs;
+ u32 val;
+
+ regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+ MAP_NOCACHE);
+
+ /*
+ * GPIO9 as input, GPIO10 as output
+ */
+ val = readl(regs + AR71XX_GPIO_REG_OE);
+ val |= QCA953X_GPIO(9);
+ val &= ~QCA953X_GPIO(10);
+ writel(val, regs + AR71XX_GPIO_REG_OE);
+
+ /*
+ * Enable GPIO10 as UART0_SOUT
+ */
+ val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
+ val &= ~QCA953X_GPIO_OUT_MUX_MASK(16);
+ val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
+ writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
+
+ /*
+ * Enable GPIO9 as UART0_SIN
+ */
+ val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
+ val &= ~QCA953X_GPIO_OUT_MUX_MASK(8);
+ val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
+ writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
+
+ /*
+ * Enable GPIO10 output
+ */
+ val = readl(regs + AR71XX_GPIO_REG_OUT);
+ val |= QCA953X_GPIO(10);
+ writel(val, regs + AR71XX_GPIO_REG_OUT);
+
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ ddr_init();
+ return 0;
+}
+#endif
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
new file mode 100644
index 0000000..07a4816
--- /dev/null
+++ b/configs/ap143_defconfig
@@ -0,0 +1,43 @@
+CONFIG_MIPS=y
+CONFIG_ARCH_ATH79=y
+CONFIG_BOARD_AP143=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATH79_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="ap143"
+CONFIG_SYS_PROMPT="ap121 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_NS16550=y
+CONFIG_DEBUG_UART_BASE=0x18020000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_SHIFT=2
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
new file mode 100644
index 0000000..8bf5e40
--- /dev/null
+++ b/include/configs/ap143.h
@@ -0,0 +1,86 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x9f000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_MHZ 325
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE 0x8000
+#define CONFIG_SYS_ICACHE_SIZE 0x10000
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN 0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_LOAD_ADDR 0x81000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK 25000000
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock2 " \
+ "rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND "sf probe;" \
+ "mtdparts default;" \
+ "bootm 0x9f300000"
+#define CONFIG_LZMA
+#define CONFIG_OF_LIBFDT
+
+#define MTDIDS_DEFAULT "nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
+ "256k(u-boot),64k(u-boot-env)," \
+ "2752k(rootfs),896k(uImage)," \
+ "64k(NVRAM),64k(ART)"
+
+#define CONFIG_ENV_SPI_MAX_HZ 25000000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_SIZE 0x10000
+
+/*
+ * Command
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#endif /* __CONFIG_H */
--
1.9.1
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