[U-Boot] [PATCH v3 1/5] sunxi: R40: add gigabit ethernet clocks

[U-Boot] [PATCH v3 1/5] sunxi: R40: add gigabit ethernet clocks

[Lothar Felten]

Add clock control entries for the gigabit interface of the Allwinner
R40/V40 CPU

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d35aa479f7..3ea473c302 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -61,7 +61,11 @@ struct sunxi_ccm_reg {
 	u32 reserved11;
 	u32 sata_clk_cfg;	/* 0xc8 SATA clock control (R40 only) */
 	u32 usb_clk_cfg;	/* 0xcc USB clock control */
-	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
+#ifdef CONFIG_MACH_SUN8I_R40
+	u32 cir0_clk_cfg;	/* 0xd0 CIR0 clock control (R40 only) */
+#else
+	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control (not for R40) */
+#endif
 	u32 reserved12[7];
 	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
 	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
@@ -104,7 +108,11 @@ struct sunxi_ccm_reg {
 	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
 	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
 	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
+#ifdef CONFIG_MACH_SUN8I_R40
+	u32 gmac_clk_cfg;	/* 0x164 GMAC clock control (R40 only) */
+#else
 	u32 reserved16;
+#endif
 	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
 	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
 	u32 reserved17[4];
-- 
2.14.1

[U-Boot] [PATCH v3 2/5] net: sun8i-emac: support R40 GMAC

[Lothar Felten]

Add support for the GMAC found in the Allwinner R40/V40 SoC.

The R40 GMAC interface is not controlled by the syscon register but
has a separate configuration register in the CCU.
The clock gate and reset bits are in a different register compared
to the other SoCs supported by this driver.
The diver uses the -gmac suffix for the R40 because the R40 also
has a different 100 MBit MAC (EMAC).

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
---
 drivers/net/sun8i_emac.c | 69 +++++++++++++++++++++++++++++++++---------------
 1 file changed, 47 insertions(+), 22 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index b6e5dafe83..83844a1d40 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -68,6 +68,8 @@
 
 #if defined(CONFIG_MACH_SUNXI_H3_H5)
 #define SUN8I_GPD8_GMAC		2
+#elif defined(CONFIG_MACH_SUN8I_R40)
+#define SUN8I_GPD8_GMAC		5
 #else
 #define SUN8I_GPD8_GMAC		4
 #endif
@@ -99,6 +101,7 @@ DECLARE_GLOBAL_DATA_PTR;
 enum emac_variant {
 	A83T_EMAC = 1,
 	H3_EMAC,
+	R40_GMAC,
 	A64_EMAC,
 };
 
@@ -279,6 +282,9 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
 	int ret;
 	u32 reg;
 
+	if (priv->variant == R40_GMAC)
+		return 0;
+
 	reg = readl(priv->sysctl_reg + 0x30);
 
 	if (priv->variant == H3_EMAC) {
@@ -630,11 +636,25 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 	}
 #endif
 
+#ifdef CONFIG_MACH_SUN8I_R40
+	/* Set clock gating for emac */
+	setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
+
+	/* De-assert EMAC */
+	setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
+
+	/* Select RGMII for R40 */
+	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+		CCM_GMAC_CTRL_GPIT_RGMII);
+	setbits_le32(&ccm->gmac_clk_cfg,
+		     CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
+#else
 	/* Set clock gating for emac */
 	setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
 
 	/* De-assert EMAC */
 	setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
+#endif
 }
 
 #if defined(CONFIG_DM_GPIO)
@@ -801,22 +821,33 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
-	if (offset < 0) {
-		debug("%s: cannot find syscon node\n", __func__);
-		return -EINVAL;
-	}
-	reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
-	if (!reg) {
-		debug("%s: cannot find reg property in syscon node\n",
-		      __func__);
+	priv->variant = dev_get_driver_data(dev);
+
+	if (!priv->variant) {
+		printf("%s: Missing variant '%s'\n", __func__,
+		       (char *)priv->variant);
 		return -EINVAL;
 	}
-	priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
-						 offset, reg);
-	if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
-		debug("%s: Cannot find syscon base address\n", __func__);
-		return -EINVAL;
+
+	if (priv->variant != R40_GMAC) {
+		offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+		if (offset < 0) {
+			debug("%s: cannot find syscon node\n", __func__);
+			return -EINVAL;
+		}
+		reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+		if (!reg) {
+			debug("%s: cannot find reg property in syscon node\n",
+			      __func__);
+			return -EINVAL;
+		}
+		priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+							 offset, reg);
+		if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+			debug("%s: Cannot find syscon base address\n",
+			      __func__);
+			return -EINVAL;
+		}
 	}
 
 	pdata->phy_interface = -1;
@@ -841,14 +872,6 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	priv->variant = dev_get_driver_data(dev);
-
-	if (!priv->variant) {
-		printf("%s: Missing variant '%s'\n", __func__,
-		       (char *)priv->variant);
-		return -EINVAL;
-	}
-
 	if (priv->variant == H3_EMAC) {
 		int parent = fdt_parent_offset(gd->fdt_blob, offset);
 
@@ -885,6 +908,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 
 static const struct udevice_id sun8i_emac_eth_ids[] = {
 	{.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
+	{.compatible = "allwinner,sun8i-r40-gmac",
+		.data = (uintptr_t)R40_GMAC },
 	{.compatible = "allwinner,sun50i-a64-emac",
 		.data = (uintptr_t)A64_EMAC },
 	{.compatible = "allwinner,sun8i-a83t-emac",
-- 
2.14.1

[U-Boot] [PATCH v3 2/5] net: sun8i-emac: support R40 GMAC

[Jagan Teki]

On Mon, Apr 23, 2018 at 8:27 PM, Lothar Felten <lothar.felten@gmail.com> wrote:
> Add support for the GMAC found in the Allwinner R40/V40 SoC.
>
> The R40 GMAC interface is not controlled by the syscon register but
> has a separate configuration register in the CCU.
> The clock gate and reset bits are in a different register compared
> to the other SoCs supported by this driver.
> The diver uses the -gmac suffix for the R40 because the R40 also
> has a different 100 MBit MAC (EMAC).
>
> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
> ---
>  drivers/net/sun8i_emac.c | 69 +++++++++++++++++++++++++++++++++---------------
>  1 file changed, 47 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index b6e5dafe83..83844a1d40 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -68,6 +68,8 @@
>
>  #if defined(CONFIG_MACH_SUNXI_H3_H5)
>  #define SUN8I_GPD8_GMAC                2
> +#elif defined(CONFIG_MACH_SUN8I_R40)
> +#define SUN8I_GPD8_GMAC                5

Can be done through driver_data?

>  #else
>  #define SUN8I_GPD8_GMAC                4
>  #endif
> @@ -99,6 +101,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  enum emac_variant {
>         A83T_EMAC = 1,
>         H3_EMAC,
> +       R40_GMAC,
>         A64_EMAC,
>  };
>
> @@ -279,6 +282,9 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
>         int ret;
>         u32 reg;
>
> +       if (priv->variant == R40_GMAC)
> +               return 0;
> +
>         reg = readl(priv->sysctl_reg + 0x30);
>
>         if (priv->variant == H3_EMAC) {
> @@ -630,11 +636,25 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
>         }
>  #endif
>
> +#ifdef CONFIG_MACH_SUN8I_R40
> +       /* Set clock gating for emac */
> +       setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
> +
> +       /* De-assert EMAC */
> +       setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
> +
> +       /* Select RGMII for R40 */
> +       setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
> +               CCM_GMAC_CTRL_GPIT_RGMII);
> +       setbits_le32(&ccm->gmac_clk_cfg,
> +                    CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
> +#else

Can be done through driver_data variant?

Jagan.

-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 2/5] net: sun8i-emac: support R40 GMAC

[Joe Hershberger]

On Mon, Apr 23, 2018 at 9:57 AM, Lothar Felten <lothar.felten@gmail.com> wrote:
> Add support for the GMAC found in the Allwinner R40/V40 SoC.
>
> The R40 GMAC interface is not controlled by the syscon register but
> has a separate configuration register in the CCU.
> The clock gate and reset bits are in a different register compared
> to the other SoCs supported by this driver.
> The diver uses the -gmac suffix for the R40 because the R40 also

diver -> driver

> has a different 100 MBit MAC (EMAC).
>
> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
> ---
>  drivers/net/sun8i_emac.c | 69 +++++++++++++++++++++++++++++++++---------------
>  1 file changed, 47 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index b6e5dafe83..83844a1d40 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -68,6 +68,8 @@
>
>  #if defined(CONFIG_MACH_SUNXI_H3_H5)
>  #define SUN8I_GPD8_GMAC                2
> +#elif defined(CONFIG_MACH_SUN8I_R40)
> +#define SUN8I_GPD8_GMAC                5
>  #else
>  #define SUN8I_GPD8_GMAC                4
>  #endif
> @@ -99,6 +101,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  enum emac_variant {
>         A83T_EMAC = 1,
>         H3_EMAC,
> +       R40_GMAC,

It probably make sense to not insert this in the list... please put it
at the end.

>         A64_EMAC,
>  };
>
> @@ -279,6 +282,9 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
>         int ret;
>         u32 reg;
>
> +       if (priv->variant == R40_GMAC)
> +               return 0;
> +
>         reg = readl(priv->sysctl_reg + 0x30);
>
>         if (priv->variant == H3_EMAC) {
> @@ -630,11 +636,25 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
>         }
>  #endif
>
> +#ifdef CONFIG_MACH_SUN8I_R40

This should check variant instead of using a CPP guard.

> +       /* Set clock gating for emac */
> +       setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
> +
> +       /* De-assert EMAC */
> +       setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
> +
> +       /* Select RGMII for R40 */
> +       setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
> +               CCM_GMAC_CTRL_GPIT_RGMII);
> +       setbits_le32(&ccm->gmac_clk_cfg,
> +                    CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
> +#else
>         /* Set clock gating for emac */
>         setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
>
>         /* De-assert EMAC */
>         setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
> +#endif
>  }
>
>  #if defined(CONFIG_DM_GPIO)
> @@ -801,22 +821,33 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
>                 return -EINVAL;
>         }
>
> -       offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
> -       if (offset < 0) {
> -               debug("%s: cannot find syscon node\n", __func__);
> -               return -EINVAL;
> -       }
> -       reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
> -       if (!reg) {
> -               debug("%s: cannot find reg property in syscon node\n",
> -                     __func__);
> +       priv->variant = dev_get_driver_data(dev);
> +
> +       if (!priv->variant) {
> +               printf("%s: Missing variant '%s'\n", __func__,
> +                      (char *)priv->variant);

This makes no sense. The if statement above verified that the value
was 0. You shouldn't cast that to a char * and try to print NULL.

>                 return -EINVAL;
>         }
> -       priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
> -                                                offset, reg);
> -       if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
> -               debug("%s: Cannot find syscon base address\n", __func__);
> -               return -EINVAL;
> +
> +       if (priv->variant != R40_GMAC) {
> +               offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
> +               if (offset < 0) {
> +                       debug("%s: cannot find syscon node\n", __func__);
> +                       return -EINVAL;
> +               }
> +               reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
> +               if (!reg) {
> +                       debug("%s: cannot find reg property in syscon node\n",
> +                             __func__);
> +                       return -EINVAL;
> +               }
> +               priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
> +                                                        offset, reg);
> +               if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
> +                       debug("%s: Cannot find syscon base address\n",
> +                             __func__);
> +                       return -EINVAL;
> +               }
>         }
>
>         pdata->phy_interface = -1;
> @@ -841,14 +872,6 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
>                 return -EINVAL;
>         }
>
> -       priv->variant = dev_get_driver_data(dev);
> -
> -       if (!priv->variant) {
> -               printf("%s: Missing variant '%s'\n", __func__,
> -                      (char *)priv->variant);

Ah, you are just moving this from here... Please add a patch before
this one that fixes this.

> -               return -EINVAL;
> -       }
> -
>         if (priv->variant == H3_EMAC) {
>                 int parent = fdt_parent_offset(gd->fdt_blob, offset);
>
> @@ -885,6 +908,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
>
>  static const struct udevice_id sun8i_emac_eth_ids[] = {
>         {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
> +       {.compatible = "allwinner,sun8i-r40-gmac",
> +               .data = (uintptr_t)R40_GMAC },
>         {.compatible = "allwinner,sun50i-a64-emac",
>                 .data = (uintptr_t)A64_EMAC },
>         {.compatible = "allwinner,sun8i-a83t-emac",
> --
> 2.14.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 3/5] sunxi: R40: add gigabit ethernet gpio pinmux

[Lothar Felten]

Add gpio mux settings for the Allwinner R40/V40 CPU.
The gigabit ethernet interface can only be routed to a fixed set of
pins.

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
---
 arch/arm/dts/sun8i-r40.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index 48ec2e855a..ee22f6eb3a 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -126,6 +126,15 @@
 			#interrupt-cells = <3>;
 			#gpio-cells = <3>;
 
+			gmac_pins_rgmii: gmac_rgmii {
+				pins =	"PA0", "PA1", "PA2",
+					"PA3", "PA4", "PA5", "PA6",
+					"PA7", "PA8", "PA10",
+					"PA11", "PA12", "PA13",
+					"PA15", "PA16";
+				function = "gmac";
+			};
+
 			i2c0_pins: i2c0_pins {
 				pins = "PB0", "PB1";
 				function = "i2c0";
-- 
2.14.1

[U-Boot] [PATCH v3 4/5] sunxi: R40: add gigabit ethernet devicetree node

[Lothar Felten]

Add a device tree node for the Allwinner R40/V40 GMAC gigabit
ethernet interface.
The R40 SoC does not use the syscon register for GMAC settings.

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
---
 arch/arm/dts/sun8i-r40.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index ee22f6eb3a..b46fcbb0b9 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -168,6 +168,27 @@
 			#size-cells = <0>;
 		};
 
+		gmac: ethernet at 01c50000 {
+			compatible = "allwinner,sun8i-r40-gmac";
+			reg = <0x01c50000 0x2000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks = <&osc24M>, <&osc24M>;
+			clock-names = "stmmaceth", "allwinner_gmac_tx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&gmac_pins_rgmii>;
+			phy-mode = "rgmii";
+			status = "disabled";
+
+			mdio: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+			};
+		};
+
 		gic: interrupt-controller at 1c81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,
-- 
2.14.1

[U-Boot] [PATCH v3 4/5] sunxi: R40: add gigabit ethernet devicetree node

[Maxime Ripard]

Hi,

On Mon, Apr 23, 2018 at 04:57:19PM +0200, Lothar Felten wrote:
> Add a device tree node for the Allwinner R40/V40 GMAC gigabit
> ethernet interface.
> The R40 SoC does not use the syscon register for GMAC settings.
> 
> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
> ---
>  arch/arm/dts/sun8i-r40.dtsi | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
> index ee22f6eb3a..b46fcbb0b9 100644
> --- a/arch/arm/dts/sun8i-r40.dtsi
> +++ b/arch/arm/dts/sun8i-r40.dtsi
> @@ -168,6 +168,27 @@
>  			#size-cells = <0>;
>  		};
>  
> +		gmac: ethernet at 01c50000 {
> +			compatible = "allwinner,sun8i-r40-gmac";
> +			reg = <0x01c50000 0x2000>;
> +			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "macirq";
> +			clocks = <&osc24M>, <&osc24M>;
> +			clock-names = "stmmaceth", "allwinner_gmac_tx";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&gmac_pins_rgmii>;
> +			phy-mode = "rgmii";

If that's going to be overwritten in the DTS, maybe we should just
drop it from the DTSI.

The rest of the serie looks good to me, however, it is a best practice
to have a changelog either in the cover letter (if you have one) or in
the patches themselves so that reviewer know what changed between the
two versions.

Thanks!
Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

[U-Boot] [PATCH v3 4/5] sunxi: R40: add gigabit ethernet devicetree node

[Joe Hershberger]

On Mon, Apr 23, 2018 at 9:57 AM, Lothar Felten <lothar.felten@gmail.com> wrote:
> Add a device tree node for the Allwinner R40/V40 GMAC gigabit
> ethernet interface.
> The R40 SoC does not use the syscon register for GMAC settings.
>
> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>

Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] [PATCH v3 5/5] configs: Bananapi_M2_Ultra: enable gigabit on the Bananapi

[Lothar Felten]

Enable the gigabit ethernet for the Bananapi M2 Ultra board.
Tested on BananaPi M2 Berry (R40), custom board (V40)

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
---
 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
 configs/Bananapi_M2_Ultra_defconfig          |  3 +++
 2 files changed, 17 insertions(+)

diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
index ab471ab0bf..25f2112fbf 100644
--- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -67,3 +67,17 @@
 	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
+
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_pins_rgmii>;
+	status = "okay";
+	phy-handle = <&rgmii_phy>;
+};
+
+&mdio {
+	rgmii_phy: ethernet-phy at 1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index 37cc2df5dc..b550dc052d 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -17,3 +17,6 @@ CONFIG_AXP_DLDO4_VOLT=2500
 CONFIG_AXP_ELDO3_VOLT=1200
 CONFIG_SCSI=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_RGMII=y
+CONFIG_MACPWR="PA17"
-- 
2.14.1

[U-Boot] [PATCH v3 5/5] configs: Bananapi_M2_Ultra: enable gigabit on the Bananapi

[Joe Hershberger]

On Mon, Apr 23, 2018 at 9:57 AM, Lothar Felten <lothar.felten@gmail.com> wrote:
> Enable the gigabit ethernet for the Bananapi M2 Ultra board.
> Tested on BananaPi M2 Berry (R40), custom board (V40)
>
> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>

Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] [PATCH v3 1/5] sunxi: R40: add gigabit ethernet clocks

[Joe Hershberger]

On Mon, Apr 23, 2018 at 9:57 AM, Lothar Felten <lothar.felten@gmail.com> wrote:
> Add clock control entries for the gigabit interface of the Allwinner
> R40/V40 CPU
>
> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>

You dropped Maxime's Acks when you sent the v3. You need to include
any acks or reviews you already got in the new version unless the
patch is substantially different.

You should use tools/patman/patman and indicate any changes using the
"Series-changes: n" tags.

Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

> ---
>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index d35aa479f7..3ea473c302 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -61,7 +61,11 @@ struct sunxi_ccm_reg {
>         u32 reserved11;
>         u32 sata_clk_cfg;       /* 0xc8 SATA clock control (R40 only) */
>         u32 usb_clk_cfg;        /* 0xcc USB clock control */
> -       u32 gmac_clk_cfg;       /* 0xd0 GMAC clock control */
> +#ifdef CONFIG_MACH_SUN8I_R40
> +       u32 cir0_clk_cfg;       /* 0xd0 CIR0 clock control (R40 only) */
> +#else
> +       u32 gmac_clk_cfg;       /* 0xd0 GMAC clock control (not for R40) */
> +#endif
>         u32 reserved12[7];
>         u32 mdfs_clk_cfg;       /* 0xf0 MDFS clock control */
>         u32 dram_clk_cfg;       /* 0xf4 DRAM configuration clock control */
> @@ -104,7 +108,11 @@ struct sunxi_ccm_reg {
>         u32 mtc_clk_cfg;        /* 0x158 MTC module clock */
>         u32 mbus0_clk_cfg;      /* 0x15c MBUS0 module clock */
>         u32 mbus1_clk_cfg;      /* 0x160 MBUS1 module clock */
> +#ifdef CONFIG_MACH_SUN8I_R40
> +       u32 gmac_clk_cfg;       /* 0x164 GMAC clock control (R40 only) */
> +#else
>         u32 reserved16;
> +#endif
>         u32 mipi_dsi_clk_cfg;   /* 0x168 MIPI DSI clock control */
>         u32 mipi_csi_clk_cfg;   /* 0x16c MIPI CSI clock control */
>         u32 reserved17[4];
> --
> 2.14.1
>
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