[U-Boot] ODROID dynamic memory initialization

[U-Boot] ODROID dynamic memory initialization

[Daniel Drake]

Hi Przemyslaw,

While looking at the old uboot from hardkernel, I'm curious about
CONFIG_CLK_BUS_DMC_220_440, which is set by default. This appears to
run the memory at a high speed, by writing certain registers in the
Dynamic Memory Controller (e.g. TIMINGROW), and clocking MPLL to
880MHz.

Your uboot patches don't seem to touch DMC regs like TIMINGROW, and
also clock the MPLL at 800MHz.

I'm wondering if there is any reason for this? Wouldn't it be better
to run at the faster speed like the vendor code does?

Thanks
Daniel

[U-Boot] ODROID dynamic memory initialization

[Daniel Drake]

On Tue, Jul 22, 2014 at 2:08 PM, Daniel Drake <drake@endlessm.com> wrote:
> While looking at the old uboot from hardkernel, I'm curious about
> CONFIG_CLK_BUS_DMC_220_440, which is set by default. This appears to
> run the memory at a high speed, by writing certain registers in the
> Dynamic Memory Controller (e.g. TIMINGROW), and clocking MPLL to
> 880MHz.
>
> Your uboot patches don't seem to touch DMC regs like TIMINGROW, and
> also clock the MPLL at 800MHz.

I looked in more detail, and now understand better the SPL vs uboot division.

The vendor code I was referring to above is SPL code.

Since we are still using the same SPL as before, it means that MPLL
and memory is already set up by the time the real/new uboot loads.

So I think there should be no need to modify MPLL, and I wonder if
most of the other clock configuration code in your patches is also
unnecessary.

Thoughts?

Thanks
Daniel

[U-Boot] ODROID dynamic memory initialization

[Przemyslaw Marczak]

Hi Daniel,

On 07/23/2014 02:27 PM, Daniel Drake wrote:
> On Tue, Jul 22, 2014 at 2:08 PM, Daniel Drake <drake@endlessm.com> wrote:
>> While looking at the old uboot from hardkernel, I'm curious about
>> CONFIG_CLK_BUS_DMC_220_440, which is set by default. This appears to
>> run the memory at a high speed, by writing certain registers in the
>> Dynamic Memory Controller (e.g. TIMINGROW), and clocking MPLL to
>> 880MHz.
>>
>> Your uboot patches don't seem to touch DMC regs like TIMINGROW, and
>> also clock the MPLL at 800MHz.

I used my private config from trats2 device, but there is Exynos4412 
rev. 1.1 - DMC freq is 400MHz.
I need to check the 880Mhz value for the MPLL and I will give you an info.

>
> I looked in more detail, and now understand better the SPL vs uboot division.
>
> The vendor code I was referring to above is SPL code.
>
> Since we are still using the same SPL as before, it means that MPLL
> and memory is already set up by the time the real/new uboot loads.
>
> So I think there should be no need to modify MPLL, and I wonder if
> most of the other clock configuration code in your patches is also
> unnecessary.
>
> Thoughts?
>
> Thanks
> Daniel
>

The BL2 is not a part of this patches, then maybe better is to configure 
the clocks for proper values by u-boot, moreover when I
disable the clock configuration in u-boot then it can't boot - probably 
because of bad uart config and maybe some more.

Thank you for testing this code, but I don't have too much time for play 
with this config now.

I will test the MPLL with 880MHz tomorrow and it should be good enough, 
but next if dev freq will be enabled in the kernel - then probably DMC 
dividers will change without TIMINGROW change.

Thanks,
-- 
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com

[U-Boot] [PATCH] odroid: set MPLL clock to 880MHz

[Przemyslaw Marczak]

This patch changes MPLL from 800MHz to 880MHz on Odroid.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
---
 board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index 2c5c107..b6f26ee 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -195,8 +195,8 @@ static void board_clock_init(void)
 	while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
 		continue;
 
-	/* Set MPLL to 800MHz */
-	set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
+	/* Set MPLL to 880MHz */
+	set = SDIV(0) | PDIV(3) | MDIV(110) | FSEL(0) | PLL_ENABLE(1);
 
 	clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
 
@@ -220,15 +220,15 @@ static void board_clock_init(void)
 	      DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
 	/*
 	 * For:
-	 * MOUTdmc = 800 MHz
-	 * MOUTdphy = 800 MHz
+	 * MOUTdmc = 880 MHz
+	 * MOUTdphy = 880 MHz
 	 *
-	 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
-	 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
-	 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
-	 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
-	 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
-	 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
+	 * aclk_acp = MOUTdmc / (ratio + 1) = 220 (3)
+	 * pclk_acp = aclk_acp / (ratio + 1) = 110 (1)
+	 * sclk_dphy = MOUTdphy / (ratio + 1) = 440 (1)
+	 * sclk_dmc = MOUTdmc / (ratio + 1) = 440 (1)
+	 * aclk_dmcd = sclk_dmc / (ratio + 1) = 220 (1)
+	 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 110 (1)
 	 */
 	set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
 	      DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
@@ -244,13 +244,13 @@ static void board_clock_init(void)
 	      C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
 	/*
 	 * For:
-	 * MOUTg2d = 800 MHz
-	 * MOUTc2c = 800 Mhz
+	 * MOUTg2d = 880 MHz
+	 * MOUTc2c = 880 Mhz
 	 * MOUTpwi = 108 MHz
 	 *
-	 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
-	 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
-	 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
+	 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 440 (1)
+	 * sclk_c2c = MOUTc2c / (ratio + 1) = 440 (1)
+	 * aclk_c2c = sclk_c2c / (ratio + 1) = 220 (1)
 	 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
 	 */
 	set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |
@@ -282,9 +282,9 @@ static void board_clock_init(void)
 	clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
 	      UART3_RATIO(15) | UART4_RATIO(15);
 	/*
-	 * For MOUTuart0-4: 800MHz
+	 * For MOUTuart0-4: 880MHz
 	 *
-	 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
+	 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 110 (7)
 	*/
 	set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
 	      UART3_RATIO(7) | UART4_RATIO(7);
@@ -298,12 +298,12 @@ static void board_clock_init(void)
 	clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
 	      MMC1_PRE_RATIO(255);
 	/*
-	 * For MOUTmmc0-3 = 800 MHz (MPLL)
+	 * For MOUTmmc0-3 = 880 MHz (MPLL)
 	 *
-	 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
-	 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
-	 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
-	 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
+	 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 110 (7)
+	 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 60 (1)
+	 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 110 (7)
+	 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 60 (1)
 	*/
 	set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
 	      MMC1_PRE_RATIO(1);
@@ -318,12 +318,12 @@ static void board_clock_init(void)
 	clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
 	      MMC3_PRE_RATIO(255);
 	/*
-	 * For MOUTmmc0-3 = 800 MHz (MPLL)
+	 * For MOUTmmc0-3 = 880 MHz (MPLL)
 	 *
-	 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
-	 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
-	 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
-	 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
+	 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 110 (7)
+	 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 60 (1)
+	 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 110 (7)
+	 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 60 (1)
 	*/
 	set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
 	      MMC3_PRE_RATIO(1);
@@ -337,10 +337,10 @@ static void board_clock_init(void)
 	/* CLK_DIV_FSYS3 */
 	clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
 	/*
-	 * For MOUTmmc4 = 800 MHz (MPLL)
+	 * For MOUTmmc4 = 880 MHz (MPLL)
 	 *
-	 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
-	 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
+	 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 110 (7)
+	 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 110 (0)
 	*/
 	set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
 
-- 
1.9.1

[U-Boot] [PATCH] odroid: set MPLL clock to 880MHz

[Przemyslaw Marczak]

Hello Daniel,

On 07/24/2014 12:42 PM, Przemyslaw Marczak wrote:
> This patch changes MPLL from 800MHz to 880MHz on Odroid.
>
> Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
> ---
>   board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
>   1 file changed, 30 insertions(+), 30 deletions(-)


Please apply this on the top of:
"[PATCH v6 00/12] Add support to Odroid U3/X2"

This change only one of MPLL divider and set the MPLL clock to 880.
But such MPLL freq makes some other clocks issue.

In u-boot, the dw mmc driver sets wrong clock(probably some bug) and the 
emmc r/w performance is lower than before.
Kernel is booting the same as before. But most of clock values are not 
integers now.
I am not sure that everything will work fine.
Can you test in on your kernel?

Thank you,
-- 
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com

[U-Boot] [PATCH] odroid: set MPLL clock to 880MHz

[Minkyu Kang]

On 24/07/14 19:42, Przemyslaw Marczak wrote:
> This patch changes MPLL from 800MHz to 880MHz on Odroid.
> 
> Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
> ---
>  board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
>  1 file changed, 30 insertions(+), 30 deletions(-)
> 

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

[U-Boot] [PATCH] odroid: set MPLL clock to 880MHz

[Przemyslaw Marczak]

Hello Minkyu,

On 09/05/2014 08:55 AM, Minkyu Kang wrote:
> On 24/07/14 19:42, Przemyslaw Marczak wrote:
>> This patch changes MPLL from 800MHz to 880MHz on Odroid.
>>
>> Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
>> ---
>>   board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
>>   1 file changed, 30 insertions(+), 30 deletions(-)
>>
>
> applied to u-boot-samsung.
>
> Thanks,
> Minkyu Kang.
>
>
Thank you for applying the Odroid patch set.

I would like to note, that this one patch was intended for MR. Daniel 
just for his tests.

This patch breaks dw mmc performance:
e.g. eMMC uImage(fat) read performance:
- before this commit: 47.6 MiB/s
- after this commit: 13.0 MiB/s
So this requires some more changes in clocks and also in dw mmc driver.

And it can break some kernel clocks divider dependencies.
It is not tested.

So please revert this patch.

Best Regards,
-- 
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com

[U-Boot] [PATCH] odroid: set MPLL clock to 880MHz

[Minkyu Kang]

On 05/09/14 19:50, Przemyslaw Marczak wrote:
> Hello Minkyu,
> 
> On 09/05/2014 08:55 AM, Minkyu Kang wrote:
>> On 24/07/14 19:42, Przemyslaw Marczak wrote:
>>> This patch changes MPLL from 800MHz to 880MHz on Odroid.
>>>
>>> Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
>>> ---
>>>   board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
>>>   1 file changed, 30 insertions(+), 30 deletions(-)
>>>
>>
>> applied to u-boot-samsung.
>>
>> Thanks,
>> Minkyu Kang.
>>
>>
> Thank you for applying the Odroid patch set.
> 
> I would like to note, that this one patch was intended for MR. Daniel just for his tests.
> 
> This patch breaks dw mmc performance:
> e.g. eMMC uImage(fat) read performance:
> - before this commit: 47.6 MiB/s
> - after this commit: 13.0 MiB/s
> So this requires some more changes in clocks and also in dw mmc driver.
> 
> And it can break some kernel clocks divider dependencies.
> It is not tested.
> 
> So please revert this patch.
> 
> Best Regards,

reverted..

Thanks,
Minkyu Kang.

[U-Boot] [PATCH] odroid: set MPLL clock to 880MHz

[Jaehoon Chung]

Hi,

On 09/11/2014 02:03 PM, Minkyu Kang wrote:
> On 05/09/14 19:50, Przemyslaw Marczak wrote:
>> Hello Minkyu,
>>
>> On 09/05/2014 08:55 AM, Minkyu Kang wrote:
>>> On 24/07/14 19:42, Przemyslaw Marczak wrote:
>>>> This patch changes MPLL from 800MHz to 880MHz on Odroid.
>>>>
>>>> Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
>>>> ---
>>>>   board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
>>>>   1 file changed, 30 insertions(+), 30 deletions(-)
>>>>
>>>
>>> applied to u-boot-samsung.
>>>
>>> Thanks,
>>> Minkyu Kang.
>>>
>>>
>> Thank you for applying the Odroid patch set.
>>
>> I would like to note, that this one patch was intended for MR. Daniel just for his tests.
>>
>> This patch breaks dw mmc performance:
>> e.g. eMMC uImage(fat) read performance:
>> - before this commit: 47.6 MiB/s
>> - after this commit: 13.0 MiB/s
>> So this requires some more changes in clocks and also in dw mmc driver.

MPLL is used to the eMMC's source clock.
If MPLL is changed to 880MHz, then eMMC's clock should not be set to correct value.
It has to test before changed MPLL clock. otherwise, we need to use other source clock.

Best Regards,
Jaehoon Chung

>>
>> And it can break some kernel clocks divider dependencies.
>> It is not tested.
>>
>> So please revert this patch.
>>
>> Best Regards,
> 
> reverted..
> 
> Thanks,
> Minkyu Kang.
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
> 

[U-Boot] [PATCH] odroid: set MPLL clock to 880MHz

[Lukasz Majewski]

Hi Jaehoon,

> Hi,
> 
> On 09/11/2014 02:03 PM, Minkyu Kang wrote:
> > On 05/09/14 19:50, Przemyslaw Marczak wrote:
> >> Hello Minkyu,
> >>
> >> On 09/05/2014 08:55 AM, Minkyu Kang wrote:
> >>> On 24/07/14 19:42, Przemyslaw Marczak wrote:
> >>>> This patch changes MPLL from 800MHz to 880MHz on Odroid.
> >>>>
> >>>> Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
> >>>> ---
> >>>>   board/samsung/odroid/odroid.c | 60
> >>>> +++++++++++++++++++++---------------------- 1 file changed, 30
> >>>> insertions(+), 30 deletions(-)
> >>>>
> >>>
> >>> applied to u-boot-samsung.
> >>>
> >>> Thanks,
> >>> Minkyu Kang.
> >>>
> >>>
> >> Thank you for applying the Odroid patch set.
> >>
> >> I would like to note, that this one patch was intended for MR.
> >> Daniel just for his tests.
> >>
> >> This patch breaks dw mmc performance:
> >> e.g. eMMC uImage(fat) read performance:
> >> - before this commit: 47.6 MiB/s
> >> - after this commit: 13.0 MiB/s
> >> So this requires some more changes in clocks and also in dw mmc
> >> driver.
> 
> MPLL is used to the eMMC's source clock.
> If MPLL is changed to 880MHz, then eMMC's clock should not be set to
> correct value. It has to test before changed MPLL clock. otherwise,
> we need to use other source clock.

Yes, correct.

But for now this patch introduces considerable performance regression.

Moreover, as Przemek had written it down to Minkyu, this patch was
supposed solely for Daniel's private usage and shouldn't be applied to
u-boot main line.

Hence I'd like to ask for removing this patch from the pull request
sent to Albert.


> 
> Best Regards,
> Jaehoon Chung
> 
> >>
> >> And it can break some kernel clocks divider dependencies.
> >> It is not tested.
> >>
> >> So please revert this patch.
> >>
> >> Best Regards,
> > 
> > reverted..
> > 
> > Thanks,
> > Minkyu Kang.
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> > 



-- 
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group