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From: dianders@chromium.org (Doug Anderson)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/8] clk: rockchip: change pll rate without a clk-notifier
Date: Wed, 17 Sep 2014 15:46:08 -0700	[thread overview]
Message-ID: <CAD=FV=VjU7E4TpPHv5Md=zLEig=zCTG8twx8L9+5hdLuERDUAw@mail.gmail.com> (raw)
In-Reply-To: <1410991974-12235-2-git-send-email-heiko@sntech.de>

Heiko,

On Wed, Sep 17, 2014 at 3:12 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> From: Doug Anderson <dianders@chromium.org>
>
> The Rockchip PLL code switches into slow mode (AKA bypass more AKA
> 24MHz mode) before actually changing the PLL.  This keeps anyone from
> using the PLL while it's changing.  However, in all known Rockchip
> SoCs nobody should ever see the 24MHz when changing the PLL supplying
> the armclk because we should reparent children to an alternate
> (faster than 24MHz) PLL.
>
> One problem is that the code to switch to an alternate parent was
> running in PRE_RATE_CHANGE.  ...and the code to switch to slow mode
> was _also_ running in PRE_RATE_CHANGE.  That meant there was no real
> guarantee that we would switch to an alternate parent before switching
> to 24MHz mode.
>
> Let's move the switch to "slow mode" straight into
> rockchip_rk3066_pll_set_rate().  That means we're guaranteed that the
> 24MHz is really a last-resort.
>
> Note that without this change on real systems we were the code to
> switch to an alternate parent at 24MHz.  In some older versions of
> that code we'd appy a (temporary) / 5 to the 24MHz causing us to run
> at 4.8MHz.  That wasn't enough to service USB interrupts in some cases
> and could lead to a system hang.
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  drivers/clk/rockchip/clk-pll.c | 63 +++++++++---------------------------------
>  1 file changed, 13 insertions(+), 50 deletions(-)

Thanks for adding my patch to your series (with the proper commit
message)!  I think you need your SoB on the patch too.  Andrew Morton
pointed to the docs in another patch I was involved in.  Specifically,
you were "on the patch delivery".  See Documentation/SubmittingPatches
section 12 (and 13).

-Doug

  reply	other threads:[~2014-09-17 22:46 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-17 22:12 [PATCH v3 0/8] ARM: Rockchip: add cpuclk handling - clock-tree part Heiko Stuebner
2014-09-17 22:12 ` [PATCH v3 1/8] clk: rockchip: change pll rate without a clk-notifier Heiko Stuebner
2014-09-17 22:46   ` Doug Anderson [this message]
2014-09-17 23:13     ` Heiko Stübner
2014-09-25 22:50       ` Mike Turquette
2014-09-17 22:12 ` [PATCH v3 2/8] clk: rockchip: fix rk3066 pll status register location Heiko Stuebner
2014-09-17 22:12 ` [PATCH v3 3/8] clk: rockchip: fix rk3288 " Heiko Stuebner
2014-09-17 22:12 ` [PATCH v3 4/8] clk: rockchip: reparent aclk_cpu_pre to the gpll Heiko Stuebner
2014-09-17 22:12 ` [PATCH v3 5/8] clk: rockchip: make tightly bound armclk child-clocks read-only Heiko Stuebner
2014-09-17 22:12 ` [PATCH v3 6/8] clk: rockchip: add new clock-type for the cpuclk Heiko Stuebner
2014-09-22 17:47   ` Doug Anderson
2014-09-22 19:21     ` Heiko Stübner
2014-09-22 19:33       ` Doug Anderson
2014-09-23  5:25       ` Thomas Abraham
2014-09-23 18:16         ` Doug Anderson
2014-09-17 22:12 ` [PATCH v3 7/8] clk: rockchip: add binding id for ARMCLK Heiko Stuebner
2014-09-22 17:08   ` Doug Anderson
2014-09-17 22:12 ` [PATCH v3 8/8] clk: rockchip: switch to using the new cpuclk type for armclk Heiko Stuebner
2014-09-22 17:51   ` Doug Anderson

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