* [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-05 2:32 ` Addy Ke
0 siblings, 0 replies; 18+ messages in thread
From: Addy Ke @ 2014-09-05 2:32 UTC (permalink / raw)
To: wsa, max.schwarz, heiko, olof, dianders
Cc: linux-i2c, linux-kernel, linux-arm-kernel, linux-rockchip, cf,
xjq, huangtao, zyw, yzq, hj, kever.yang, hl, caesar.wang,
zhengsq, Addy Ke
I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.
The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
drivers/i2c/busses/i2c-rk3x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..76b6604 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,8 +433,8 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
- /* SCL rate = (clk rate) / (8 * DIV) */
- div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
+ /* SCL rate = (clk rate) / (8 * (DIV + 2)) */
+ div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
/* The lower and upper half of the CLKDIV reg describe the length of
* SCL low & high periods. */
--
1.8.3.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-05 2:32 ` Addy Ke
0 siblings, 0 replies; 18+ messages in thread
From: Addy Ke @ 2014-09-05 2:32 UTC (permalink / raw)
To: wsa-z923LK4zBo2bacvFa/9K2g, max.schwarz-BGeptl67XyCzQB+pC5nmwQ,
heiko-4mtYJXux2i+zQB+pC5nmwQ, olof-nZhT3qVonbNeoWH0uzbU5w,
dianders-F7+t8E8rja9g9hUCZPvPmw
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cf-TNX95d0MmH7DzftRWevZcw, xjq-TNX95d0MmH7DzftRWevZcw,
huangtao-TNX95d0MmH7DzftRWevZcw, zyw-TNX95d0MmH7DzftRWevZcw,
yzq-TNX95d0MmH7DzftRWevZcw, hj-TNX95d0MmH7DzftRWevZcw,
kever.yang-TNX95d0MmH7DzftRWevZcw, hl-TNX95d0MmH7DzftRWevZcw,
caesar.wang-TNX95d0MmH7DzftRWevZcw,
zhengsq-TNX95d0MmH7DzftRWevZcw, Addy Ke
I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.
The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
drivers/i2c/busses/i2c-rk3x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..76b6604 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,8 +433,8 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
- /* SCL rate = (clk rate) / (8 * DIV) */
- div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
+ /* SCL rate = (clk rate) / (8 * (DIV + 2)) */
+ div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
/* The lower and upper half of the CLKDIV reg describe the length of
* SCL low & high periods. */
--
1.8.3.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-05 2:32 ` Addy Ke
0 siblings, 0 replies; 18+ messages in thread
From: Addy Ke @ 2014-09-05 2:32 UTC (permalink / raw)
To: linux-arm-kernel
I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.
The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
drivers/i2c/busses/i2c-rk3x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..76b6604 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,8 +433,8 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
- /* SCL rate = (clk rate) / (8 * DIV) */
- div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
+ /* SCL rate = (clk rate) / (8 * (DIV + 2)) */
+ div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
/* The lower and upper half of the CLKDIV reg describe the length of
* SCL low & high periods. */
--
1.8.3.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
2014-09-05 2:32 ` Addy Ke
@ 2014-09-05 4:31 ` Doug Anderson
-1 siblings, 0 replies; 18+ messages in thread
From: Doug Anderson @ 2014-09-05 4:31 UTC (permalink / raw)
To: Addy Ke
Cc: Wolfram Sang, max.schwarz, Heiko Stübner, Olof Johansson,
linux-i2c, linux-kernel, linux-arm-kernel, linux-rockchip,
Eddie Cai, Jianqun Xu, Tao Huang, Chris, 姚智情,
han jiang, Kever Yang, Lin Huang, 晓腾王,
Shunqian Zheng
Addy,
On Thu, Sep 4, 2014 at 7:32 PM, Addy Ke <addy.ke@rock-chips.com> wrote:
> I2C_CLKDIV register descripted in the previous version of
> RK3x chip manual is incorrect. Plus 1 is required.
>
> The correct formula:
> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
> - SCL = PCLK / (CLK Divsor)
I'll trust that you tested this with a scope
> It will be updated to the latest version of chip manual.
>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
> ---
> drivers/i2c/busses/i2c-rk3x.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
> index e637c32..76b6604 100644
> --- a/drivers/i2c/busses/i2c-rk3x.c
> +++ b/drivers/i2c/busses/i2c-rk3x.c
> @@ -433,8 +433,8 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
> unsigned long i2c_rate = clk_get_rate(i2c->clk);
> unsigned int div;
>
> - /* SCL rate = (clk rate) / (8 * DIV) */
> - div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
> + /* SCL rate = (clk rate) / (8 * (DIV + 2)) */
> + div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
Given the bug I just fixed in the Rockchip SPI driver, I was a little
worried about div becoming -1 (and thus being a really large positive
number since div is unsigned).
However, it seems that you get saved by the next statement:
div = DIV_ROUND_UP(div, 2);
In the testing I did with the Linux macros, that magically transformed
a div of 0xFFFFFFFF (-1) to 0, so it's not technically a bug. ...but
it's very non-obvious. Can you do something a little cleaner?
-Doug
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-05 4:31 ` Doug Anderson
0 siblings, 0 replies; 18+ messages in thread
From: Doug Anderson @ 2014-09-05 4:31 UTC (permalink / raw)
To: linux-arm-kernel
Addy,
On Thu, Sep 4, 2014 at 7:32 PM, Addy Ke <addy.ke@rock-chips.com> wrote:
> I2C_CLKDIV register descripted in the previous version of
> RK3x chip manual is incorrect. Plus 1 is required.
>
> The correct formula:
> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
> - SCL = PCLK / (CLK Divsor)
I'll trust that you tested this with a scope
> It will be updated to the latest version of chip manual.
>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
> ---
> drivers/i2c/busses/i2c-rk3x.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
> index e637c32..76b6604 100644
> --- a/drivers/i2c/busses/i2c-rk3x.c
> +++ b/drivers/i2c/busses/i2c-rk3x.c
> @@ -433,8 +433,8 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
> unsigned long i2c_rate = clk_get_rate(i2c->clk);
> unsigned int div;
>
> - /* SCL rate = (clk rate) / (8 * DIV) */
> - div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
> + /* SCL rate = (clk rate) / (8 * (DIV + 2)) */
> + div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
Given the bug I just fixed in the Rockchip SPI driver, I was a little
worried about div becoming -1 (and thus being a really large positive
number since div is unsigned).
However, it seems that you get saved by the next statement:
div = DIV_ROUND_UP(div, 2);
In the testing I did with the Linux macros, that magically transformed
a div of 0xFFFFFFFF (-1) to 0, so it's not technically a bug. ...but
it's very non-obvious. Can you do something a little cleaner?
-Doug
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-05 10:17 ` addy ke
0 siblings, 0 replies; 18+ messages in thread
From: addy ke @ 2014-09-05 10:17 UTC (permalink / raw)
To: dianders
Cc: wsa, max.schwarz, heiko, olof, linux-i2c, linux-kernel,
linux-arm-kernel, linux-rockchip, cf, xjq, huangtao, zyw, yzq,
hj, kever.yang, hl, caesar.wang, zhengsq
> Addy,
>
> On Thu, Sep 4, 2014 at 7:32 PM, Addy Ke <addy.ke@rock-chips.com> wrote:
>> I2C_CLKDIV register descripted in the previous version of
>> RK3x chip manual is incorrect. Plus 1 is required.
>>
>> The correct formula:
>> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
>> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
>> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
>> - SCL = PCLK / (CLK Divsor)
>
> I'll trust that you tested this with a scope
>
Yes ,I have tested on RK3188 and RK3288, and confirmed by oscilloscope.
>
>> It will be updated to the latest version of chip manual.
>>
>> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
>> ---
>> drivers/i2c/busses/i2c-rk3x.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
>> index e637c32..76b6604 100644
>> --- a/drivers/i2c/busses/i2c-rk3x.c
>> +++ b/drivers/i2c/busses/i2c-rk3x.c
>> @@ -433,8 +433,8 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
>> unsigned long i2c_rate = clk_get_rate(i2c->clk);
>> unsigned int div;
>>
>> - /* SCL rate = (clk rate) / (8 * DIV) */
>> - div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
>> + /* SCL rate = (clk rate) / (8 * (DIV + 2)) */
>> + div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
>
> Given the bug I just fixed in the Rockchip SPI driver, I was a little
> worried about div becoming -1 (and thus being a really large positive
> number since div is unsigned).
>
> However, it seems that you get saved by the next statement:
> div = DIV_ROUND_UP(div, 2);
>
> In the testing I did with the Linux macros, that magically transformed
> a div of 0xFFFFFFFF (-1) to 0, so it's not technically a bug. ...but
> it's very non-obvious. Can you do something a little cleaner?
The following modifications is reasonable?
static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
{
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
/* set DIV = DIVH = DIVL
* SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
* = (clk rate) / (16 * (DIV + 1))
*/
div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
}
>
> -Doug
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-05 10:17 ` addy ke
0 siblings, 0 replies; 18+ messages in thread
From: addy ke @ 2014-09-05 10:17 UTC (permalink / raw)
To: dianders-F7+t8E8rja9g9hUCZPvPmw
Cc: wsa-z923LK4zBo2bacvFa/9K2g, max.schwarz-BGeptl67XyCzQB+pC5nmwQ,
heiko-4mtYJXux2i+zQB+pC5nmwQ, olof-nZhT3qVonbNeoWH0uzbU5w,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cf-TNX95d0MmH7DzftRWevZcw, xjq-TNX95d0MmH7DzftRWevZcw,
huangtao-TNX95d0MmH7DzftRWevZcw, zyw-TNX95d0MmH7DzftRWevZcw,
yzq-TNX95d0MmH7DzftRWevZcw, hj-TNX95d0MmH7DzftRWevZcw,
kever.yang-TNX95d0MmH7DzftRWevZcw, hl-TNX95d0MmH7DzftRWevZcw,
caesar.wang-TNX95d0MmH7DzftRWevZcw,
zhengsq-TNX95d0MmH7DzftRWevZcw
> Addy,
>
> On Thu, Sep 4, 2014 at 7:32 PM, Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>> I2C_CLKDIV register descripted in the previous version of
>> RK3x chip manual is incorrect. Plus 1 is required.
>>
>> The correct formula:
>> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
>> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
>> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
>> - SCL = PCLK / (CLK Divsor)
>
> I'll trust that you tested this with a scope
>
Yes ,I have tested on RK3188 and RK3288, and confirmed by oscilloscope.
>
>> It will be updated to the latest version of chip manual.
>>
>> Signed-off-by: Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> drivers/i2c/busses/i2c-rk3x.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
>> index e637c32..76b6604 100644
>> --- a/drivers/i2c/busses/i2c-rk3x.c
>> +++ b/drivers/i2c/busses/i2c-rk3x.c
>> @@ -433,8 +433,8 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
>> unsigned long i2c_rate = clk_get_rate(i2c->clk);
>> unsigned int div;
>>
>> - /* SCL rate = (clk rate) / (8 * DIV) */
>> - div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
>> + /* SCL rate = (clk rate) / (8 * (DIV + 2)) */
>> + div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
>
> Given the bug I just fixed in the Rockchip SPI driver, I was a little
> worried about div becoming -1 (and thus being a really large positive
> number since div is unsigned).
>
> However, it seems that you get saved by the next statement:
> div = DIV_ROUND_UP(div, 2);
>
> In the testing I did with the Linux macros, that magically transformed
> a div of 0xFFFFFFFF (-1) to 0, so it's not technically a bug. ...but
> it's very non-obvious. Can you do something a little cleaner?
The following modifications is reasonable?
static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
{
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
/* set DIV = DIVH = DIVL
* SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
* = (clk rate) / (16 * (DIV + 1))
*/
div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
}
>
> -Doug
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-05 10:17 ` addy ke
0 siblings, 0 replies; 18+ messages in thread
From: addy ke @ 2014-09-05 10:17 UTC (permalink / raw)
To: linux-arm-kernel
> Addy,
>
> On Thu, Sep 4, 2014 at 7:32 PM, Addy Ke <addy.ke@rock-chips.com> wrote:
>> I2C_CLKDIV register descripted in the previous version of
>> RK3x chip manual is incorrect. Plus 1 is required.
>>
>> The correct formula:
>> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
>> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
>> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
>> - SCL = PCLK / (CLK Divsor)
>
> I'll trust that you tested this with a scope
>
Yes ,I have tested on RK3188 and RK3288, and confirmed by oscilloscope.
>
>> It will be updated to the latest version of chip manual.
>>
>> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
>> ---
>> drivers/i2c/busses/i2c-rk3x.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
>> index e637c32..76b6604 100644
>> --- a/drivers/i2c/busses/i2c-rk3x.c
>> +++ b/drivers/i2c/busses/i2c-rk3x.c
>> @@ -433,8 +433,8 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
>> unsigned long i2c_rate = clk_get_rate(i2c->clk);
>> unsigned int div;
>>
>> - /* SCL rate = (clk rate) / (8 * DIV) */
>> - div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
>> + /* SCL rate = (clk rate) / (8 * (DIV + 2)) */
>> + div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
>
> Given the bug I just fixed in the Rockchip SPI driver, I was a little
> worried about div becoming -1 (and thus being a really large positive
> number since div is unsigned).
>
> However, it seems that you get saved by the next statement:
> div = DIV_ROUND_UP(div, 2);
>
> In the testing I did with the Linux macros, that magically transformed
> a div of 0xFFFFFFFF (-1) to 0, so it's not technically a bug. ...but
> it's very non-obvious. Can you do something a little cleaner?
The following modifications is reasonable?
static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
{
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
/* set DIV = DIVH = DIVL
* SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
* = (clk rate) / (16 * (DIV + 1))
*/
div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
}
>
> -Doug
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
2014-09-05 10:17 ` addy ke
@ 2014-09-05 15:20 ` Doug Anderson
-1 siblings, 0 replies; 18+ messages in thread
From: Doug Anderson @ 2014-09-05 15:20 UTC (permalink / raw)
To: addy ke
Cc: Wolfram Sang, max.schwarz, Heiko Stübner, Olof Johansson,
linux-i2c, linux-kernel, linux-arm-kernel, linux-rockchip,
Eddie Cai, Jianqun Xu, Tao Huang, Chris, 姚智情,
han jiang, Kever Yang, Lin Huang, 晓腾王,
Shunqian Zheng
Addy,
On Fri, Sep 5, 2014 at 3:17 AM, addy ke <addy.ke@rock-chips.com> wrote:
> The following modifications is reasonable?
>
> static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
> {
> unsigned long i2c_rate = clk_get_rate(i2c->clk);
> unsigned int div;
>
> /* set DIV = DIVH = DIVL
> * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
> * = (clk rate) / (16 * (DIV + 1))
> */
> div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
>
> i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
> }
Yes, that looks much cleaner and is a nice solution, thanks! Can you
send up a new patch version?
-Doug
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-05 15:20 ` Doug Anderson
0 siblings, 0 replies; 18+ messages in thread
From: Doug Anderson @ 2014-09-05 15:20 UTC (permalink / raw)
To: linux-arm-kernel
Addy,
On Fri, Sep 5, 2014 at 3:17 AM, addy ke <addy.ke@rock-chips.com> wrote:
> The following modifications is reasonable?
>
> static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
> {
> unsigned long i2c_rate = clk_get_rate(i2c->clk);
> unsigned int div;
>
> /* set DIV = DIVH = DIVL
> * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
> * = (clk rate) / (16 * (DIV + 1))
> */
> div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
>
> i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
> }
Yes, that looks much cleaner and is a nice solution, thanks! Can you
send up a new patch version?
-Doug
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-08 3:38 ` Addy Ke
0 siblings, 0 replies; 18+ messages in thread
From: Addy Ke @ 2014-09-08 3:38 UTC (permalink / raw)
To: wsa, max.schwarz, heiko, olof, dianders
Cc: linux-i2c, linux-kernel, linux-arm-kernel, linux-rockchip, cf,
xjq, huangtao, zyw, yzq, hj, kever.yang, hl, caesar.wang,
zhengsq, Addy Ke
I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.
The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
changes since v1:
- make it more cleaner, suggested by Doug Anderson
drivers/i2c/busses/i2c-rk3x.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..93cfc83 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
- /* SCL rate = (clk rate) / (8 * DIV) */
- div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
-
- /* The lower and upper half of the CLKDIV reg describe the length of
- * SCL low & high periods. */
- div = DIV_ROUND_UP(div, 2);
+ /* set DIV = DIVH = DIVL
+ * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
+ * = (clk rate) / (16 * (DIV + 1))
+ */
+ div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
}
--
1.8.3.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-08 3:38 ` Addy Ke
0 siblings, 0 replies; 18+ messages in thread
From: Addy Ke @ 2014-09-08 3:38 UTC (permalink / raw)
To: wsa-z923LK4zBo2bacvFa/9K2g, max.schwarz-BGeptl67XyCzQB+pC5nmwQ,
heiko-4mtYJXux2i+zQB+pC5nmwQ, olof-nZhT3qVonbNeoWH0uzbU5w,
dianders-F7+t8E8rja9g9hUCZPvPmw
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cf-TNX95d0MmH7DzftRWevZcw, xjq-TNX95d0MmH7DzftRWevZcw,
huangtao-TNX95d0MmH7DzftRWevZcw, zyw-TNX95d0MmH7DzftRWevZcw,
yzq-TNX95d0MmH7DzftRWevZcw, hj-TNX95d0MmH7DzftRWevZcw,
kever.yang-TNX95d0MmH7DzftRWevZcw, hl-TNX95d0MmH7DzftRWevZcw,
caesar.wang-TNX95d0MmH7DzftRWevZcw,
zhengsq-TNX95d0MmH7DzftRWevZcw, Addy Ke
I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.
The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
changes since v1:
- make it more cleaner, suggested by Doug Anderson
drivers/i2c/busses/i2c-rk3x.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..93cfc83 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
- /* SCL rate = (clk rate) / (8 * DIV) */
- div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
-
- /* The lower and upper half of the CLKDIV reg describe the length of
- * SCL low & high periods. */
- div = DIV_ROUND_UP(div, 2);
+ /* set DIV = DIVH = DIVL
+ * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
+ * = (clk rate) / (16 * (DIV + 1))
+ */
+ div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
}
--
1.8.3.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-08 3:38 ` Addy Ke
0 siblings, 0 replies; 18+ messages in thread
From: Addy Ke @ 2014-09-08 3:38 UTC (permalink / raw)
To: linux-arm-kernel
I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.
The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
changes since v1:
- make it more cleaner, suggested by Doug Anderson
drivers/i2c/busses/i2c-rk3x.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..93cfc83 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
- /* SCL rate = (clk rate) / (8 * DIV) */
- div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
-
- /* The lower and upper half of the CLKDIV reg describe the length of
- * SCL low & high periods. */
- div = DIV_ROUND_UP(div, 2);
+ /* set DIV = DIVH = DIVL
+ * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
+ * = (clk rate) / (16 * (DIV + 1))
+ */
+ div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
}
--
1.8.3.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
2014-09-08 3:38 ` Addy Ke
@ 2014-09-08 4:15 ` Doug Anderson
-1 siblings, 0 replies; 18+ messages in thread
From: Doug Anderson @ 2014-09-08 4:15 UTC (permalink / raw)
To: Addy Ke
Cc: Wolfram Sang, max.schwarz, Heiko Stübner, Olof Johansson,
linux-i2c, linux-kernel, linux-arm-kernel, linux-rockchip,
Eddie Cai, Jianqun Xu, Tao Huang, Chris, 姚智情,
han jiang, Kever Yang, Lin Huang, 晓腾王,
Shunqian Zheng
Addy,
On Sun, Sep 7, 2014 at 8:38 PM, Addy Ke <addy.ke@rock-chips.com> wrote:
> I2C_CLKDIV register descripted in the previous version of
> RK3x chip manual is incorrect. Plus 1 is required.
>
> The correct formula:
> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
> - SCL = PCLK / (CLK Divsor)
>
> It will be updated to the latest version of chip manual.
>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
> ---
> changes since v1:
> - make it more cleaner, suggested by Doug Anderson
>
> drivers/i2c/busses/i2c-rk3x.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-08 4:15 ` Doug Anderson
0 siblings, 0 replies; 18+ messages in thread
From: Doug Anderson @ 2014-09-08 4:15 UTC (permalink / raw)
To: linux-arm-kernel
Addy,
On Sun, Sep 7, 2014 at 8:38 PM, Addy Ke <addy.ke@rock-chips.com> wrote:
> I2C_CLKDIV register descripted in the previous version of
> RK3x chip manual is incorrect. Plus 1 is required.
>
> The correct formula:
> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
> - SCL = PCLK / (CLK Divsor)
>
> It will be updated to the latest version of chip manual.
>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
> ---
> changes since v1:
> - make it more cleaner, suggested by Doug Anderson
>
> drivers/i2c/busses/i2c-rk3x.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-20 12:19 ` Wolfram Sang
0 siblings, 0 replies; 18+ messages in thread
From: Wolfram Sang @ 2014-09-20 12:19 UTC (permalink / raw)
To: Addy Ke
Cc: max.schwarz, heiko, olof, dianders, linux-i2c, linux-kernel,
linux-arm-kernel, linux-rockchip, cf, xjq, huangtao, zyw, yzq,
hj, kever.yang, hl, caesar.wang, zhengsq
[-- Attachment #1: Type: text/plain, Size: 534 bytes --]
On Mon, Sep 08, 2014 at 11:38:25AM +0800, Addy Ke wrote:
> I2C_CLKDIV register descripted in the previous version of
> RK3x chip manual is incorrect. Plus 1 is required.
>
> The correct formula:
> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
> - SCL = PCLK / (CLK Divsor)
>
> It will be updated to the latest version of chip manual.
>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
Applied to for-next, thanks!
[-- Attachment #2: Digital signature --]
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-20 12:19 ` Wolfram Sang
0 siblings, 0 replies; 18+ messages in thread
From: Wolfram Sang @ 2014-09-20 12:19 UTC (permalink / raw)
To: Addy Ke
Cc: max.schwarz-BGeptl67XyCzQB+pC5nmwQ, heiko-4mtYJXux2i+zQB+pC5nmwQ,
olof-nZhT3qVonbNeoWH0uzbU5w, dianders-F7+t8E8rja9g9hUCZPvPmw,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cf-TNX95d0MmH7DzftRWevZcw, xjq-TNX95d0MmH7DzftRWevZcw,
huangtao-TNX95d0MmH7DzftRWevZcw, zyw-TNX95d0MmH7DzftRWevZcw,
yzq-TNX95d0MmH7DzftRWevZcw, hj-TNX95d0MmH7DzftRWevZcw,
kever.yang-TNX95d0MmH7DzftRWevZcw, hl-TNX95d0MmH7DzftRWevZcw,
caesar.wang-TNX95d0MmH7DzftRWevZcw,
zhengsq-TNX95d0MmH7DzftRWevZcw
[-- Attachment #1: Type: text/plain, Size: 559 bytes --]
On Mon, Sep 08, 2014 at 11:38:25AM +0800, Addy Ke wrote:
> I2C_CLKDIV register descripted in the previous version of
> RK3x chip manual is incorrect. Plus 1 is required.
>
> The correct formula:
> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
> - SCL = PCLK / (CLK Divsor)
>
> It will be updated to the latest version of chip manual.
>
> Signed-off-by: Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Applied to for-next, thanks!
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
@ 2014-09-20 12:19 ` Wolfram Sang
0 siblings, 0 replies; 18+ messages in thread
From: Wolfram Sang @ 2014-09-20 12:19 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Sep 08, 2014 at 11:38:25AM +0800, Addy Ke wrote:
> I2C_CLKDIV register descripted in the previous version of
> RK3x chip manual is incorrect. Plus 1 is required.
>
> The correct formula:
> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
> - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
> - SCL = PCLK / (CLK Divsor)
>
> It will be updated to the latest version of chip manual.
>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
Applied to for-next, thanks!
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^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2014-09-20 12:19 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-09-05 2:32 [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency Addy Ke
2014-09-05 2:32 ` Addy Ke
2014-09-05 2:32 ` Addy Ke
2014-09-05 4:31 ` Doug Anderson
2014-09-05 4:31 ` Doug Anderson
2014-09-05 10:17 ` addy ke
2014-09-05 10:17 ` addy ke
2014-09-05 10:17 ` addy ke
2014-09-05 15:20 ` Doug Anderson
2014-09-05 15:20 ` Doug Anderson
2014-09-08 3:38 ` [PATCH v2] " Addy Ke
2014-09-08 3:38 ` Addy Ke
2014-09-08 3:38 ` Addy Ke
2014-09-08 4:15 ` Doug Anderson
2014-09-08 4:15 ` Doug Anderson
2014-09-20 12:19 ` Wolfram Sang
2014-09-20 12:19 ` Wolfram Sang
2014-09-20 12:19 ` Wolfram Sang
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