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From: Alex Deucher <alexdeucher@gmail.com>
To: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: "Mark Yacoub" <markyacoub@chromium.org>,
	"Bhawanpreet Lakha" <bhawanpreet.lakha@amd.com>,
	nicholas.choi@amd.com,
	"Linux Doc Mailing List" <linux-doc@vger.kernel.org>,
	"Michel Dänzer" <michel@daenzer.net>,
	"Roman Li" <roman.li@amd.com>,
	"amd-gfx list" <amd-gfx@lists.freedesktop.org>,
	"Nicholas Kazlauskas" <nicholas.kazlauskas@amd.com>,
	"Marek Olšák" <marek.olsak@amd.com>,
	"Aurabindo Pillai" <aurabindo.pillai@amd.com>,
	"Sean Paul" <seanpaul@chromium.org>,
	"Maling list - DRI developers" <dri-devel@lists.freedesktop.org>,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Qingqing Zhuo" <qingqing.zhuo@amd.com>,
	"Christian König" <christian.koenig@amd.com>,
	"Roman Gilg" <subdiff@gmail.com>
Subject: Re: [PATCH 6/6] Documentation/gpu: Add DC glossary
Date: Mon, 29 Nov 2021 15:08:55 -0500	[thread overview]
Message-ID: <CADnq5_NVcHizoY_xRM4d09B2s9DzWwDhn=YrgJ-3COXNANzE3A@mail.gmail.com> (raw)
In-Reply-To: <20211125153830.1352994-7-Rodrigo.Siqueira@amd.com>

On Thu, Nov 25, 2021 at 10:40 AM Rodrigo Siqueira
<Rodrigo.Siqueira@amd.com> wrote:
>
> In the DC driver, we have multiple acronyms that are not obvious most of
> the time. This commit introduces a DC glossary in order to make it
> easier to navigate through our driver.
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
>  Documentation/gpu/amdgpu-dc/amdgpu-dc.rst   |   2 +-
>  Documentation/gpu/amdgpu-dc/dc-glossary.rst | 257 ++++++++++++++++++++
>  2 files changed, 258 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/gpu/amdgpu-dc/dc-glossary.rst
>
> diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst
> index 2e45e83d9a2a..15405c43786a 100644
> --- a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst
> +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst
> @@ -26,4 +26,4 @@ table of content:
>     amdgpu-dcn-overview.rst
>     amdgpu-dm.rst
>     amdgpu-dc-debug.rst
> -
> +   dc-glossary.rst
> diff --git a/Documentation/gpu/amdgpu-dc/dc-glossary.rst b/Documentation/gpu/amdgpu-dc/dc-glossary.rst
> new file mode 100644
> index 000000000000..48698fc1799f
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu-dc/dc-glossary.rst
> @@ -0,0 +1,257 @@
> +===========
> +DC Glossary
> +===========
> +
> +.. glossary::
> +
> +    ABM
> +      Adaptive Backlight Modulation
> +
> +    APU
> +      Accelerated Processing Unit
> +
> +    ASIC
> +      Application-Specific Integrated Circuit
> +
> +    ASSR
> +      Alternate Scrambler Seed Reset
> +
> +    AZ
> +      Azalia (HD audio DMA engine)
> +
> +    BPC
> +      Bits Per Colour/Component
> +
> +    BPP
> +      Bits Per Pixel
> +
> +    Clocks
> +      * PCLK: Pixel Clock
> +      * SYMCLK: Symbol Clock
> +      * SOCCLK: GPU Engine Clock
> +      * DISPCLK: Display Clock
> +      * DPPCLK: DPP Clock
> +      * DCFCLK: Display Controller Fabric Clock
> +      * REFCLK: Real Time Reference Clock
> +      * PPLL: Pixel PLL
> +      * FCLK: Fabric Clock
> +      * MCLK: Memory Clock
> +      * CPLIB: Content Protection Library

CPLIB is not a clock.  It should be split out as its own item.

> +
> +    CRC
> +      Cyclic Redundancy Check
> +
> +    CRTC
> +      Cathode Ray Tube Controller - commonly called "Controller" - Generates
> +      raw stream of pixels, clocked at pixel clock
> +
> +    CVT
> +      Coordinated Video Timings
> +
> +    DAL
> +      Display Abstraction layer
> +
> +    DC (Software)
> +      Display Core
> +
> +    DC (Hardware)
> +      Display Controller
> +
> +    DCC
> +      Delta Colour Compression
> +
> +    DCE
> +      Display Controller Engine
> +
> +    DCHUB
> +      Display Controller Hub
> +
> +    ARB
> +      Arbiter
> +
> +    VTG
> +      Vertical Timing Generator
> +
> +    DCN
> +      Display Core Next
> +
> +    DCCG
> +      Display Clock Generator block
> +
> +    DDC
> +      Display Data Channel
> +
> +    DFS
> +      Digital Frequency Synthesizer
> +
> +    DIO
> +      Display IO
> +
> +    DPP
> +      Display Pipes and Planes
> +
> +    DSC
> +      Display Stream Compression (Reduce the amount of bits to represent pixel
> +      count while at the same pixel clock)
> +
> +    dGPU
> +      discrete GPU
> +
> +    DMIF
> +      Display Memory Interface
> +
> +    DML
> +      Display Mode Library
> +
> +    DMCU
> +      Display Micro Controller Unit
> +
> +    DMCUB
> +      Display Micro-Controller Unit, version B

Make Micro Controller vs. Micro-Controller consistent for these.

> +
> +    DPCD
> +      DisplayPort Configuration Data
> +
> +    DPM(S)
> +      Display Power Management (Signaling)
> +
> +    DRR
> +      Dynamic Refresh Rate
> +
> +    DWB
> +      Display writeback
> +
> +    ECP
> +      Enhanced Content Protection
> +
> +    FB
> +      Frame Buffer
> +
> +    FBC
> +      Frame Buffer Compression
> +
> +    FEC
> +      Forward Error Correction
> +
> +    FRL
> +      Fixed Rate Link
> +
> +    GCO
> +      Graphical Controller Object
> +
> +    GMC
> +      Graphic Memory Controller
> +
> +    GSL
> +      Global Swap Lock
> +
> +    iGPU
> +      integrated GPU
> +
> +    IH
> +      Interrupt Handler
> +
> +    ISR
> +      Interrupt Service Request
> +
> +    ISV
> +      Independent Software Vendor
> +
> +    KMD
> +      Kernel Mode Driver
> +
> +    LB
> +      Line Buffer
> +
> +    LFC
> +      Low Framerate Compensation
> +
> +    LTTPR
> +      Link Training Tunable Phy Repeater
> +
> +    LUT
> +      Lookup Table
> +
> +    MALL
> +      Memory Access at Last Level
> +
> +    MC
> +      Memory Controller
> +
> +    MPC
> +      Multiple pipes and plane combine
> +
> +    MPO
> +      Multi Plane Overlay
> +
> +    MST
> +      Multi Stream Transport
> +
> +    NBP State
> +      Northbridge Power State
> +
> +    NBIO
> +      North Bridge Input/Output
> +
> +    ODM
> +      Output Data Mapping
> +
> +    OPM
> +      Output Protection Manager
> +
> +    OPP
> +      Output Plane Processor
> +
> +    OPTC
> +      Output Pipe Timing Combiner
> +
> +    OTG
> +      Output Timing Generator
> +
> +    PCON
> +      Power Controller
> +
> +    PGFSM
> +      Power Gate Finite State Machine
> +
> +    PPLib
> +      PowerPlay Library

Maybe say that powerplay is the power management component.

> +
> +    PSR
> +      Panel Self Refresh
> +
> +    SCL
> +      Scaler
> +
> +    SDP
> +      Scalable Data Port
> +
> +    SMU
> +      System Management Unit
> +
> +    SLS
> +      Single Large Surface
> +
> +    SST
> +      Single Stream Transport
> +
> +    TMDS
> +      Transition-Minimized Differential Signaling
> +
> +    TMZ
> +      Trusted Memory Zone
> +
> +    TTU
> +      Time to Underflow
> +
> +    VRR
> +      Variable Refresh Rate
> +
> +    UVD
> +      Unified Video Decoder
> +
> +    VCE
> +      Video Compression Engine
> +
> +    VCN
> +      Video Codec Next
> --
> 2.25.1
>

WARNING: multiple messages have this Message-ID (diff)
From: Alex Deucher <alexdeucher@gmail.com>
To: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: "Mark Yacoub" <markyacoub@chromium.org>,
	"Bhawanpreet Lakha" <bhawanpreet.lakha@amd.com>,
	nicholas.choi@amd.com,
	"Linux Doc Mailing List" <linux-doc@vger.kernel.org>,
	"Simon Ser" <contact@emersion.fr>,
	"Michel Dänzer" <michel@daenzer.net>,
	"Roman Li" <roman.li@amd.com>,
	"amd-gfx list" <amd-gfx@lists.freedesktop.org>,
	"Nicholas Kazlauskas" <nicholas.kazlauskas@amd.com>,
	"Marek Olšák" <marek.olsak@amd.com>,
	"Pekka Paalanen" <ppaalanen@gmail.com>,
	"Aurabindo Pillai" <aurabindo.pillai@amd.com>,
	"Sean Paul" <seanpaul@chromium.org>,
	"Maling list - DRI developers" <dri-devel@lists.freedesktop.org>,
	"Bas Nieuwenhuizen" <bas@basnieuwenhuizen.nl>,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Qingqing Zhuo" <qingqing.zhuo@amd.com>,
	"Christian König" <christian.koenig@amd.com>,
	"Harry Wentland" <Harry.Wentland@amd.com>,
	"Roman Gilg" <subdiff@gmail.com>
Subject: Re: [PATCH 6/6] Documentation/gpu: Add DC glossary
Date: Mon, 29 Nov 2021 15:08:55 -0500	[thread overview]
Message-ID: <CADnq5_NVcHizoY_xRM4d09B2s9DzWwDhn=YrgJ-3COXNANzE3A@mail.gmail.com> (raw)
In-Reply-To: <20211125153830.1352994-7-Rodrigo.Siqueira@amd.com>

On Thu, Nov 25, 2021 at 10:40 AM Rodrigo Siqueira
<Rodrigo.Siqueira@amd.com> wrote:
>
> In the DC driver, we have multiple acronyms that are not obvious most of
> the time. This commit introduces a DC glossary in order to make it
> easier to navigate through our driver.
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
>  Documentation/gpu/amdgpu-dc/amdgpu-dc.rst   |   2 +-
>  Documentation/gpu/amdgpu-dc/dc-glossary.rst | 257 ++++++++++++++++++++
>  2 files changed, 258 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/gpu/amdgpu-dc/dc-glossary.rst
>
> diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst
> index 2e45e83d9a2a..15405c43786a 100644
> --- a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst
> +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst
> @@ -26,4 +26,4 @@ table of content:
>     amdgpu-dcn-overview.rst
>     amdgpu-dm.rst
>     amdgpu-dc-debug.rst
> -
> +   dc-glossary.rst
> diff --git a/Documentation/gpu/amdgpu-dc/dc-glossary.rst b/Documentation/gpu/amdgpu-dc/dc-glossary.rst
> new file mode 100644
> index 000000000000..48698fc1799f
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu-dc/dc-glossary.rst
> @@ -0,0 +1,257 @@
> +===========
> +DC Glossary
> +===========
> +
> +.. glossary::
> +
> +    ABM
> +      Adaptive Backlight Modulation
> +
> +    APU
> +      Accelerated Processing Unit
> +
> +    ASIC
> +      Application-Specific Integrated Circuit
> +
> +    ASSR
> +      Alternate Scrambler Seed Reset
> +
> +    AZ
> +      Azalia (HD audio DMA engine)
> +
> +    BPC
> +      Bits Per Colour/Component
> +
> +    BPP
> +      Bits Per Pixel
> +
> +    Clocks
> +      * PCLK: Pixel Clock
> +      * SYMCLK: Symbol Clock
> +      * SOCCLK: GPU Engine Clock
> +      * DISPCLK: Display Clock
> +      * DPPCLK: DPP Clock
> +      * DCFCLK: Display Controller Fabric Clock
> +      * REFCLK: Real Time Reference Clock
> +      * PPLL: Pixel PLL
> +      * FCLK: Fabric Clock
> +      * MCLK: Memory Clock
> +      * CPLIB: Content Protection Library

CPLIB is not a clock.  It should be split out as its own item.

> +
> +    CRC
> +      Cyclic Redundancy Check
> +
> +    CRTC
> +      Cathode Ray Tube Controller - commonly called "Controller" - Generates
> +      raw stream of pixels, clocked at pixel clock
> +
> +    CVT
> +      Coordinated Video Timings
> +
> +    DAL
> +      Display Abstraction layer
> +
> +    DC (Software)
> +      Display Core
> +
> +    DC (Hardware)
> +      Display Controller
> +
> +    DCC
> +      Delta Colour Compression
> +
> +    DCE
> +      Display Controller Engine
> +
> +    DCHUB
> +      Display Controller Hub
> +
> +    ARB
> +      Arbiter
> +
> +    VTG
> +      Vertical Timing Generator
> +
> +    DCN
> +      Display Core Next
> +
> +    DCCG
> +      Display Clock Generator block
> +
> +    DDC
> +      Display Data Channel
> +
> +    DFS
> +      Digital Frequency Synthesizer
> +
> +    DIO
> +      Display IO
> +
> +    DPP
> +      Display Pipes and Planes
> +
> +    DSC
> +      Display Stream Compression (Reduce the amount of bits to represent pixel
> +      count while at the same pixel clock)
> +
> +    dGPU
> +      discrete GPU
> +
> +    DMIF
> +      Display Memory Interface
> +
> +    DML
> +      Display Mode Library
> +
> +    DMCU
> +      Display Micro Controller Unit
> +
> +    DMCUB
> +      Display Micro-Controller Unit, version B

Make Micro Controller vs. Micro-Controller consistent for these.

> +
> +    DPCD
> +      DisplayPort Configuration Data
> +
> +    DPM(S)
> +      Display Power Management (Signaling)
> +
> +    DRR
> +      Dynamic Refresh Rate
> +
> +    DWB
> +      Display writeback
> +
> +    ECP
> +      Enhanced Content Protection
> +
> +    FB
> +      Frame Buffer
> +
> +    FBC
> +      Frame Buffer Compression
> +
> +    FEC
> +      Forward Error Correction
> +
> +    FRL
> +      Fixed Rate Link
> +
> +    GCO
> +      Graphical Controller Object
> +
> +    GMC
> +      Graphic Memory Controller
> +
> +    GSL
> +      Global Swap Lock
> +
> +    iGPU
> +      integrated GPU
> +
> +    IH
> +      Interrupt Handler
> +
> +    ISR
> +      Interrupt Service Request
> +
> +    ISV
> +      Independent Software Vendor
> +
> +    KMD
> +      Kernel Mode Driver
> +
> +    LB
> +      Line Buffer
> +
> +    LFC
> +      Low Framerate Compensation
> +
> +    LTTPR
> +      Link Training Tunable Phy Repeater
> +
> +    LUT
> +      Lookup Table
> +
> +    MALL
> +      Memory Access at Last Level
> +
> +    MC
> +      Memory Controller
> +
> +    MPC
> +      Multiple pipes and plane combine
> +
> +    MPO
> +      Multi Plane Overlay
> +
> +    MST
> +      Multi Stream Transport
> +
> +    NBP State
> +      Northbridge Power State
> +
> +    NBIO
> +      North Bridge Input/Output
> +
> +    ODM
> +      Output Data Mapping
> +
> +    OPM
> +      Output Protection Manager
> +
> +    OPP
> +      Output Plane Processor
> +
> +    OPTC
> +      Output Pipe Timing Combiner
> +
> +    OTG
> +      Output Timing Generator
> +
> +    PCON
> +      Power Controller
> +
> +    PGFSM
> +      Power Gate Finite State Machine
> +
> +    PPLib
> +      PowerPlay Library

Maybe say that powerplay is the power management component.

> +
> +    PSR
> +      Panel Self Refresh
> +
> +    SCL
> +      Scaler
> +
> +    SDP
> +      Scalable Data Port
> +
> +    SMU
> +      System Management Unit
> +
> +    SLS
> +      Single Large Surface
> +
> +    SST
> +      Single Stream Transport
> +
> +    TMDS
> +      Transition-Minimized Differential Signaling
> +
> +    TMZ
> +      Trusted Memory Zone
> +
> +    TTU
> +      Time to Underflow
> +
> +    VRR
> +      Variable Refresh Rate
> +
> +    UVD
> +      Unified Video Decoder
> +
> +    VCE
> +      Video Compression Engine
> +
> +    VCN
> +      Video Codec Next
> --
> 2.25.1
>

WARNING: multiple messages have this Message-ID (diff)
From: Alex Deucher <alexdeucher@gmail.com>
To: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: "Simon Ser" <contact@emersion.fr>,
	"Michel Dänzer" <michel@daenzer.net>,
	"Bas Nieuwenhuizen" <bas@basnieuwenhuizen.nl>,
	"Marek Olšák" <marek.olsak@amd.com>,
	"Roman Gilg" <subdiff@gmail.com>,
	"Nicholas Kazlauskas" <nicholas.kazlauskas@amd.com>,
	"Harry Wentland" <Harry.Wentland@amd.com>,
	"Mark Yacoub" <markyacoub@chromium.org>,
	"Sean Paul" <seanpaul@chromium.org>,
	"Pekka Paalanen" <ppaalanen@gmail.com>,
	"Linux Doc Mailing List" <linux-doc@vger.kernel.org>,
	"Qingqing Zhuo" <qingqing.zhuo@amd.com>,
	"Roman Li" <roman.li@amd.com>,
	"amd-gfx list" <amd-gfx@lists.freedesktop.org>,
	"Aurabindo Pillai" <aurabindo.pillai@amd.com>,
	nicholas.choi@amd.com,
	"Maling list - DRI developers" <dri-devel@lists.freedesktop.org>,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Bhawanpreet Lakha" <bhawanpreet.lakha@amd.com>,
	"Christian König" <christian.koenig@amd.com>
Subject: Re: [PATCH 6/6] Documentation/gpu: Add DC glossary
Date: Mon, 29 Nov 2021 15:08:55 -0500	[thread overview]
Message-ID: <CADnq5_NVcHizoY_xRM4d09B2s9DzWwDhn=YrgJ-3COXNANzE3A@mail.gmail.com> (raw)
In-Reply-To: <20211125153830.1352994-7-Rodrigo.Siqueira@amd.com>

On Thu, Nov 25, 2021 at 10:40 AM Rodrigo Siqueira
<Rodrigo.Siqueira@amd.com> wrote:
>
> In the DC driver, we have multiple acronyms that are not obvious most of
> the time. This commit introduces a DC glossary in order to make it
> easier to navigate through our driver.
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
>  Documentation/gpu/amdgpu-dc/amdgpu-dc.rst   |   2 +-
>  Documentation/gpu/amdgpu-dc/dc-glossary.rst | 257 ++++++++++++++++++++
>  2 files changed, 258 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/gpu/amdgpu-dc/dc-glossary.rst
>
> diff --git a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst
> index 2e45e83d9a2a..15405c43786a 100644
> --- a/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst
> +++ b/Documentation/gpu/amdgpu-dc/amdgpu-dc.rst
> @@ -26,4 +26,4 @@ table of content:
>     amdgpu-dcn-overview.rst
>     amdgpu-dm.rst
>     amdgpu-dc-debug.rst
> -
> +   dc-glossary.rst
> diff --git a/Documentation/gpu/amdgpu-dc/dc-glossary.rst b/Documentation/gpu/amdgpu-dc/dc-glossary.rst
> new file mode 100644
> index 000000000000..48698fc1799f
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu-dc/dc-glossary.rst
> @@ -0,0 +1,257 @@
> +===========
> +DC Glossary
> +===========
> +
> +.. glossary::
> +
> +    ABM
> +      Adaptive Backlight Modulation
> +
> +    APU
> +      Accelerated Processing Unit
> +
> +    ASIC
> +      Application-Specific Integrated Circuit
> +
> +    ASSR
> +      Alternate Scrambler Seed Reset
> +
> +    AZ
> +      Azalia (HD audio DMA engine)
> +
> +    BPC
> +      Bits Per Colour/Component
> +
> +    BPP
> +      Bits Per Pixel
> +
> +    Clocks
> +      * PCLK: Pixel Clock
> +      * SYMCLK: Symbol Clock
> +      * SOCCLK: GPU Engine Clock
> +      * DISPCLK: Display Clock
> +      * DPPCLK: DPP Clock
> +      * DCFCLK: Display Controller Fabric Clock
> +      * REFCLK: Real Time Reference Clock
> +      * PPLL: Pixel PLL
> +      * FCLK: Fabric Clock
> +      * MCLK: Memory Clock
> +      * CPLIB: Content Protection Library

CPLIB is not a clock.  It should be split out as its own item.

> +
> +    CRC
> +      Cyclic Redundancy Check
> +
> +    CRTC
> +      Cathode Ray Tube Controller - commonly called "Controller" - Generates
> +      raw stream of pixels, clocked at pixel clock
> +
> +    CVT
> +      Coordinated Video Timings
> +
> +    DAL
> +      Display Abstraction layer
> +
> +    DC (Software)
> +      Display Core
> +
> +    DC (Hardware)
> +      Display Controller
> +
> +    DCC
> +      Delta Colour Compression
> +
> +    DCE
> +      Display Controller Engine
> +
> +    DCHUB
> +      Display Controller Hub
> +
> +    ARB
> +      Arbiter
> +
> +    VTG
> +      Vertical Timing Generator
> +
> +    DCN
> +      Display Core Next
> +
> +    DCCG
> +      Display Clock Generator block
> +
> +    DDC
> +      Display Data Channel
> +
> +    DFS
> +      Digital Frequency Synthesizer
> +
> +    DIO
> +      Display IO
> +
> +    DPP
> +      Display Pipes and Planes
> +
> +    DSC
> +      Display Stream Compression (Reduce the amount of bits to represent pixel
> +      count while at the same pixel clock)
> +
> +    dGPU
> +      discrete GPU
> +
> +    DMIF
> +      Display Memory Interface
> +
> +    DML
> +      Display Mode Library
> +
> +    DMCU
> +      Display Micro Controller Unit
> +
> +    DMCUB
> +      Display Micro-Controller Unit, version B

Make Micro Controller vs. Micro-Controller consistent for these.

> +
> +    DPCD
> +      DisplayPort Configuration Data
> +
> +    DPM(S)
> +      Display Power Management (Signaling)
> +
> +    DRR
> +      Dynamic Refresh Rate
> +
> +    DWB
> +      Display writeback
> +
> +    ECP
> +      Enhanced Content Protection
> +
> +    FB
> +      Frame Buffer
> +
> +    FBC
> +      Frame Buffer Compression
> +
> +    FEC
> +      Forward Error Correction
> +
> +    FRL
> +      Fixed Rate Link
> +
> +    GCO
> +      Graphical Controller Object
> +
> +    GMC
> +      Graphic Memory Controller
> +
> +    GSL
> +      Global Swap Lock
> +
> +    iGPU
> +      integrated GPU
> +
> +    IH
> +      Interrupt Handler
> +
> +    ISR
> +      Interrupt Service Request
> +
> +    ISV
> +      Independent Software Vendor
> +
> +    KMD
> +      Kernel Mode Driver
> +
> +    LB
> +      Line Buffer
> +
> +    LFC
> +      Low Framerate Compensation
> +
> +    LTTPR
> +      Link Training Tunable Phy Repeater
> +
> +    LUT
> +      Lookup Table
> +
> +    MALL
> +      Memory Access at Last Level
> +
> +    MC
> +      Memory Controller
> +
> +    MPC
> +      Multiple pipes and plane combine
> +
> +    MPO
> +      Multi Plane Overlay
> +
> +    MST
> +      Multi Stream Transport
> +
> +    NBP State
> +      Northbridge Power State
> +
> +    NBIO
> +      North Bridge Input/Output
> +
> +    ODM
> +      Output Data Mapping
> +
> +    OPM
> +      Output Protection Manager
> +
> +    OPP
> +      Output Plane Processor
> +
> +    OPTC
> +      Output Pipe Timing Combiner
> +
> +    OTG
> +      Output Timing Generator
> +
> +    PCON
> +      Power Controller
> +
> +    PGFSM
> +      Power Gate Finite State Machine
> +
> +    PPLib
> +      PowerPlay Library

Maybe say that powerplay is the power management component.

> +
> +    PSR
> +      Panel Self Refresh
> +
> +    SCL
> +      Scaler
> +
> +    SDP
> +      Scalable Data Port
> +
> +    SMU
> +      System Management Unit
> +
> +    SLS
> +      Single Large Surface
> +
> +    SST
> +      Single Stream Transport
> +
> +    TMDS
> +      Transition-Minimized Differential Signaling
> +
> +    TMZ
> +      Trusted Memory Zone
> +
> +    TTU
> +      Time to Underflow
> +
> +    VRR
> +      Variable Refresh Rate
> +
> +    UVD
> +      Unified Video Decoder
> +
> +    VCE
> +      Video Compression Engine
> +
> +    VCN
> +      Video Codec Next
> --
> 2.25.1
>

  reply	other threads:[~2021-11-29 20:09 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-25 15:38 [PATCH 0/6] Expand display core documentation Rodrigo Siqueira
2021-11-25 15:38 ` Rodrigo Siqueira
2021-11-25 15:38 ` [PATCH 1/6] Documentation/gpu: Reorganize DC documentation Rodrigo Siqueira
2021-11-25 15:38   ` Rodrigo Siqueira
2021-11-26 10:35   ` Christian König
2021-11-26 15:40     ` Daniel Vetter
2021-11-26 15:40       ` Daniel Vetter
2021-11-26 15:40       ` Daniel Vetter
2021-11-26 15:42   ` Daniel Vetter
2021-11-26 15:42     ` Daniel Vetter
2021-11-26 15:42     ` Daniel Vetter
2021-11-29 12:06     ` Jani Nikula
2021-11-29 12:06       ` Jani Nikula
2021-11-30 15:46       ` Rodrigo Siqueira Jordao
2021-11-30 15:46         ` Rodrigo Siqueira Jordao
2021-11-30 15:48         ` Harry Wentland
2021-11-30 15:48           ` Harry Wentland
2021-11-30 15:59           ` Rodrigo Siqueira Jordao
2021-11-30 15:59             ` Rodrigo Siqueira Jordao
2021-11-30 16:03             ` Harry Wentland
2021-11-30 16:03               ` Harry Wentland
2021-11-30 20:38             ` Yann Dirson
2021-11-30 20:38               ` Yann Dirson
2021-11-30 20:38               ` Yann Dirson
2021-11-25 15:38 ` [PATCH 2/6] Documentation/gpu: Document amdgpu_dm_visual_confirm debugfs entry Rodrigo Siqueira
2021-11-25 15:38   ` Rodrigo Siqueira
2021-11-25 15:38 ` [PATCH 3/6] Documentation/gpu: Document pipe split visual confirmation Rodrigo Siqueira
2021-11-25 15:38   ` Rodrigo Siqueira
2021-11-25 15:38 ` [PATCH 4/6] Documentation/gpu: How to collect DTN log Rodrigo Siqueira
2021-11-25 15:38   ` Rodrigo Siqueira
2021-11-25 15:38 ` [PATCH 5/6] Documentation/gpu: Add basic overview of DC pipeline Rodrigo Siqueira
2021-11-25 15:38 ` [PATCH 6/6] Documentation/gpu: Add DC glossary Rodrigo Siqueira
2021-11-25 15:38   ` Rodrigo Siqueira
2021-11-29 20:08   ` Alex Deucher [this message]
2021-11-29 20:08     ` Alex Deucher
2021-11-29 20:08     ` Alex Deucher
2021-11-29 20:48     ` ydirson
2021-11-29 20:48       ` ydirson
2021-11-29 20:48       ` ydirson
2021-11-30 10:09       ` Christian König
2021-11-30 10:09         ` Christian König
2021-11-30 10:09         ` Christian König
2021-11-30 14:39       ` Alex Deucher
2021-11-30 14:39         ` Alex Deucher
2021-11-30 14:39         ` Alex Deucher
2021-11-30 15:53       ` Rodrigo Siqueira Jordao
2021-11-30 15:53         ` Rodrigo Siqueira Jordao
2021-11-30 15:53         ` Rodrigo Siqueira Jordao
2021-11-30 19:55         ` Yann Dirson
2021-11-30 19:55           ` Yann Dirson
2021-11-30 19:55           ` Yann Dirson

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