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* [PATCH] drm/amdgpu: change pp_dpm clk/mclk/pcie input format
@ 2018-04-19 20:51 welu
       [not found] ` <1524171079-657-1-git-send-email-wei.lu2-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 4+ messages in thread
From: welu @ 2018-04-19 20:51 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: welu

1. support more than 8 values when setting get_pp_dpm_mclk/
sclk/pcie, the former design just parse command format like
"echo xxxx >　pp_dpm_sclk" and current can parse "echo xx xxx
 xxxx > pp_dpm_sclk" whose operation is more user-friendly
and convinent and can offer more values;
2. be compatible with former design like "xx".
Bug:KFD-385

Change-Id: Id7d95ce45f4ee0564b18ebcfc16976f1a5c6bf72
Signed-off-by: welu <wei.lu2@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 95 ++++++++++++++++++++--------------
 1 file changed, 55 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 744f105..58f46f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -466,23 +466,27 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 	struct amdgpu_device *adev = ddev->dev_private;
 	int ret;
 	long level;
-	uint32_t i, mask = 0;
-	char sub_str[2];
+	uint32_t mask = 0;
+	char *sub_str = NULL;
+	char *tmp;
+	char buf_cpy[count];
+	const char delimiter[3] = {' ', '\n', '\0'};
 
-	for (i = 0; i < strlen(buf); i++) {
-		if (*(buf + i) == '\n')
-			continue;
-		sub_str[0] = *(buf + i);
-		sub_str[1] = '\0';
-		ret = kstrtol(sub_str, 0, &level);
+	memcpy(buf_cpy, buf, count+1);
+	tmp = buf_cpy;
+	while (tmp[0]) {
+		sub_str =  strsep(&tmp, delimiter);
+		if (strlen(sub_str)) {
+			ret = kstrtol(sub_str, 0, &level);
 
-		if (ret) {
-			count = -EINVAL;
-			goto fail;
-		}
-		mask |= 1 << level;
+			if (ret) {
+				count = -EINVAL;
+				goto fail;
+			}
+			mask |= 1 << level;
+		} else
+			break;
 	}
-
 	if (adev->powerplay.pp_funcs->force_clock_level)
 		amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 
@@ -512,21 +516,26 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 	struct amdgpu_device *adev = ddev->dev_private;
 	int ret;
 	long level;
-	uint32_t i, mask = 0;
-	char sub_str[2];
+	uint32_t mask = 0;
+	char *sub_str = NULL;
+	char *tmp;
+	char buf_cpy[count];
+	const char delimiter[3] = {' ', '\n', '\0'};
 
-	for (i = 0; i < strlen(buf); i++) {
-		if (*(buf + i) == '\n')
-			continue;
-		sub_str[0] = *(buf + i);
-		sub_str[1] = '\0';
-		ret = kstrtol(sub_str, 0, &level);
+	memcpy(buf_cpy, buf, count+1);
+	tmp = buf_cpy;
+	while (tmp[0]) {
+		sub_str =  strsep(&tmp, delimiter);
+		if (strlen(sub_str)) {
+			ret = kstrtol(sub_str, 0, &level);
 
-		if (ret) {
-			count = -EINVAL;
-			goto fail;
-		}
-		mask |= 1 << level;
+			if (ret) {
+				count = -EINVAL;
+				goto fail;
+			}
+			mask |= 1 << level;
+		} else
+			break;
 	}
 	if (adev->powerplay.pp_funcs->force_clock_level)
 		amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -557,21 +566,27 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 	struct amdgpu_device *adev = ddev->dev_private;
 	int ret;
 	long level;
-	uint32_t i, mask = 0;
-	char sub_str[2];
+	uint32_t mask = 0;
+	char *sub_str = NULL;
+	char *tmp;
+	char buf_cpy[count];
+	const char delimiter[3] = {' ', '\n', '\0'};
 
-	for (i = 0; i < strlen(buf); i++) {
-		if (*(buf + i) == '\n')
-			continue;
-		sub_str[0] = *(buf + i);
-		sub_str[1] = '\0';
-		ret = kstrtol(sub_str, 0, &level);
+	memcpy(buf_cpy, buf, count+1);
+	tmp = buf_cpy;
 
-		if (ret) {
-			count = -EINVAL;
-			goto fail;
-		}
-		mask |= 1 << level;
+	while (tmp[0]) {
+		sub_str =  strsep(&tmp, delimiter);
+		if (strlen(sub_str)) {
+			ret = kstrtol(sub_str, 0, &level);
+
+			if (ret) {
+				count = -EINVAL;
+				goto fail;
+			}
+			mask |= 1 << level;
+		} else
+			break;
 	}
 	if (adev->powerplay.pp_funcs->force_clock_level)
 		amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: change pp_dpm clk/mclk/pcie input format
       [not found] ` <1524171079-657-1-git-send-email-wei.lu2-5C7GfCeVMHo@public.gmane.org>
@ 2018-04-23 20:06   ` Alex Deucher
       [not found]     ` <CADnq5_NyeoyGQTqq3okvFpjNrRN2CSU+trFSTENT9cor2=aj7w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
  0 siblings, 1 reply; 4+ messages in thread
From: Alex Deucher @ 2018-04-23 20:06 UTC (permalink / raw)
  To: welu; +Cc: amd-gfx list

On Thu, Apr 19, 2018 at 4:51 PM, welu <wei.lu2@amd.com> wrote:
> 1. support more than 8 values when setting get_pp_dpm_mclk/
> sclk/pcie, the former design just parse command format like
> "echo xxxx >　pp_dpm_sclk" and current can parse "echo xx xxx
>  xxxx > pp_dpm_sclk" whose operation is more user-friendly
> and convinent and can offer more values;
> 2. be compatible with former design like "xx".
> Bug:KFD-385

Please update the documentation labeled "DOC: pp_dpm_sclk pp_dpm_mclk
pp_dpm_pcie", With that fixed, patch is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

>
> Change-Id: Id7d95ce45f4ee0564b18ebcfc16976f1a5c6bf72
> Signed-off-by: welu <wei.lu2@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 95 ++++++++++++++++++++--------------
>  1 file changed, 55 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 744f105..58f46f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -466,23 +466,27 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
>         struct amdgpu_device *adev = ddev->dev_private;
>         int ret;
>         long level;
> -       uint32_t i, mask = 0;
> -       char sub_str[2];
> +       uint32_t mask = 0;
> +       char *sub_str = NULL;
> +       char *tmp;
> +       char buf_cpy[count];
> +       const char delimiter[3] = {' ', '\n', '\0'};
>
> -       for (i = 0; i < strlen(buf); i++) {
> -               if (*(buf + i) == '\n')
> -                       continue;
> -               sub_str[0] = *(buf + i);
> -               sub_str[1] = '\0';
> -               ret = kstrtol(sub_str, 0, &level);
> +       memcpy(buf_cpy, buf, count+1);
> +       tmp = buf_cpy;
> +       while (tmp[0]) {
> +               sub_str =  strsep(&tmp, delimiter);
> +               if (strlen(sub_str)) {
> +                       ret = kstrtol(sub_str, 0, &level);
>
> -               if (ret) {
> -                       count = -EINVAL;
> -                       goto fail;
> -               }
> -               mask |= 1 << level;
> +                       if (ret) {
> +                               count = -EINVAL;
> +                               goto fail;
> +                       }
> +                       mask |= 1 << level;
> +               } else
> +                       break;
>         }
> -
>         if (adev->powerplay.pp_funcs->force_clock_level)
>                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
>
> @@ -512,21 +516,26 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
>         struct amdgpu_device *adev = ddev->dev_private;
>         int ret;
>         long level;
> -       uint32_t i, mask = 0;
> -       char sub_str[2];
> +       uint32_t mask = 0;
> +       char *sub_str = NULL;
> +       char *tmp;
> +       char buf_cpy[count];
> +       const char delimiter[3] = {' ', '\n', '\0'};
>
> -       for (i = 0; i < strlen(buf); i++) {
> -               if (*(buf + i) == '\n')
> -                       continue;
> -               sub_str[0] = *(buf + i);
> -               sub_str[1] = '\0';
> -               ret = kstrtol(sub_str, 0, &level);
> +       memcpy(buf_cpy, buf, count+1);
> +       tmp = buf_cpy;
> +       while (tmp[0]) {
> +               sub_str =  strsep(&tmp, delimiter);
> +               if (strlen(sub_str)) {
> +                       ret = kstrtol(sub_str, 0, &level);
>
> -               if (ret) {
> -                       count = -EINVAL;
> -                       goto fail;
> -               }
> -               mask |= 1 << level;
> +                       if (ret) {
> +                               count = -EINVAL;
> +                               goto fail;
> +                       }
> +                       mask |= 1 << level;
> +               } else
> +                       break;
>         }
>         if (adev->powerplay.pp_funcs->force_clock_level)
>                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
> @@ -557,21 +566,27 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
>         struct amdgpu_device *adev = ddev->dev_private;
>         int ret;
>         long level;
> -       uint32_t i, mask = 0;
> -       char sub_str[2];
> +       uint32_t mask = 0;
> +       char *sub_str = NULL;
> +       char *tmp;
> +       char buf_cpy[count];
> +       const char delimiter[3] = {' ', '\n', '\0'};
>
> -       for (i = 0; i < strlen(buf); i++) {
> -               if (*(buf + i) == '\n')
> -                       continue;
> -               sub_str[0] = *(buf + i);
> -               sub_str[1] = '\0';
> -               ret = kstrtol(sub_str, 0, &level);
> +       memcpy(buf_cpy, buf, count+1);
> +       tmp = buf_cpy;
>
> -               if (ret) {
> -                       count = -EINVAL;
> -                       goto fail;
> -               }
> -               mask |= 1 << level;
> +       while (tmp[0]) {
> +               sub_str =  strsep(&tmp, delimiter);
> +               if (strlen(sub_str)) {
> +                       ret = kstrtol(sub_str, 0, &level);
> +
> +                       if (ret) {
> +                               count = -EINVAL;
> +                               goto fail;
> +                       }
> +                       mask |= 1 << level;
> +               } else
> +                       break;
>         }
>         if (adev->powerplay.pp_funcs->force_clock_level)
>                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: change pp_dpm clk/mclk/pcie input format
       [not found]     ` <CADnq5_NyeoyGQTqq3okvFpjNrRN2CSU+trFSTENT9cor2=aj7w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-04-24 13:22       ` Lu, Wei
  0 siblings, 0 replies; 4+ messages in thread
From: Lu, Wei @ 2018-04-24 13:22 UTC (permalink / raw)
  To: Alex Deucher; +Cc: amd-gfx list


[-- Attachment #1.1: Type: text/plain, Size: 6383 bytes --]

hi Alex,


I have sent the patch with "Add: DOC " and last patch to  amd-gfx-PD4FTy7X32mzQB+pC5nmwQ@public.gmane.orgedesktop.org already.

please check.


Thanks!


Wei

________________________________
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: 23 April 2018 16:06:16
To: Lu, Wei
Cc: amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: change pp_dpm clk/mclk/pcie input format

On Thu, Apr 19, 2018 at 4:51 PM, welu <wei.lu2-5C7GfCeVMHo@public.gmane.org> wrote:
> 1. support more than 8 values when setting get_pp_dpm_mclk/
> sclk/pcie, the former design just parse command format like
> "echo xxxx >　pp_dpm_sclk" and current can parse "echo xx xxx
>  xxxx > pp_dpm_sclk" whose operation is more user-friendly
> and convinent and can offer more values;
> 2. be compatible with former design like "xx".
> Bug:KFD-385

Please update the documentation labeled "DOC: pp_dpm_sclk pp_dpm_mclk
pp_dpm_pcie", With that fixed, patch is:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>

>
> Change-Id: Id7d95ce45f4ee0564b18ebcfc16976f1a5c6bf72
> Signed-off-by: welu <wei.lu2-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 95 ++++++++++++++++++++--------------
>  1 file changed, 55 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 744f105..58f46f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -466,23 +466,27 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
>         struct amdgpu_device *adev = ddev->dev_private;
>         int ret;
>         long level;
> -       uint32_t i, mask = 0;
> -       char sub_str[2];
> +       uint32_t mask = 0;
> +       char *sub_str = NULL;
> +       char *tmp;
> +       char buf_cpy[count];
> +       const char delimiter[3] = {' ', '\n', '\0'};
>
> -       for (i = 0; i < strlen(buf); i++) {
> -               if (*(buf + i) == '\n')
> -                       continue;
> -               sub_str[0] = *(buf + i);
> -               sub_str[1] = '\0';
> -               ret = kstrtol(sub_str, 0, &level);
> +       memcpy(buf_cpy, buf, count+1);
> +       tmp = buf_cpy;
> +       while (tmp[0]) {
> +               sub_str =  strsep(&tmp, delimiter);
> +               if (strlen(sub_str)) {
> +                       ret = kstrtol(sub_str, 0, &level);
>
> -               if (ret) {
> -                       count = -EINVAL;
> -                       goto fail;
> -               }
> -               mask |= 1 << level;
> +                       if (ret) {
> +                               count = -EINVAL;
> +                               goto fail;
> +                       }
> +                       mask |= 1 << level;
> +               } else
> +                       break;
>         }
> -
>         if (adev->powerplay.pp_funcs->force_clock_level)
>                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
>
> @@ -512,21 +516,26 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
>         struct amdgpu_device *adev = ddev->dev_private;
>         int ret;
>         long level;
> -       uint32_t i, mask = 0;
> -       char sub_str[2];
> +       uint32_t mask = 0;
> +       char *sub_str = NULL;
> +       char *tmp;
> +       char buf_cpy[count];
> +       const char delimiter[3] = {' ', '\n', '\0'};
>
> -       for (i = 0; i < strlen(buf); i++) {
> -               if (*(buf + i) == '\n')
> -                       continue;
> -               sub_str[0] = *(buf + i);
> -               sub_str[1] = '\0';
> -               ret = kstrtol(sub_str, 0, &level);
> +       memcpy(buf_cpy, buf, count+1);
> +       tmp = buf_cpy;
> +       while (tmp[0]) {
> +               sub_str =  strsep(&tmp, delimiter);
> +               if (strlen(sub_str)) {
> +                       ret = kstrtol(sub_str, 0, &level);
>
> -               if (ret) {
> -                       count = -EINVAL;
> -                       goto fail;
> -               }
> -               mask |= 1 << level;
> +                       if (ret) {
> +                               count = -EINVAL;
> +                               goto fail;
> +                       }
> +                       mask |= 1 << level;
> +               } else
> +                       break;
>         }
>         if (adev->powerplay.pp_funcs->force_clock_level)
>                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
> @@ -557,21 +566,27 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
>         struct amdgpu_device *adev = ddev->dev_private;
>         int ret;
>         long level;
> -       uint32_t i, mask = 0;
> -       char sub_str[2];
> +       uint32_t mask = 0;
> +       char *sub_str = NULL;
> +       char *tmp;
> +       char buf_cpy[count];
> +       const char delimiter[3] = {' ', '\n', '\0'};
>
> -       for (i = 0; i < strlen(buf); i++) {
> -               if (*(buf + i) == '\n')
> -                       continue;
> -               sub_str[0] = *(buf + i);
> -               sub_str[1] = '\0';
> -               ret = kstrtol(sub_str, 0, &level);
> +       memcpy(buf_cpy, buf, count+1);
> +       tmp = buf_cpy;
>
> -               if (ret) {
> -                       count = -EINVAL;
> -                       goto fail;
> -               }
> -               mask |= 1 << level;
> +       while (tmp[0]) {
> +               sub_str =  strsep(&tmp, delimiter);
> +               if (strlen(sub_str)) {
> +                       ret = kstrtol(sub_str, 0, &level);
> +
> +                       if (ret) {
> +                               count = -EINVAL;
> +                               goto fail;
> +                       }
> +                       mask |= 1 << level;
> +               } else
> +                       break;
>         }
>         if (adev->powerplay.pp_funcs->force_clock_level)
>                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [PATCH] drm/amdgpu: change pp_dpm clk/mclk/pcie input format.
@ 2018-04-24 13:20 welu
  0 siblings, 0 replies; 4+ messages in thread
From: welu @ 2018-04-24 13:20 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: welu

1. support more than 8 values when setting get_pp_dpm_mclk/
sclk/pcie, the former design just parse command format like
"echo xxxx >　pp_dpm_sclk" and current can parse "echo xx xxx
 xxxx > pp_dpm_sclk" whose operation is more user-friendly
and convinent and can offer more values;
2. be compatible with former design like "xx".
3. add DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
Bug:KFD-385
Tested-by: Wei Lu <wei.lu2@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: welu <wei.lu2@amd.com>

Change-Id: I29f1b68fa7fc1f4982854359a3bd2d6ea6e48005
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 103 +++++++++++++++++++--------------
 1 file changed, 59 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 27d8dd7..d9802d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -574,10 +574,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the power state and the clock information for those levels.
  *
  * To manually adjust these states, first select manual using
- * power_dpm_force_performance_level.  Writing a string of the level
- * numbers to the file will select which levels you want to enable.
- * E.g., writing 456 to the file will enable levels 4, 5, and 6.
- *
+ * power_dpm_force_performance_level.
+ * Secondly,Enter a new value for each level by inputing a string that
+ * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
+ * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
  */
 
 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
@@ -602,23 +602,27 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 	struct amdgpu_device *adev = ddev->dev_private;
 	int ret;
 	long level;
-	uint32_t i, mask = 0;
-	char sub_str[2];
+	uint32_t mask = 0;
+	char *sub_str = NULL;
+	char *tmp;
+	char buf_cpy[count];
+	const char delimiter[3] = {' ', '\n', '\0'};
 
-	for (i = 0; i < strlen(buf); i++) {
-		if (*(buf + i) == '\n')
-			continue;
-		sub_str[0] = *(buf + i);
-		sub_str[1] = '\0';
-		ret = kstrtol(sub_str, 0, &level);
+	memcpy(buf_cpy, buf, count+1);
+	tmp = buf_cpy;
+	while (tmp[0]) {
+		sub_str =  strsep(&tmp, delimiter);
+		if (strlen(sub_str)) {
+			ret = kstrtol(sub_str, 0, &level);
 
-		if (ret) {
-			count = -EINVAL;
-			goto fail;
-		}
-		mask |= 1 << level;
+			if (ret) {
+				count = -EINVAL;
+				goto fail;
+			}
+			mask |= 1 << level;
+		} else
+			break;
 	}
-
 	if (adev->powerplay.pp_funcs->force_clock_level)
 		amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 
@@ -648,21 +652,26 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 	struct amdgpu_device *adev = ddev->dev_private;
 	int ret;
 	long level;
-	uint32_t i, mask = 0;
-	char sub_str[2];
+	uint32_t mask = 0;
+	char *sub_str = NULL;
+	char *tmp;
+	char buf_cpy[count];
+	const char delimiter[3] = {' ', '\n', '\0'};
 
-	for (i = 0; i < strlen(buf); i++) {
-		if (*(buf + i) == '\n')
-			continue;
-		sub_str[0] = *(buf + i);
-		sub_str[1] = '\0';
-		ret = kstrtol(sub_str, 0, &level);
+	memcpy(buf_cpy, buf, count+1);
+	tmp = buf_cpy;
+	while (tmp[0]) {
+		sub_str =  strsep(&tmp, delimiter);
+		if (strlen(sub_str)) {
+			ret = kstrtol(sub_str, 0, &level);
 
-		if (ret) {
-			count = -EINVAL;
-			goto fail;
-		}
-		mask |= 1 << level;
+			if (ret) {
+				count = -EINVAL;
+				goto fail;
+			}
+			mask |= 1 << level;
+		} else
+			break;
 	}
 	if (adev->powerplay.pp_funcs->force_clock_level)
 		amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -693,21 +702,27 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 	struct amdgpu_device *adev = ddev->dev_private;
 	int ret;
 	long level;
-	uint32_t i, mask = 0;
-	char sub_str[2];
+	uint32_t mask = 0;
+	char *sub_str = NULL;
+	char *tmp;
+	char buf_cpy[count];
+	const char delimiter[3] = {' ', '\n', '\0'};
 
-	for (i = 0; i < strlen(buf); i++) {
-		if (*(buf + i) == '\n')
-			continue;
-		sub_str[0] = *(buf + i);
-		sub_str[1] = '\0';
-		ret = kstrtol(sub_str, 0, &level);
+	memcpy(buf_cpy, buf, count+1);
+	tmp = buf_cpy;
 
-		if (ret) {
-			count = -EINVAL;
-			goto fail;
-		}
-		mask |= 1 << level;
+	while (tmp[0]) {
+		sub_str =  strsep(&tmp, delimiter);
+		if (strlen(sub_str)) {
+			ret = kstrtol(sub_str, 0, &level);
+
+			if (ret) {
+				count = -EINVAL;
+				goto fail;
+			}
+			mask |= 1 << level;
+		} else
+			break;
 	}
 	if (adev->powerplay.pp_funcs->force_clock_level)
 		amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-04-24 13:22 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-19 20:51 [PATCH] drm/amdgpu: change pp_dpm clk/mclk/pcie input format welu
     [not found] ` <1524171079-657-1-git-send-email-wei.lu2-5C7GfCeVMHo@public.gmane.org>
2018-04-23 20:06   ` Alex Deucher
     [not found]     ` <CADnq5_NyeoyGQTqq3okvFpjNrRN2CSU+trFSTENT9cor2=aj7w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-04-24 13:22       ` Lu, Wei
2018-04-24 13:20 welu

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