Re: [PATCH 36/40] drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu: Mark local functions invoked by reference as static

[Alex Deucher <alexdeucher@gmail.com>]

On Thu, Nov 26, 2020 at 8:44 AM Lee Jones <lee.jones@linaro.org> wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
>  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:538:6: warning: no previous prototype for ‘pp_rv_set_wm_ranges’ [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:590:6: warning: no previous prototype for ‘pp_rv_set_pme_wa_enable’ [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:601:6: warning: no previous prototype for ‘pp_rv_set_active_display_count’ [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:614:6: warning: no previous prototype for ‘pp_rv_set_min_deep_sleep_dcfclk’ [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:627:6: warning: no previous prototype for ‘pp_rv_set_hard_min_dcefclk_by_freq’ [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:640:6: warning: no previous prototype for ‘pp_rv_set_hard_min_fclk_by_freq’ [-Wmissing-prototypes]
>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Leo Li <sunpeng.li@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: "Christian König" <christian.koenig@amd.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Lee Jones <lee.jones@linaro.org>

Applied.  Thanks!

Alex

> ---
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c   | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index 84065c12d4b85..ac0a0539854ef 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -535,7 +535,7 @@ bool dm_pp_get_static_clocks(
>         return true;
>  }
>
> -void pp_rv_set_wm_ranges(struct pp_smu *pp,
> +static void pp_rv_set_wm_ranges(struct pp_smu *pp,
>                 struct pp_smu_wm_range_sets *ranges)
>  {
>         const struct dc_context *ctx = pp->dm;
> @@ -587,7 +587,7 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
>                                                            &wm_with_clock_ranges);
>  }
>
> -void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
> +static void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
>  {
>         const struct dc_context *ctx = pp->dm;
>         struct amdgpu_device *adev = ctx->driver_context;
> @@ -598,7 +598,7 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
>                 pp_funcs->notify_smu_enable_pwe(pp_handle);
>  }
>
> -void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
> +static void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
>  {
>         const struct dc_context *ctx = pp->dm;
>         struct amdgpu_device *adev = ctx->driver_context;
> @@ -611,7 +611,7 @@ void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
>         pp_funcs->set_active_display_count(pp_handle, count);
>  }
>
> -void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)
> +static void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)
>  {
>         const struct dc_context *ctx = pp->dm;
>         struct amdgpu_device *adev = ctx->driver_context;
> @@ -624,7 +624,7 @@ void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)
>         pp_funcs->set_min_deep_sleep_dcefclk(pp_handle, clock);
>  }
>
> -void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)
> +static void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)
>  {
>         const struct dc_context *ctx = pp->dm;
>         struct amdgpu_device *adev = ctx->driver_context;
> @@ -637,7 +637,7 @@ void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)
>         pp_funcs->set_hard_min_dcefclk_by_freq(pp_handle, clock);
>  }
>
> -void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz)
> +static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz)
>  {
>         const struct dc_context *ctx = pp->dm;
>         struct amdgpu_device *adev = ctx->driver_context;
> @@ -661,7 +661,7 @@ static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
>         return PP_SMU_RESULT_OK;
>  }
>
> -enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
> +static enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
>  {
>         const struct dc_context *ctx = pp->dm;
>         struct amdgpu_device *adev = ctx->driver_context;
> --
> 2.25.1
>
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