* [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC
@ 2021-07-26 13:40 Rajesh Patil
2021-07-26 13:40 ` [PATCH V4 1/4] arm64: dts: sc7280: Add QSPI node Rajesh Patil
` (4 more replies)
0 siblings, 5 replies; 18+ messages in thread
From: Rajesh Patil @ 2021-07-26 13:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Rajesh Patil
Roja Rani Yarubandi (4):
arm64: dts: sc7280: Add QSPI node
arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
arm64: dts: sc7280: Update QUPv3 Debug UART DT node
arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 133 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3169 +++++++++++++++++++++++--------
2 files changed, 2482 insertions(+), 820 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH V4 1/4] arm64: dts: sc7280: Add QSPI node
2021-07-26 13:40 [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
@ 2021-07-26 13:40 ` Rajesh Patil
2021-07-26 16:07 ` Matthias Kaehlcke
2021-07-26 13:40 ` [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
` (3 subsequent siblings)
4 siblings, 1 reply; 18+ messages in thread
From: Rajesh Patil @ 2021-07-26 13:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Roja Rani Yarubandi,
Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Add QSPI DT node for SC7280 SoC.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
Changes in V4:
- As per Stephen's comment updated spi-max-frequency to 37.5MHz, moved
qspi_opp_table from /soc to / (root).
Changes in V3:
- Broken the huge V2 patch into 3 smaller patches.
1. QSPI DT nodes
2. QUP wrapper_0 DT nodes
3. QUP wrapper_1 DT nodes
Changes in V2:
- As per Doug's comments removed pinmux/pinconf subnodes.
- As per Doug's comments split of SPI, UART nodes has been done.
- Moved QSPI node before aps_smmu as per the order.
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 27 ++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 +++++++++++++++++++++++++++++++++
2 files changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 73225e3..b0bfd8e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -269,6 +269,20 @@
};
};
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <37500000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -346,6 +360,19 @@
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+&qspi_cs0 {
+ bias-disable;
+};
+
+&qspi_clk {
+ bias-disable;
+};
+
+&qspi_data01 {
+ /* High-Z when no transfers; nice to park the lines */
+ bias-pull-up;
+};
+
&qup_uart5_default {
tx {
pins = "gpio46";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 5764c5b..ca6e36b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -415,6 +415,25 @@
method = "smc";
};
+ qspi_opp_table: qspi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@@ -1301,6 +1320,24 @@
};
};
+ qspi: spi@88dc000 {
+ compatible = "qcom,qspi-v1";
+ reg = <0 0x088dc000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <&gcc GCC_QSPI_CORE_CLK>;
+ clock-names = "iface", "core";
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0
+ &cnoc2 SLAVE_QSPI_0 0>;
+ interconnect-names = "qspi-config";
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qspi_opp_table>;
+ status = "disabled";
+
+ };
+
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
@@ -1492,6 +1529,31 @@
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
+ qspi_clk: qspi-clk {
+ pins = "gpio14";
+ function = "qspi_clk";
+ };
+
+ qspi_cs0: qspi-cs0 {
+ pins = "gpio15";
+ function = "qspi_cs";
+ };
+
+ qspi_cs1: qspi-cs1 {
+ pins = "gpio19";
+ function = "qspi_cs";
+ };
+
+ qspi_data01: qspi-data01 {
+ pins = "gpio12", "gpio13";
+ function = "qspi_data";
+ };
+
+ qspi_data12: qspi-data12 {
+ pins = "gpio16", "gpio17";
+ function = "qspi_data";
+ };
+
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-07-26 13:40 [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-07-26 13:40 ` [PATCH V4 1/4] arm64: dts: sc7280: Add QSPI node Rajesh Patil
@ 2021-07-26 13:40 ` Rajesh Patil
2021-07-26 16:02 ` Matthias Kaehlcke
2021-07-27 19:20 ` Stephen Boyd
2021-07-26 13:40 ` [PATCH V4 3/4] arm64: dts: sc7280: Update QUPv3 Debug UART DT node Rajesh Patil
` (2 subsequent siblings)
4 siblings, 2 replies; 18+ messages in thread
From: Rajesh Patil @ 2021-07-26 13:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Roja Rani Yarubandi,
Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
Changes in V4:
- As per Bjorn's comment, added QUP Wrapper_0 nodes
other than debug-uart node
- Dropped interconnect votes for wrapper_0 node
Changes in V3:
- Broken the huge V2 patch into 3 smaller patches.
1. QSPI DT nodes
2. QUP wrapper_0 DT nodes
3. QUP wrapper_1 DT nodes
Changes in V2:
- As per Doug's comments removed pinmux/pinconf subnodes.
- As per Doug's comments split of SPI, UART nodes has been done.
- Moved QSPI node before aps_smmu as per the order.
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 84 ++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 720 ++++++++++++++++++++++++++++++++
2 files changed, 804 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index b0bfd8e..f63cf51 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -358,6 +358,16 @@
vdda18-supply = <&vreg_l1c_1p8>;
};
+&uart7 {
+ status = "okay";
+
+ /delete-property/interrupts;
+ interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
+};
+
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
&qspi_cs0 {
@@ -428,3 +438,77 @@
bias-pull-up;
};
};
+&qup_uart7_cts {
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+};
+
+&qup_uart7_rts {
+ /* We'll drive RTS, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_tx {
+ /* We'll drive TX, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
+};
+
+&tlmm {
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts {
+ pins = "gpio28";
+ function = "gpio";
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts {
+ pins = "gpio29";
+ function = "gpio";
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx {
+ pins = "gpio30";
+ function = "gpio";
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ bias-pull-up;
+ };
+
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx {
+ pins = "gpio31";
+ function = "gpio";
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index ca6e36b..455e58f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -520,6 +520,25 @@
};
+ qup_opp_table: qup-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
@@ -529,8 +548,305 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ iommus = <&apps_smmu 0x123 0x0>;
status = "disabled";
+ i2c0: i2c@980000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00980000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi0: spi@980000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00980000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>, <&qup_spi0_cs_gpio>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart0: serial@980000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00980000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c1: i2c@984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00984000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi1: spi@984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00984000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>, <&qup_spi1_cs_gpio>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart1: serial@984000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00984000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c2: i2c@988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>, <&qup_spi2_cs_gpio>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart2: serial@988000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c3: i2c@98c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0098c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0098c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>, <&qup_spi3_cs_gpio>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart3: serial@98c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0098c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c4: i2c@990000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00990000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi4: spi@990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00990000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>, <&qup_spi4_cs_gpio>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart4: serial@990000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00990000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c5: i2c@994000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00994000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi5: spi@994000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00994000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>, <&qup_spi5_cs_gpio>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
uart5: serial@994000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x00994000 0 0x4000>;
@@ -541,6 +857,110 @@
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ i2c6: i2c@998000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>, <&qup_spi6_cs_gpio>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart6: serial@998000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c7: i2c@99c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi7: spi@99c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>, <&qup_spi7_cs_gpio>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart7: serial@99c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
};
cnoc2: interconnect@1500000 {
@@ -1554,11 +1974,311 @@
function = "qspi_data";
};
+ qup_i2c0_data_clk:qup-i2c0-data-clk {
+ pins = "gpio0", "gpio1";
+ function = "qup00";
+ };
+
+ qup_i2c1_data_clk:qup-i2c1-data-clk {
+ pins = "gpio4", "gpio5";
+ function = "qup01";
+ };
+
+ qup_i2c2_data_clk:qup-i2c2-data-clk {
+ pins = "gpio8", "gpio9";
+ function = "qup02";
+ };
+
+ qup_i2c3_data_clk:qup-i2c3-data-clk {
+ pins = "gpio12", "gpio13";
+ function = "qup03";
+ };
+
+ qup_i2c4_data_clk:qup-i2c4-data-clk {
+ pins = "gpio16", "gpio17";
+ function = "qup04";
+ };
+
+ qup_i2c5_data_clk:qup-i2c5-data-clk {
+ pins = "gpio20", "gpio21";
+ function = "qup05";
+ };
+
+ qup_i2c6_data_clk:qup-i2c6-data-clk {
+ pins = "gpio24", "gpio25";
+ function = "qup06";
+ };
+
+ qup_i2c7_data_clk:qup-i2c7-data-clk {
+ pins = "gpio28", "gpio29";
+ function = "qup07";
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk {
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup00";
+ };
+
+ qup_spi0_cs: qup-spi0-cs {
+ pins = "gpio3";
+ function = "qup00";
+ };
+
+ qup_spi0_cs_gpio: qup-spi0-cs_gpio {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk {
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup01";
+ };
+
+ qup_spi1_cs: qup-spi1-cs {
+ pins = "gpio7";
+ function = "qup01";
+ };
+
+ qup_spi1_cs_gpio: qup-spi1-cs_gpio {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk {
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup02";
+ };
+
+ qup_spi2_cs: qup-spi2-cs {
+ pins = "gpio11";
+ function = "qup02";
+ };
+
+ qup_spi2_cs_gpio: qup-spi2-cs_gpio {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk {
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup03";
+ };
+
+ qup_spi3_cs: qup-spi3-cs {
+ pins = "gpio15";
+ function = "qup03";
+ };
+
+ qup_spi3_cs_gpio: qup-spi3-cs_gpio {
+ pins = "gpio15";
+ function = "gpio";
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk {
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup04";
+ };
+
+ qup_spi4_cs: qup-spi4-cs {
+ pins = "gpio19";
+ function = "qup04";
+ };
+
+ qup_spi4_cs_gpio: qup-spi4-cs_gpio {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk {
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup05";
+ };
+
+ qup_spi5_cs: qup-spi5-cs {
+ pins = "gpio23";
+ function = "qup05";
+ };
+
+ qup_spi5_cs_gpio: qup-spi5-cs_gpio {
+ pins = "gpio23";
+ function = "gpio";
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk {
+ pins = "gpio24", "gpio25", "gpio26";
+ function = "qup06";
+ };
+
+ qup_spi6_cs: qup-spi6-cs {
+ pins = "gpio27";
+ function = "qup06";
+ };
+
+ qup_spi6_cs_gpio: qup-spi6-cs_gpio {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ qup_spi7_data_clk: qup-spi7-data-clk {
+ pins = "gpio28", "gpio29", "gpio30";
+ function = "qup07";
+ };
+
+ qup_spi7_cs: qup-spi7-cs {
+ pins = "gpio31";
+ function = "qup07";
+ };
+
+ qup_spi7_cs_gpio: qup-spi7-cs_gpio {
+ pins = "gpio31";
+ function = "gpio";
+ };
+
+ qup_uart0_cts: qup-uart0-cts {
+ pins = "gpio0";
+ function = "qup00";
+ };
+
+ qup_uart0_rts: qup-uart0-rts {
+ pins = "gpio1";
+ function = "qup00";
+ };
+
+ qup_uart0_tx: qup-uart0-tx {
+ pins = "gpio2";
+ function = "qup00";
+ };
+
+ qup_uart0_rx: qup-uart0-rx {
+ pins = "gpio3";
+ function = "qup00";
+ };
+
+ qup_uart1_cts: qup-uart1-cts {
+ pins = "gpio4";
+ function = "qup01";
+ };
+
+ qup_uart1_rts: qup-uart1-rts {
+ pins = "gpio5";
+ function = "qup01";
+ };
+
+ qup_uart1_tx: qup-uart1-tx {
+ pins = "gpio6";
+ function = "qup01";
+ };
+
+ qup_uart1_rx: qup-uart1-rx {
+ pins = "gpio7";
+ function = "qup01";
+ };
+
+ qup_uart2_cts: qup-uart2-cts {
+ pins = "gpio8";
+ function = "qup02";
+ };
+
+ qup_uart2_rts: qup-uart2-rts {
+ pins = "gpio9";
+ function = "qup02";
+ };
+
+ qup_uart2_tx: qup-uart2-tx {
+ pins = "gpio10";
+ function = "qup02";
+ };
+
+ qup_uart2_rx: qup-uart2-rx {
+ pins = "gpio11";
+ function = "qup02";
+ };
+
+ qup_uart3_cts: qup-uart3-cts {
+ pins = "gpio12";
+ function = "qup03";
+ };
+
+ qup_uart3_rts: qup-uart3-rts {
+ pins = "gpio13";
+ function = "qup03";
+ };
+
+ qup_uart3_tx: qup-uart3-tx {
+ pins = "gpio14";
+ function = "qup03";
+ };
+
+ qup_uart3_rx: qup-uart3-rx {
+ pins = "gpio15";
+ function = "qup03";
+ };
+
+ qup_uart4_cts: qup-uart4-cts {
+ pins = "gpio16";
+ function = "qup04";
+ };
+
+ qup_uart4_rts: qup-uart4-rts {
+ pins = "gpio17";
+ function = "qup04";
+ };
+
+ qup_uart4_tx: qup-uart4-tx {
+ pins = "gpio18";
+ function = "qup04";
+ };
+
+ qup_uart4_rx: qup-uart4-rx {
+ pins = "gpio19";
+ function = "qup04";
+ };
+
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
};
+ qup_uart6_cts: qup-uart6-cts {
+ pins = "gpio24";
+ function = "qup06";
+ };
+
+ qup_uart6_rts: qup-uart6-rts {
+ pins = "gpio25";
+ function = "qup06";
+ };
+
+ qup_uart6_tx: qup-uart6-tx {
+ pins = "gpio26";
+ function = "qup06";
+ };
+
+ qup_uart6_rx: qup-uart6-rx {
+ pins = "gpio27";
+ function = "qup06";
+ };
+
+ qup_uart7_cts: qup-uart7-cts {
+ pins = "gpio28";
+ function = "qup07";
+ };
+
+ qup_uart7_rts: qup-uart7-rts {
+ pins = "gpio29";
+ function = "qup07";
+ };
+
+ qup_uart7_tx: qup-uart7-tx {
+ pins = "gpio30";
+ function = "qup07";
+ };
+
+ qup_uart7_rx: qup-uart7-rx {
+ pins = "gpio31";
+ function = "qup07";
+ };
+
sdc1_on: sdc1-on {
clk {
pins = "sdc1_clk";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V4 3/4] arm64: dts: sc7280: Update QUPv3 Debug UART DT node
2021-07-26 13:40 [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-07-26 13:40 ` [PATCH V4 1/4] arm64: dts: sc7280: Add QSPI node Rajesh Patil
2021-07-26 13:40 ` [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
@ 2021-07-26 13:40 ` Rajesh Patil
2021-07-26 15:42 ` Matthias Kaehlcke
2021-07-26 13:40 ` [PATCH V4 4/4] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
2021-07-27 0:14 ` [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Stephen Boyd
4 siblings, 1 reply; 18+ messages in thread
From: Rajesh Patil @ 2021-07-26 13:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Roja Rani Yarubandi,
Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Update QUPv3 Debug UART DT node with the interconnect names and
functions for SC7280 SoC.
Split the Debug UART pin control functions.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
Changes in V4:
- As per Bjorn's comment, posting this debug-uart node update
as seperate patch
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 18 +++++++-----------
arch/arm64/boot/dts/qcom/sc7280.dtsi | 28 ++++++++++++++++++++++++----
2 files changed, 31 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index f63cf51..a50c9e5 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -383,18 +383,14 @@
bias-pull-up;
};
-&qup_uart5_default {
- tx {
- pins = "gpio46";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart5_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
- rx {
- pins = "gpio47";
- drive-strength = <2>;
- bias-pull-up;
- };
+&qup_uart5_rx {
+ drive-strength = <2>;
+ bias-pull-up;
};
&sdc1_on {
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 455e58f..951818f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -853,8 +853,13 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_uart5_default>;
+ pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -2234,9 +2239,24 @@
function = "qup04";
};
- qup_uart5_default: qup-uart5-default {
- pins = "gpio46", "gpio47";
- function = "qup13";
+ qup_uart5_cts: qup-uart5-cts {
+ pins = "gpio20";
+ function = "qup05";
+ };
+
+ qup_uart5_rts: qup-uart5-rts {
+ pins = "gpio21";
+ function = "qup05";
+ };
+
+ qup_uart5_tx: qup-uart5-tx {
+ pins = "gpio22";
+ function = "qup05";
+ };
+
+ qup_uart5_rx: qup-uart5-rx {
+ pins = "gpio23";
+ function = "qup05";
};
qup_uart6_cts: qup-uart6-cts {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V4 4/4] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
2021-07-26 13:40 [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (2 preceding siblings ...)
2021-07-26 13:40 ` [PATCH V4 3/4] arm64: dts: sc7280: Update QUPv3 Debug UART DT node Rajesh Patil
@ 2021-07-26 13:40 ` Rajesh Patil
2021-07-27 0:14 ` [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Stephen Boyd
4 siblings, 0 replies; 18+ messages in thread
From: Rajesh Patil @ 2021-07-26 13:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Roja Rani Yarubandi,
Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Add QUPv3 wrapper_1 DT nodes for SC7280 SoC.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
Changes in V4:
- Dropped interconnect votes for wrapper_1 node
- Corrected QUP Wrapper_1 SE node's pin control functions like below
QUP Wrapper_0: SE0-SE7 uses qup00 - qup07 pin-cntrl functions.
QUP Wrapper_1: SE0-SE7 uses qup10 - qup17 pin-cntrl functions.
Changes in V3:
- Broken the huge V2 patch into 3 smaller patches.
1. QSPI DT nodes
2. QUP wrapper_0 DT nodes
3. QUP wrapper_1 DT nodes
Changes in V2:
- As per Doug's comments removed pinmux/pinconf subnodes.
- As per Doug's comments split of SPI, UART nodes has been done.
- Moved QSPI node before aps_smmu as per the order.
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 749 ++++++++++++++++++++++++++++++++
2 files changed, 753 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index a50c9e5..6695a97 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -315,6 +315,10 @@
cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
};
+&qupv3_id_1 {
+ status = "okay";
+};
+
&uart5 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 951818f..54c0952 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -968,6 +968,435 @@
};
};
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ iommus = <&apps_smmu 0x43 0x0>;
+ status = "disabled";
+
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi8: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>, <&qup_spi8_cs_gpio>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart8: serial@a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>, <&qup_spi9_cs_gpio>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart9: serial@a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>, <&qup_spi10_cs_gpio>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart10: serial@a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>, <&qup_spi11_cs_gpio>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart11: serial@a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>, <&qup_spi12_cs_gpio>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart12: serial@a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>, <&qup_spi13_cs_gpio>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart13: serial@a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>, <&qup_spi14_cs_gpio>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart14: serial@a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>, <&qup_spi15_cs_gpio>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart15: serial@a9c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+ };
+
cnoc2: interconnect@1500000 {
reg = <0 0x01500000 0 0x1000>;
compatible = "qcom,sc7280-cnoc2";
@@ -2019,6 +2448,46 @@
function = "qup07";
};
+ qup_i2c8_data_clk:qup-i2c8-data-clk {
+ pins = "gpio32", "gpio33";
+ function = "qup10";
+ };
+
+ qup_i2c9_data_clk:qup-i2c9-data-clk {
+ pins = "gpio36", "gpio37";
+ function = "qup11";
+ };
+
+ qup_i2c10_data_clk:qup-i2c10-data-clk {
+ pins = "gpio40", "gpio41";
+ function = "qup12";
+ };
+
+ qup_i2c11_data_clk:qup-i2c11-data-clk {
+ pins = "gpio44", "gpio45";
+ function = "qup13";
+ };
+
+ qup_i2c12_data_clk:qup-i2c12-data-clk {
+ pins = "gpio48", "gpio49";
+ function = "qup14";
+ };
+
+ qup_i2c13_data_clk:qup-i2c13-data-clk {
+ pins = "gpio52", "gpio53";
+ function = "qup15";
+ };
+
+ qup_i2c14_data_clk:qup-i2c14-data-clk {
+ pins = "gpio56", "gpio57";
+ function = "qup16";
+ };
+
+ qup_i2c15_data_clk:qup-i2c15-data-clk {
+ pins = "gpio60", "gpio61";
+ function = "qup17";
+ };
+
qup_spi0_data_clk: qup-spi0-data-clk {
pins = "gpio0", "gpio1", "gpio2";
function = "qup00";
@@ -2139,6 +2608,126 @@
function = "gpio";
};
+ qup_spi8_data_clk: qup-spi8-data-clk {
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup10";
+ };
+
+ qup_spi8_cs: qup-spi8-cs {
+ pins = "gpio35";
+ function = "qup10";
+ };
+
+ qup_spi8_cs_gpio: qup-spi8-cs_gpio {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk {
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup11";
+ };
+
+ qup_spi9_cs: qup-spi9-cs {
+ pins = "gpio39";
+ function = "qup11";
+ };
+
+ qup_spi9_cs_gpio: qup-spi9-cs_gpio {
+ pins = "gpio39";
+ function = "gpio";
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk {
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup12";
+ };
+
+ qup_spi10_cs: qup-spi10-cs {
+ pins = "gpio43";
+ function = "qup12";
+ };
+
+ qup_spi10_cs_gpio: qup-spi10-cs_gpio {
+ pins = "gpio43";
+ function = "gpio";
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk {
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup13";
+ };
+
+ qup_spi11_cs: qup-spi11-cs {
+ pins = "gpio47";
+ function = "qup13";
+ };
+
+ qup_spi11_cs_gpio: qup-spi11-cs_gpio {
+ pins = "gpio47";
+ function = "gpio";
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk {
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup14";
+ };
+
+ qup_spi12_cs: qup-spi12-cs {
+ pins = "gpio51";
+ function = "qup14";
+ };
+
+ qup_spi12_cs_gpio: qup-spi12-cs_gpio {
+ pins = "gpio51";
+ function = "gpio";
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk {
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup15";
+ };
+
+ qup_spi13_cs: qup-spi13-cs {
+ pins = "gpio55";
+ function = "qup15";
+ };
+
+ qup_spi13_cs_gpio: qup-spi13-cs_gpio {
+ pins = "gpio55";
+ function = "gpio";
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk {
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup16";
+ };
+
+ qup_spi14_cs: qup-spi14-cs {
+ pins = "gpio59";
+ function = "qup16";
+ };
+
+ qup_spi14_cs_gpio: qup-spi14-cs_gpio {
+ pins = "gpio59";
+ function = "gpio";
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk {
+ pins = "gpio60", "gpio61", "gpio62";
+ function = "qup17";
+ };
+
+ qup_spi15_cs: qup-spi15-cs {
+ pins = "gpio63";
+ function = "qup17";
+ };
+
+ qup_spi15_cs_gpio: qup-spi15-cs_gpio {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
qup_uart0_cts: qup-uart0-cts {
pins = "gpio0";
function = "qup00";
@@ -2379,6 +2968,166 @@
bias-bus-hold;
};
};
+
+ qup_uart8_cts: qup-uart8-cts {
+ pins = "gpio32";
+ function = "qup10";
+ };
+
+ qup_uart8_rts: qup-uart8-rts {
+ pins = "gpio33";
+ function = "qup10";
+ };
+
+ qup_uart8_tx: qup-uart8-tx {
+ pins = "gpio34";
+ function = "qup10";
+ };
+
+ qup_uart8_rx: qup-uart8-rx {
+ pins = "gpio35";
+ function = "qup10";
+ };
+
+ qup_uart9_cts: qup-uart9-cts {
+ pins = "gpio36";
+ function = "qup11";
+ };
+
+ qup_uart9_rts: qup-uart9-rts {
+ pins = "gpio37";
+ function = "qup11";
+ };
+
+ qup_uart9_tx: qup-uart9-tx {
+ pins = "gpio38";
+ function = "qup11";
+ };
+
+ qup_uart9_rx: qup-uart9-rx {
+ pins = "gpio39";
+ function = "qup11";
+ };
+
+ qup_uart10_cts: qup-uart10-cts {
+ pins = "gpio40";
+ function = "qup12";
+ };
+
+ qup_uart10_rts: qup-uart10-rts {
+ pins = "gpio41";
+ function = "qup12";
+ };
+
+ qup_uart10_tx: qup-uart10-tx {
+ pins = "gpio42";
+ function = "qup12";
+ };
+
+ qup_uart10_rx: qup-uart10-rx {
+ pins = "gpio43";
+ function = "qup12";
+ };
+
+ qup_uart11_cts: qup-uart11-cts {
+ pins = "gpio44";
+ function = "qup13";
+ };
+
+ qup_uart11_rts: qup-uart11-rts {
+ pins = "gpio45";
+ function = "qup13";
+ };
+
+ qup_uart11_tx: qup-uart11-tx {
+ pins = "gpio46";
+ function = "qup13";
+ };
+
+ qup_uart11_rx: qup-uart11-rx {
+ pins = "gpio47";
+ function = "qup13";
+ };
+
+ qup_uart12_cts: qup-uart12-cts {
+ pins = "gpio48";
+ function = "qup14";
+ };
+
+ qup_uart12_rts: qup-uart12-rts {
+ pins = "gpio49";
+ function = "qup14";
+ };
+
+ qup_uart12_tx: qup-uart12-tx {
+ pins = "gpio50";
+ function = "qup14";
+ };
+
+ qup_uart12_rx: qup-uart12-rx {
+ pins = "gpio51";
+ function = "qup14";
+ };
+
+ qup_uart13_cts: qup-uart13-cts {
+ pins = "gpio52";
+ function = "qup15";
+ };
+
+ qup_uart13_rts: qup-uart13-rts {
+ pins = "gpio53";
+ function = "qup15";
+ };
+
+ qup_uart13_tx: qup-uart13-tx {
+ pins = "gpio54";
+ function = "qup15";
+ };
+
+ qup_uart13_rx: qup-uart13-rx {
+ pins = "gpio55";
+ function = "qup15";
+ };
+
+ qup_uart14_cts: qup-uart14-cts {
+ pins = "gpio56";
+ function = "qup16";
+ };
+
+ qup_uart14_rts: qup-uart14-rts {
+ pins = "gpio57";
+ function = "qup16";
+ };
+
+ qup_uart14_tx: qup-uart14-tx {
+ pins = "gpio58";
+ function = "qup16";
+ };
+
+ qup_uart14_rx: qup-uart14-rx {
+ pins = "gpio59";
+ function = "qup16";
+ };
+
+ qup_uart15_cts: qup-uart15-cts {
+ pins = "gpio60";
+ function = "qup17";
+ };
+
+ qup_uart15_rts: qup-uart15-rts {
+ pins = "gpio61";
+ function = "qup17";
+ };
+
+ qup_uart15_tx: qup-uart15-tx {
+ pins = "gpio62";
+ function = "qup17";
+ };
+
+ qup_uart15_rx: qup-uart15-rx {
+ pins = "gpio63";
+ function = "qup17";
+ };
};
apps_smmu: iommu@15000000 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH V4 3/4] arm64: dts: sc7280: Update QUPv3 Debug UART DT node
2021-07-26 13:40 ` [PATCH V4 3/4] arm64: dts: sc7280: Update QUPv3 Debug UART DT node Rajesh Patil
@ 2021-07-26 15:42 ` Matthias Kaehlcke
2021-08-11 12:04 ` rajpat
0 siblings, 1 reply; 18+ messages in thread
From: Matthias Kaehlcke @ 2021-07-26 15:42 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On Mon, Jul 26, 2021 at 07:10:46PM +0530, Rajesh Patil wrote:
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>
> Update QUPv3 Debug UART DT node with the interconnect names and
> functions for SC7280 SoC.
>
> Split the Debug UART pin control functions.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> ---
> Changes in V4:
> - As per Bjorn's comment, posting this debug-uart node update
> as seperate patch
>
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 18 +++++++-----------
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 28 ++++++++++++++++++++++++----
> 2 files changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index f63cf51..a50c9e5 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -383,18 +383,14 @@
> bias-pull-up;
> };
>
> -&qup_uart5_default {
> - tx {
> - pins = "gpio46";
> - drive-strength = <2>;
> - bias-disable;
> - };
> +&qup_uart5_tx {
> + drive-strength = <2>;
> + bias-disable;
> +};
>
> - rx {
> - pins = "gpio47";
> - drive-strength = <2>;
> - bias-pull-up;
> - };
> +&qup_uart5_rx {
> + drive-strength = <2>;
> + bias-pull-up;
> };
>
> &sdc1_on {
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 455e58f..951818f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -853,8 +853,13 @@
> clock-names = "se";
> clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> pinctrl-names = "default";
> - pinctrl-0 = <&qup_uart5_default>;
> + pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
Most of the above should be added by patch '[2/4] arm64: dts: sc7280: Add QUPv3
wrapper_0 nodes'.
I have to say I dislike that the SoC DT file dictates which UART to use for
the serial console. Technically it could be any of them, right? uart5 is
used because that's what the IDP does, and the rest of the world is expected
to follow. Why not configure uart5 as "qcom,geni-uart" by default and
overwrite the compatible string and pinctrl in the board file? You could even
add 'qup-uartN-all' (or similar) pinconfigs to sc7280.dtsi, which would make
the changes in the board file trivial.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-07-26 13:40 ` [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
@ 2021-07-26 16:02 ` Matthias Kaehlcke
2021-08-11 12:13 ` rajpat
2021-07-27 19:20 ` Stephen Boyd
1 sibling, 1 reply; 18+ messages in thread
From: Matthias Kaehlcke @ 2021-07-26 16:02 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On Mon, Jul 26, 2021 at 07:10:45PM +0530, Rajesh Patil wrote:
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>
> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> ---
> Changes in V4:
> - As per Bjorn's comment, added QUP Wrapper_0 nodes
> other than debug-uart node
> - Dropped interconnect votes for wrapper_0 node
>
> Changes in V3:
> - Broken the huge V2 patch into 3 smaller patches.
> 1. QSPI DT nodes
> 2. QUP wrapper_0 DT nodes
> 3. QUP wrapper_1 DT nodes
>
> Changes in V2:
> - As per Doug's comments removed pinmux/pinconf subnodes.
> - As per Doug's comments split of SPI, UART nodes has been done.
> - Moved QSPI node before aps_smmu as per the order.
>
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 84 ++++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 720 ++++++++++++++++++++++++++++++++
> 2 files changed, 804 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index b0bfd8e..f63cf51 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -358,6 +358,16 @@
> vdda18-supply = <&vreg_l1c_1p8>;
> };
>
> +&uart7 {
> + status = "okay";
> +
> + /delete-property/interrupts;
> + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
> + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
> +};
> +
> /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>
> &qspi_cs0 {
> @@ -428,3 +438,77 @@
> bias-pull-up;
> };
> };
> +&qup_uart7_cts {
> + /*
> + * Configure a pull-down on CTS to match the pull of
> + * the Bluetooth module.
> + */
> + bias-pull-down;
> +};
> +
> +&qup_uart7_rts {
> + /* We'll drive RTS, so no pull */
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +&qup_uart7_tx {
> + /* We'll drive TX, so no pull */
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +&qup_uart7_rx {
> + /*
> + * Configure a pull-up on RX. This is needed to avoid
> + * garbage data when the TX pin of the Bluetooth module is
> + * in tri-state (module powered off or not driving the
> + * signal yet).
> + */
> + bias-pull-up;
> +};
> +
> +&tlmm {
> + qup_uart7_sleep_cts: qup-uart7-sleep-cts {
> + pins = "gpio28";
> + function = "gpio";
> + /*
> + * Configure a pull-down on CTS to match the pull of
> + * the Bluetooth module.
> + */
> + bias-pull-down;
> + };
> +
> + qup_uart7_sleep_rts: qup-uart7-sleep-rts {
> + pins = "gpio29";
> + function = "gpio";
> + /*
> + * Configure pull-down on RTS. As RTS is active low
> + * signal, pull it low to indicate the BT SoC that it
> + * can wakeup the system anytime from suspend state by
> + * pulling RX low (by sending wakeup bytes).
> + */
> + bias-pull-down;
> + };
> +
> + qup_uart7_sleep_tx: qup-uart7-sleep-tx {
> + pins = "gpio30";
> + function = "gpio";
> + /*
> + * Configure pull-up on TX when it isn't actively driven
> + * to prevent BT SoC from receiving garbage during sleep.
> + */
> + bias-pull-up;
> + };
> +
> + qup_uart7_sleep_rx: qup-uart7-sleep-rx {
> + pins = "gpio31";
> + function = "gpio";
> + /*
> + * Configure a pull-up on RX. This is needed to avoid
> + * garbage data when the TX pin of the Bluetooth module
> + * is floating which may cause spurious wakeups.
> + */
> + bias-pull-up;
> + };
> +};
How the patches of this series are split strikes me as a bit odd. Supposedly
this patch adds the QUPv3 wrapper_0 DT nodes for the SC7280, however the
above is the pin configuration for the Bluetooth UART of the SC7280 IDP board.
I don't see a good reason why that should be part of this patch. It should be
a separate change whose subject indicates that it configures the Bluetooth UART
of the SC7280 IDP.
Without this conflation of SoC and board DT it would seem perfectly reasonable
to squash this patch and '[4/4] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes'
into a single one, they are essentially doing the same thing, I see no need to
have different patches for the wrapper 0 and 1 nodes.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 1/4] arm64: dts: sc7280: Add QSPI node
2021-07-26 13:40 ` [PATCH V4 1/4] arm64: dts: sc7280: Add QSPI node Rajesh Patil
@ 2021-07-26 16:07 ` Matthias Kaehlcke
2021-08-11 12:14 ` rajpat
0 siblings, 1 reply; 18+ messages in thread
From: Matthias Kaehlcke @ 2021-07-26 16:07 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On Mon, Jul 26, 2021 at 07:10:44PM +0530, Rajesh Patil wrote:
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>
> Add QSPI DT node for SC7280 SoC.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> ---
> Changes in V4:
> - As per Stephen's comment updated spi-max-frequency to 37.5MHz, moved
> qspi_opp_table from /soc to / (root).
>
> Changes in V3:
> - Broken the huge V2 patch into 3 smaller patches.
> 1. QSPI DT nodes
> 2. QUP wrapper_0 DT nodes
> 3. QUP wrapper_1 DT nodes
>
> Changes in V2:
> - As per Doug's comments removed pinmux/pinconf subnodes.
> - As per Doug's comments split of SPI, UART nodes has been done.
> - Moved QSPI node before aps_smmu as per the order.
>
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 27 ++++++++++++++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 +++++++++++++++++++++++++++++++++
> 2 files changed, 89 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index 73225e3..b0bfd8e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -269,6 +269,20 @@
> };
> };
>
> +&qspi {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <37500000>;
> + spi-tx-bus-width = <2>;
> + spi-rx-bus-width = <2>;
> + };
> +};
> +
> &qupv3_id_0 {
> status = "okay";
> };
> @@ -346,6 +360,19 @@
>
> /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>
> +&qspi_cs0 {
> + bias-disable;
> +};
> +
> +&qspi_clk {
> + bias-disable;
> +};
> +
> +&qspi_data01 {
> + /* High-Z when no transfers; nice to park the lines */
> + bias-pull-up;
> +};
> +
This configures the SPI flash of the SC7280 IDP board, which is neither
mentioned in the subject nor the body of the commit message. IMO this
should be split out into a separate patch.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC
2021-07-26 13:40 [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (3 preceding siblings ...)
2021-07-26 13:40 ` [PATCH V4 4/4] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
@ 2021-07-27 0:14 ` Stephen Boyd
2021-08-11 12:14 ` rajpat
4 siblings, 1 reply; 18+ messages in thread
From: Stephen Boyd @ 2021-07-27 0:14 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rajesh Patil, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit
Quoting Rajesh Patil (2021-07-26 06:40:43)
> Roja Rani Yarubandi (4):
> arm64: dts: sc7280: Add QSPI node
> arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
> arm64: dts: sc7280: Update QUPv3 Debug UART DT node
> arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
Please include a changelog in the cover letter and Cc me on the
subsequent rounds of this series. Thanks.
>
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 133 +-
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 3169 +++++++++++++++++++++++--------
> 2 files changed, 2482 insertions(+), 820 deletions(-)
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-07-26 13:40 ` [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
2021-07-26 16:02 ` Matthias Kaehlcke
@ 2021-07-27 19:20 ` Stephen Boyd
2021-08-11 12:17 ` rajpat
1 sibling, 1 reply; 18+ messages in thread
From: Stephen Boyd @ 2021-07-27 19:20 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rajesh Patil, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, Roja Rani Yarubandi,
Rajesh Patil
Quoting Rajesh Patil (2021-07-26 06:40:45)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index ca6e36b..455e58f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -520,6 +520,25 @@
>
> };
>
> + qup_opp_table: qup-opp-table {
Surely this can live underneath a qup node parallel to the i2c and spi
devices?
> + compatible = "operating-points-v2";
> +
> + opp-75000000 {
> + opp-hz = /bits/ 64 <75000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-128000000 {
> + opp-hz = /bits/ 64 <128000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +
> qupv3_id_0: geniqup@9c0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0 0x009c0000 0 0x2000>;
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 3/4] arm64: dts: sc7280: Update QUPv3 Debug UART DT node
2021-07-26 15:42 ` Matthias Kaehlcke
@ 2021-08-11 12:04 ` rajpat
0 siblings, 0 replies; 18+ messages in thread
From: rajpat @ 2021-08-11 12:04 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi, swboyd
On 2021-07-26 21:12, Matthias Kaehlcke wrote:
> On Mon, Jul 26, 2021 at 07:10:46PM +0530, Rajesh Patil wrote:
>> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>>
>> Update QUPv3 Debug UART DT node with the interconnect names and
>> functions for SC7280 SoC.
>>
>> Split the Debug UART pin control functions.
>>
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>> ---
>> Changes in V4:
>> - As per Bjorn's comment, posting this debug-uart node update
>> as seperate patch
>>
>> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 18 +++++++-----------
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 28
>> ++++++++++++++++++++++++----
>> 2 files changed, 31 insertions(+), 15 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> index f63cf51..a50c9e5 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> @@ -383,18 +383,14 @@
>> bias-pull-up;
>> };
>>
>> -&qup_uart5_default {
>> - tx {
>> - pins = "gpio46";
>> - drive-strength = <2>;
>> - bias-disable;
>> - };
>> +&qup_uart5_tx {
>> + drive-strength = <2>;
>> + bias-disable;
>> +};
>>
>> - rx {
>> - pins = "gpio47";
>> - drive-strength = <2>;
>> - bias-pull-up;
>> - };
>> +&qup_uart5_rx {
>> + drive-strength = <2>;
>> + bias-pull-up;
>> };
>>
>> &sdc1_on {
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 455e58f..951818f 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -853,8 +853,13 @@
>> clock-names = "se";
>> clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
>> pinctrl-names = "default";
>> - pinctrl-0 = <&qup_uart5_default>;
>> + pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>,
>> <&qup_uart5_rx>;
>> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&rpmhpd SC7280_CX>;
>> + operating-points-v2 = <&qup_opp_table>;
>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt
>> SLAVE_QUP_CORE_0 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
>> + interconnect-names = "qup-core", "qup-config";
>
>
> Most of the above should be added by patch '[2/4] arm64: dts: sc7280:
> Add QUPv3
> wrapper_0 nodes'.
Based on the comments on v3 [1], I have added this as a separate patch
[1] https://lore.kernel.org/patchwork/patch/1441257/
>
> I have to say I dislike that the SoC DT file dictates which UART to use
> for
> the serial console. Technically it could be any of them, right? uart5
> is
> used because that's what the IDP does, and the rest of the world is
> expected
> to follow. Why not configure uart5 as "qcom,geni-uart" by default and
> overwrite the compatible string and pinctrl in the board file? You
> could even
> add 'qup-uartN-all' (or similar) pinconfigs to sc7280.dtsi, which would
> make
> the changes in the board file trivial.
Okay, will make the compatible as "qcom,geni-uart" in SoC dt and later
modify it in idp dts as "qcom,geni-debug-uart".
Thanks,
Rajesh
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-07-26 16:02 ` Matthias Kaehlcke
@ 2021-08-11 12:13 ` rajpat
2021-08-11 14:52 ` Matthias Kaehlcke
0 siblings, 1 reply; 18+ messages in thread
From: rajpat @ 2021-08-11 12:13 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On 2021-07-26 21:32, Matthias Kaehlcke wrote:
> On Mon, Jul 26, 2021 at 07:10:45PM +0530, Rajesh Patil wrote:
>> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>>
>> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
>>
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>> ---
>> Changes in V4:
>> - As per Bjorn's comment, added QUP Wrapper_0 nodes
>> other than debug-uart node
>> - Dropped interconnect votes for wrapper_0 node
>>
>> Changes in V3:
>> - Broken the huge V2 patch into 3 smaller patches.
>> 1. QSPI DT nodes
>> 2. QUP wrapper_0 DT nodes
>> 3. QUP wrapper_1 DT nodes
>>
>> Changes in V2:
>> - As per Doug's comments removed pinmux/pinconf subnodes.
>> - As per Doug's comments split of SPI, UART nodes has been done.
>> - Moved QSPI node before aps_smmu as per the order.
>>
>> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 84 ++++
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 720
>> ++++++++++++++++++++++++++++++++
>> 2 files changed, 804 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> index b0bfd8e..f63cf51 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> @@ -358,6 +358,16 @@
>> vdda18-supply = <&vreg_l1c_1p8>;
>> };
>>
>> +&uart7 {
>> + status = "okay";
>> +
>> + /delete-property/interrupts;
>> + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
>> + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
>> + pinctrl-names = "default", "sleep";
>> + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>,
>> <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
>> +};
>> +
>> /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>>
>> &qspi_cs0 {
>> @@ -428,3 +438,77 @@
>> bias-pull-up;
>> };
>> };
>> +&qup_uart7_cts {
>> + /*
>> + * Configure a pull-down on CTS to match the pull of
>> + * the Bluetooth module.
>> + */
>> + bias-pull-down;
>> +};
>> +
>> +&qup_uart7_rts {
>> + /* We'll drive RTS, so no pull */
>> + drive-strength = <2>;
>> + bias-disable;
>> +};
>> +
>> +&qup_uart7_tx {
>> + /* We'll drive TX, so no pull */
>> + drive-strength = <2>;
>> + bias-disable;
>> +};
>> +
>> +&qup_uart7_rx {
>> + /*
>> + * Configure a pull-up on RX. This is needed to avoid
>> + * garbage data when the TX pin of the Bluetooth module is
>> + * in tri-state (module powered off or not driving the
>> + * signal yet).
>> + */
>> + bias-pull-up;
>> +};
>> +
>> +&tlmm {
>> + qup_uart7_sleep_cts: qup-uart7-sleep-cts {
>> + pins = "gpio28";
>> + function = "gpio";
>> + /*
>> + * Configure a pull-down on CTS to match the pull of
>> + * the Bluetooth module.
>> + */
>> + bias-pull-down;
>> + };
>> +
>> + qup_uart7_sleep_rts: qup-uart7-sleep-rts {
>> + pins = "gpio29";
>> + function = "gpio";
>> + /*
>> + * Configure pull-down on RTS. As RTS is active low
>> + * signal, pull it low to indicate the BT SoC that it
>> + * can wakeup the system anytime from suspend state by
>> + * pulling RX low (by sending wakeup bytes).
>> + */
>> + bias-pull-down;
>> + };
>> +
>> + qup_uart7_sleep_tx: qup-uart7-sleep-tx {
>> + pins = "gpio30";
>> + function = "gpio";
>> + /*
>> + * Configure pull-up on TX when it isn't actively driven
>> + * to prevent BT SoC from receiving garbage during sleep.
>> + */
>> + bias-pull-up;
>> + };
>>
>> + qup_uart7_sleep_rx: qup-uart7-sleep-rx {
>> + pins = "gpio31";
>> + function = "gpio";
>> + /*
>> + * Configure a pull-up on RX. This is needed to avoid
>> + * garbage data when the TX pin of the Bluetooth module
>> + * is floating which may cause spurious wakeups.
>> + */
>> + bias-pull-up;
>> + };
>> +};
>
> How the patches of this series are split strikes me as a bit odd.
> Supposedly
> this patch adds the QUPv3 wrapper_0 DT nodes for the SC7280, however
> the
> above is the pin configuration for the Bluetooth UART of the SC7280 IDP
> board.
> I don't see a good reason why that should be part of this patch. It
> should be
> a separate change whose subject indicates that it configures the
> Bluetooth UART
> of the SC7280 IDP.
>
Okay will split this up.
> Without this conflation of SoC and board DT it would seem perfectly
> reasonable
> to squash this patch and '[4/4] arm64: dts: sc7280: Add QUPv3 wrapper_1
> nodes'
> into a single one, they are essentially doing the same thing, I see no
> need to
> have different patches for the wrapper 0 and 1 nodes.
Previously when QUP wrapper 0 and wrapper 1 nodes were added in single
patch, we faced some git issues as the patch was huge. Hence we split it
up.
https://partnerissuetracker.corp.google.com/issues/177045897#comment12
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 1/4] arm64: dts: sc7280: Add QSPI node
2021-07-26 16:07 ` Matthias Kaehlcke
@ 2021-08-11 12:14 ` rajpat
0 siblings, 0 replies; 18+ messages in thread
From: rajpat @ 2021-08-11 12:14 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On 2021-07-26 21:37, Matthias Kaehlcke wrote:
> On Mon, Jul 26, 2021 at 07:10:44PM +0530, Rajesh Patil wrote:
>> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>>
>> Add QSPI DT node for SC7280 SoC.
>>
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>> ---
>> Changes in V4:
>> - As per Stephen's comment updated spi-max-frequency to 37.5MHz,
>> moved
>> qspi_opp_table from /soc to / (root).
>>
>> Changes in V3:
>> - Broken the huge V2 patch into 3 smaller patches.
>> 1. QSPI DT nodes
>> 2. QUP wrapper_0 DT nodes
>> 3. QUP wrapper_1 DT nodes
>>
>> Changes in V2:
>> - As per Doug's comments removed pinmux/pinconf subnodes.
>> - As per Doug's comments split of SPI, UART nodes has been done.
>> - Moved QSPI node before aps_smmu as per the order.
>>
>> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 27 ++++++++++++++
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 62
>> +++++++++++++++++++++++++++++++++
>> 2 files changed, 89 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> index 73225e3..b0bfd8e 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> @@ -269,6 +269,20 @@
>> };
>> };
>>
>> +&qspi {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
>> +
>> + flash@0 {
>> + compatible = "jedec,spi-nor";
>> + reg = <0>;
>> + spi-max-frequency = <37500000>;
>> + spi-tx-bus-width = <2>;
>> + spi-rx-bus-width = <2>;
>> + };
>> +};
>> +
>> &qupv3_id_0 {
>> status = "okay";
>> };
>> @@ -346,6 +360,19 @@
>>
>> /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>>
>> +&qspi_cs0 {
>> + bias-disable;
>> +};
>> +
>> +&qspi_clk {
>> + bias-disable;
>> +};
>> +
>> +&qspi_data01 {
>> + /* High-Z when no transfers; nice to park the lines */
>> + bias-pull-up;
>> +};
>> +
>
> This configures the SPI flash of the SC7280 IDP board, which is neither
> mentioned in the subject nor the body of the commit message. IMO this
> should be split out into a separate patch.
Okay.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC
2021-07-27 0:14 ` [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Stephen Boyd
@ 2021-08-11 12:14 ` rajpat
0 siblings, 0 replies; 18+ messages in thread
From: rajpat @ 2021-08-11 12:14 UTC (permalink / raw)
To: Stephen Boyd
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On 2021-07-27 05:44, Stephen Boyd wrote:
> Quoting Rajesh Patil (2021-07-26 06:40:43)
>> Roja Rani Yarubandi (4):
>> arm64: dts: sc7280: Add QSPI node
>> arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
>> arm64: dts: sc7280: Update QUPv3 Debug UART DT node
>> arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
>
> Please include a changelog in the cover letter and Cc me on the
> subsequent rounds of this series. Thanks.
>
Okay.
>>
>> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 133 +-
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 3169
>> +++++++++++++++++++++++--------
>> 2 files changed, 2482 insertions(+), 820 deletions(-)
>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-07-27 19:20 ` Stephen Boyd
@ 2021-08-11 12:17 ` rajpat
0 siblings, 0 replies; 18+ messages in thread
From: rajpat @ 2021-08-11 12:17 UTC (permalink / raw)
To: Stephen Boyd
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On 2021-07-28 00:50, Stephen Boyd wrote:
> Quoting Rajesh Patil (2021-07-26 06:40:45)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index ca6e36b..455e58f 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -520,6 +520,25 @@
>>
>> };
>>
>> + qup_opp_table: qup-opp-table {
>
> Surely this can live underneath a qup node parallel to the i2c and spi
> devices?
>
But this is common to both qup0 and qup1 right?
>> + compatible = "operating-points-v2";
>> +
>> + opp-75000000 {
>> + opp-hz = /bits/ 64 <75000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-100000000 {
>> + opp-hz = /bits/ 64 <100000000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-128000000 {
>> + opp-hz = /bits/ 64 <128000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> + };
>> +
>> qupv3_id_0: geniqup@9c0000 {
>> compatible = "qcom,geni-se-qup";
>> reg = <0 0x009c0000 0 0x2000>;
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-11 12:13 ` rajpat
@ 2021-08-11 14:52 ` Matthias Kaehlcke
2021-08-12 7:13 ` rajpat
0 siblings, 1 reply; 18+ messages in thread
From: Matthias Kaehlcke @ 2021-08-11 14:52 UTC (permalink / raw)
To: rajpat
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit, Roja Rani Yarubandi
On Wed, Aug 11, 2021 at 05:43:48PM +0530, rajpat@codeaurora.org wrote:
> On 2021-07-26 21:32, Matthias Kaehlcke wrote:
> > On Mon, Jul 26, 2021 at 07:10:45PM +0530, Rajesh Patil wrote:
> > > From: Roja Rani Yarubandi <rojay@codeaurora.org>
> > >
> > > Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
> > >
> > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > > ---
> > > Changes in V4:
> > > - As per Bjorn's comment, added QUP Wrapper_0 nodes
> > > other than debug-uart node
> > > - Dropped interconnect votes for wrapper_0 node
> > >
> > > Changes in V3:
> > > - Broken the huge V2 patch into 3 smaller patches.
> > > 1. QSPI DT nodes
> > > 2. QUP wrapper_0 DT nodes
> > > 3. QUP wrapper_1 DT nodes
> > >
> > > Changes in V2:
> > > - As per Doug's comments removed pinmux/pinconf subnodes.
> > > - As per Doug's comments split of SPI, UART nodes has been done.
> > > - Moved QSPI node before aps_smmu as per the order.
> > >
> > > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 84 ++++
> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 720
> > > ++++++++++++++++++++++++++++++++
> > > 2 files changed, 804 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > index b0bfd8e..f63cf51 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > @@ -358,6 +358,16 @@
> > > vdda18-supply = <&vreg_l1c_1p8>;
> > > };
> > >
> > > +&uart7 {
> > > + status = "okay";
> > > +
> > > + /delete-property/interrupts;
> > > + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
> > > + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
> > > + pinctrl-names = "default", "sleep";
> > > + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>,
> > > <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
> > > +};
> > > +
> > > /* PINCTRL - additions to nodes defined in sc7280.dtsi */
> > >
> > > &qspi_cs0 {
> > > @@ -428,3 +438,77 @@
> > > bias-pull-up;
> > > };
> > > };
> > > +&qup_uart7_cts {
> > > + /*
> > > + * Configure a pull-down on CTS to match the pull of
> > > + * the Bluetooth module.
> > > + */
> > > + bias-pull-down;
> > > +};
> > > +
> > > +&qup_uart7_rts {
> > > + /* We'll drive RTS, so no pull */
> > > + drive-strength = <2>;
> > > + bias-disable;
> > > +};
> > > +
> > > +&qup_uart7_tx {
> > > + /* We'll drive TX, so no pull */
> > > + drive-strength = <2>;
> > > + bias-disable;
> > > +};
> > > +
> > > +&qup_uart7_rx {
> > > + /*
> > > + * Configure a pull-up on RX. This is needed to avoid
> > > + * garbage data when the TX pin of the Bluetooth module is
> > > + * in tri-state (module powered off or not driving the
> > > + * signal yet).
> > > + */
> > > + bias-pull-up;
> > > +};
> > > +
> > > +&tlmm {
> > > + qup_uart7_sleep_cts: qup-uart7-sleep-cts {
> > > + pins = "gpio28";
> > > + function = "gpio";
> > > + /*
> > > + * Configure a pull-down on CTS to match the pull of
> > > + * the Bluetooth module.
> > > + */
> > > + bias-pull-down;
> > > + };
> > > +
> > > + qup_uart7_sleep_rts: qup-uart7-sleep-rts {
> > > + pins = "gpio29";
> > > + function = "gpio";
> > > + /*
> > > + * Configure pull-down on RTS. As RTS is active low
> > > + * signal, pull it low to indicate the BT SoC that it
> > > + * can wakeup the system anytime from suspend state by
> > > + * pulling RX low (by sending wakeup bytes).
> > > + */
> > > + bias-pull-down;
> > > + };
> > > +
> > > + qup_uart7_sleep_tx: qup-uart7-sleep-tx {
> > > + pins = "gpio30";
> > > + function = "gpio";
> > > + /*
> > > + * Configure pull-up on TX when it isn't actively driven
> > > + * to prevent BT SoC from receiving garbage during sleep.
> > > + */
> > > + bias-pull-up;
> > > + };
> > >
> > > + qup_uart7_sleep_rx: qup-uart7-sleep-rx {
> > > + pins = "gpio31";
> > > + function = "gpio";
> > > + /*
> > > + * Configure a pull-up on RX. This is needed to avoid
> > > + * garbage data when the TX pin of the Bluetooth module
> > > + * is floating which may cause spurious wakeups.
> > > + */
> > > + bias-pull-up;
> > > + };
> > > +};
> >
> > How the patches of this series are split strikes me as a bit odd.
> > Supposedly
> > this patch adds the QUPv3 wrapper_0 DT nodes for the SC7280, however the
> > above is the pin configuration for the Bluetooth UART of the SC7280 IDP
> > board.
> > I don't see a good reason why that should be part of this patch. It
> > should be
> > a separate change whose subject indicates that it configures the
> > Bluetooth UART
> > of the SC7280 IDP.
> >
>
> Okay will split this up.
>
> > Without this conflation of SoC and board DT it would seem perfectly
> > reasonable
> > to squash this patch and '[4/4] arm64: dts: sc7280: Add QUPv3 wrapper_1
> > nodes'
> > into a single one, they are essentially doing the same thing, I see no
> > need to
> > have different patches for the wrapper 0 and 1 nodes.
>
> Previously when QUP wrapper 0 and wrapper 1 nodes were added in single
> patch, we faced some git issues as the patch was huge. Hence we split it up.
> https://partnerissuetracker.corp.google.com/issues/177045897#comment12
That bug tracker entry isn't public, this is what the comment says:
> I suspect that diff is just having a hard time since your patch touches so
> much stuff. Presumably you could make it happier if you broke your patch
> into smaller changes. For instance:
>
> One patch that adds the quad SPI. After all the quad SPI isn't really
> related to the other QUP stuff. One patch that fixes up the existing
> "uart5" and the QUP it's on to be how it's supposed to be. One patch
> that adds all the new stuff.
If I understand correctly the problem wasn't that the QUP wrappers are
added in a single patch (which should be pretty straightforward to
review), but that the previous patch(es) do too many things at once.
Adding both QUP wrappers is conceptionally a single thing, the problem
is intermingling that with adding board specific Bluetooth nodes, board
flash nodes, pinconf for UART, etc
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-11 14:52 ` Matthias Kaehlcke
@ 2021-08-12 7:13 ` rajpat
2021-08-12 12:49 ` Matthias Kaehlcke
0 siblings, 1 reply; 18+ messages in thread
From: rajpat @ 2021-08-12 7:13 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On 2021-08-11 20:22, Matthias Kaehlcke wrote:
> On Wed, Aug 11, 2021 at 05:43:48PM +0530, rajpat@codeaurora.org wrote:
>> On 2021-07-26 21:32, Matthias Kaehlcke wrote:
>> > On Mon, Jul 26, 2021 at 07:10:45PM +0530, Rajesh Patil wrote:
>> > > From: Roja Rani Yarubandi <rojay@codeaurora.org>
>> > >
>> > > Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
>> > >
>> > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>> > > ---
>> > > Changes in V4:
>> > > - As per Bjorn's comment, added QUP Wrapper_0 nodes
>> > > other than debug-uart node
>> > > - Dropped interconnect votes for wrapper_0 node
>> > >
>> > > Changes in V3:
>> > > - Broken the huge V2 patch into 3 smaller patches.
>> > > 1. QSPI DT nodes
>> > > 2. QUP wrapper_0 DT nodes
>> > > 3. QUP wrapper_1 DT nodes
>> > >
>> > > Changes in V2:
>> > > - As per Doug's comments removed pinmux/pinconf subnodes.
>> > > - As per Doug's comments split of SPI, UART nodes has been done.
>> > > - Moved QSPI node before aps_smmu as per the order.
>> > >
>> > > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 84 ++++
>> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 720
>> > > ++++++++++++++++++++++++++++++++
>> > > 2 files changed, 804 insertions(+)
>> > >
>> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> > > b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> > > index b0bfd8e..f63cf51 100644
>> > > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> > > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> > > @@ -358,6 +358,16 @@
>> > > vdda18-supply = <&vreg_l1c_1p8>;
>> > > };
>> > >
>> > > +&uart7 {
>> > > + status = "okay";
>> > > +
>> > > + /delete-property/interrupts;
>> > > + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
>> > > + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
>> > > + pinctrl-names = "default", "sleep";
>> > > + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>,
>> > > <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
>> > > +};
>> > > +
>> > > /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>> > >
>> > > &qspi_cs0 {
>> > > @@ -428,3 +438,77 @@
>> > > bias-pull-up;
>> > > };
>> > > };
>> > > +&qup_uart7_cts {
>> > > + /*
>> > > + * Configure a pull-down on CTS to match the pull of
>> > > + * the Bluetooth module.
>> > > + */
>> > > + bias-pull-down;
>> > > +};
>> > > +
>> > > +&qup_uart7_rts {
>> > > + /* We'll drive RTS, so no pull */
>> > > + drive-strength = <2>;
>> > > + bias-disable;
>> > > +};
>> > > +
>> > > +&qup_uart7_tx {
>> > > + /* We'll drive TX, so no pull */
>> > > + drive-strength = <2>;
>> > > + bias-disable;
>> > > +};
>> > > +
>> > > +&qup_uart7_rx {
>> > > + /*
>> > > + * Configure a pull-up on RX. This is needed to avoid
>> > > + * garbage data when the TX pin of the Bluetooth module is
>> > > + * in tri-state (module powered off or not driving the
>> > > + * signal yet).
>> > > + */
>> > > + bias-pull-up;
>> > > +};
>> > > +
>> > > +&tlmm {
>> > > + qup_uart7_sleep_cts: qup-uart7-sleep-cts {
>> > > + pins = "gpio28";
>> > > + function = "gpio";
>> > > + /*
>> > > + * Configure a pull-down on CTS to match the pull of
>> > > + * the Bluetooth module.
>> > > + */
>> > > + bias-pull-down;
>> > > + };
>> > > +
>> > > + qup_uart7_sleep_rts: qup-uart7-sleep-rts {
>> > > + pins = "gpio29";
>> > > + function = "gpio";
>> > > + /*
>> > > + * Configure pull-down on RTS. As RTS is active low
>> > > + * signal, pull it low to indicate the BT SoC that it
>> > > + * can wakeup the system anytime from suspend state by
>> > > + * pulling RX low (by sending wakeup bytes).
>> > > + */
>> > > + bias-pull-down;
>> > > + };
>> > > +
>> > > + qup_uart7_sleep_tx: qup-uart7-sleep-tx {
>> > > + pins = "gpio30";
>> > > + function = "gpio";
>> > > + /*
>> > > + * Configure pull-up on TX when it isn't actively driven
>> > > + * to prevent BT SoC from receiving garbage during sleep.
>> > > + */
>> > > + bias-pull-up;
>> > > + };
>> > >
>> > > + qup_uart7_sleep_rx: qup-uart7-sleep-rx {
>> > > + pins = "gpio31";
>> > > + function = "gpio";
>> > > + /*
>> > > + * Configure a pull-up on RX. This is needed to avoid
>> > > + * garbage data when the TX pin of the Bluetooth module
>> > > + * is floating which may cause spurious wakeups.
>> > > + */
>> > > + bias-pull-up;
>> > > + };
>> > > +};
>> >
>> > How the patches of this series are split strikes me as a bit odd.
>> > Supposedly
>> > this patch adds the QUPv3 wrapper_0 DT nodes for the SC7280, however the
>> > above is the pin configuration for the Bluetooth UART of the SC7280 IDP
>> > board.
>> > I don't see a good reason why that should be part of this patch. It
>> > should be
>> > a separate change whose subject indicates that it configures the
>> > Bluetooth UART
>> > of the SC7280 IDP.
>> >
>>
>> Okay will split this up.
>>
>> > Without this conflation of SoC and board DT it would seem perfectly
>> > reasonable
>> > to squash this patch and '[4/4] arm64: dts: sc7280: Add QUPv3 wrapper_1
>> > nodes'
>> > into a single one, they are essentially doing the same thing, I see no
>> > need to
>> > have different patches for the wrapper 0 and 1 nodes.
>>
>> Previously when QUP wrapper 0 and wrapper 1 nodes were added in single
>> patch, we faced some git issues as the patch was huge. Hence we split
>> it up.
>> https://partnerissuetracker.corp.google.com/issues/177045897#comment12
>
> That bug tracker entry isn't public, this is what the comment says:
>
>> I suspect that diff is just having a hard time since your patch
>> touches so
>> much stuff. Presumably you could make it happier if you broke your
>> patch
>> into smaller changes. For instance:
>>
>> One patch that adds the quad SPI. After all the quad SPI isn't really
>> related to the other QUP stuff. One patch that fixes up the existing
>> "uart5" and the QUP it's on to be how it's supposed to be. One patch
>> that adds all the new stuff.
>
> If I understand correctly the problem wasn't that the QUP wrappers are
> added in a single patch (which should be pretty straightforward to
> review), but that the previous patch(es) do too many things at once.
> Adding both QUP wrappers is conceptionally a single thing, the problem
> is intermingling that with adding board specific Bluetooth nodes, board
> flash nodes, pinconf for UART, etc
Even after splitting the patches as suggested(i.e., additions and
modifications separately), if I add qup wrapper0 and wrapper1 nodes in
single patch the git diff is getting messed up. pasted the diff for
reference
+ qup_spi14_cs_gpio: qup-spi14-cs_gpio {
+ pins = "gpio59";
+ function = "gpio";
+ };
- assigned-clocks = <&gcc
GCC_USB30_PRIM_MOCK_UTMI_CLK>,
- <&gcc
GCC_USB30_PRIM_MASTER_CLK>;
- assigned-clock-rates = <19200000>, <200000000>;
+ qup_spi15_data_clk: qup-spi15-data-clk {
+ pins = "gpio60", "gpio61", "gpio62";
+ function = "qup17";
+ };
- interrupts-extended = <&intc GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 14
IRQ_TYPE_EDGE_BOTH>,
- <&pdc 15
IRQ_TYPE_EDGE_BOTH>,
- <&pdc 17
IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
- "dm_hs_phy_irq", "ss_phy_irq";
+ qup_spi15_cs: qup-spi15-cs {
+ pins = "gpio63";
+ function = "qup17";
+ };
- power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ qup_spi15_cs_gpio: qup-spi15-cs_gpio {
+ pins = "gpio63";
+ function = "gpio";
+ };
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-08-12 7:13 ` rajpat
@ 2021-08-12 12:49 ` Matthias Kaehlcke
0 siblings, 0 replies; 18+ messages in thread
From: Matthias Kaehlcke @ 2021-08-12 12:49 UTC (permalink / raw)
To: rajpat
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
linux-kernel, devicetree, rnayak, saiprakash.ranjan, msavaliy,
skakit
On Thu, Aug 12, 2021 at 12:43:11PM +0530, rajpat@codeaurora.org wrote:
> On 2021-08-11 20:22, Matthias Kaehlcke wrote:
> > On Wed, Aug 11, 2021 at 05:43:48PM +0530, rajpat@codeaurora.org wrote:
> > > On 2021-07-26 21:32, Matthias Kaehlcke wrote:
> > > > On Mon, Jul 26, 2021 at 07:10:45PM +0530, Rajesh Patil wrote:
> > > > > From: Roja Rani Yarubandi <rojay@codeaurora.org>
> > > > >
> > > > > Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
> > > > >
> > > > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> > > > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > > > > ---
> > > > > Changes in V4:
> > > > > - As per Bjorn's comment, added QUP Wrapper_0 nodes
> > > > > other than debug-uart node
> > > > > - Dropped interconnect votes for wrapper_0 node
> > > > >
> > > > > Changes in V3:
> > > > > - Broken the huge V2 patch into 3 smaller patches.
> > > > > 1. QSPI DT nodes
> > > > > 2. QUP wrapper_0 DT nodes
> > > > > 3. QUP wrapper_1 DT nodes
> > > > >
> > > > > Changes in V2:
> > > > > - As per Doug's comments removed pinmux/pinconf subnodes.
> > > > > - As per Doug's comments split of SPI, UART nodes has been done.
> > > > > - Moved QSPI node before aps_smmu as per the order.
> > > > >
> > > > > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 84 ++++
> > > > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 720
> > > > > ++++++++++++++++++++++++++++++++
> > > > > 2 files changed, 804 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > > > b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > > > index b0bfd8e..f63cf51 100644
> > > > > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > > > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > > > @@ -358,6 +358,16 @@
> > > > > vdda18-supply = <&vreg_l1c_1p8>;
> > > > > };
> > > > >
> > > > > +&uart7 {
> > > > > + status = "okay";
> > > > > +
> > > > > + /delete-property/interrupts;
> > > > > + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
> > > > > + pinctrl-names = "default", "sleep";
> > > > > + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>,
> > > > > <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
> > > > > +};
> > > > > +
> > > > > /* PINCTRL - additions to nodes defined in sc7280.dtsi */
> > > > >
> > > > > &qspi_cs0 {
> > > > > @@ -428,3 +438,77 @@
> > > > > bias-pull-up;
> > > > > };
> > > > > };
> > > > > +&qup_uart7_cts {
> > > > > + /*
> > > > > + * Configure a pull-down on CTS to match the pull of
> > > > > + * the Bluetooth module.
> > > > > + */
> > > > > + bias-pull-down;
> > > > > +};
> > > > > +
> > > > > +&qup_uart7_rts {
> > > > > + /* We'll drive RTS, so no pull */
> > > > > + drive-strength = <2>;
> > > > > + bias-disable;
> > > > > +};
> > > > > +
> > > > > +&qup_uart7_tx {
> > > > > + /* We'll drive TX, so no pull */
> > > > > + drive-strength = <2>;
> > > > > + bias-disable;
> > > > > +};
> > > > > +
> > > > > +&qup_uart7_rx {
> > > > > + /*
> > > > > + * Configure a pull-up on RX. This is needed to avoid
> > > > > + * garbage data when the TX pin of the Bluetooth module is
> > > > > + * in tri-state (module powered off or not driving the
> > > > > + * signal yet).
> > > > > + */
> > > > > + bias-pull-up;
> > > > > +};
> > > > > +
> > > > > +&tlmm {
> > > > > + qup_uart7_sleep_cts: qup-uart7-sleep-cts {
> > > > > + pins = "gpio28";
> > > > > + function = "gpio";
> > > > > + /*
> > > > > + * Configure a pull-down on CTS to match the pull of
> > > > > + * the Bluetooth module.
> > > > > + */
> > > > > + bias-pull-down;
> > > > > + };
> > > > > +
> > > > > + qup_uart7_sleep_rts: qup-uart7-sleep-rts {
> > > > > + pins = "gpio29";
> > > > > + function = "gpio";
> > > > > + /*
> > > > > + * Configure pull-down on RTS. As RTS is active low
> > > > > + * signal, pull it low to indicate the BT SoC that it
> > > > > + * can wakeup the system anytime from suspend state by
> > > > > + * pulling RX low (by sending wakeup bytes).
> > > > > + */
> > > > > + bias-pull-down;
> > > > > + };
> > > > > +
> > > > > + qup_uart7_sleep_tx: qup-uart7-sleep-tx {
> > > > > + pins = "gpio30";
> > > > > + function = "gpio";
> > > > > + /*
> > > > > + * Configure pull-up on TX when it isn't actively driven
> > > > > + * to prevent BT SoC from receiving garbage during sleep.
> > > > > + */
> > > > > + bias-pull-up;
> > > > > + };
> > > > >
> > > > > + qup_uart7_sleep_rx: qup-uart7-sleep-rx {
> > > > > + pins = "gpio31";
> > > > > + function = "gpio";
> > > > > + /*
> > > > > + * Configure a pull-up on RX. This is needed to avoid
> > > > > + * garbage data when the TX pin of the Bluetooth module
> > > > > + * is floating which may cause spurious wakeups.
> > > > > + */
> > > > > + bias-pull-up;
> > > > > + };
> > > > > +};
> > > >
> > > > How the patches of this series are split strikes me as a bit odd.
> > > > Supposedly
> > > > this patch adds the QUPv3 wrapper_0 DT nodes for the SC7280, however the
> > > > above is the pin configuration for the Bluetooth UART of the SC7280 IDP
> > > > board.
> > > > I don't see a good reason why that should be part of this patch. It
> > > > should be
> > > > a separate change whose subject indicates that it configures the
> > > > Bluetooth UART
> > > > of the SC7280 IDP.
> > > >
> > >
> > > Okay will split this up.
> > >
> > > > Without this conflation of SoC and board DT it would seem perfectly
> > > > reasonable
> > > > to squash this patch and '[4/4] arm64: dts: sc7280: Add QUPv3 wrapper_1
> > > > nodes'
> > > > into a single one, they are essentially doing the same thing, I see no
> > > > need to
> > > > have different patches for the wrapper 0 and 1 nodes.
> > >
> > > Previously when QUP wrapper 0 and wrapper 1 nodes were added in single
> > > patch, we faced some git issues as the patch was huge. Hence we
> > > split it up.
> > > https://partnerissuetracker.corp.google.com/issues/177045897#comment12
> >
> > That bug tracker entry isn't public, this is what the comment says:
> >
> > > I suspect that diff is just having a hard time since your patch
> > > touches so
> > > much stuff. Presumably you could make it happier if you broke your
> > > patch
> > > into smaller changes. For instance:
> > >
> > > One patch that adds the quad SPI. After all the quad SPI isn't really
> > > related to the other QUP stuff. One patch that fixes up the existing
> > > "uart5" and the QUP it's on to be how it's supposed to be. One patch
> > > that adds all the new stuff.
> >
> > If I understand correctly the problem wasn't that the QUP wrappers are
> > added in a single patch (which should be pretty straightforward to
> > review), but that the previous patch(es) do too many things at once.
> > Adding both QUP wrappers is conceptionally a single thing, the problem
> > is intermingling that with adding board specific Bluetooth nodes, board
> > flash nodes, pinconf for UART, etc
>
> Even after splitting the patches as suggested(i.e., additions and
> modifications separately), if I add qup wrapper0 and wrapper1 nodes in
> single patch the git diff is getting messed up. pasted the diff for
> reference
>
>
> + qup_spi14_cs_gpio: qup-spi14-cs_gpio {
> + pins = "gpio59";
> + function = "gpio";
> + };
>
> - assigned-clocks = <&gcc
> GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> - <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> - assigned-clock-rates = <19200000>, <200000000>;
> + qup_spi15_data_clk: qup-spi15-data-clk {
> + pins = "gpio60", "gpio61", "gpio62";
> + function = "qup17";
> + };
>
> - interrupts-extended = <&intc GIC_SPI 131
> IRQ_TYPE_LEVEL_HIGH>,
> - <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
> - <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
> - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
> - "dm_hs_phy_irq", "ss_phy_irq";
> + qup_spi15_cs: qup-spi15-cs {
> + pins = "gpio63";
> + function = "qup17";
> + };
>
>
> - power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
> + qup_spi15_cs_gpio: qup-spi15-cs_gpio {
> + pins = "gpio63";
> + function = "gpio";
> + };
>
If the diffs actually end up more messy with a single patch in this case
then there is no point for it. Thanks for trying.
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2021-08-12 12:49 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-26 13:40 [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-07-26 13:40 ` [PATCH V4 1/4] arm64: dts: sc7280: Add QSPI node Rajesh Patil
2021-07-26 16:07 ` Matthias Kaehlcke
2021-08-11 12:14 ` rajpat
2021-07-26 13:40 ` [PATCH V4 2/4] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
2021-07-26 16:02 ` Matthias Kaehlcke
2021-08-11 12:13 ` rajpat
2021-08-11 14:52 ` Matthias Kaehlcke
2021-08-12 7:13 ` rajpat
2021-08-12 12:49 ` Matthias Kaehlcke
2021-07-27 19:20 ` Stephen Boyd
2021-08-11 12:17 ` rajpat
2021-07-26 13:40 ` [PATCH V4 3/4] arm64: dts: sc7280: Update QUPv3 Debug UART DT node Rajesh Patil
2021-07-26 15:42 ` Matthias Kaehlcke
2021-08-11 12:04 ` rajpat
2021-07-26 13:40 ` [PATCH V4 4/4] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
2021-07-27 0:14 ` [PATCH V4 0/4] Add QSPI and QUPv3 DT nodes for SC7280 SoC Stephen Boyd
2021-08-11 12:14 ` rajpat
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