From: Bin Meng <bmeng.cn@gmail.com>
To: Atish Patra <Atish.Patra@wdc.com>
Cc: "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
"sagark@eecs.berkeley.edu" <sagark@eecs.berkeley.edu>,
"kbastian@mail.uni-paderborn.de" <kbastian@mail.uni-paderborn.de>,
Anup Patel <Anup.Patel@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>
Subject: Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
Date: Fri, 18 Dec 2020 16:42:40 +0800 [thread overview]
Message-ID: <CAEUhbmVEAxf3OCp=89MCx7qQiN0wKd3QM4k8t20r9Sbq+JA_-w@mail.gmail.com> (raw)
In-Reply-To: <67cbbde886c3ae6e57e837e79f466f4156a910f8.camel@wdc.com>
Hi Atish,
On Fri, Dec 18, 2020 at 4:00 PM Atish Patra <Atish.Patra@wdc.com> wrote:
>
> On Fri, 2020-12-18 at 15:33 +0800, Bin Meng wrote:
> > Hi Atish,
> >
> > On Fri, Dec 18, 2020 at 3:27 PM Atish Patra <Atish.Patra@wdc.com>
> > wrote:
> > >
> > > On Fri, 2020-12-18 at 15:21 +0800, Bin Meng wrote:
> > > > Hi Atish,
> > > >
> > > > On Fri, Dec 18, 2020 at 5:48 AM Atish Patra <atish.patra@wdc.com>
> > > > wrote:
> > > > >
> > > > > Currently, we place the DTB at 2MB from 4GB or end of DRAM
> > > > > which
> > > > > ever is
> > > > > lesser. However, Linux kernel can address only 1GB of memory
> > > > > for
> > > > > RV32.
> > > > > Thus, it can not map anything beyond 3GB (assuming 2GB is the
> > > > > starting address).
> > > > > As a result, it can not process DT and panic if opensbi dynamic
> > > > > firmware
> > > > > is used.
> > > > >
> > > > > Fix this by placing the DTB at 2MB from 3GB or end of DRAM
> > > > > whichever is lower.
> > > > >
> > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > > > > ---
> > > > > hw/riscv/boot.c | 4 ++--
> > > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > > >
> > > >
> > > > With this patch, 32-bit sifive_u still does not boot kernel with
> > > > the
> > > > following patch applied on 5.10:
> > > > https://patchwork.kernel.org/project/linux-riscv/patch/20201217074855.1948743-1-atish.patra@wdc.com/
> > > >
> > > > Command I used:
> > > > $ qemu-system-riscv32 -nographic -M sifive_u -m 1G -smp 5 -kernel
> > > > arch/riscv/boot/Image
> > > >
> > > > 32-bit virt cannot boot the same kernel image with memory set to
> > > > 2G
> > > > either:
> > > > $ qemu-system-riscv32 -nographic -M virt -m 2G -smp 4 -kernel
> > > > arch/riscv/boot/Image
> > > >
> > >
> > > Hi Bin,
> > > As mentioned in the email on the linux mailing list, this patch
> > > only
> > > solves 2GB problem. sifive_u problem is solved by Alistair's
> > > patch[1].
> > >
> > > He is planning to send the PR soon. The issue with sifive_u boot
> > > was it
> > > was failing the 32 bit test earlier resulting a 2MB aligned address
> > > instead of 4MB.
> >
> > Ah, I see. However my testing shows that virt with 2G still does not
> > boot with this patch.
> >
>
> Strange. I verified again with following combination with -bios and
> without bios parameter.
>
> 1. virt 32/64 with 1GB/2GB memory
> 2. sifive_u 32/64 bit with 1GB/2GB memory (Alistair's patch included)
>
> Can you share the boot log along with the head commit of Qemu and
> commandline ? I am using 5.10 kernel with my kernel fix.
>
I was using Alistair's QEMU repo for testing and 5.10 kernel with your
kernel fix:
$ git checkout -b testing pull-riscv-to-apply-20201217-1
$ apply this patch
$ mkdir build;cd build;../configure
--target-list=riscv64-softmmu,riscv32-softmmu;make -j
$ ./qemu-system-riscv32 -nographic -M virt -m 2G -smp 4 -kernel
~/work/git/linux/arch/riscv/boot/Image
OpenSBI v0.8
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : riscv-virtio,qemu
Platform Features : timer,mfdeleg
Platform HART Count : 4
Boot HART ID : 3
Boot HART ISA : rv32imafdcsu
BOOT HART Features : pmp,scounteren,mcounteren,time
BOOT HART PMP Count : 16
Firmware Base : 0x80000000
Firmware Size : 104 KB
Runtime SBI Version : 0.2
MIDELEG : 0x00000222
MEDELEG : 0x0000b109
PMP0 : 0x80000000-0x8001ffff (A)
PMP1 : 0x00000000-0xffffffff (A,R,W,X)
<hangs here>
$ ./qemu-system-riscv32 -nographic -M sifive_u -m 2G -smp 5 -kernel
~/work/git/linux/arch/riscv/boot/Image
OpenSBI v0.8
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : SiFive HiFive Unleashed A00
Platform Features : timer,mfdeleg
Platform HART Count : 5
Boot HART ID : 4
Boot HART ISA : rv32imafdcsu
BOOT HART Features : pmp,scounteren,mcounteren
BOOT HART PMP Count : 16
Firmware Base : 0x80000000
Firmware Size : 112 KB
Runtime SBI Version : 0.2
MIDELEG : 0x00000222
MEDELEG : 0x0000b109
PMP0 : 0x80000000-0x8001ffff (A)
PMP1 : 0x00000000-0xffffffff (A,R,W,X)
<hangs here>
The following is sifive_u with 1G:
$ ./qemu-system-riscv32 -nographic -M sifive_u -m 1G -smp 5 -kernel
~/work/git/linux/arch/riscv/boot/Image
OpenSBI v0.8
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : SiFive HiFive Unleashed A00
Platform Features : timer,mfdeleg
Platform HART Count : 5
Boot HART ID : 3
Boot HART ISA : rv32imafdcsu
BOOT HART Features : pmp,scounteren,mcounteren
BOOT HART PMP Count : 16
Firmware Base : 0x80000000
Firmware Size : 112 KB
Runtime SBI Version : 0.2
MIDELEG : 0x00000222
MEDELEG : 0x0000b109
PMP0 : 0x80000000-0x8001ffff (A)
PMP1 : 0x00000000-0xffffffff (A,R,W,X)
[ 0.000000] Linux version 5.10.0-00001-gbf0dad61896d
(bmeng@pek-vx-bsp2) (riscv64-linux-gcc (GCC) 8.1.0, GNU ld (GNU
Binutils) 2.30) #1 SMP Thu Dec 17 16:48:13 CST 2020
[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80400000
[ 0.000000] efi: UEFI not found.
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000080400000-0x00000000bfffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080400000-0x00000000bfffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x00000000bfffffff]
[ 0.000000] SBI specification v0.2 detected
[ 0.000000] SBI implementation ID=0x1 Version=0x8
[ 0.000000] SBI v0.2 TIME extension detected
[ 0.000000] SBI v0.2 IPI extension detected
[ 0.000000] SBI v0.2 RFENCE extension detected
[ 0.000000] SBI v0.2 HSM extension detected
[ 0.000000] CPU with hartid=0 is not available
[ 0.000000] CPU with hartid=0 is not available
Regards,
Bin
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Atish Patra <Atish.Patra@wdc.com>
Cc: "sagark@eecs.berkeley.edu" <sagark@eecs.berkeley.edu>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
"kbastian@mail.uni-paderborn.de"
<kbastian@mail.uni-paderborn.de>,
Alistair Francis <Alistair.Francis@wdc.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
Anup Patel <Anup.Patel@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB
Date: Fri, 18 Dec 2020 16:42:40 +0800 [thread overview]
Message-ID: <CAEUhbmVEAxf3OCp=89MCx7qQiN0wKd3QM4k8t20r9Sbq+JA_-w@mail.gmail.com> (raw)
In-Reply-To: <67cbbde886c3ae6e57e837e79f466f4156a910f8.camel@wdc.com>
Hi Atish,
On Fri, Dec 18, 2020 at 4:00 PM Atish Patra <Atish.Patra@wdc.com> wrote:
>
> On Fri, 2020-12-18 at 15:33 +0800, Bin Meng wrote:
> > Hi Atish,
> >
> > On Fri, Dec 18, 2020 at 3:27 PM Atish Patra <Atish.Patra@wdc.com>
> > wrote:
> > >
> > > On Fri, 2020-12-18 at 15:21 +0800, Bin Meng wrote:
> > > > Hi Atish,
> > > >
> > > > On Fri, Dec 18, 2020 at 5:48 AM Atish Patra <atish.patra@wdc.com>
> > > > wrote:
> > > > >
> > > > > Currently, we place the DTB at 2MB from 4GB or end of DRAM
> > > > > which
> > > > > ever is
> > > > > lesser. However, Linux kernel can address only 1GB of memory
> > > > > for
> > > > > RV32.
> > > > > Thus, it can not map anything beyond 3GB (assuming 2GB is the
> > > > > starting address).
> > > > > As a result, it can not process DT and panic if opensbi dynamic
> > > > > firmware
> > > > > is used.
> > > > >
> > > > > Fix this by placing the DTB at 2MB from 3GB or end of DRAM
> > > > > whichever is lower.
> > > > >
> > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > > > > ---
> > > > > hw/riscv/boot.c | 4 ++--
> > > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > > >
> > > >
> > > > With this patch, 32-bit sifive_u still does not boot kernel with
> > > > the
> > > > following patch applied on 5.10:
> > > > https://patchwork.kernel.org/project/linux-riscv/patch/20201217074855.1948743-1-atish.patra@wdc.com/
> > > >
> > > > Command I used:
> > > > $ qemu-system-riscv32 -nographic -M sifive_u -m 1G -smp 5 -kernel
> > > > arch/riscv/boot/Image
> > > >
> > > > 32-bit virt cannot boot the same kernel image with memory set to
> > > > 2G
> > > > either:
> > > > $ qemu-system-riscv32 -nographic -M virt -m 2G -smp 4 -kernel
> > > > arch/riscv/boot/Image
> > > >
> > >
> > > Hi Bin,
> > > As mentioned in the email on the linux mailing list, this patch
> > > only
> > > solves 2GB problem. sifive_u problem is solved by Alistair's
> > > patch[1].
> > >
> > > He is planning to send the PR soon. The issue with sifive_u boot
> > > was it
> > > was failing the 32 bit test earlier resulting a 2MB aligned address
> > > instead of 4MB.
> >
> > Ah, I see. However my testing shows that virt with 2G still does not
> > boot with this patch.
> >
>
> Strange. I verified again with following combination with -bios and
> without bios parameter.
>
> 1. virt 32/64 with 1GB/2GB memory
> 2. sifive_u 32/64 bit with 1GB/2GB memory (Alistair's patch included)
>
> Can you share the boot log along with the head commit of Qemu and
> commandline ? I am using 5.10 kernel with my kernel fix.
>
I was using Alistair's QEMU repo for testing and 5.10 kernel with your
kernel fix:
$ git checkout -b testing pull-riscv-to-apply-20201217-1
$ apply this patch
$ mkdir build;cd build;../configure
--target-list=riscv64-softmmu,riscv32-softmmu;make -j
$ ./qemu-system-riscv32 -nographic -M virt -m 2G -smp 4 -kernel
~/work/git/linux/arch/riscv/boot/Image
OpenSBI v0.8
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : riscv-virtio,qemu
Platform Features : timer,mfdeleg
Platform HART Count : 4
Boot HART ID : 3
Boot HART ISA : rv32imafdcsu
BOOT HART Features : pmp,scounteren,mcounteren,time
BOOT HART PMP Count : 16
Firmware Base : 0x80000000
Firmware Size : 104 KB
Runtime SBI Version : 0.2
MIDELEG : 0x00000222
MEDELEG : 0x0000b109
PMP0 : 0x80000000-0x8001ffff (A)
PMP1 : 0x00000000-0xffffffff (A,R,W,X)
<hangs here>
$ ./qemu-system-riscv32 -nographic -M sifive_u -m 2G -smp 5 -kernel
~/work/git/linux/arch/riscv/boot/Image
OpenSBI v0.8
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : SiFive HiFive Unleashed A00
Platform Features : timer,mfdeleg
Platform HART Count : 5
Boot HART ID : 4
Boot HART ISA : rv32imafdcsu
BOOT HART Features : pmp,scounteren,mcounteren
BOOT HART PMP Count : 16
Firmware Base : 0x80000000
Firmware Size : 112 KB
Runtime SBI Version : 0.2
MIDELEG : 0x00000222
MEDELEG : 0x0000b109
PMP0 : 0x80000000-0x8001ffff (A)
PMP1 : 0x00000000-0xffffffff (A,R,W,X)
<hangs here>
The following is sifive_u with 1G:
$ ./qemu-system-riscv32 -nographic -M sifive_u -m 1G -smp 5 -kernel
~/work/git/linux/arch/riscv/boot/Image
OpenSBI v0.8
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : SiFive HiFive Unleashed A00
Platform Features : timer,mfdeleg
Platform HART Count : 5
Boot HART ID : 3
Boot HART ISA : rv32imafdcsu
BOOT HART Features : pmp,scounteren,mcounteren
BOOT HART PMP Count : 16
Firmware Base : 0x80000000
Firmware Size : 112 KB
Runtime SBI Version : 0.2
MIDELEG : 0x00000222
MEDELEG : 0x0000b109
PMP0 : 0x80000000-0x8001ffff (A)
PMP1 : 0x00000000-0xffffffff (A,R,W,X)
[ 0.000000] Linux version 5.10.0-00001-gbf0dad61896d
(bmeng@pek-vx-bsp2) (riscv64-linux-gcc (GCC) 8.1.0, GNU ld (GNU
Binutils) 2.30) #1 SMP Thu Dec 17 16:48:13 CST 2020
[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80400000
[ 0.000000] efi: UEFI not found.
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000080400000-0x00000000bfffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080400000-0x00000000bfffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x00000000bfffffff]
[ 0.000000] SBI specification v0.2 detected
[ 0.000000] SBI implementation ID=0x1 Version=0x8
[ 0.000000] SBI v0.2 TIME extension detected
[ 0.000000] SBI v0.2 IPI extension detected
[ 0.000000] SBI v0.2 RFENCE extension detected
[ 0.000000] SBI v0.2 HSM extension detected
[ 0.000000] CPU with hartid=0 is not available
[ 0.000000] CPU with hartid=0 is not available
Regards,
Bin
next prev parent reply other threads:[~2020-12-18 8:44 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-17 21:48 [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB Atish Patra
2020-12-17 21:48 ` Atish Patra
2020-12-17 22:31 ` Palmer Dabbelt
2020-12-17 22:31 ` Palmer Dabbelt
2020-12-17 22:35 ` Atish Patra
2020-12-17 22:35 ` Atish Patra
2020-12-17 22:39 ` Palmer Dabbelt
2020-12-17 22:39 ` Palmer Dabbelt
2020-12-18 7:21 ` Bin Meng
2020-12-18 7:21 ` Bin Meng
2020-12-18 7:27 ` Atish Patra
2020-12-18 7:27 ` Atish Patra
2020-12-18 7:33 ` Bin Meng
2020-12-18 7:33 ` Bin Meng
2020-12-18 8:00 ` Atish Patra
2020-12-18 8:00 ` Atish Patra
2020-12-18 8:42 ` Bin Meng [this message]
2020-12-18 8:42 ` Bin Meng
2020-12-18 19:46 ` Atish Patra
2020-12-18 19:46 ` Atish Patra
2020-12-22 5:35 ` Bin Meng
2020-12-22 5:35 ` Bin Meng
2020-12-22 19:59 ` Atish Patra
2020-12-22 19:59 ` Atish Patra
2020-12-23 1:20 ` Bin Meng
2020-12-23 1:20 ` Bin Meng
2020-12-29 4:49 ` Bin Meng
2020-12-29 4:49 ` Bin Meng
2021-01-04 20:24 ` Atish Patra
2021-01-04 20:24 ` Atish Patra
2021-01-05 3:06 ` Bin Meng
2021-01-05 3:06 ` Bin Meng
2021-01-05 3:11 ` Bin Meng
2021-01-05 3:11 ` Bin Meng
2021-01-05 21:02 ` Alistair Francis
2021-01-05 21:02 ` Alistair Francis
2021-01-05 23:44 ` Atish Patra
2021-01-05 23:44 ` Atish Patra
2021-01-06 0:04 ` Bin Meng
2021-01-06 0:04 ` Bin Meng
2021-01-06 2:14 ` Atish Patra
2021-01-06 2:14 ` Atish Patra
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