* [PATCH] riscv: fu540: dts: Correct reg size of clint node
@ 2020-10-20 5:33 Pragnesh Patel
2020-10-20 6:15 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA47C2AB8@ATCPCS16.andestech.com>
0 siblings, 2 replies; 3+ messages in thread
From: Pragnesh Patel @ 2020-10-20 5:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index a06e1b11c6..b7cd600b8c 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -62,7 +62,7 @@
&cpu2_intc 3 &cpu2_intc 7
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
- reg = <0x0 0x2000000 0x0 0xc0000>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
u-boot,dm-spl;
};
prci: clock-controller at 10000000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] riscv: fu540: dts: Correct reg size of clint node
2020-10-20 5:33 [PATCH] riscv: fu540: dts: Correct reg size of clint node Pragnesh Patel
@ 2020-10-20 6:15 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA47C2AB8@ATCPCS16.andestech.com>
1 sibling, 0 replies; 3+ messages in thread
From: Bin Meng @ 2020-10-20 6:15 UTC (permalink / raw)
To: u-boot
On Tue, Oct 20, 2020 at 1:33 PM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
> arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] riscv: fu540: dts: Correct reg size of clint node
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA47C2AB8@ATCPCS16.andestech.com>
@ 2020-10-21 3:33 ` Rick Chen
0 siblings, 0 replies; 3+ messages in thread
From: Rick Chen @ 2020-10-21 3:33 UTC (permalink / raw)
To: u-boot
> From: Pragnesh Patel [mailto:pragnesh.patel at sifive.com]
> Sent: Tuesday, October 20, 2020 1:33 PM
> To: u-boot at lists.denx.de; atish.patra at wdc.com; palmerdabbelt at google.com; bmeng.cn at gmail.com; paul.walmsley at sifive.com
> Cc: anup.patel at wdc.com; sagar.kadam at sifive.com; Rick Jian-Zhi Chen(???); Pragnesh Patel; Bin Meng; Jagan Teki; Sean Anderson
> Subject: [PATCH] riscv: fu540: dts: Correct reg size of clint node
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
> arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen <rick@andestech.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-10-21 3:33 UTC | newest]
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2020-10-20 5:33 [PATCH] riscv: fu540: dts: Correct reg size of clint node Pragnesh Patel
2020-10-20 6:15 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA47C2AB8@ATCPCS16.andestech.com>
2020-10-21 3:33 ` Rick Chen
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