All of lore.kernel.org
 help / color / mirror / Atom feed
From: Bin Meng <bmeng.cn@gmail.com>
To: Leif Lindholm <leif@nuviainc.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Alistair Francis" <alistair@alistair23.me>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
	"Jason Wang" <jasowang@redhat.com>,
	"Palmer Dabbelt" <palmerdabbelt@google.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	qemu-arm <qemu-arm@nongnu.org>,
	"Alistair Francis" <Alistair.Francis@wdc.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>
Subject: Re: [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support
Date: Mon, 31 Aug 2020 06:15:52 +0800	[thread overview]
Message-ID: <CAEUhbmVYpSVE+C+KyEa2Ono5p-SLtC1vE=YwE_3FJK6POEJCCg@mail.gmail.com> (raw)
In-Reply-To: <20200830125659.GD20124@vanye>

Hi Leif,

On Sun, Aug 30, 2020 at 8:57 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> Hi Bin,
>
> On Sat, Aug 29, 2020 at 23:17:24 +0800, Bin Meng wrote:
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > This adds support for Microchip PolarFire SoC Icicle Kit board.
> > The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
> > E51 plus four U54 cores and many on-chip peripherals and an FPGA.
> >
> > For more details about Microchip PolarFire SoC, please see:
> > https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
> >
> > The Icicle Kit board information can be found here:
> > https://www.microsemi.com/existing-parts/parts/152514
> >
> > Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
> > The RISC-V CPU and HART codes has been updated to set the core's
> > reset vector based on a configurable property from machine codes.
> >
> > The following perepherals are created as an unimplemented device:
> >
> > - Bus Error Uint 0/1/2/3/4
> > - L2 cache controller
> > - SYSREG
> > - MPUCFG
> > - IOSCBCFG
> > - GPIO
> >
> > The following perepherals are emulated:
> > - SiFive CLINT
> > - SiFive PLIC
> > - PolarFire SoC Multi-Mode UART
> > - SiFive PDMA
> > - Cadence eMMC/SDHCI controller
> > - Cadence Gigabit Ethernet MAC
> >
> > The BIOS image used by this machine is hss.bin, aka Hart Software
> > Services, which can be built from:
> > https://github.com/polarfire-soc/hart-software-services
>
> Are there any version requirements, or additional qemu patches, that
> need to be taken into account. Should I expect to see output on stdio?

Thanks for trying!

Did you apply the patch to skip the DDR memory initialization
mentioned in this page?
https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit

>
> I tried to build hss 3faaaaf8ce0d, using
> https://github.com/riscv/riscv-gnu-toolchain (7f1f4ab5b0e0), which
> ends up being a gcc 10.1. That caused me to raise
> https://github.com/polarfire-soc/hart-software-services/issues/2.

Yes, GCC 10 does not build is a known issue. Currently I am using GCC
9 to build HSS.

>
> Suppressing that warning gets me a hss.bin, but neither that, nor one
> I build with Debian's 8.3 riscv64-linux-gnu- produces any output when
> I apply this set on top of 39335fab59. (Even when I change the wait to
> nowait.)
>

Regards,
Bin


WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Leif Lindholm <leif@nuviainc.com>
Cc: "Alistair Francis" <Alistair.Francis@wdc.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Palmer Dabbelt" <palmerdabbelt@google.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
	"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
	"Jason Wang" <jasowang@redhat.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	qemu-arm <qemu-arm@nongnu.org>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>
Subject: Re: [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support
Date: Mon, 31 Aug 2020 06:15:52 +0800	[thread overview]
Message-ID: <CAEUhbmVYpSVE+C+KyEa2Ono5p-SLtC1vE=YwE_3FJK6POEJCCg@mail.gmail.com> (raw)
In-Reply-To: <20200830125659.GD20124@vanye>

Hi Leif,

On Sun, Aug 30, 2020 at 8:57 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> Hi Bin,
>
> On Sat, Aug 29, 2020 at 23:17:24 +0800, Bin Meng wrote:
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > This adds support for Microchip PolarFire SoC Icicle Kit board.
> > The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
> > E51 plus four U54 cores and many on-chip peripherals and an FPGA.
> >
> > For more details about Microchip PolarFire SoC, please see:
> > https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
> >
> > The Icicle Kit board information can be found here:
> > https://www.microsemi.com/existing-parts/parts/152514
> >
> > Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
> > The RISC-V CPU and HART codes has been updated to set the core's
> > reset vector based on a configurable property from machine codes.
> >
> > The following perepherals are created as an unimplemented device:
> >
> > - Bus Error Uint 0/1/2/3/4
> > - L2 cache controller
> > - SYSREG
> > - MPUCFG
> > - IOSCBCFG
> > - GPIO
> >
> > The following perepherals are emulated:
> > - SiFive CLINT
> > - SiFive PLIC
> > - PolarFire SoC Multi-Mode UART
> > - SiFive PDMA
> > - Cadence eMMC/SDHCI controller
> > - Cadence Gigabit Ethernet MAC
> >
> > The BIOS image used by this machine is hss.bin, aka Hart Software
> > Services, which can be built from:
> > https://github.com/polarfire-soc/hart-software-services
>
> Are there any version requirements, or additional qemu patches, that
> need to be taken into account. Should I expect to see output on stdio?

Thanks for trying!

Did you apply the patch to skip the DDR memory initialization
mentioned in this page?
https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit

>
> I tried to build hss 3faaaaf8ce0d, using
> https://github.com/riscv/riscv-gnu-toolchain (7f1f4ab5b0e0), which
> ends up being a gcc 10.1. That caused me to raise
> https://github.com/polarfire-soc/hart-software-services/issues/2.

Yes, GCC 10 does not build is a known issue. Currently I am using GCC
9 to build HSS.

>
> Suppressing that warning gets me a hss.bin, but neither that, nor one
> I build with Debian's 8.3 riscv64-linux-gnu- produces any output when
> I apply this set on top of 39335fab59. (Even when I change the wait to
> nowait.)
>

Regards,
Bin


  reply	other threads:[~2020-08-30 22:16 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-29 15:17 [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-08-29 15:17 ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 01/16] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 02/16] hw/riscv: hart: " Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 03/16] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 07/16] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 09/16] hw/dma: Add SiFive platform DMA controller emulation Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-29 15:17 ` [PATCH v2 16/16] hw/riscv: sifive_u: Connect a DMA controller Bin Meng
2020-08-29 15:17   ` Bin Meng
2020-08-30 12:56 ` [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Leif Lindholm
2020-08-30 12:56   ` Leif Lindholm
2020-08-30 22:15   ` Bin Meng [this message]
2020-08-30 22:15     ` Bin Meng
2020-08-30 23:35     ` Leif Lindholm
2020-08-30 23:35       ` Leif Lindholm

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAEUhbmVYpSVE+C+KyEa2Ono5p-SLtC1vE=YwE_3FJK6POEJCCg@mail.gmail.com' \
    --to=bmeng.cn@gmail.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=alistair@alistair23.me \
    --cc=bin.meng@windriver.com \
    --cc=edgar.iglesias@gmail.com \
    --cc=f4bug@amsat.org \
    --cc=jasowang@redhat.com \
    --cc=kbastian@mail.uni-paderborn.de \
    --cc=leif@nuviainc.com \
    --cc=marcandre.lureau@redhat.com \
    --cc=palmer@dabbelt.com \
    --cc=palmerdabbelt@google.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=sagark@eecs.berkeley.edu \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.