From: Bin Meng <bmeng.cn@gmail.com>
To: Dylan Jhong <dylan@andestech.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Alan Kao <alankao@andestech.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
ruinland@andestech.com,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH 1/3] Andes RISC-V PLIC
Date: Wed, 10 Mar 2021 14:05:51 +0800 [thread overview]
Message-ID: <CAEUhbmVgQzzS4DSOKM_zBxMMAb0bCZBJOZfQ7BUop84SaikZxg@mail.gmail.com> (raw)
In-Reply-To: <20210310033358.30499-2-dylan@andestech.com>
On Wed, Mar 10, 2021 at 11:34 AM Dylan Jhong <dylan@andestech.com> wrote:
>
> Andes PLIC (Platform-Level Interrupt Controller) device provides an
> interrupt controller functionality based on Andes's PLIC specification.
>
> The Andes PLIC can handle either external interrupts (PLIC)
> or interprocessor interrupts (PLICSW).
>
> While Andes PLIC spec includes vector interrupt and interrupt preemption,
> we leave them as future items for now.
>
> Signed-off-by: Dylan Jhong <dylan@andestech.com>
> Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
> ---
> hw/intc/Kconfig | 3 +
> hw/intc/andes_plic.c | 505 +++++++++++++++++++++++++++++++++++
> hw/intc/meson.build | 1 +
> include/hw/intc/andes_plic.h | 130 +++++++++
> 4 files changed, 639 insertions(+)
> create mode 100644 hw/intc/andes_plic.c
> create mode 100644 include/hw/intc/andes_plic.h
Is the Andes PLIC spec public available?
What's the difference between Andres's implementation and the SiFive's?
Regards,
Bin
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Dylan Jhong <dylan@andestech.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
ruinland@andestech.com, Alan Kao <alankao@andestech.com>
Subject: Re: [PATCH 1/3] Andes RISC-V PLIC
Date: Wed, 10 Mar 2021 14:05:51 +0800 [thread overview]
Message-ID: <CAEUhbmVgQzzS4DSOKM_zBxMMAb0bCZBJOZfQ7BUop84SaikZxg@mail.gmail.com> (raw)
In-Reply-To: <20210310033358.30499-2-dylan@andestech.com>
On Wed, Mar 10, 2021 at 11:34 AM Dylan Jhong <dylan@andestech.com> wrote:
>
> Andes PLIC (Platform-Level Interrupt Controller) device provides an
> interrupt controller functionality based on Andes's PLIC specification.
>
> The Andes PLIC can handle either external interrupts (PLIC)
> or interprocessor interrupts (PLICSW).
>
> While Andes PLIC spec includes vector interrupt and interrupt preemption,
> we leave them as future items for now.
>
> Signed-off-by: Dylan Jhong <dylan@andestech.com>
> Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
> ---
> hw/intc/Kconfig | 3 +
> hw/intc/andes_plic.c | 505 +++++++++++++++++++++++++++++++++++
> hw/intc/meson.build | 1 +
> include/hw/intc/andes_plic.h | 130 +++++++++
> 4 files changed, 639 insertions(+)
> create mode 100644 hw/intc/andes_plic.c
> create mode 100644 include/hw/intc/andes_plic.h
Is the Andes PLIC spec public available?
What's the difference between Andres's implementation and the SiFive's?
Regards,
Bin
next prev parent reply other threads:[~2021-03-10 6:07 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-10 3:33 [PATCH 0/3] Support Andes AE350 Platform Dylan Jhong
2021-03-10 3:33 ` Dylan Jhong
2021-03-10 3:33 ` [PATCH 1/3] Andes RISC-V PLIC Dylan Jhong
2021-03-10 3:33 ` Dylan Jhong
2021-03-10 6:05 ` Bin Meng [this message]
2021-03-10 6:05 ` Bin Meng
2021-03-11 6:52 ` Dylan Jhong
2021-03-11 6:52 ` Dylan Jhong
2021-03-10 7:50 ` Yixun Lan
2021-03-11 15:42 ` Alistair Francis
2021-03-11 15:42 ` Alistair Francis
2021-03-10 3:33 ` [PATCH 2/3] Andes RISC-V PLMT Dylan Jhong
2021-03-10 3:33 ` Dylan Jhong
2021-03-10 3:33 ` [PATCH 3/3] Andes AE350 RISC-V Machine Dylan Jhong
2021-03-10 3:33 ` Dylan Jhong
2021-03-10 6:15 ` Bin Meng
2021-03-10 6:15 ` Bin Meng
2021-03-11 6:50 ` Dylan Jhong
2021-03-11 6:50 ` Dylan Jhong
2021-03-11 15:46 ` Alistair Francis
2021-03-11 15:46 ` Alistair Francis
2021-03-12 1:07 ` Bin Meng
2021-03-12 1:07 ` Bin Meng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAEUhbmVgQzzS4DSOKM_zBxMMAb0bCZBJOZfQ7BUop84SaikZxg@mail.gmail.com \
--to=bmeng.cn@gmail.com \
--cc=Alistair.Francis@wdc.com \
--cc=alankao@andestech.com \
--cc=dylan@andestech.com \
--cc=kbastian@mail.uni-paderborn.de \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=ruinland@andestech.com \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.