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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@opensource.wdc.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	wilfred.mallawa@wdc.com,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair23@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
Date: Mon, 10 Jan 2022 15:34:01 +0800	[thread overview]
Message-ID: <CAEUhbmVjdMfF5G-xbjBCFWE13PGtVG9WveXfDSyAAO3Q0Fpukw@mail.gmail.com> (raw)
In-Reply-To: <20220110061321.4040589-1-alistair.francis@opensource.wdc.com>

On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following change was made to rectify incorrectly set stride length
> on the PLIC. Where it should be 32bit and not 24bit (0x18). This was

PLIC [1]

> discovered whilst attempting to fix a bug where a timer_interrupt was
> not serviced on TockOS-OpenTitan.
>

[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/

> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
>  hw/riscv/opentitan.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@opensource.wdc.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	 Alistair Francis <alistair23@gmail.com>,
	wilfred.mallawa@wdc.com
Subject: Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
Date: Mon, 10 Jan 2022 15:34:01 +0800	[thread overview]
Message-ID: <CAEUhbmVjdMfF5G-xbjBCFWE13PGtVG9WveXfDSyAAO3Q0Fpukw@mail.gmail.com> (raw)
In-Reply-To: <20220110061321.4040589-1-alistair.francis@opensource.wdc.com>

On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following change was made to rectify incorrectly set stride length
> on the PLIC. Where it should be 32bit and not 24bit (0x18). This was

PLIC [1]

> discovered whilst attempting to fix a bug where a timer_interrupt was
> not serviced on TockOS-OpenTitan.
>

[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/

> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
>  hw/riscv/opentitan.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


  parent reply	other threads:[~2022-01-10  8:03 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-10  6:13 [PATCH 1/2] riscv: opentitan: fixup plic stride len Alistair Francis
2022-01-10  6:13 ` [PATCH 2/2] hw: timer: ibex_timer: update/add reg address Alistair Francis
2022-01-10  6:16   ` Alistair Francis
2022-01-10  6:16     ` Alistair Francis
2022-01-10  7:40   ` Bin Meng
2022-01-10  7:40     ` Bin Meng
2022-01-10  6:15 ` [PATCH 1/2] riscv: opentitan: fixup plic stride len Alistair Francis
2022-01-10  6:15   ` Alistair Francis
2022-01-10  7:34 ` Bin Meng [this message]
2022-01-10  7:34   ` Bin Meng
2022-01-10 23:24   ` Wilfred Mallawa
2022-01-10 23:24     ` Wilfred Mallawa

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