From: Alistair Francis <alistair23@gmail.com> To: Alistair Francis <alistair.francis@opensource.wdc.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, wilfred.mallawa@wdc.com, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com> Subject: Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address Date: Mon, 10 Jan 2022 16:16:41 +1000 [thread overview] Message-ID: <CAKmqyKM3mEvEuj7p8f+rnv7rG6FmLAuxH6xxAKBX9gwsKTPjQQ@mail.gmail.com> (raw) In-Reply-To: <20220110061321.4040589-2-alistair.francis@opensource.wdc.com> On Mon, Jan 10, 2022 at 4:13 PM Alistair Francis <alistair.francis@opensource.wdc.com> wrote: > > From: Wilfred Mallawa <wilfred.mallawa@wdc.com> > > The following changes: > 1. Fixes the incorrectly set CTRL register address. As > per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table > > The CTRL register is @ 0x04. > > This was found when attempting to fixup a bug where a timer_interrupt > was not serviced on TockOS-OpenTitan. > > 2. Adds ALERT_TEST register as documented on [1], adding repective > switch cases to error handle and later implement functionality. > > Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/timer/ibex_timer.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c > index 66e1f8e48c..096588ac8a 100644 > --- a/hw/timer/ibex_timer.c > +++ b/hw/timer/ibex_timer.c > @@ -34,7 +34,9 @@ > #include "target/riscv/cpu.h" > #include "migration/vmstate.h" > > -REG32(CTRL, 0x00) > +REG32(ALERT_TEST, 0x00) > + FIELD(ALERT_TEST, FATAL_FAULT, 0, 1) > +REG32(CTRL, 0x04) > FIELD(CTRL, ACTIVE, 0, 1) > REG32(CFG0, 0x100) > FIELD(CFG0, PRESCALE, 0, 12) > @@ -143,6 +145,10 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr, > uint64_t retvalue = 0; > > switch (addr >> 2) { > + case R_ALERT_TEST: > + qemu_log_mask(LOG_GUEST_ERROR, > + "Attempted to read ALERT_TEST, a write only register"); > + break; > case R_CTRL: > retvalue = s->timer_ctrl; > break; > @@ -186,6 +192,9 @@ static void ibex_timer_write(void *opaque, hwaddr addr, > uint32_t val = val64; > > switch (addr >> 2) { > + case R_ALERT_TEST: > + qemu_log_mask(LOG_UNIMP, "Alert triggering not supported"); > + break; > case R_CTRL: > s->timer_ctrl = val; > break; > -- > 2.34.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Alistair Francis <alistair.francis@opensource.wdc.com> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Bin Meng <bmeng.cn@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, wilfred.mallawa@wdc.com Subject: Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address Date: Mon, 10 Jan 2022 16:16:41 +1000 [thread overview] Message-ID: <CAKmqyKM3mEvEuj7p8f+rnv7rG6FmLAuxH6xxAKBX9gwsKTPjQQ@mail.gmail.com> (raw) In-Reply-To: <20220110061321.4040589-2-alistair.francis@opensource.wdc.com> On Mon, Jan 10, 2022 at 4:13 PM Alistair Francis <alistair.francis@opensource.wdc.com> wrote: > > From: Wilfred Mallawa <wilfred.mallawa@wdc.com> > > The following changes: > 1. Fixes the incorrectly set CTRL register address. As > per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table > > The CTRL register is @ 0x04. > > This was found when attempting to fixup a bug where a timer_interrupt > was not serviced on TockOS-OpenTitan. > > 2. Adds ALERT_TEST register as documented on [1], adding repective > switch cases to error handle and later implement functionality. > > Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/timer/ibex_timer.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c > index 66e1f8e48c..096588ac8a 100644 > --- a/hw/timer/ibex_timer.c > +++ b/hw/timer/ibex_timer.c > @@ -34,7 +34,9 @@ > #include "target/riscv/cpu.h" > #include "migration/vmstate.h" > > -REG32(CTRL, 0x00) > +REG32(ALERT_TEST, 0x00) > + FIELD(ALERT_TEST, FATAL_FAULT, 0, 1) > +REG32(CTRL, 0x04) > FIELD(CTRL, ACTIVE, 0, 1) > REG32(CFG0, 0x100) > FIELD(CFG0, PRESCALE, 0, 12) > @@ -143,6 +145,10 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr, > uint64_t retvalue = 0; > > switch (addr >> 2) { > + case R_ALERT_TEST: > + qemu_log_mask(LOG_GUEST_ERROR, > + "Attempted to read ALERT_TEST, a write only register"); > + break; > case R_CTRL: > retvalue = s->timer_ctrl; > break; > @@ -186,6 +192,9 @@ static void ibex_timer_write(void *opaque, hwaddr addr, > uint32_t val = val64; > > switch (addr >> 2) { > + case R_ALERT_TEST: > + qemu_log_mask(LOG_UNIMP, "Alert triggering not supported"); > + break; > case R_CTRL: > s->timer_ctrl = val; > break; > -- > 2.34.1 >
next prev parent reply other threads:[~2022-01-10 6:24 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-10 6:13 [PATCH 1/2] riscv: opentitan: fixup plic stride len Alistair Francis 2022-01-10 6:13 ` [PATCH 2/2] hw: timer: ibex_timer: update/add reg address Alistair Francis 2022-01-10 6:16 ` Alistair Francis [this message] 2022-01-10 6:16 ` Alistair Francis 2022-01-10 7:40 ` Bin Meng 2022-01-10 7:40 ` Bin Meng 2022-01-10 6:15 ` [PATCH 1/2] riscv: opentitan: fixup plic stride len Alistair Francis 2022-01-10 6:15 ` Alistair Francis 2022-01-10 7:34 ` Bin Meng 2022-01-10 7:34 ` Bin Meng 2022-01-10 23:24 ` Wilfred Mallawa 2022-01-10 23:24 ` Wilfred Mallawa
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