All of lore.kernel.org
 help / color / mirror / Atom feed
From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH 7/7] riscv: Add some comments to start.S
Date: Mon, 14 Sep 2020 13:26:42 +0800	[thread overview]
Message-ID: <CAEUhbmVwCcbfjGyzOyEBaKo8x5aNXjicNr57fX=hABjQD+2oVQ@mail.gmail.com> (raw)
In-Reply-To: <20200907181659.92449-8-seanga2@gmail.com>

On Tue, Sep 8, 2020 at 2:17 AM Sean Anderson <seanga2@gmail.com> wrote:
>
> This adds comments regarding the ordering and purpose of certain
> instructions as I understand them.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
>  arch/riscv/cpu/start.S | 19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 59d3d7bbf4..c659c6df53 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -43,7 +43,10 @@ _start:
>         csrr    a0, CSR_MHARTID
>  #endif
>
> -       /* save hart id and dtb pointer */
> +       /*
> +        * Save hart id and dtb pointer. The thread pointer register is not

U-Boot does not use tp register in C code.

> +        * modified by C code, and may be used in trap handlers.
> +        */
>         mv      tp, a0
>         mv      s1, a1
>
> @@ -54,10 +57,18 @@ _start:
>          */
>         mv      gp, zero
>
> +       /*
> +        * Set the trap handler. This must happen after initializing tp and gp
> +        * because the handler may use these registers.
> +        */
>         la      t0, trap_entry
>         csrw    MODE_PREFIX(tvec), t0
>
> -       /* mask all interrupts */
> +       /*
> +        * Mask all interrupts. Interrupts are disabled globally (in m/sstatus)
> +        * for U-Boot, but we will need to read m/sip to determine if we get an
> +        * IPI
> +        */
>         csrw    MODE_PREFIX(ie), zero
>
>  #if CONFIG_IS_ENABLED(SMP)
> @@ -407,6 +418,10 @@ secondary_hart_relocate:
>         mv      gp, a2
>  #endif
>
> +/*
> + * Interrupts are disabled globally, but they can still be read from m/sip. The
> + * wfi function will wake us up if we get an IPI, even if we do not trap.
> + */
>  secondary_hart_loop:
>         wfi

Regards,
Bin

  reply	other threads:[~2020-09-14  5:26 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-07 18:16 [PATCH 0/7] riscv: Correctly handle IPIs already pending upon boot Sean Anderson
2020-09-07 18:16 ` [PATCH 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs" Sean Anderson
2020-09-09  7:50   ` Rick Chen
2020-09-09 10:23     ` Sean Anderson
2020-09-10  6:39       ` Rick Chen
2020-09-10 10:18         ` Sean Anderson
2020-09-11  7:38   ` Bin Meng
2020-09-11 10:22     ` Sean Anderson
2020-09-11 14:45       ` Bin Meng
2020-09-11 18:30         ` Sean Anderson
2020-09-14  3:10           ` Rick Chen
2020-09-14 12:45             ` Sean Anderson
2020-09-07 18:16 ` [PATCH 2/7] riscv: Match memory barriers between send_ipi_many and handle_ipi Sean Anderson
2020-09-11  7:45   ` Bin Meng
2020-09-07 18:16 ` [PATCH 3/7] riscv: Use NULL as a sentinel value for smp_call_function Sean Anderson
2020-09-09  8:33   ` Rick Chen
2020-09-09  9:01     ` Rick Chen
2020-09-09 10:16       ` Sean Anderson
2020-09-09 10:26         ` Heinrich Schuchardt
2020-09-09 10:36           ` Sean Anderson
2020-09-10  8:09         ` Rick Chen
2020-09-14  3:21         ` Rick Chen
2020-09-11  8:04   ` Bin Meng
2020-09-14  1:58     ` Leo Liang
2020-09-14  2:07       ` Bin Meng
2020-09-14  6:10         ` Leo Liang
2020-09-14  6:15           ` Bin Meng
2020-09-14 14:05     ` Sean Anderson
2020-09-07 18:16 ` [PATCH 4/7] riscv: Clear pending IPIs on initialization Sean Anderson
2020-09-14  2:08   ` Bin Meng
2020-09-07 18:16 ` [PATCH 5/7] riscv: Add fence to available_harts_lock Sean Anderson
2020-09-10  3:26   ` Rick Chen
2020-09-11 10:39     ` Sean Anderson
2020-09-11 14:47   ` Bin Meng
2020-09-07 18:16 ` [PATCH 6/7] riscv: Ensure gp is NULL or points to valid data Sean Anderson
2020-09-14  5:25   ` Bin Meng
2020-09-14 13:03     ` Sean Anderson
2020-09-14 13:27       ` Sean Anderson
2020-09-07 18:16 ` [PATCH 7/7] riscv: Add some comments to start.S Sean Anderson
2020-09-14  5:26   ` Bin Meng [this message]
2020-09-09  2:02 ` [PATCH 0/7] riscv: Correctly handle IPIs already pending upon boot Rick Chen
2020-09-09  2:38   ` Sean Anderson
2020-09-09  2:44     ` Sean Anderson
2020-09-10  7:08     ` Rick Chen
2020-09-10 10:49       ` Sean Anderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAEUhbmVwCcbfjGyzOyEBaKo8x5aNXjicNr57fX=hABjQD+2oVQ@mail.gmail.com' \
    --to=bmeng.cn@gmail.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.