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From: Rick Chen <rickchen36@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs"
Date: Mon, 14 Sep 2020 11:10:45 +0800	[thread overview]
Message-ID: <CAN5B=eLQMDXmq3BRQNM9pFwDL0C6g1HmDc2tf4XzAcPBDpZjQg@mail.gmail.com> (raw)
In-Reply-To: <ffc35d01-83c3-aeea-4501-af7fe62d90c2@gmail.com>

HI Sean

> On 9/11/20 10:45 AM, Bin Meng wrote:
> > On Fri, Sep 11, 2020 at 6:22 PM Sean Anderson <seanga2@gmail.com> wrote:
> >>
> >> On 9/11/20 3:38 AM, Bin Meng wrote:
> >>> Hi Sean,
> >>>
> >>> On Tue, Sep 8, 2020 at 2:17 AM Sean Anderson <seanga2@gmail.com> wrote:
> >>>>
> >>>> Clearing MIP doesn't do anything. Whoops. The following commits should
> >>>
> >>> Which following commits?
> >>>
> >>>> tackle this problem in a more robust manner.
> >>>>
> >>>> This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6.
> >>>>
> >>>> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> >>>> ---
> >>>>
> >>>>  arch/riscv/cpu/start.S | 2 --
> >>>>  1 file changed, 2 deletions(-)
> >>>>
> >>>> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> >>>> index bf9fdf369b..e3222b1ea7 100644
> >>>> --- a/arch/riscv/cpu/start.S
> >>>> +++ b/arch/riscv/cpu/start.S
> >>>> @@ -65,8 +65,6 @@ _start:
> >>>>  #else
> >>>>         li      t0, SIE_SSIE
> >>>>  #endif
> >>>> -       /* Clear any pending IPIs */
> >>>> -       csrc    MODE_PREFIX(ip), t0
> >>>
> >>> Did you mean the clearing MIP.MSIP actually does nothing, but the
> >>> following commit is the correct fix?
> >>
> >> Yes, but we also need
> >
> > Is MIP.MSIP read-only on K210?

Since clear mip will not affect anything in K210 and it is writable
for other RISC-V platforms.
I will prefer to keep this instruction stay here for standard startup
initialization.

Thanks,
Rick

>
> I think so. See [1] where only ssip, stip, and seip are written (and
> new_mip is not otherwise used). The spec doesn't require MIP.MSIP to be
> writable at all.
>
> --Sean
>
> [1] https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/CSR.scala#L859

  reply	other threads:[~2020-09-14  3:10 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-07 18:16 [PATCH 0/7] riscv: Correctly handle IPIs already pending upon boot Sean Anderson
2020-09-07 18:16 ` [PATCH 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs" Sean Anderson
2020-09-09  7:50   ` Rick Chen
2020-09-09 10:23     ` Sean Anderson
2020-09-10  6:39       ` Rick Chen
2020-09-10 10:18         ` Sean Anderson
2020-09-11  7:38   ` Bin Meng
2020-09-11 10:22     ` Sean Anderson
2020-09-11 14:45       ` Bin Meng
2020-09-11 18:30         ` Sean Anderson
2020-09-14  3:10           ` Rick Chen [this message]
2020-09-14 12:45             ` Sean Anderson
2020-09-07 18:16 ` [PATCH 2/7] riscv: Match memory barriers between send_ipi_many and handle_ipi Sean Anderson
2020-09-11  7:45   ` Bin Meng
2020-09-07 18:16 ` [PATCH 3/7] riscv: Use NULL as a sentinel value for smp_call_function Sean Anderson
2020-09-09  8:33   ` Rick Chen
2020-09-09  9:01     ` Rick Chen
2020-09-09 10:16       ` Sean Anderson
2020-09-09 10:26         ` Heinrich Schuchardt
2020-09-09 10:36           ` Sean Anderson
2020-09-10  8:09         ` Rick Chen
2020-09-14  3:21         ` Rick Chen
2020-09-11  8:04   ` Bin Meng
2020-09-14  1:58     ` Leo Liang
2020-09-14  2:07       ` Bin Meng
2020-09-14  6:10         ` Leo Liang
2020-09-14  6:15           ` Bin Meng
2020-09-14 14:05     ` Sean Anderson
2020-09-07 18:16 ` [PATCH 4/7] riscv: Clear pending IPIs on initialization Sean Anderson
2020-09-14  2:08   ` Bin Meng
2020-09-07 18:16 ` [PATCH 5/7] riscv: Add fence to available_harts_lock Sean Anderson
2020-09-10  3:26   ` Rick Chen
2020-09-11 10:39     ` Sean Anderson
2020-09-11 14:47   ` Bin Meng
2020-09-07 18:16 ` [PATCH 6/7] riscv: Ensure gp is NULL or points to valid data Sean Anderson
2020-09-14  5:25   ` Bin Meng
2020-09-14 13:03     ` Sean Anderson
2020-09-14 13:27       ` Sean Anderson
2020-09-07 18:16 ` [PATCH 7/7] riscv: Add some comments to start.S Sean Anderson
2020-09-14  5:26   ` Bin Meng
2020-09-09  2:02 ` [PATCH 0/7] riscv: Correctly handle IPIs already pending upon boot Rick Chen
2020-09-09  2:38   ` Sean Anderson
2020-09-09  2:44     ` Sean Anderson
2020-09-10  7:08     ` Rick Chen
2020-09-10 10:49       ` Sean Anderson

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