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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
Date: Tue, 21 Apr 2020 10:17:23 +0800	[thread overview]
Message-ID: <CAEUhbmW0u9-qOR_WyobeodLJ0jqEChSQNfrJ-ckT+up_fzgCMw@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKNegLq5NG+qr_ayZc-_ks5cddZ1mGGWSPCEQ8tgSkOXTg@mail.gmail.com>

On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Palmer,
> > >
> > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> > > <alistair.francis@wdc.com> wrote:
> > > >
> > > > At present the board serial number is hard-coded to 1, and passed
> > > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > > > the serial number to generate a unique MAC address for the on-chip
> > > > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > > > created and connected to the same subnet, they all have the same
> > > > MAC address hence it creates a unusable network.
> > > >
> > > > A new "serial" property is introduced to specify the board serial
> > > > number. When not given, the default serial number 1 is used.
> > > >
> > >
> > > Could you please take this for v5.0.0?
>
> Applied to the RISC-V tree for 5.1
>

Sigh, this patch was submitted on Mar 7 and that is before soft freeze ...

Any chance to get this in 5.0?

Regards,
Bin


WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
Date: Tue, 21 Apr 2020 10:17:23 +0800	[thread overview]
Message-ID: <CAEUhbmW0u9-qOR_WyobeodLJ0jqEChSQNfrJ-ckT+up_fzgCMw@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKNegLq5NG+qr_ayZc-_ks5cddZ1mGGWSPCEQ8tgSkOXTg@mail.gmail.com>

On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Palmer,
> > >
> > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> > > <alistair.francis@wdc.com> wrote:
> > > >
> > > > At present the board serial number is hard-coded to 1, and passed
> > > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > > > the serial number to generate a unique MAC address for the on-chip
> > > > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > > > created and connected to the same subnet, they all have the same
> > > > MAC address hence it creates a unusable network.
> > > >
> > > > A new "serial" property is introduced to specify the board serial
> > > > number. When not given, the default serial number 1 is used.
> > > >
> > >
> > > Could you please take this for v5.0.0?
>
> Applied to the RISC-V tree for 5.1
>

Sigh, this patch was submitted on Mar 7 and that is before soft freeze ...

Any chance to get this in 5.0?

Regards,
Bin


  reply	other threads:[~2020-04-21  2:20 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-06 21:36 [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u Alistair Francis
2020-03-06 21:36 ` Alistair Francis
2020-03-06 21:36 ` [PATCH v3 1/3] riscv/sifive_u: Fix up file ordering Alistair Francis
2020-03-06 21:36   ` Alistair Francis
2020-03-07  1:14   ` Bin Meng
2020-03-07  1:14     ` Bin Meng
2020-03-06 21:36 ` [PATCH v3 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC Alistair Francis
2020-03-06 21:36   ` Alistair Francis
2020-03-06 21:36 ` [PATCH v3 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine Alistair Francis
2020-03-06 21:36   ` Alistair Francis
2020-03-24  2:08 ` [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u Bin Meng
2020-03-24  2:08   ` Bin Meng
2020-04-02  5:39   ` Bin Meng
2020-04-02  5:39     ` Bin Meng
2020-04-20 19:17     ` Alistair Francis
2020-04-20 19:17       ` Alistair Francis
2020-04-21  2:17       ` Bin Meng [this message]
2020-04-21  2:17         ` Bin Meng
2020-04-21 17:40         ` Alistair Francis
2020-04-21 17:40           ` Alistair Francis
2020-04-21 17:54           ` Palmer Dabbelt
2020-04-21 17:54             ` Palmer Dabbelt
2020-04-03 16:01   ` Palmer Dabbelt
2020-04-03 16:01     ` Palmer Dabbelt

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