From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u Date: Fri, 6 Mar 2020 13:36:45 -0800 [thread overview] Message-ID: <cover.1583530528.git.alistair.francis@wdc.com> (raw) At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to specify the board serial number. When not given, the default serial number 1 is used. v3: - Improve machine function names v2: - Fix the serial setting so it correctly sets Alistair Francis (2): riscv/sifive_u: Fix up file ordering riscv/sifive_u: Add a serial property to the sifive_u SoC Bin Meng (1): riscv/sifive_u: Add a serial property to the sifive_u machine hw/riscv/sifive_u.c | 137 +++++++++++++++++++++--------------- include/hw/riscv/sifive_u.h | 3 + 2 files changed, 85 insertions(+), 55 deletions(-) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u Date: Fri, 6 Mar 2020 13:36:45 -0800 [thread overview] Message-ID: <cover.1583530528.git.alistair.francis@wdc.com> (raw) At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to specify the board serial number. When not given, the default serial number 1 is used. v3: - Improve machine function names v2: - Fix the serial setting so it correctly sets Alistair Francis (2): riscv/sifive_u: Fix up file ordering riscv/sifive_u: Add a serial property to the sifive_u SoC Bin Meng (1): riscv/sifive_u: Add a serial property to the sifive_u machine hw/riscv/sifive_u.c | 137 +++++++++++++++++++++--------------- include/hw/riscv/sifive_u.h | 3 + 2 files changed, 85 insertions(+), 55 deletions(-) -- 2.25.1
next reply other threads:[~2020-03-06 21:45 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-06 21:36 Alistair Francis [this message] 2020-03-06 21:36 ` [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u Alistair Francis 2020-03-06 21:36 ` [PATCH v3 1/3] riscv/sifive_u: Fix up file ordering Alistair Francis 2020-03-06 21:36 ` Alistair Francis 2020-03-07 1:14 ` Bin Meng 2020-03-07 1:14 ` Bin Meng 2020-03-06 21:36 ` [PATCH v3 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC Alistair Francis 2020-03-06 21:36 ` Alistair Francis 2020-03-06 21:36 ` [PATCH v3 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine Alistair Francis 2020-03-06 21:36 ` Alistair Francis 2020-03-24 2:08 ` [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u Bin Meng 2020-03-24 2:08 ` Bin Meng 2020-04-02 5:39 ` Bin Meng 2020-04-02 5:39 ` Bin Meng 2020-04-20 19:17 ` Alistair Francis 2020-04-20 19:17 ` Alistair Francis 2020-04-21 2:17 ` Bin Meng 2020-04-21 2:17 ` Bin Meng 2020-04-21 17:40 ` Alistair Francis 2020-04-21 17:40 ` Alistair Francis 2020-04-21 17:54 ` Palmer Dabbelt 2020-04-21 17:54 ` Palmer Dabbelt 2020-04-03 16:01 ` Palmer Dabbelt 2020-04-03 16:01 ` Palmer Dabbelt
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