[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[Andes]

From: Rick Chen <rick@andestech.com>

Changes in v3:
Patch 1
- Rename plic_init() as enable_ipi()
- Remove PLIC_BASE_GET() from enable_ipi()
Patch 2
- Add a space before (PLMT)
Patch 6
- Fix some mis-alignments
- Recovery isa string of CPU1

Changes in v2:
- Drop patch1 and replace by simple-bus driver
- Rename nds_plic as andes_plic
- Move initialize plic to PLIC_BASE_GET() and called automatically
- Rename nds_plmt as andes_plmt
- Recovery dts isa string

Rick Chen (7):
  riscv: Add a SYSCON driver for Andestech's PLIC
  riscv: Add a SYSCON driver for Andestech's PLMT
  riscv: ae350: disable ATCPIT100 timer
  riscv: ax25: Add platform-specific Kconfig options
  riscv: ax25: Andes specific cache shall only support in M-mode
  riscv: dts: ae350 support SMP
  riscv: ae350: enable SMP

 arch/riscv/Kconfig                   |  18 ++++++
 arch/riscv/cpu/ax25/Kconfig          |   7 +++
 arch/riscv/dts/ae350_32.dts          |  81 +++++++++++++++++++-------
 arch/riscv/dts/ae350_64.dts          |  81 +++++++++++++++++++-------
 arch/riscv/include/asm/global_data.h |   6 ++
 arch/riscv/include/asm/syscon.h      |   3 +-
 arch/riscv/lib/Makefile              |   2 +
 arch/riscv/lib/andes_plic.c          | 110 +++++++++++++++++++++++++++++++++++
 arch/riscv/lib/andes_plmt.c          |  53 +++++++++++++++++
 board/AndesTech/ax25-ae350/Kconfig   |   1 +
 configs/ae350_rv32_defconfig         |   1 -
 configs/ae350_rv64_defconfig         |   1 -
 12 files changed, 317 insertions(+), 47 deletions(-)
 create mode 100644 arch/riscv/lib/andes_plic.c
 create mode 100644 arch/riscv/lib/andes_plmt.c

-- 
2.7.4

[U-Boot] [PATCH v3 1/7] riscv: Add a SYSCON driver for Andestech's PLIC

[Andes]

From: Rick Chen <rick@andestech.com>

The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
V3:
 - Rename plic_init() as enable_ipi().
 - Declase as static.
 - Remove PLIC_BASE_GET() from enable_ipi().

 arch/riscv/Kconfig                   |   9 +++
 arch/riscv/include/asm/global_data.h |   3 +
 arch/riscv/include/asm/syscon.h      |   2 +-
 arch/riscv/lib/Makefile              |   1 +
 arch/riscv/lib/andes_plic.c          | 110 +++++++++++++++++++++++++++++++++++
 5 files changed, 124 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/lib/andes_plic.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3a4470d..511768b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -109,6 +109,15 @@ config SIFIVE_CLINT
 	  The SiFive CLINT block holds memory-mapped control and status registers
 	  associated with software and timer interrupts.
 
+config ANDES_PLIC
+	bool
+	depends on RISCV_MMODE
+	select REGMAP
+	select SYSCON
+	help
+	  The Andes PLIC block holds memory-mapped claim and pending registers
+	  associated with software interrupt.
+
 config RISCV_RDTIME
 	bool
 	default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 80e3165..b867910 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,6 +18,9 @@ struct arch_global_data {
 #ifdef CONFIG_SIFIVE_CLINT
 	void __iomem *clint;	/* clint base address */
 #endif
+#ifdef CONFIG_ANDES_PLIC
+	void __iomem *plic;	/* plic base address */
+#endif
 #ifdef CONFIG_SMP
 	struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index d311ee6..c1b4b86 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -9,11 +9,11 @@
 /*
  * System controllers in a RISC-V system
  *
- * So far only SiFive's Core Local Interruptor (CLINT) is defined.
  */
 enum {
 	RISCV_NONE,
 	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
+	RISCV_SYSCON_PLIC,	/* Platform Level Interrupt Controller (PLIC) */
 };
 
 #endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 35dbf64..1bf554b 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
 obj-y	+= cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
 obj-y	+= interrupts.o
 obj-y	+= reset.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
new file mode 100644
index 0000000..67ab561
--- /dev/null
+++ b/arch/riscv/lib/andes_plic.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen <rick@andestech.com>
+ *
+ * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
+ * The PLIC block holds memory-mapped claim and pending registers
+ * associated with software interrupt.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+#include <cpu.h>
+
+/* pending register */
+#define PENDING_REG(base, hart)	((ulong)(base) + 0x1000 + (hart) * 8)
+/* enable register */
+#define ENABLE_REG(base, hart)	((ulong)(base) + 0x2000 + (hart) * 0x80)
+/* claim register */
+#define CLAIM_REG(base, hart)	((ulong)(base) + 0x200004 + (hart) * 0x1000)
+
+#define ENABLE_HART_IPI         (0x80808080)
+#define SEND_IPI_TO_HART(hart)  (0x80>>hart)
+
+DECLARE_GLOBAL_DATA_PTR;
+static int init_plic(void);
+
+#define PLIC_BASE_GET(void)						\
+	do {								\
+		long *ret;						\
+									\
+		if (!gd->arch.plic) {					\
+			ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
+			if (IS_ERR(ret))				\
+				return PTR_ERR(ret);			\
+			gd->arch.plic = ret;				\
+			init_plic();					\
+		}							\
+	} while (0)
+
+static int enable_ipi(int harts)
+{
+	int i;
+	int en = ENABLE_HART_IPI;
+
+	for (i = 0; i < harts ;i++)
+	{
+		en = en >> i;
+		writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
+	}
+
+	return 0;
+}
+
+static int init_plic(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_find_first_device(UCLASS_CPU, &dev);
+	if (ret)
+		return ret;
+
+	if (ret == 0 && dev != NULL) {
+		ret = cpu_get_count(dev);
+		enable_ipi(ret);
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
+int riscv_send_ipi(int hart)
+{
+	PLIC_BASE_GET();
+
+	writel(SEND_IPI_TO_HART(hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
+
+	return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+	u32 source_id;
+
+	PLIC_BASE_GET();
+
+	source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+	writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+
+	return 0;
+}
+
+static const struct udevice_id andes_plic_ids[] = {
+	{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
+	{ }
+};
+
+U_BOOT_DRIVER(nds_plic) = {
+	.name		= "andes_plic",
+	.id		= UCLASS_SYSCON,
+	.of_match	= andes_plic_ids,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
-- 
2.7.4

[U-Boot] [PATCH v3 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

[Andes]

From: Rick Chen <rick@andestech.com>

The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
V3:
 - Add a space before (PLMT).

 arch/riscv/Kconfig                   |  9 ++++++
 arch/riscv/include/asm/global_data.h |  3 ++
 arch/riscv/include/asm/syscon.h      |  1 +
 arch/riscv/lib/Makefile              |  1 +
 arch/riscv/lib/andes_plmt.c          | 53 ++++++++++++++++++++++++++++++++++++
 5 files changed, 67 insertions(+)
 create mode 100644 arch/riscv/lib/andes_plmt.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 511768b..ae8ff7b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -118,6 +118,15 @@ config ANDES_PLIC
 	  The Andes PLIC block holds memory-mapped claim and pending registers
 	  associated with software interrupt.
 
+config ANDES_PLMT
+	bool
+	depends on RISCV_MMODE
+	select REGMAP
+	select SYSCON
+	help
+	  The Andes PLMT block holds memory-mapped mtime register
+	  associated with timer tick.
+
 config RISCV_RDTIME
 	bool
 	default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index b867910..dffcd45 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,6 +21,9 @@ struct arch_global_data {
 #ifdef CONFIG_ANDES_PLIC
 	void __iomem *plic;	/* plic base address */
 #endif
+#ifdef CONFIG_ANDES_PLMT
+	void __iomem *plmt;	/* plmt base address */
+#endif
 #ifdef CONFIG_SMP
 	struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index c1b4b86..6e12574 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -14,6 +14,7 @@ enum {
 	RISCV_NONE,
 	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
 	RISCV_SYSCON_PLIC,	/* Platform Level Interrupt Controller (PLIC) */
+	RISCV_SYSCON_PLMT,	/* Platform Level Machine Timer (PLMT) */
 };
 
 #endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 1bf554b..1c332db 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -12,6 +12,7 @@ obj-y	+= cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 obj-y	+= interrupts.o
 obj-y	+= reset.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
new file mode 100644
index 0000000..12d7e0e
--- /dev/null
+++ b/arch/riscv/lib/andes_plmt.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen <rick@andestech.com>
+ *
+ * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
+ * The PLMT block holds memory-mapped mtime register
+ * associated with timer tick.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+
+/* mtime register */
+#define MTIME_REG(base)			((ulong)(base))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLMT_BASE_GET(void)						\
+	do {								\
+		long *ret;						\
+									\
+		if (!gd->arch.plmt) {					\
+			ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
+			if (IS_ERR(ret))				\
+				return PTR_ERR(ret);			\
+			gd->arch.plmt = ret;				\
+		}							\
+	} while (0)
+
+int riscv_get_time(u64 *time)
+{
+	PLMT_BASE_GET();
+
+	*time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+
+	return 0;
+}
+
+static const struct udevice_id nds_plmt_ids[] = {
+	{ .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
+	{ }
+};
+
+U_BOOT_DRIVER(nds_plmt) = {
+	.name		= "nds_plmt",
+	.id		= UCLASS_SYSCON,
+	.of_match	= nds_plmt_ids,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
-- 
2.7.4

[U-Boot] [PATCH v3 3/7] riscv: ae350: disable ATCPIT100 timer

[Andes]

From: Rick Chen <rick@andestech.com>

Disable ATCPIT100 SoC timer and replace by PLMT.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 configs/ae350_rv32_defconfig | 1 -
 configs/ae350_rv64_defconfig | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index 5837b48..e13c7de 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -33,4 +33,3 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
-CONFIG_ATCPIT100_TIMER=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index b250d3f..a41f918 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -34,4 +34,3 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
-CONFIG_ATCPIT100_TIMER=y
-- 
2.7.4

[U-Boot] [PATCH v3 4/7] riscv: ax25: Add platform-specific Kconfig options

[Andes]

From: Rick Chen <rick@andestech.com>

Add ax25 RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/riscv/cpu/ax25/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index e9dbca2..68bd4e9 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,5 +1,11 @@
 config RISCV_NDS
 	bool
+	select ARCH_EARLY_INIT_R
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER
+	imply ANDES_PLIC if RISCV_MMODE
+	imply ANDES_PLMT if RISCV_MMODE
 	help
 	  Run U-Boot on AndeStar V5 platforms and use some specific features
 	  which are provided by Andes Technology AndeStar V5 families.
-- 
2.7.4

[U-Boot] [PATCH v3 5/7] riscv: ax25: Andes specific cache shall only support in M-mode

[Andes]

From: Rick Chen <rick@andestech.com>

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/riscv/cpu/ax25/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 68bd4e9..6b4b92e 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -14,6 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
 	bool "AndeStar V5 families specific cache support"
+	depends on RISCV_MMODE
 	help
 	  Provide Andes Technology AndeStar V5 families specific cache support.
 
-- 
2.7.4

[U-Boot] [PATCH v3 6/7] riscv: dts: ae350 support SMP

[Andes]

From: Rick Chen <rick@andestech.com>

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
V3:
 - Fix some mis-alignments.
 - Recovery isa string of CPU1.

 arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
 arch/riscv/dts/ae350_64.dts | 81 +++++++++++++++++++++++++++++++++------------
 2 files changed, 118 insertions(+), 44 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0679827..2ec01a5 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -26,16 +26,49 @@
 			status = "okay";
 			compatible = "riscv";
 			riscv,isa = "rv32imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
 			mmu-type = "riscv,sv32";
 			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
 			CPU0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				interrupt-controller;
 				compatible = "riscv,cpu-intc";
 			};
 		};
+		CPU1: cpu at 1 {
+			device_type = "cpu";
+			reg = <1>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv32";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+		L2: l2-cache at e0500000 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <0x40000>;
+			reg = <0x0 0xe0500000 0x0 0x40000>;
+		};
 	};
 
 	memory at 0 {
@@ -46,32 +79,32 @@
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "andestech,riscv-ae350-soc";
+		compatible = "simple-bus";
 		ranges;
 
-	plic0: interrupt-controller at e4000000 {
-		compatible = "riscv,plic0";
-		#address-cells = <1>;
-		#interrupt-cells = <1>;
-		interrupt-controller;
-		reg = <0xe4000000 0x2000000>;
-		riscv,ndev=<71>;
-		interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
-	};
+		plic0: interrupt-controller at e4000000 {
+			compatible = "riscv,plic0";
+			#address-cells = <1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xe4000000 0x2000000>;
+			riscv,ndev=<71>;
+			interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
+		};
 
-	plic1: interrupt-controller at e6400000 {
-		compatible = "riscv,plic1";
-		#address-cells = <1>;
-		#interrupt-cells = <1>;
-		interrupt-controller;
-		reg = <0xe6400000 0x400000>;
-		riscv,ndev=<1>;
-		interrupts-extended = <&CPU0_intc 3>;
-	};
+		plic1: interrupt-controller at e6400000 {
+			compatible = "riscv,plic1";
+			#address-cells = <1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xe6400000 0x400000>;
+			riscv,ndev=<2>;
+			interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
+		};
 
-	plmt0 at e6000000 {
-		compatible = "riscv,plmt0";
-			interrupts-extended = <&CPU0_intc 7>;
+		plmt0 at e6000000 {
+			compatible = "riscv,plmt0";
+			interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
 			reg = <0xe6000000 0x100000>;
 		};
 	};
@@ -146,6 +179,10 @@
 		interrupt-parent = <&plic0>;
 	};
 
+	pmu {
+		compatible = "riscv,base-pmu";
+	};
+
 	virtio_mmio at fe007000 {
 		interrupts = <0x17 0x4>;
 		interrupt-parent = <0x2>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index e48c298..cde5cde 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -26,16 +26,49 @@
 			status = "okay";
 			compatible = "riscv";
 			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
 			mmu-type = "riscv,sv39";
 			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
 			CPU0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				interrupt-controller;
 				compatible = "riscv,cpu-intc";
 			};
 		};
+		CPU1: cpu at 1 {
+			device_type = "cpu";
+			reg = <1>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+		L2: l2-cache at e0500000 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <0x40000>;
+			reg = <0x0 0xe0500000 0x0 0x40000>;
+		};
 	};
 
 	memory at 0 {
@@ -46,32 +79,32 @@
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
-		compatible = "andestech,riscv-ae350-soc";
+		compatible = "simple-bus";
 		ranges;
 
-	plic0: interrupt-controller at e4000000 {
-		compatible = "riscv,plic0";
-		#address-cells = <2>;
-		#interrupt-cells = <2>;
-		interrupt-controller;
-		reg = <0x0 0xe4000000 0x0 0x2000000>;
-		riscv,ndev=<71>;
-		interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
-	};
+		plic0: interrupt-controller at e4000000 {
+			compatible = "riscv,plic0";
+			#address-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0x0 0xe4000000 0x0 0x2000000>;
+			riscv,ndev=<71>;
+			interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
+		};
 
-	plic1: interrupt-controller at e6400000 {
-		compatible = "riscv,plic1";
-		#address-cells = <2>;
-		#interrupt-cells = <2>;
-		interrupt-controller;
-		reg = <0x0 0xe6400000 0x0 0x400000>;
-		riscv,ndev=<1>;
-		interrupts-extended = <&CPU0_intc 3>;
-	};
+		plic1: interrupt-controller at e6400000 {
+			compatible = "riscv,plic1";
+			#address-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0x0 0xe6400000 0x0 0x400000>;
+			riscv,ndev=<2>;
+			interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
+		};
 
-	plmt0 at e6000000 {
-		compatible = "riscv,plmt0";
-			interrupts-extended = <&CPU0_intc 7>;
+		plmt0 at e6000000 {
+			compatible = "riscv,plmt0";
+			interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
 			reg = <0x0 0xe6000000 0x0 0x100000>;
 		};
 	};
@@ -146,6 +179,10 @@
 		interrupt-parent = <&plic0>;
 	};
 
+	pmu {
+		compatible = "riscv,base-pmu";
+	};
+
 	virtio_mmio at fe007000 {
 		interrupts = <0x17 0x4>;
 		interrupt-parent = <0x2>;
-- 
2.7.4

[U-Boot] [PATCH v3 7/7] riscv: ae350: enable SMP

[Andes]

From: Rick Chen <rick@andestech.com>

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 board/AndesTech/ax25-ae350/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index 44cb302..5e682b6 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -24,5 +24,6 @@ config ENV_OFFSET
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select RISCV_NDS
+	imply SMP
 
 endif
-- 
2.7.4

[U-Boot] [PATCH v3 1/7] riscv: Add a SYSCON driver for Andestech's PLIC

[Bin Meng]

On Mon, Apr 1, 2019 at 4:29 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> The Platform-Level Interrupt Controller (PLIC)
> block holds memory-mapped claim and pending registers
> associated with software interrupt. It is required
> for handling IPI.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> V3:
>  - Rename plic_init() as enable_ipi().
>  - Declase as static.
>  - Remove PLIC_BASE_GET() from enable_ipi().
>
>  arch/riscv/Kconfig                   |   9 +++
>  arch/riscv/include/asm/global_data.h |   3 +
>  arch/riscv/include/asm/syscon.h      |   2 +-
>  arch/riscv/lib/Makefile              |   1 +
>  arch/riscv/lib/andes_plic.c          | 110 +++++++++++++++++++++++++++++++++++
>  5 files changed, 124 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/lib/andes_plic.c
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 6/7] riscv: dts: ae350 support SMP

[Bin Meng]

On Mon, Apr 1, 2019 at 4:29 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> V3:
>  - Fix some mis-alignments.
>  - Recovery isa string of CPU1.
>
>  arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
>  arch/riscv/dts/ae350_64.dts | 81 +++++++++++++++++++++++++++++++++------------
>  2 files changed, 118 insertions(+), 44 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[Bin Meng]

Hi Rick,

On Mon, Apr 1, 2019 at 4:29 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Changes in v3:
> Patch 1
> - Rename plic_init() as enable_ipi()
> - Remove PLIC_BASE_GET() from enable_ipi()
> Patch 2
> - Add a space before (PLMT)
> Patch 6
> - Fix some mis-alignments
> - Recovery isa string of CPU1
>
> Changes in v2:
> - Drop patch1 and replace by simple-bus driver
> - Rename nds_plic as andes_plic
> - Move initialize plic to PLIC_BASE_GET() and called automatically
> - Rename nds_plmt as andes_plmt
> - Recovery dts isa string
>
> Rick Chen (7):
>   riscv: Add a SYSCON driver for Andestech's PLIC
>   riscv: Add a SYSCON driver for Andestech's PLMT
>   riscv: ae350: disable ATCPIT100 timer
>   riscv: ax25: Add platform-specific Kconfig options
>   riscv: ax25: Andes specific cache shall only support in M-mode
>   riscv: dts: ae350 support SMP
>   riscv: ae350: enable SMP
>

Looks good to me. Are you going to send PR to Tom to include SMP
series in v2019.04?

Regards,
Bin

[U-Boot] [PATCH v3 1/7] riscv: Add a SYSCON driver for Andestech's PLIC

[Auer, Lukas]

Hi Rick,

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen <rick@andestech.com>
> 
> The Platform-Level Interrupt Controller (PLIC)
> block holds memory-mapped claim and pending registers
> associated with software interrupt. It is required
> for handling IPI.
> 
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> V3:
>  - Rename plic_init() as enable_ipi().
>  - Declase as static.
>  - Remove PLIC_BASE_GET() from enable_ipi().
> 

Take a look at patman [1], it makes it really easy to handle different
versions of a patch series. :)

[1]: https://github.com/u-boot/u-boot/blob/master/tools/patman/README

>  arch/riscv/Kconfig                   |   9 +++
>  arch/riscv/include/asm/global_data.h |   3 +
>  arch/riscv/include/asm/syscon.h      |   2 +-
>  arch/riscv/lib/Makefile              |   1 +
>  arch/riscv/lib/andes_plic.c          | 110 +++++++++++++++++++++++++++++++++++
>  5 files changed, 124 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/lib/andes_plic.c
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 3a4470d..511768b 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -109,6 +109,15 @@ config SIFIVE_CLINT
>  	  The SiFive CLINT block holds memory-mapped control and status registers
>  	  associated with software and timer interrupts.
>  
> +config ANDES_PLIC
> +	bool
> +	depends on RISCV_MMODE
> +	select REGMAP
> +	select SYSCON
> +	help
> +	  The Andes PLIC block holds memory-mapped claim and pending registers
> +	  associated with software interrupt.
> +
>  config RISCV_RDTIME
>  	bool
>  	default y if RISCV_SMODE
> diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> index 80e3165..b867910 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -18,6 +18,9 @@ struct arch_global_data {
>  #ifdef CONFIG_SIFIVE_CLINT
>  	void __iomem *clint;	/* clint base address */
>  #endif
> +#ifdef CONFIG_ANDES_PLIC
> +	void __iomem *plic;	/* plic base address */
> +#endif
>  #ifdef CONFIG_SMP
>  	struct ipi_data ipi[CONFIG_NR_CPUS];
>  #endif
> diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> index d311ee6..c1b4b86 100644
> --- a/arch/riscv/include/asm/syscon.h
> +++ b/arch/riscv/include/asm/syscon.h
> @@ -9,11 +9,11 @@
>  /*
>   * System controllers in a RISC-V system
>   *

nit: can you also drop the empty comment line above?

> - * So far only SiFive's Core Local Interruptor (CLINT) is defined.
>   */
>  enum {
>  	RISCV_NONE,
>  	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
> +	RISCV_SYSCON_PLIC,	/* Platform Level Interrupt Controller (PLIC) */
>  };
>  
>  #endif /* _ASM_SYSCON_H */
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index 35dbf64..1bf554b 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
>  obj-y	+= cache.o
>  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
>  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> +obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
>  obj-y	+= interrupts.o
>  obj-y	+= reset.o
>  obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> new file mode 100644
> index 0000000..67ab561
> --- /dev/null
> +++ b/arch/riscv/lib/andes_plic.c
> @@ -0,0 +1,110 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> + *
> + * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
> + * The PLIC block holds memory-mapped claim and pending registers
> + * associated with software interrupt.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +#include <dm/uclass-internal.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/syscon.h>
> +#include <cpu.h>
> +
> +/* pending register */
> +#define PENDING_REG(base, hart)	((ulong)(base) + 0x1000 + (hart) * 8)
> +/* enable register */
> +#define ENABLE_REG(base, hart)	((ulong)(base) + 0x2000 + (hart) * 0x80)
> +/* claim register */
> +#define CLAIM_REG(base, hart)	((ulong)(base) + 0x200004 + (hart) * 0x1000)
> +
> +#define ENABLE_HART_IPI         (0x80808080)
> +#define SEND_IPI_TO_HART(hart)  (0x80>>hart)
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +static int init_plic(void);
> +
> +#define PLIC_BASE_GET(void)						\
> +	do {								\
> +		long *ret;						\
> +									\
> +		if (!gd->arch.plic) {					\
> +			ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
> +			if (IS_ERR(ret))				\
> +				return PTR_ERR(ret);			\
> +			gd->arch.plic = ret;				\
> +			init_plic();					\
> +		}							\
> +	} while (0)
> +
> +static int enable_ipi(int harts)
> +{
> +	int i;
> +	int en = ENABLE_HART_IPI;
> +
> +	for (i = 0; i < harts ;i++)
> +	{
> +		en = en >> i;
> +		writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
> +	}
> +
> +	return 0;
> +}
> +
> +static int init_plic(void)
> +{
> +	struct udevice *dev;
> +	int ret;
> +
> +	ret = uclass_find_first_device(UCLASS_CPU, &dev);
> +	if (ret)
> +		return ret;
> +
> +	if (ret == 0 && dev != NULL) {
> +		ret = cpu_get_count(dev);

You should check first, if cpu_get_count() has returned an error before
using its return value.

> +		enable_ipi(ret);
> +		return 0;
> +	}
> +
> +	return -ENODEV;
> +}
> +
> +int riscv_send_ipi(int hart)
> +{
> +	PLIC_BASE_GET();
> +
> +	writel(SEND_IPI_TO_HART(hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
> +
> +	return 0;
> +}
> +
> +int riscv_clear_ipi(int hart)
> +{
> +	u32 source_id;
> +
> +	PLIC_BASE_GET();
> +
> +	source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> +	writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> +
> +	return 0;
> +}
> +
> +static const struct udevice_id andes_plic_ids[] = {
> +	{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },

Would a compatible string of "andes,plic1" be more suitable?

> +	{ }
> +};
> +
> +U_BOOT_DRIVER(nds_plic) = {

nit: andes_plic

> +	.name		= "andes_plic",
> +	.id		= UCLASS_SYSCON,
> +	.of_match	= andes_plic_ids,
> +	.flags		= DM_FLAG_PRE_RELOC,
> +};

There are a couple of checkpatch issues in this patch. I have copied
the relevant ones below.

CHECK: spaces preferred around that '>>' (ctx:VxV)
#135: FILE: arch/riscv/lib/andes_plic.c:29:
+#define SEND_IPI_TO_HART(hart)  (0x80>>hart)

ERROR: that open brace { should be on the previous line
#158: FILE: arch/riscv/lib/andes_plic.c:52:
+	for (i = 0; i < harts ;i++)
+	{

ERROR: space required after that ';' (ctx:WxV)
#158: FILE: arch/riscv/lib/andes_plic.c:52:
+	for (i = 0; i < harts ;i++)

CHECK: Comparison to NULL could be written "dev"
#176: FILE: arch/riscv/lib/andes_plic.c:70:
+	if (ret == 0 && dev != NULL) {

WARNING: line over 80 characters
#189: FILE: arch/riscv/lib/andes_plic.c:83:
+	writel(SEND_IPI_TO_HART(hart), (void __iomem *)PENDING_REG(gd-
>arch.plic, gd->arch.boot_hart));

Thanks,
Lukas

[U-Boot] [PATCH v3 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

[Auer, Lukas]

Hi Rick,

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen <rick@andestech.com>
> 
> The platform-Level Machine Timer (PLMT) block
> holds memory-mapped mtime register associated
> with timer tick.
> 
> This driver implements the riscv_get_time() which
> is required by the generic RISC-V timer driver.
> 
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> V3:
>  - Add a space before (PLMT).
> 
>  arch/riscv/Kconfig                   |  9 ++++++
>  arch/riscv/include/asm/global_data.h |  3 ++
>  arch/riscv/include/asm/syscon.h      |  1 +
>  arch/riscv/lib/Makefile              |  1 +
>  arch/riscv/lib/andes_plmt.c          | 53 ++++++++++++++++++++++++++++++++++++
>  5 files changed, 67 insertions(+)
>  create mode 100644 arch/riscv/lib/andes_plmt.c
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 511768b..ae8ff7b 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -118,6 +118,15 @@ config ANDES_PLIC
>  	  The Andes PLIC block holds memory-mapped claim and pending registers
>  	  associated with software interrupt.
>  
> +config ANDES_PLMT
> +	bool
> +	depends on RISCV_MMODE
> +	select REGMAP
> +	select SYSCON
> +	help
> +	  The Andes PLMT block holds memory-mapped mtime register
> +	  associated with timer tick.
> +
>  config RISCV_RDTIME
>  	bool
>  	default y if RISCV_SMODE
> diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> index b867910..dffcd45 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -21,6 +21,9 @@ struct arch_global_data {
>  #ifdef CONFIG_ANDES_PLIC
>  	void __iomem *plic;	/* plic base address */
>  #endif
> +#ifdef CONFIG_ANDES_PLMT
> +	void __iomem *plmt;	/* plmt base address */
> +#endif
>  #ifdef CONFIG_SMP
>  	struct ipi_data ipi[CONFIG_NR_CPUS];
>  #endif
> diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> index c1b4b86..6e12574 100644
> --- a/arch/riscv/include/asm/syscon.h
> +++ b/arch/riscv/include/asm/syscon.h
> @@ -14,6 +14,7 @@ enum {
>  	RISCV_NONE,
>  	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
>  	RISCV_SYSCON_PLIC,	/* Platform Level Interrupt Controller (PLIC) */
> +	RISCV_SYSCON_PLMT,	/* Platform Level Machine Timer (PLMT) */
>  };
>  
>  #endif /* _ASM_SYSCON_H */
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index 1bf554b..1c332db 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -12,6 +12,7 @@ obj-y	+= cache.o
>  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
>  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
>  obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> +obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
>  obj-y	+= interrupts.o
>  obj-y	+= reset.o
>  obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
> new file mode 100644
> index 0000000..12d7e0e
> --- /dev/null
> +++ b/arch/riscv/lib/andes_plmt.c
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> + *
> + * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
> + * The PLMT block holds memory-mapped mtime register
> + * associated with timer tick.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/syscon.h>
> +
> +/* mtime register */
> +#define MTIME_REG(base)			((ulong)(base))
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define PLMT_BASE_GET(void)						\
> +	do {								\
> +		long *ret;						\
> +									\
> +		if (!gd->arch.plmt) {					\
> +			ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
> +			if (IS_ERR(ret))				\
> +				return PTR_ERR(ret);			\
> +			gd->arch.plmt = ret;				\
> +		}							\
> +	} while (0)
> +
> +int riscv_get_time(u64 *time)
> +{
> +	PLMT_BASE_GET();
> +
> +	*time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
> +
> +	return 0;
> +}
> +
> +static const struct udevice_id nds_plmt_ids[] = {
> +	{ .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },

Would a compatible string of "andes,plmt0" be more suitable?

> +	{ }
> +};
> +
> +U_BOOT_DRIVER(nds_plmt) = {
> +	.name		= "nds_plmt",

nit: andes_plmt

Thanks,
Lukas

> +	.id		= UCLASS_SYSCON,
> +	.of_match	= nds_plmt_ids,
> +	.flags		= DM_FLAG_PRE_RELOC,
> +};

[U-Boot] [PATCH v3 1/7] riscv: Add a SYSCON driver for Andestech's PLIC

[Bin Meng]

Hi Lukas,

On Mon, Apr 1, 2019 at 5:08 PM Auer, Lukas
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Hi Rick,
>
> On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> > From: Rick Chen <rick@andestech.com>
> >
> > The Platform-Level Interrupt Controller (PLIC)
> > block holds memory-mapped claim and pending registers
> > associated with software interrupt. It is required
> > for handling IPI.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> > V3:
> >  - Rename plic_init() as enable_ipi().
> >  - Declase as static.
> >  - Remove PLIC_BASE_GET() from enable_ipi().
> >
>
> Take a look at patman [1], it makes it really easy to handle different
> versions of a patch series. :)
>
> [1]: https://github.com/u-boot/u-boot/blob/master/tools/patman/README
>
> >  arch/riscv/Kconfig                   |   9 +++
> >  arch/riscv/include/asm/global_data.h |   3 +
> >  arch/riscv/include/asm/syscon.h      |   2 +-
> >  arch/riscv/lib/Makefile              |   1 +
> >  arch/riscv/lib/andes_plic.c          | 110 +++++++++++++++++++++++++++++++++++
> >  5 files changed, 124 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/riscv/lib/andes_plic.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 3a4470d..511768b 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -109,6 +109,15 @@ config SIFIVE_CLINT
> >         The SiFive CLINT block holds memory-mapped control and status registers
> >         associated with software and timer interrupts.
> >
> > +config ANDES_PLIC
> > +     bool
> > +     depends on RISCV_MMODE
> > +     select REGMAP
> > +     select SYSCON
> > +     help
> > +       The Andes PLIC block holds memory-mapped claim and pending registers
> > +       associated with software interrupt.
> > +
> >  config RISCV_RDTIME
> >       bool
> >       default y if RISCV_SMODE
> > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> > index 80e3165..b867910 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -18,6 +18,9 @@ struct arch_global_data {
> >  #ifdef CONFIG_SIFIVE_CLINT
> >       void __iomem *clint;    /* clint base address */
> >  #endif
> > +#ifdef CONFIG_ANDES_PLIC
> > +     void __iomem *plic;     /* plic base address */
> > +#endif
> >  #ifdef CONFIG_SMP
> >       struct ipi_data ipi[CONFIG_NR_CPUS];
> >  #endif
> > diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> > index d311ee6..c1b4b86 100644
> > --- a/arch/riscv/include/asm/syscon.h
> > +++ b/arch/riscv/include/asm/syscon.h
> > @@ -9,11 +9,11 @@
> >  /*
> >   * System controllers in a RISC-V system
> >   *
>
> nit: can you also drop the empty comment line above?
>
> > - * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> >   */
> >  enum {
> >       RISCV_NONE,
> >       RISCV_SYSCON_CLINT,     /* Core Local Interruptor (CLINT) */
> > +     RISCV_SYSCON_PLIC,      /* Platform Level Interrupt Controller (PLIC) */
> >  };
> >
> >  #endif /* _ASM_SYSCON_H */
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index 35dbf64..1bf554b 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
> >  obj-y        += cache.o
> >  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> >  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > +obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> >  obj-y        += interrupts.o
> >  obj-y        += reset.o
> >  obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > new file mode 100644
> > index 0000000..67ab561
> > --- /dev/null
> > +++ b/arch/riscv/lib/andes_plic.c
> > @@ -0,0 +1,110 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> > + *
> > + * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
> > + * The PLIC block holds memory-mapped claim and pending registers
> > + * associated with software interrupt.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <dm/device-internal.h>
> > +#include <dm/lists.h>
> > +#include <dm/uclass-internal.h>
> > +#include <regmap.h>
> > +#include <syscon.h>
> > +#include <asm/io.h>
> > +#include <asm/syscon.h>
> > +#include <cpu.h>
> > +
> > +/* pending register */
> > +#define PENDING_REG(base, hart)      ((ulong)(base) + 0x1000 + (hart) * 8)
> > +/* enable register */
> > +#define ENABLE_REG(base, hart)       ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > +/* claim register */
> > +#define CLAIM_REG(base, hart)        ((ulong)(base) + 0x200004 + (hart) * 0x1000)
> > +
> > +#define ENABLE_HART_IPI         (0x80808080)
> > +#define SEND_IPI_TO_HART(hart)  (0x80>>hart)
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +static int init_plic(void);
> > +
> > +#define PLIC_BASE_GET(void)                                          \
> > +     do {                                                            \
> > +             long *ret;                                              \
> > +                                                                     \
> > +             if (!gd->arch.plic) {                                   \
> > +                     ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
> > +                     if (IS_ERR(ret))                                \
> > +                             return PTR_ERR(ret);                    \
> > +                     gd->arch.plic = ret;                            \
> > +                     init_plic();                                    \
> > +             }                                                       \
> > +     } while (0)
> > +
> > +static int enable_ipi(int harts)
> > +{
> > +     int i;
> > +     int en = ENABLE_HART_IPI;
> > +
> > +     for (i = 0; i < harts ;i++)
> > +     {
> > +             en = en >> i;
> > +             writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static int init_plic(void)
> > +{
> > +     struct udevice *dev;
> > +     int ret;
> > +
> > +     ret = uclass_find_first_device(UCLASS_CPU, &dev);
> > +     if (ret)
> > +             return ret;
> > +
> > +     if (ret == 0 && dev != NULL) {
> > +             ret = cpu_get_count(dev);
>
> You should check first, if cpu_get_count() has returned an error before
> using its return value.
>
> > +             enable_ipi(ret);
> > +             return 0;
> > +     }
> > +
> > +     return -ENODEV;
> > +}
> > +
> > +int riscv_send_ipi(int hart)
> > +{
> > +     PLIC_BASE_GET();
> > +
> > +     writel(SEND_IPI_TO_HART(hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
> > +
> > +     return 0;
> > +}
> > +
> > +int riscv_clear_ipi(int hart)
> > +{
> > +     u32 source_id;
> > +
> > +     PLIC_BASE_GET();
> > +
> > +     source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> > +     writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> > +
> > +     return 0;
> > +}
> > +
> > +static const struct udevice_id andes_plic_ids[] = {
> > +     { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
>
> Would a compatible string of "andes,plic1" be more suitable?
>
> > +     { }
> > +};
> > +
> > +U_BOOT_DRIVER(nds_plic) = {
>
> nit: andes_plic
>
> > +     .name           = "andes_plic",
> > +     .id             = UCLASS_SYSCON,
> > +     .of_match       = andes_plic_ids,
> > +     .flags          = DM_FLAG_PRE_RELOC,
> > +};
>
> There are a couple of checkpatch issues in this patch. I have copied
> the relevant ones below.
>

Thanks for the checking the issues by yourself. I was under the
impression that patman checks will be performed in the travis, but
looks it isn't.

Rick, please use patman, as Lukas suggested, to help your custodian work!

> CHECK: spaces preferred around that '>>' (ctx:VxV)
> #135: FILE: arch/riscv/lib/andes_plic.c:29:
> +#define SEND_IPI_TO_HART(hart)  (0x80>>hart)
>
> ERROR: that open brace { should be on the previous line
> #158: FILE: arch/riscv/lib/andes_plic.c:52:
> +       for (i = 0; i < harts ;i++)
> +       {
>
> ERROR: space required after that ';' (ctx:WxV)
> #158: FILE: arch/riscv/lib/andes_plic.c:52:
> +       for (i = 0; i < harts ;i++)
>
> CHECK: Comparison to NULL could be written "dev"
> #176: FILE: arch/riscv/lib/andes_plic.c:70:
> +       if (ret == 0 && dev != NULL) {
>
> WARNING: line over 80 characters
> #189: FILE: arch/riscv/lib/andes_plic.c:83:
> +       writel(SEND_IPI_TO_HART(hart), (void __iomem *)PENDING_REG(gd-
> >arch.plic, gd->arch.boot_hart));
>

Regards,
Bin

[U-Boot] [PATCH v3 3/7] riscv: ae350: disable ATCPIT100 timer

[Auer, Lukas]

Hi Rick,

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen <rick@andestech.com>
> 
> Disable ATCPIT100 SoC timer and replace by PLMT.
> 
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>  configs/ae350_rv32_defconfig | 1 -
>  configs/ae350_rv64_defconfig | 1 -
>  2 files changed, 2 deletions(-)
> 
> diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
> index 5837b48..e13c7de 100644
> --- a/configs/ae350_rv32_defconfig
> +++ b/configs/ae350_rv32_defconfig
> @@ -33,4 +33,3 @@ CONFIG_BAUDRATE=38400
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_ATCSPI200_SPI=y
> -CONFIG_ATCPIT100_TIMER=y
> diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
> index b250d3f..a41f918 100644
> --- a/configs/ae350_rv64_defconfig
> +++ b/configs/ae350_rv64_defconfig
> @@ -34,4 +34,3 @@ CONFIG_BAUDRATE=38400
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_ATCSPI200_SPI=y
> -CONFIG_ATCPIT100_TIMER=y

This may break bisectability, since the board won't have a working
timer until the next patch. You may consider squashing them.

Other than that.

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

Thanks,
Lukas

[U-Boot] [PATCH v3 4/7] riscv: ax25: Add platform-specific Kconfig options

[Auer, Lukas]

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen <rick@andestech.com>
> 
> Add ax25 RISC-V platform-specific Kconfig options, to include
> CPU and timer drivers.
> 
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>  arch/riscv/cpu/ax25/Kconfig | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [PATCH v3 5/7] riscv: ax25: Andes specific cache shall only support in M-mode

[Auer, Lukas]

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen <rick@andestech.com>
> 
> Limit the cache configuration only can be supported in M mode.
> It can not be manipulated in S mode.
> 
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>  arch/riscv/cpu/ax25/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [PATCH v3 6/7] riscv: dts: ae350 support SMP

[Auer, Lukas]

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen <rick@andestech.com>
> 
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
> V3:
>  - Fix some mis-alignments.
>  - Recovery isa string of CPU1.
> 
>  arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
>  arch/riscv/dts/ae350_64.dts | 81 +++++++++++++++++++++++++++++++++------------
>  2 files changed, 118 insertions(+), 44 deletions(-)
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [PATCH v3 7/7] riscv: ae350: enable SMP

[Auer, Lukas]

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen <rick@andestech.com>
> 
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>  board/AndesTech/ax25-ae350/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn@gmail.com> 於 2019年4月1日 週一 下午5:01寫道：
>
> Hi Rick,
>
> On Mon, Apr 1, 2019 at 4:29 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > Changes in v3:
> > Patch 1
> > - Rename plic_init() as enable_ipi()
> > - Remove PLIC_BASE_GET() from enable_ipi()
> > Patch 2
> > - Add a space before (PLMT)
> > Patch 6
> > - Fix some mis-alignments
> > - Recovery isa string of CPU1
> >
> > Changes in v2:
> > - Drop patch1 and replace by simple-bus driver
> > - Rename nds_plic as andes_plic
> > - Move initialize plic to PLIC_BASE_GET() and called automatically
> > - Rename nds_plmt as andes_plmt
> > - Recovery dts isa string
> >
> > Rick Chen (7):
> >   riscv: Add a SYSCON driver for Andestech's PLIC
> >   riscv: Add a SYSCON driver for Andestech's PLMT
> >   riscv: ae350: disable ATCPIT100 timer
> >   riscv: ax25: Add platform-specific Kconfig options
> >   riscv: ax25: Andes specific cache shall only support in M-mode
> >   riscv: dts: ae350 support SMP
> >   riscv: ae350: enable SMP
> >
>
> Looks good to me. Are you going to send PR to Tom to include SMP
> series in v2019.04?
>

Thanks for your review.
But there seem have some suggestions from Lukas to be fixed.
After that I will send PR to Tom ASAP.

Thanks
Rick
> Regards,
> Bin

[U-Boot] [PATCH v3 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

[Rick Chen]

Hi Lukas

Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月1日 週一 下午5:09寫道：
>
> Hi Rick,
>
> On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> > From: Rick Chen <rick@andestech.com>
> >
> > The platform-Level Machine Timer (PLMT) block
> > holds memory-mapped mtime register associated
> > with timer tick.
> >
> > This driver implements the riscv_get_time() which
> > is required by the generic RISC-V timer driver.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> > V3:
> >  - Add a space before (PLMT).
> >
> >  arch/riscv/Kconfig                   |  9 ++++++
> >  arch/riscv/include/asm/global_data.h |  3 ++
> >  arch/riscv/include/asm/syscon.h      |  1 +
> >  arch/riscv/lib/Makefile              |  1 +
> >  arch/riscv/lib/andes_plmt.c          | 53 ++++++++++++++++++++++++++++++++++++
> >  5 files changed, 67 insertions(+)
> >  create mode 100644 arch/riscv/lib/andes_plmt.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 511768b..ae8ff7b 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -118,6 +118,15 @@ config ANDES_PLIC
> >         The Andes PLIC block holds memory-mapped claim and pending registers
> >         associated with software interrupt.
> >
> > +config ANDES_PLMT
> > +     bool
> > +     depends on RISCV_MMODE
> > +     select REGMAP
> > +     select SYSCON
> > +     help
> > +       The Andes PLMT block holds memory-mapped mtime register
> > +       associated with timer tick.
> > +
> >  config RISCV_RDTIME
> >       bool
> >       default y if RISCV_SMODE
> > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> > index b867910..dffcd45 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -21,6 +21,9 @@ struct arch_global_data {
> >  #ifdef CONFIG_ANDES_PLIC
> >       void __iomem *plic;     /* plic base address */
> >  #endif
> > +#ifdef CONFIG_ANDES_PLMT
> > +     void __iomem *plmt;     /* plmt base address */
> > +#endif
> >  #ifdef CONFIG_SMP
> >       struct ipi_data ipi[CONFIG_NR_CPUS];
> >  #endif
> > diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> > index c1b4b86..6e12574 100644
> > --- a/arch/riscv/include/asm/syscon.h
> > +++ b/arch/riscv/include/asm/syscon.h
> > @@ -14,6 +14,7 @@ enum {
> >       RISCV_NONE,
> >       RISCV_SYSCON_CLINT,     /* Core Local Interruptor (CLINT) */
> >       RISCV_SYSCON_PLIC,      /* Platform Level Interrupt Controller (PLIC) */
> > +     RISCV_SYSCON_PLMT,      /* Platform Level Machine Timer (PLMT) */
> >  };
> >
> >  #endif /* _ASM_SYSCON_H */
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index 1bf554b..1c332db 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -12,6 +12,7 @@ obj-y       += cache.o
> >  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> >  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> >  obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> > +obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
> >  obj-y        += interrupts.o
> >  obj-y        += reset.o
> >  obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
> > new file mode 100644
> > index 0000000..12d7e0e
> > --- /dev/null
> > +++ b/arch/riscv/lib/andes_plmt.c
> > @@ -0,0 +1,53 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> > + *
> > + * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
> > + * The PLMT block holds memory-mapped mtime register
> > + * associated with timer tick.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <regmap.h>
> > +#include <syscon.h>
> > +#include <asm/io.h>
> > +#include <asm/syscon.h>
> > +
> > +/* mtime register */
> > +#define MTIME_REG(base)                      ((ulong)(base))
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define PLMT_BASE_GET(void)                                          \
> > +     do {                                                            \
> > +             long *ret;                                              \
> > +                                                                     \
> > +             if (!gd->arch.plmt) {                                   \
> > +                     ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
> > +                     if (IS_ERR(ret))                                \
> > +                             return PTR_ERR(ret);                    \
> > +                     gd->arch.plmt = ret;                            \
> > +             }                                                       \
> > +     } while (0)
> > +
> > +int riscv_get_time(u64 *time)
> > +{
> > +     PLMT_BASE_GET();
> > +
> > +     *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
> > +
> > +     return 0;
> > +}
> > +
> > +static const struct udevice_id nds_plmt_ids[] = {
> > +     { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
>
> Would a compatible string of "andes,plmt0" be more suitable?
>
> > +     { }
> > +};
> > +
> > +U_BOOT_DRIVER(nds_plmt) = {
> > +     .name           = "nds_plmt",
>
> nit: andes_plmt

OK
I will rename it.

Thanks
Rick

>
> Thanks,
> Lukas
>
> > +     .id             = UCLASS_SYSCON,
> > +     .of_match       = nds_plmt_ids,
> > +     .flags          = DM_FLAG_PRE_RELOC,
> > +};

[U-Boot] [PATCH v3 1/7] riscv: Add a SYSCON driver for Andestech's PLIC

[Rick Chen]

Hi Lukas

>Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月1日 週一 下午5:08寫道：
>
> Hi Rick,
>
> On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> > From: Rick Chen <rick@andestech.com>
> >
> > The Platform-Level Interrupt Controller (PLIC)
> > block holds memory-mapped claim and pending registers
> > associated with software interrupt. It is required
> > for handling IPI.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> > V3:
> >  - Rename plic_init() as enable_ipi().
> >  - Declase as static.
> >  - Remove PLIC_BASE_GET() from enable_ipi().
> >
>
> Take a look at patman [1], it makes it really easy to handle different
> versions of a patch series. :)

OK
Thanks :)

>
> [1]: https://github.com/u-boot/u-boot/blob/master/tools/patman/README
>
> >  arch/riscv/Kconfig                   |   9 +++
> >  arch/riscv/include/asm/global_data.h |   3 +
> >  arch/riscv/include/asm/syscon.h      |   2 +-
> >  arch/riscv/lib/Makefile              |   1 +
> >  arch/riscv/lib/andes_plic.c          | 110 +++++++++++++++++++++++++++++++++++
> >  5 files changed, 124 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/riscv/lib/andes_plic.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 3a4470d..511768b 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -109,6 +109,15 @@ config SIFIVE_CLINT
> >         The SiFive CLINT block holds memory-mapped control and status registers
> >         associated with software and timer interrupts.
> >
> > +config ANDES_PLIC
> > +     bool
> > +     depends on RISCV_MMODE
> > +     select REGMAP
> > +     select SYSCON
> > +     help
> > +       The Andes PLIC block holds memory-mapped claim and pending registers
> > +       associated with software interrupt.
> > +
> >  config RISCV_RDTIME
> >       bool
> >       default y if RISCV_SMODE
> > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> > index 80e3165..b867910 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -18,6 +18,9 @@ struct arch_global_data {
> >  #ifdef CONFIG_SIFIVE_CLINT
> >       void __iomem *clint;    /* clint base address */
> >  #endif
> > +#ifdef CONFIG_ANDES_PLIC
> > +     void __iomem *plic;     /* plic base address */
> > +#endif
> >  #ifdef CONFIG_SMP
> >       struct ipi_data ipi[CONFIG_NR_CPUS];
> >  #endif
> > diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> > index d311ee6..c1b4b86 100644
> > --- a/arch/riscv/include/asm/syscon.h
> > +++ b/arch/riscv/include/asm/syscon.h
> > @@ -9,11 +9,11 @@
> >  /*
> >   * System controllers in a RISC-V system
> >   *
>
> nit: can you also drop the empty comment line above?

OK

>
> > - * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> >   */
> >  enum {
> >       RISCV_NONE,
> >       RISCV_SYSCON_CLINT,     /* Core Local Interruptor (CLINT) */
> > +     RISCV_SYSCON_PLIC,      /* Platform Level Interrupt Controller (PLIC) */
> >  };
> >
> >  #endif /* _ASM_SYSCON_H */
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index 35dbf64..1bf554b 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
> >  obj-y        += cache.o
> >  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> >  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > +obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> >  obj-y        += interrupts.o
> >  obj-y        += reset.o
> >  obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > new file mode 100644
> > index 0000000..67ab561
> > --- /dev/null
> > +++ b/arch/riscv/lib/andes_plic.c
> > @@ -0,0 +1,110 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> > + *
> > + * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
> > + * The PLIC block holds memory-mapped claim and pending registers
> > + * associated with software interrupt.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <dm/device-internal.h>
> > +#include <dm/lists.h>
> > +#include <dm/uclass-internal.h>
> > +#include <regmap.h>
> > +#include <syscon.h>
> > +#include <asm/io.h>
> > +#include <asm/syscon.h>
> > +#include <cpu.h>
> > +
> > +/* pending register */
> > +#define PENDING_REG(base, hart)      ((ulong)(base) + 0x1000 + (hart) * 8)
> > +/* enable register */
> > +#define ENABLE_REG(base, hart)       ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > +/* claim register */
> > +#define CLAIM_REG(base, hart)        ((ulong)(base) + 0x200004 + (hart) * 0x1000)
> > +
> > +#define ENABLE_HART_IPI         (0x80808080)
> > +#define SEND_IPI_TO_HART(hart)  (0x80>>hart)
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +static int init_plic(void);
> > +
> > +#define PLIC_BASE_GET(void)                                          \
> > +     do {                                                            \
> > +             long *ret;                                              \
> > +                                                                     \
> > +             if (!gd->arch.plic) {                                   \
> > +                     ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
> > +                     if (IS_ERR(ret))                                \
> > +                             return PTR_ERR(ret);                    \
> > +                     gd->arch.plic = ret;                            \
> > +                     init_plic();                                    \
> > +             }                                                       \
> > +     } while (0)
> > +
> > +static int enable_ipi(int harts)
> > +{
> > +     int i;
> > +     int en = ENABLE_HART_IPI;
> > +
> > +     for (i = 0; i < harts ;i++)
> > +     {
> > +             en = en >> i;
> > +             writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static int init_plic(void)
> > +{
> > +     struct udevice *dev;
> > +     int ret;
> > +
> > +     ret = uclass_find_first_device(UCLASS_CPU, &dev);
> > +     if (ret)
> > +             return ret;
> > +
> > +     if (ret == 0 && dev != NULL) {
> > +             ret = cpu_get_count(dev);
>
> You should check first, if cpu_get_count() has returned an error before
> using its return value.

OK
I will check the return value from cpu_get_count().

>
> > +             enable_ipi(ret);
> > +             return 0;
> > +     }
> > +
> > +     return -ENODEV;
> > +}
> > +
> > +int riscv_send_ipi(int hart)
> > +{
> > +     PLIC_BASE_GET();
> > +
> > +     writel(SEND_IPI_TO_HART(hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
> > +
> > +     return 0;
> > +}
> > +
> > +int riscv_clear_ipi(int hart)
> > +{
> > +     u32 source_id;
> > +
> > +     PLIC_BASE_GET();
> > +
> > +     source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> > +     writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> > +
> > +     return 0;
> > +}
> > +
> > +static const struct udevice_id andes_plic_ids[] = {
> > +     { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
>
> Would a compatible string of "andes,plic1" be more suitable?

I got and sync the dts from our kernel team.
If I shall change the string, I need to discuss with them.
Some of them are not in office this week.
So I prefer not change in this series.

>
> > +     { }
> > +};
> > +
> > +U_BOOT_DRIVER(nds_plic) = {
>
> nit: andes_plic

OK

> +     .name           = "andes_plic",
> > +     .id             = UCLASS_SYSCON,
> > +     .of_match       = andes_plic_ids,
> > +     .flags          = DM_FLAG_PRE_RELOC,
> > +};
>
> There are a couple of checkpatch issues in this patch. I have copied
> the relevant ones below.
>

I will check patchs in the next patchsets

Thanks
Rick

> CHECK: spaces preferred around that '>>' (ctx:VxV)
> #135: FILE: arch/riscv/lib/andes_plic.c:29:
> +#define SEND_IPI_TO_HART(hart)  (0x80>>hart)
>
> ERROR: that open brace { should be on the previous line
> #158: FILE: arch/riscv/lib/andes_plic.c:52:
> +       for (i = 0; i < harts ;i++)
> +       {
>
> ERROR: space required after that ';' (ctx:WxV)
> #158: FILE: arch/riscv/lib/andes_plic.c:52:
> +       for (i = 0; i < harts ;i++)
>
> CHECK: Comparison to NULL could be written "dev"
> #176: FILE: arch/riscv/lib/andes_plic.c:70:
> +       if (ret == 0 && dev != NULL) {
>
> WARNING: line over 80 characters
> #189: FILE: arch/riscv/lib/andes_plic.c:83:
> +       writel(SEND_IPI_TO_HART(hart), (void __iomem *)PENDING_REG(gd-
> >arch.plic, gd->arch.boot_hart));
>
> Thanks,
> Lukas

[U-Boot] [PATCH v3 3/7] riscv: ae350: disable ATCPIT100 timer

[Rick Chen]

Hi Lukas

Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月1日 週一 下午5:13寫道：
>
> Hi Rick,
>
> On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> > From: Rick Chen <rick@andestech.com>
> >
> > Disable ATCPIT100 SoC timer and replace by PLMT.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >  configs/ae350_rv32_defconfig | 1 -
> >  configs/ae350_rv64_defconfig | 1 -
> >  2 files changed, 2 deletions(-)
> >
> > diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
> > index 5837b48..e13c7de 100644
> > --- a/configs/ae350_rv32_defconfig
> > +++ b/configs/ae350_rv32_defconfig
> > @@ -33,4 +33,3 @@ CONFIG_BAUDRATE=38400
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_ATCSPI200_SPI=y
> > -CONFIG_ATCPIT100_TIMER=y
> > diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
> > index b250d3f..a41f918 100644
> > --- a/configs/ae350_rv64_defconfig
> > +++ b/configs/ae350_rv64_defconfig
> > @@ -34,4 +34,3 @@ CONFIG_BAUDRATE=38400
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_ATCSPI200_SPI=y
> > -CONFIG_ATCPIT100_TIMER=y
>
> This may break bisectability, since the board won't have a working
> timer until the next patch. You may consider squashing them.

OK
I will combine them as one.

Thanks
Rick

>
> Other than that.
>
> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
>
> Thanks,
> Lukas

[U-Boot] [PATCH v3 1/7] riscv: Add a SYSCON driver for Andestech's PLIC

[Auer, Lukas]

Hi Rick,

On Tue, 2019-04-02 at 10:12 +0800, Rick Chen wrote:
> Hi Lukas
> 
> > Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月1日 週一 下午5:08寫道：
> > 
> > Hi Rick,
> > 
> > On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> > > From: Rick Chen <rick@andestech.com>
> > > 
> > > The Platform-Level Interrupt Controller (PLIC)
> > > block holds memory-mapped claim and pending registers
> > > associated with software interrupt. It is required
> > > for handling IPI.
> > > 
> > > Signed-off-by: Rick Chen <rick@andestech.com>
> > > Cc: Greentime Hu <greentime@andestech.com>
> > > ---
> > > V3:
> > >  - Rename plic_init() as enable_ipi().
> > >  - Declase as static.
> > >  - Remove PLIC_BASE_GET() from enable_ipi().
> > > 
> > 
> > Take a look at patman [1], it makes it really easy to handle different
> > versions of a patch series. :)
> 
> OK
> Thanks :)
> 
> > [1]: https://github.com/u-boot/u-boot/blob/master/tools/patman/README
> > 
> > >  arch/riscv/Kconfig                   |   9 +++
> > >  arch/riscv/include/asm/global_data.h |   3 +
> > >  arch/riscv/include/asm/syscon.h      |   2 +-
> > >  arch/riscv/lib/Makefile              |   1 +
> > >  arch/riscv/lib/andes_plic.c          | 110 +++++++++++++++++++++++++++++++++++
> > >  5 files changed, 124 insertions(+), 1 deletion(-)
> > >  create mode 100644 arch/riscv/lib/andes_plic.c
> > > 
> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > index 3a4470d..511768b 100644
> > > --- a/arch/riscv/Kconfig
> > > +++ b/arch/riscv/Kconfig
> > > @@ -109,6 +109,15 @@ config SIFIVE_CLINT
> > >         The SiFive CLINT block holds memory-mapped control and status registers
> > >         associated with software and timer interrupts.
> > > 
> > > +config ANDES_PLIC
> > > +     bool
> > > +     depends on RISCV_MMODE
> > > +     select REGMAP
> > > +     select SYSCON
> > > +     help
> > > +       The Andes PLIC block holds memory-mapped claim and pending registers
> > > +       associated with software interrupt.
> > > +
> > >  config RISCV_RDTIME
> > >       bool
> > >       default y if RISCV_SMODE
> > > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> > > index 80e3165..b867910 100644
> > > --- a/arch/riscv/include/asm/global_data.h
> > > +++ b/arch/riscv/include/asm/global_data.h
> > > @@ -18,6 +18,9 @@ struct arch_global_data {
> > >  #ifdef CONFIG_SIFIVE_CLINT
> > >       void __iomem *clint;    /* clint base address */
> > >  #endif
> > > +#ifdef CONFIG_ANDES_PLIC
> > > +     void __iomem *plic;     /* plic base address */
> > > +#endif
> > >  #ifdef CONFIG_SMP
> > >       struct ipi_data ipi[CONFIG_NR_CPUS];
> > >  #endif
> > > diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> > > index d311ee6..c1b4b86 100644
> > > --- a/arch/riscv/include/asm/syscon.h
> > > +++ b/arch/riscv/include/asm/syscon.h
> > > @@ -9,11 +9,11 @@
> > >  /*
> > >   * System controllers in a RISC-V system
> > >   *
> > 
> > nit: can you also drop the empty comment line above?
> 
> OK
> 
> > > - * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> > >   */
> > >  enum {
> > >       RISCV_NONE,
> > >       RISCV_SYSCON_CLINT,     /* Core Local Interruptor (CLINT) */
> > > +     RISCV_SYSCON_PLIC,      /* Platform Level Interrupt Controller (PLIC) */
> > >  };
> > > 
> > >  #endif /* _ASM_SYSCON_H */
> > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > > index 35dbf64..1bf554b 100644
> > > --- a/arch/riscv/lib/Makefile
> > > +++ b/arch/riscv/lib/Makefile
> > > @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
> > >  obj-y        += cache.o
> > >  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> > >  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > > +obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> > >  obj-y        += interrupts.o
> > >  obj-y        += reset.o
> > >  obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > > new file mode 100644
> > > index 0000000..67ab561
> > > --- /dev/null
> > > +++ b/arch/riscv/lib/andes_plic.c
> > > @@ -0,0 +1,110 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2019, Rick Chen <rick@andestech.com>
> > > + *
> > > + * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
> > > + * The PLIC block holds memory-mapped claim and pending registers
> > > + * associated with software interrupt.
> > > + */
> > > +
> > > +#include <common.h>
> > > +#include <dm.h>
> > > +#include <dm/device-internal.h>
> > > +#include <dm/lists.h>
> > > +#include <dm/uclass-internal.h>
> > > +#include <regmap.h>
> > > +#include <syscon.h>
> > > +#include <asm/io.h>
> > > +#include <asm/syscon.h>
> > > +#include <cpu.h>
> > > +
> > > +/* pending register */
> > > +#define PENDING_REG(base, hart)      ((ulong)(base) + 0x1000 + (hart) * 8)
> > > +/* enable register */
> > > +#define ENABLE_REG(base, hart)       ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > > +/* claim register */
> > > +#define CLAIM_REG(base, hart)        ((ulong)(base) + 0x200004 + (hart) * 0x1000)
> > > +
> > > +#define ENABLE_HART_IPI         (0x80808080)
> > > +#define SEND_IPI_TO_HART(hart)  (0x80>>hart)
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +static int init_plic(void);
> > > +
> > > +#define PLIC_BASE_GET(void)                                          \
> > > +     do {                                                            \
> > > +             long *ret;                                              \
> > > +                                                                     \
> > > +             if (!gd->arch.plic) {                                   \
> > > +                     ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
> > > +                     if (IS_ERR(ret))                                \
> > > +                             return PTR_ERR(ret);                    \
> > > +                     gd->arch.plic = ret;                            \
> > > +                     init_plic();                                    \
> > > +             }                                                       \
> > > +     } while (0)
> > > +
> > > +static int enable_ipi(int harts)
> > > +{
> > > +     int i;
> > > +     int en = ENABLE_HART_IPI;
> > > +
> > > +     for (i = 0; i < harts ;i++)
> > > +     {
> > > +             en = en >> i;
> > > +             writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
> > > +     }
> > > +
> > > +     return 0;
> > > +}
> > > +
> > > +static int init_plic(void)
> > > +{
> > > +     struct udevice *dev;
> > > +     int ret;
> > > +
> > > +     ret = uclass_find_first_device(UCLASS_CPU, &dev);
> > > +     if (ret)
> > > +             return ret;
> > > +
> > > +     if (ret == 0 && dev != NULL) {
> > > +             ret = cpu_get_count(dev);
> > 
> > You should check first, if cpu_get_count() has returned an error before
> > using its return value.
> 
> OK
> I will check the return value from cpu_get_count().
> 
> > > +             enable_ipi(ret);
> > > +             return 0;
> > > +     }
> > > +
> > > +     return -ENODEV;
> > > +}
> > > +
> > > +int riscv_send_ipi(int hart)
> > > +{
> > > +     PLIC_BASE_GET();
> > > +
> > > +     writel(SEND_IPI_TO_HART(hart), (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
> > > +
> > > +     return 0;
> > > +}
> > > +
> > > +int riscv_clear_ipi(int hart)
> > > +{
> > > +     u32 source_id;
> > > +
> > > +     PLIC_BASE_GET();
> > > +
> > > +     source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> > > +     writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
> > > +
> > > +     return 0;
> > > +}
> > > +
> > > +static const struct udevice_id andes_plic_ids[] = {
> > > +     { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
> > 
> > Would a compatible string of "andes,plic1" be more suitable?
> 
> I got and sync the dts from our kernel team.
> If I shall change the string, I need to discuss with them.
> Some of them are not in office this week.
> So I prefer not change in this series.
> 

That makes sense. I think it's fine, if you sync the device tree once
it is included in the upstream kernel.

Thanks,
Lukas

> > > +     { }
> > > +};
> > > +
> > > +U_BOOT_DRIVER(nds_plic) = {
> > 
> > nit: andes_plic
> 
> OK
> 
> > +     .name           = "andes_plic",
> > > +     .id             = UCLASS_SYSCON,
> > > +     .of_match       = andes_plic_ids,
> > > +     .flags          = DM_FLAG_PRE_RELOC,
> > > +};
> > 
> > There are a couple of checkpatch issues in this patch. I have copied
> > the relevant ones below.
> > 
> 
> I will check patchs in the next patchsets
> 
> Thanks
> Rick
> 
> > CHECK: spaces preferred around that '>>' (ctx:VxV)
> > #135: FILE: arch/riscv/lib/andes_plic.c:29:
> > +#define SEND_IPI_TO_HART(hart)  (0x80>>hart)
> > 
> > ERROR: that open brace { should be on the previous line
> > #158: FILE: arch/riscv/lib/andes_plic.c:52:
> > +       for (i = 0; i < harts ;i++)
> > +       {
> > 
> > ERROR: space required after that ';' (ctx:WxV)
> > #158: FILE: arch/riscv/lib/andes_plic.c:52:
> > +       for (i = 0; i < harts ;i++)
> > 
> > CHECK: Comparison to NULL could be written "dev"
> > #176: FILE: arch/riscv/lib/andes_plic.c:70:
> > +       if (ret == 0 && dev != NULL) {
> > 
> > WARNING: line over 80 characters
> > #189: FILE: arch/riscv/lib/andes_plic.c:83:
> > +       writel(SEND_IPI_TO_HART(hart), (void __iomem *)PENDING_REG(gd-
> > > arch.plic, gd->arch.boot_hart));
> > 
> > Thanks,
> > Lukas

[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[Rick Chen]

Hi Bin and Lukas

Rick Chen <rickchen36@gmail.com> 於 2019年4月2日 週二 上午9:22寫道：
>
> Hi Bin
>
> Bin Meng <bmeng.cn@gmail.com> 於 2019年4月1日 週一 下午5:01寫道：
> >
> > Hi Rick,
> >
> > On Mon, Apr 1, 2019 at 4:29 PM Andes <uboot@andestech.com> wrote:
> > >
> > > From: Rick Chen <rick@andestech.com>
> > >
> > > Changes in v3:
> > > Patch 1
> > > - Rename plic_init() as enable_ipi()
> > > - Remove PLIC_BASE_GET() from enable_ipi()
> > > Patch 2
> > > - Add a space before (PLMT)
> > > Patch 6
> > > - Fix some mis-alignments
> > > - Recovery isa string of CPU1
> > >
> > > Changes in v2:
> > > - Drop patch1 and replace by simple-bus driver
> > > - Rename nds_plic as andes_plic
> > > - Move initialize plic to PLIC_BASE_GET() and called automatically
> > > - Rename nds_plmt as andes_plmt
> > > - Recovery dts isa string
> > >
> > > Rick Chen (7):
> > >   riscv: Add a SYSCON driver for Andestech's PLIC
> > >   riscv: Add a SYSCON driver for Andestech's PLMT
> > >   riscv: ae350: disable ATCPIT100 timer
> > >   riscv: ax25: Add platform-specific Kconfig options
> > >   riscv: ax25: Andes specific cache shall only support in M-mode
> > >   riscv: dts: ae350 support SMP
> > >   riscv: ae350: enable SMP
> > >
> >
> > Looks good to me. Are you going to send PR to Tom to include SMP
> > series in v2019.04?
> >
>
> Thanks for your review.
> But there seem have some suggestions from Lukas to be fixed.
> After that I will send PR to Tom ASAP.
>

I have send V4 and Lukas have reviewed it.
When I try to sync to master, I found that there seem
have CONFIG_DEFAULT_DEVICE_TREE failures issue in u-boot.git master.
Troy have reported it actually. But u-boot-riscv.git is fine.
So I am not sure if I shall sync to master now.
Or I shall wait until it has been fixed.

Rick

> Thanks
> Rick
> > Regards,
> > Bin

[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[Bin Meng]

Hi Rick,

On Wed, Apr 3, 2019 at 9:37 AM Rick Chen <rickchen36@gmail.com> wrote:
>
> Hi Bin and Lukas
>
> Rick Chen <rickchen36@gmail.com> 於 2019年4月2日 週二 上午9:22寫道：
> >
> > Hi Bin
> >
> > Bin Meng <bmeng.cn@gmail.com> 於 2019年4月1日 週一 下午5:01寫道：
> > >
> > > Hi Rick,
> > >
> > > On Mon, Apr 1, 2019 at 4:29 PM Andes <uboot@andestech.com> wrote:
> > > >
> > > > From: Rick Chen <rick@andestech.com>
> > > >
> > > > Changes in v3:
> > > > Patch 1
> > > > - Rename plic_init() as enable_ipi()
> > > > - Remove PLIC_BASE_GET() from enable_ipi()
> > > > Patch 2
> > > > - Add a space before (PLMT)
> > > > Patch 6
> > > > - Fix some mis-alignments
> > > > - Recovery isa string of CPU1
> > > >
> > > > Changes in v2:
> > > > - Drop patch1 and replace by simple-bus driver
> > > > - Rename nds_plic as andes_plic
> > > > - Move initialize plic to PLIC_BASE_GET() and called automatically
> > > > - Rename nds_plmt as andes_plmt
> > > > - Recovery dts isa string
> > > >
> > > > Rick Chen (7):
> > > >   riscv: Add a SYSCON driver for Andestech's PLIC
> > > >   riscv: Add a SYSCON driver for Andestech's PLMT
> > > >   riscv: ae350: disable ATCPIT100 timer
> > > >   riscv: ax25: Add platform-specific Kconfig options
> > > >   riscv: ax25: Andes specific cache shall only support in M-mode
> > > >   riscv: dts: ae350 support SMP
> > > >   riscv: ae350: enable SMP
> > > >
> > >
> > > Looks good to me. Are you going to send PR to Tom to include SMP
> > > series in v2019.04?
> > >
> >
> > Thanks for your review.
> > But there seem have some suggestions from Lukas to be fixed.
> > After that I will send PR to Tom ASAP.
> >
>
> I have send V4 and Lukas have reviewed it.
> When I try to sync to master, I found that there seem
> have CONFIG_DEFAULT_DEVICE_TREE failures issue in u-boot.git master.
> Troy have reported it actually. But u-boot-riscv.git is fine.
> So I am not sure if I shall sync to master now.
> Or I shall wait until it has been fixed.
>

The CONFIG_DEFAULT_DEVICE_TREE fix was reviewed by Lukas and me. I
suppose it's good to send PR now?

Regards,
Bin

[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn@gmail.com> 於 2019年4月4日 週四 下午9:49寫道：
>
> Hi Rick,
>
> On Wed, Apr 3, 2019 at 9:37 AM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > Hi Bin and Lukas
> >
> > Rick Chen <rickchen36@gmail.com> 於 2019年4月2日 週二 上午9:22寫道：
> > >
> > > Hi Bin
> > >
> > > Bin Meng <bmeng.cn@gmail.com> 於 2019年4月1日 週一 下午5:01寫道：
> > > >
> > > > Hi Rick,
> > > >
> > > > On Mon, Apr 1, 2019 at 4:29 PM Andes <uboot@andestech.com> wrote:
> > > > >
> > > > > From: Rick Chen <rick@andestech.com>
> > > > >
> > > > > Changes in v3:
> > > > > Patch 1
> > > > > - Rename plic_init() as enable_ipi()
> > > > > - Remove PLIC_BASE_GET() from enable_ipi()
> > > > > Patch 2
> > > > > - Add a space before (PLMT)
> > > > > Patch 6
> > > > > - Fix some mis-alignments
> > > > > - Recovery isa string of CPU1
> > > > >
> > > > > Changes in v2:
> > > > > - Drop patch1 and replace by simple-bus driver
> > > > > - Rename nds_plic as andes_plic
> > > > > - Move initialize plic to PLIC_BASE_GET() and called automatically
> > > > > - Rename nds_plmt as andes_plmt
> > > > > - Recovery dts isa string
> > > > >
> > > > > Rick Chen (7):
> > > > >   riscv: Add a SYSCON driver for Andestech's PLIC
> > > > >   riscv: Add a SYSCON driver for Andestech's PLMT
> > > > >   riscv: ae350: disable ATCPIT100 timer
> > > > >   riscv: ax25: Add platform-specific Kconfig options
> > > > >   riscv: ax25: Andes specific cache shall only support in M-mode
> > > > >   riscv: dts: ae350 support SMP
> > > > >   riscv: ae350: enable SMP
> > > > >
> > > >
> > > > Looks good to me. Are you going to send PR to Tom to include SMP
> > > > series in v2019.04?
> > > >
> > >
> > > Thanks for your review.
> > > But there seem have some suggestions from Lukas to be fixed.
> > > After that I will send PR to Tom ASAP.
> > >
> >
> > I have send V4 and Lukas have reviewed it.
> > When I try to sync to master, I found that there seem
> > have CONFIG_DEFAULT_DEVICE_TREE failures issue in u-boot.git master.
> > Troy have reported it actually. But u-boot-riscv.git is fine.
> > So I am not sure if I shall sync to master now.
> > Or I shall wait until it has been fixed.
> >
>
> The CONFIG_DEFAULT_DEVICE_TREE fix was reviewed by Lukas and me. I
> suppose it's good to send PR now?
>

Yes
I was on Ching-Ming festival last week.
After re-sync to master and travis verification.
I will send a PR right away.

Thanks
Rick

> Regards,
> Bin