From: Bin Meng <bmeng.cn@gmail.com> To: Kito Cheng <kito.cheng@sifive.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, frank.chang@sifive.com, Richard Henderson <richard.henderson@linaro.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com> Subject: Re: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V Date: Tue, 6 Jul 2021 13:51:01 +0800 [thread overview] Message-ID: <CAEUhbmWxsKV26wN2viPVtTLfWsbZHEghM-nGJePH7qROEp7MFg@mail.gmail.com> (raw) In-Reply-To: <20210706035015.122899-1-kito.cheng@sifive.com> On Tue, Jul 6, 2021 at 11:50 AM Kito Cheng <kito.cheng@sifive.com> wrote: > > Set I, M, A, F, D and C bit for hwcap if misa is set. > > V3 Changes: > - Simplify logic of getting hwcap. > > V2 Changes: > - Only set imafdc bits, sync with upstream linux kernel. These changelogs should not be in the commit message, but should be put below --- > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > --- > linux-user/elfload.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 598ab8aa13..42ef2a1148 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, > #define ELF_CLASS ELFCLASS64 > #endif > > +#define ELF_HWCAP get_elf_hwcap() > + > +static uint32_t get_elf_hwcap(void) > +{ > +#define MISA_BIT(EXT) (1 << (EXT - 'A')) > + RISCVCPU *cpu = RISCV_CPU(thread_cpu); > + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') > + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); > + > + return cpu->env.misa & mask; > +#undef MISA_BIT > +} > + > static inline void init_thread(struct target_pt_regs *regs, > struct image_info *infop) > { Regards, Bin
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com> To: Kito Cheng <kito.cheng@sifive.com> Cc: Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, frank.chang@sifive.com, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Richard Henderson <richard.henderson@linaro.org> Subject: Re: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V Date: Tue, 6 Jul 2021 13:51:01 +0800 [thread overview] Message-ID: <CAEUhbmWxsKV26wN2viPVtTLfWsbZHEghM-nGJePH7qROEp7MFg@mail.gmail.com> (raw) In-Reply-To: <20210706035015.122899-1-kito.cheng@sifive.com> On Tue, Jul 6, 2021 at 11:50 AM Kito Cheng <kito.cheng@sifive.com> wrote: > > Set I, M, A, F, D and C bit for hwcap if misa is set. > > V3 Changes: > - Simplify logic of getting hwcap. > > V2 Changes: > - Only set imafdc bits, sync with upstream linux kernel. These changelogs should not be in the commit message, but should be put below --- > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > --- > linux-user/elfload.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 598ab8aa13..42ef2a1148 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, > #define ELF_CLASS ELFCLASS64 > #endif > > +#define ELF_HWCAP get_elf_hwcap() > + > +static uint32_t get_elf_hwcap(void) > +{ > +#define MISA_BIT(EXT) (1 << (EXT - 'A')) > + RISCVCPU *cpu = RISCV_CPU(thread_cpu); > + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') > + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); > + > + return cpu->env.misa & mask; > +#undef MISA_BIT > +} > + > static inline void init_thread(struct target_pt_regs *regs, > struct image_info *infop) > { Regards, Bin
next prev parent reply other threads:[~2021-07-06 5:52 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-06 3:50 [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V Kito Cheng 2021-07-06 4:42 ` Richard Henderson 2021-07-06 5:51 ` Bin Meng [this message] 2021-07-06 5:51 ` Bin Meng 2021-07-07 19:15 ` Laurent Vivier
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=CAEUhbmWxsKV26wN2viPVtTLfWsbZHEghM-nGJePH7qROEp7MFg@mail.gmail.com \ --to=bmeng.cn@gmail.com \ --cc=alistair.francis@wdc.com \ --cc=frank.chang@sifive.com \ --cc=kito.cheng@sifive.com \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ --cc=richard.henderson@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.