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From: Frank Chang <frank.chang@sifive.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
Date: Wed, 24 Feb 2021 08:43:48 +0800	[thread overview]
Message-ID: <CAE_xrPiU0kL5nkcL3RbRSNyRv1FCVYk1pOVXp_rVFFB8dhaMCg@mail.gmail.com> (raw)
In-Reply-To: <500b1f4a-1fe8-9e4f-cdee-2c2b35a53edb@linaro.org>

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On Wed, Feb 24, 2021 at 2:24 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 2/23/21 12:19 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> > commit: c445593, but other TB_FLAGS bits for rvv and rvh were
> > not shift as well so these bits may overlap with each other when
> > rvv is enabled.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> > -#define TB_FLAGS_MMU_MASK   7
> >  #define TB_FLAGS_PRIV_MMU_MASK                3
> >  #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
> >  #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> ...
> > +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
> > +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
> > +FIELD(TB_FLAGS, LMUL, 4, 2)
> > +FIELD(TB_FLAGS, SEW, 6, 3)
> > +FIELD(TB_FLAGS, VILL, 9, 1)
> >  /* Is a Hypervisor instruction load/store allowed? */
> > -FIELD(TB_FLAGS, HLSX, 9, 1)
> > +FIELD(TB_FLAGS, HLSX, 10, 1)
>
> The only other thing that I'd add at this point is a comment about
> MSTATUS_FS
> -- a 2-bit field at bit 13 -- for the benefit of the next person that adds
> something to TB_FLAGS.
>
>
In fact, in RVV patchset, both MSTATUS_FS and MSTATUS_VS are skipped
and I also add the comments to state that.
The bits are also rearranged to fill the empty bit holes in RVV patchset on
my local branch:

  FIELD(TB_FLAGS, MEM_IDX, 0, 3)
  FIELD(TB_FLAGS, LMUL, 3, 3)
  FIELD(TB_FLAGS, SEW, 6, 3)
  /* Skip MSTATUS_VS (0x600) bits */
  FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
  FIELD(TB_FLAGS, VILL, 12, 1)
  /* Skip MSTATUS_FS (0x6000) bits */
  /* Is a Hypervisor instruction load/store allowed? */
  FIELD(TB_FLAGS, HLSX, 15, 1)

Thanks for the review.
Frank Chang


>
> r~
>

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WARNING: multiple messages have this Message-ID (diff)
From: Frank Chang <frank.chang@sifive.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Sagar Karandikar <sagark@eecs.berkeley.edu>,
	 Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: Re: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
Date: Wed, 24 Feb 2021 08:43:48 +0800	[thread overview]
Message-ID: <CAE_xrPiU0kL5nkcL3RbRSNyRv1FCVYk1pOVXp_rVFFB8dhaMCg@mail.gmail.com> (raw)
In-Reply-To: <500b1f4a-1fe8-9e4f-cdee-2c2b35a53edb@linaro.org>

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On Wed, Feb 24, 2021 at 2:24 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 2/23/21 12:19 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> > commit: c445593, but other TB_FLAGS bits for rvv and rvh were
> > not shift as well so these bits may overlap with each other when
> > rvv is enabled.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> > -#define TB_FLAGS_MMU_MASK   7
> >  #define TB_FLAGS_PRIV_MMU_MASK                3
> >  #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
> >  #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> ...
> > +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
> > +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
> > +FIELD(TB_FLAGS, LMUL, 4, 2)
> > +FIELD(TB_FLAGS, SEW, 6, 3)
> > +FIELD(TB_FLAGS, VILL, 9, 1)
> >  /* Is a Hypervisor instruction load/store allowed? */
> > -FIELD(TB_FLAGS, HLSX, 9, 1)
> > +FIELD(TB_FLAGS, HLSX, 10, 1)
>
> The only other thing that I'd add at this point is a comment about
> MSTATUS_FS
> -- a 2-bit field at bit 13 -- for the benefit of the next person that adds
> something to TB_FLAGS.
>
>
In fact, in RVV patchset, both MSTATUS_FS and MSTATUS_VS are skipped
and I also add the comments to state that.
The bits are also rearranged to fill the empty bit holes in RVV patchset on
my local branch:

  FIELD(TB_FLAGS, MEM_IDX, 0, 3)
  FIELD(TB_FLAGS, LMUL, 3, 3)
  FIELD(TB_FLAGS, SEW, 6, 3)
  /* Skip MSTATUS_VS (0x600) bits */
  FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
  FIELD(TB_FLAGS, VILL, 12, 1)
  /* Skip MSTATUS_FS (0x6000) bits */
  /* Is a Hypervisor instruction load/store allowed? */
  FIELD(TB_FLAGS, HLSX, 15, 1)

Thanks for the review.
Frank Chang


>
> r~
>

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  reply	other threads:[~2021-02-24  0:45 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-23  8:19 [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang
2021-02-23  8:19 ` frank.chang
2021-02-23 18:24 ` Richard Henderson
2021-02-23 18:24   ` Richard Henderson
2021-02-24  0:43   ` Frank Chang [this message]
2021-02-24  0:43     ` Frank Chang

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