* [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
@ 2021-02-23 8:19 ` frank.chang
0 siblings, 0 replies; 6+ messages in thread
From: frank.chang @ 2021-02-23 8:19 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 12 ++++++------
target/riscv/translate.c | 2 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb4..116b16b9362 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -370,7 +370,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 7
#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
@@ -379,12 +378,13 @@ typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
-FIELD(TB_FLAGS, LMUL, 3, 2)
-FIELD(TB_FLAGS, SEW, 5, 3)
-FIELD(TB_FLAGS, VILL, 8, 1)
+FIELD(TB_FLAGS, MEM_IDX, 0, 3)
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
+FIELD(TB_FLAGS, LMUL, 4, 2)
+FIELD(TB_FLAGS, SEW, 6, 3)
+FIELD(TB_FLAGS, VILL, 9, 1)
/* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, HLSX, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0f28b5f41e4..9b518cdff46 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -802,7 +802,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
uint32_t tb_flags = ctx->base.tb->flags;
ctx->pc_succ_insn = ctx->base.pc_first;
- ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
+ ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
#if !defined(CONFIG_USER_ONLY)
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
@ 2021-02-23 8:19 ` frank.chang
0 siblings, 0 replies; 6+ messages in thread
From: frank.chang @ 2021-02-23 8:19 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 12 ++++++------
target/riscv/translate.c | 2 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb4..116b16b9362 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -370,7 +370,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 7
#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
@@ -379,12 +378,13 @@ typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
-FIELD(TB_FLAGS, LMUL, 3, 2)
-FIELD(TB_FLAGS, SEW, 5, 3)
-FIELD(TB_FLAGS, VILL, 8, 1)
+FIELD(TB_FLAGS, MEM_IDX, 0, 3)
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
+FIELD(TB_FLAGS, LMUL, 4, 2)
+FIELD(TB_FLAGS, SEW, 6, 3)
+FIELD(TB_FLAGS, VILL, 9, 1)
/* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, HLSX, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0f28b5f41e4..9b518cdff46 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -802,7 +802,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
uint32_t tb_flags = ctx->base.tb->flags;
ctx->pc_succ_insn = ctx->base.pc_first;
- ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
+ ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
#if !defined(CONFIG_USER_ONLY)
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
2021-02-23 8:19 ` frank.chang
@ 2021-02-23 18:24 ` Richard Henderson
-1 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2021-02-23 18:24 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann
On 2/23/21 12:19 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> commit: c445593, but other TB_FLAGS bits for rvv and rvh were
> not shift as well so these bits may overlap with each other when
> rvv is enabled.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> -#define TB_FLAGS_MMU_MASK 7
> #define TB_FLAGS_PRIV_MMU_MASK 3
> #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
...
> +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
> +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
> +FIELD(TB_FLAGS, LMUL, 4, 2)
> +FIELD(TB_FLAGS, SEW, 6, 3)
> +FIELD(TB_FLAGS, VILL, 9, 1)
> /* Is a Hypervisor instruction load/store allowed? */
> -FIELD(TB_FLAGS, HLSX, 9, 1)
> +FIELD(TB_FLAGS, HLSX, 10, 1)
The only other thing that I'd add at this point is a comment about MSTATUS_FS
-- a 2-bit field at bit 13 -- for the benefit of the next person that adds
something to TB_FLAGS.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
@ 2021-02-23 18:24 ` Richard Henderson
0 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2021-02-23 18:24 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, Sagar Karandikar, Bastian Koppelmann
On 2/23/21 12:19 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> commit: c445593, but other TB_FLAGS bits for rvv and rvh were
> not shift as well so these bits may overlap with each other when
> rvv is enabled.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> -#define TB_FLAGS_MMU_MASK 7
> #define TB_FLAGS_PRIV_MMU_MASK 3
> #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
...
> +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
> +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
> +FIELD(TB_FLAGS, LMUL, 4, 2)
> +FIELD(TB_FLAGS, SEW, 6, 3)
> +FIELD(TB_FLAGS, VILL, 9, 1)
> /* Is a Hypervisor instruction load/store allowed? */
> -FIELD(TB_FLAGS, HLSX, 9, 1)
> +FIELD(TB_FLAGS, HLSX, 10, 1)
The only other thing that I'd add at this point is a comment about MSTATUS_FS
-- a 2-bit field at bit 13 -- for the benefit of the next person that adds
something to TB_FLAGS.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
2021-02-23 18:24 ` Richard Henderson
@ 2021-02-24 0:43 ` Frank Chang
-1 siblings, 0 replies; 6+ messages in thread
From: Frank Chang @ 2021-02-24 0:43 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
[-- Attachment #1: Type: text/plain, Size: 1799 bytes --]
On Wed, Feb 24, 2021 at 2:24 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 2/23/21 12:19 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> > commit: c445593, but other TB_FLAGS bits for rvv and rvh were
> > not shift as well so these bits may overlap with each other when
> > rvv is enabled.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> > -#define TB_FLAGS_MMU_MASK 7
> > #define TB_FLAGS_PRIV_MMU_MASK 3
> > #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
> > #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> ...
> > +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
> > +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
> > +FIELD(TB_FLAGS, LMUL, 4, 2)
> > +FIELD(TB_FLAGS, SEW, 6, 3)
> > +FIELD(TB_FLAGS, VILL, 9, 1)
> > /* Is a Hypervisor instruction load/store allowed? */
> > -FIELD(TB_FLAGS, HLSX, 9, 1)
> > +FIELD(TB_FLAGS, HLSX, 10, 1)
>
> The only other thing that I'd add at this point is a comment about
> MSTATUS_FS
> -- a 2-bit field at bit 13 -- for the benefit of the next person that adds
> something to TB_FLAGS.
>
>
In fact, in RVV patchset, both MSTATUS_FS and MSTATUS_VS are skipped
and I also add the comments to state that.
The bits are also rearranged to fill the empty bit holes in RVV patchset on
my local branch:
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
FIELD(TB_FLAGS, LMUL, 3, 3)
FIELD(TB_FLAGS, SEW, 6, 3)
/* Skip MSTATUS_VS (0x600) bits */
FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
FIELD(TB_FLAGS, VILL, 12, 1)
/* Skip MSTATUS_FS (0x6000) bits */
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 15, 1)
Thanks for the review.
Frank Chang
>
> r~
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
@ 2021-02-24 0:43 ` Frank Chang
0 siblings, 0 replies; 6+ messages in thread
From: Frank Chang @ 2021-02-24 0:43 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
[-- Attachment #1: Type: text/plain, Size: 1799 bytes --]
On Wed, Feb 24, 2021 at 2:24 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 2/23/21 12:19 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> > commit: c445593, but other TB_FLAGS bits for rvv and rvh were
> > not shift as well so these bits may overlap with each other when
> > rvv is enabled.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> > -#define TB_FLAGS_MMU_MASK 7
> > #define TB_FLAGS_PRIV_MMU_MASK 3
> > #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
> > #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> ...
> > +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
> > +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
> > +FIELD(TB_FLAGS, LMUL, 4, 2)
> > +FIELD(TB_FLAGS, SEW, 6, 3)
> > +FIELD(TB_FLAGS, VILL, 9, 1)
> > /* Is a Hypervisor instruction load/store allowed? */
> > -FIELD(TB_FLAGS, HLSX, 9, 1)
> > +FIELD(TB_FLAGS, HLSX, 10, 1)
>
> The only other thing that I'd add at this point is a comment about
> MSTATUS_FS
> -- a 2-bit field at bit 13 -- for the benefit of the next person that adds
> something to TB_FLAGS.
>
>
In fact, in RVV patchset, both MSTATUS_FS and MSTATUS_VS are skipped
and I also add the comments to state that.
The bits are also rearranged to fill the empty bit holes in RVV patchset on
my local branch:
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
FIELD(TB_FLAGS, LMUL, 3, 3)
FIELD(TB_FLAGS, SEW, 6, 3)
/* Skip MSTATUS_VS (0x600) bits */
FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
FIELD(TB_FLAGS, VILL, 12, 1)
/* Skip MSTATUS_FS (0x6000) bits */
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 15, 1)
Thanks for the review.
Frank Chang
>
> r~
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-02-24 0:45 UTC | newest]
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2021-02-23 8:19 [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang
2021-02-23 8:19 ` frank.chang
2021-02-23 18:24 ` Richard Henderson
2021-02-23 18:24 ` Richard Henderson
2021-02-24 0:43 ` Frank Chang
2021-02-24 0:43 ` Frank Chang
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