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From: Daniel Baluta <daniel.baluta@gmail.com>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Daniel Baluta <daniel.baluta@nxp.com>,
	Linux-ALSA <alsa-devel@alsa-project.org>,
	Viorel Suman <viorel.suman@nxp.com>,
	Timur Tabi <timur@kernel.org>, Xiubo Li <Xiubo.Lee@gmail.com>,
	linuxppc-dev@lists.ozlabs.org,
	"S.j. Wang" <shengjiu.wang@nxp.com>,
	"Angus Ainslie (Purism)" <angus@akkea.ca>,
	Takashi Iwai <tiwai@suse.com>, Mark Brown <broonie@kernel.org>,
	dl-linux-imx <linux-imx@nxp.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Lucas Stach <l.stach@pengutronix.de>
Subject: Re: [alsa-devel] [PATCH 09/10] ASoC: fsl_sai: Add support for SAI new version
Date: Thu, 25 Jul 2019 09:06:28 +0300	[thread overview]
Message-ID: <CAEnQRZC+5OWwBJfifjeD_8zD3z9efdNMb4Ey0P1Ka+y63v-XNA@mail.gmail.com> (raw)
In-Reply-To: <20190724233212.GD6859@Asurada-Nvidia.nvidia.com>

On Thu, Jul 25, 2019 at 2:32 AM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
>
> On Mon, Jul 22, 2019 at 03:48:32PM +0300, Daniel Baluta wrote:
> > New IP version introduces Version ID and Parameter registers
> > and optionally added Timestamp feature.
> >
> > VERID and PARAM registers are placed at the top of registers
> > address space and some registers are shifted according to
> > the following table:
> >
> > Tx/Rx data registers and Tx/Rx FIFO registers keep their
> > addresses, all other registers are shifted by 8.
>
> Feels like Lucas's approach is neater. I saw that Register TMR
> at 0x60 is exceptional during your previous discussion. So can
> we apply an offset-cancellation for it exceptionally? I haven't
> checked all the registers so this would look okay to me as well
> if there are more than just Register TMR.

It is not just TMR exceptional. There are like half of the registers.
Thus: half of the registers need to be shifted and half of them
need to stay the same as in previous version of SAI.

I'm not seeing yet a neater approach. Lucas idea would somehow
work if regmap will allow some sort of translation function applied
over registers before being accessed.

Maybe Mark has some clues here?

thanks,
daniel.

WARNING: multiple messages have this Message-ID (diff)
From: Daniel Baluta <daniel.baluta@gmail.com>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Linux-ALSA <alsa-devel@alsa-project.org>,
	Fabio Estevam <festevam@gmail.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Timur Tabi <timur@kernel.org>, Xiubo Li <Xiubo.Lee@gmail.com>,
	Daniel Baluta <daniel.baluta@nxp.com>,
	"S.j. Wang" <shengjiu.wang@nxp.com>,
	"Angus Ainslie \(Purism\)" <angus@akkea.ca>,
	Takashi Iwai <tiwai@suse.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Mark Brown <broonie@kernel.org>, dl-linux-imx <linux-imx@nxp.com>,
	Viorel Suman <viorel.suman@nxp.com>,
	linuxppc-dev@lists.ozlabs.org,
	Lucas Stach <l.stach@pengutronix.de>
Subject: Re: [alsa-devel] [PATCH 09/10] ASoC: fsl_sai: Add support for SAI new version
Date: Thu, 25 Jul 2019 09:06:28 +0300	[thread overview]
Message-ID: <CAEnQRZC+5OWwBJfifjeD_8zD3z9efdNMb4Ey0P1Ka+y63v-XNA@mail.gmail.com> (raw)
In-Reply-To: <20190724233212.GD6859@Asurada-Nvidia.nvidia.com>

On Thu, Jul 25, 2019 at 2:32 AM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
>
> On Mon, Jul 22, 2019 at 03:48:32PM +0300, Daniel Baluta wrote:
> > New IP version introduces Version ID and Parameter registers
> > and optionally added Timestamp feature.
> >
> > VERID and PARAM registers are placed at the top of registers
> > address space and some registers are shifted according to
> > the following table:
> >
> > Tx/Rx data registers and Tx/Rx FIFO registers keep their
> > addresses, all other registers are shifted by 8.
>
> Feels like Lucas's approach is neater. I saw that Register TMR
> at 0x60 is exceptional during your previous discussion. So can
> we apply an offset-cancellation for it exceptionally? I haven't
> checked all the registers so this would look okay to me as well
> if there are more than just Register TMR.

It is not just TMR exceptional. There are like half of the registers.
Thus: half of the registers need to be shifted and half of them
need to stay the same as in previous version of SAI.

I'm not seeing yet a neater approach. Lucas idea would somehow
work if regmap will allow some sort of translation function applied
over registers before being accessed.

Maybe Mark has some clues here?

thanks,
daniel.

  reply	other threads:[~2019-07-25  6:06 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-22 12:48 [PATCH 00/10] Add support for new SAI IP version Daniel Baluta
2019-07-22 12:48 ` Daniel Baluta
2019-07-22 12:48 ` [PATCH 01/10] ASoC: fsl_sai: add of_match data Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-23 17:00   ` Mark Brown
2019-07-23 17:00     ` Mark Brown
2019-07-24  6:42     ` [alsa-devel] " Daniel Baluta
2019-07-24  6:42       ` Daniel Baluta
2019-07-24 22:34   ` Nicolin Chen
2019-07-24 22:34     ` Nicolin Chen
2019-07-25  6:00     ` [alsa-devel] " Daniel Baluta
2019-07-25  6:00       ` Daniel Baluta
2019-07-25  6:00       ` Daniel Baluta
2019-07-22 12:48 ` [PATCH 02/10] ASoC: fsl_sai: derive TX FIFO watermark from FIFO depth Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-22 12:48 ` [PATCH 03/10] ASoC: fsl_sai: Add registers definition for multiple datalines Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-22 12:48 ` [PATCH 04/10] ASoC: fsl_sai: Update Tx/Rx channel enable mask Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-22 12:48 ` [PATCH 05/10] ASoC: fsl_sai: Add support to enable multiple data lines Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-22 12:55   ` Lucas Stach
2019-07-22 12:55     ` Lucas Stach
2019-07-24  8:58     ` [alsa-devel] " Daniel Baluta
2019-07-24  8:58       ` Daniel Baluta
2019-07-22 12:48 ` [PATCH 06/10] ASoC: dt-bindings: Document dl_mask property Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-22 12:56   ` Lucas Stach
2019-07-22 12:56     ` Lucas Stach
2019-07-24 23:13   ` Nicolin Chen
2019-07-24 23:13     ` Nicolin Chen
2019-07-24 23:13     ` Nicolin Chen
2019-07-25  6:08     ` [alsa-devel] " Daniel Baluta
2019-07-25  6:08       ` Daniel Baluta
2019-07-25  6:08       ` Daniel Baluta
2019-07-22 12:48 ` [PATCH 07/10] ASoC: fsl_sai: Add support for FIFO combine mode Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-22 13:01   ` Lucas Stach
2019-07-22 13:01     ` Lucas Stach
2019-07-22 12:48 ` [PATCH 08/10] ASoC: dt-bindings: Document fcomb_mode property Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-24 23:22   ` Nicolin Chen
2019-07-24 23:22     ` Nicolin Chen
2019-07-25  6:02     ` [alsa-devel] " Daniel Baluta
2019-07-25  6:02       ` Daniel Baluta
2019-07-25 17:39       ` Nicolin Chen
2019-07-25 17:39         ` Nicolin Chen
2019-07-25 17:39         ` Nicolin Chen
2019-07-22 12:48 ` [PATCH 09/10] ASoC: fsl_sai: Add support for SAI new version Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-24 23:32   ` Nicolin Chen
2019-07-24 23:32     ` Nicolin Chen
2019-07-25  6:06     ` Daniel Baluta [this message]
2019-07-25  6:06       ` [alsa-devel] " Daniel Baluta
2019-07-22 12:48 ` [PATCH 10/10] ASoC: fsl_sai: Add support for imx7ulp/imx8mq Daniel Baluta
2019-07-22 12:48   ` Daniel Baluta
2019-07-22 13:04   ` Lucas Stach
2019-07-22 13:04     ` Lucas Stach

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