From: Rob Clark <robdclark@gmail.com> To: Sharat Masetty <smasetty@codeaurora.org>, freedreno <freedreno@lists.freedesktop.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, dri-devel@freedesktop.org, linux-arm-msm <linux-arm-msm@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Georgi Djakov <georgi.djakov@linaro.org>, Matthias Kaehlcke <mka@chromium.org> Subject: Re: [Freedreno] [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth Date: Mon, 18 May 2020 09:25:41 -0700 [thread overview] Message-ID: <CAF6AEGtoNwUGX-r7QytGn5hSU-VD4RJZyhcb3WdgAgAFR5BK4A@mail.gmail.com> (raw) In-Reply-To: <20200518142333.GA10796@jcrouse1-lnx.qualcomm.com> On Mon, May 18, 2020 at 7:23 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote: > > This patches replaces the previously used static DDR vote and uses > > dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling > > GPU frequency. > > > > Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> > > --- > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +----- > > 1 file changed, 1 insertion(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > index 2d8124b..79433d3 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > @@ -141,11 +141,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) > > > > gmu->freq = gmu->gpu_freqs[perf_index]; > > > > - /* > > - * Eventually we will want to scale the path vote with the frequency but > > - * for now leave it at max so that the performance is nominal. > > - */ > > - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); > > + dev_pm_opp_set_bw(&gpu->pdev->dev, opp); > > } > > This adds an implicit requirement that all targets need bandwidth settings > defined in the OPP or they won't get a bus vote at all. I would prefer that > there be an default escape valve but if not you'll need to add > bandwidth values for the sdm845 OPP that target doesn't regress. > it looks like we could maybe do something like: ret = dev_pm_opp_set_bw(...); if (ret) { dev_warn_once(dev, "no bandwidth settings"); icc_set_bw(...); } ? BR, -R > Jordan > > > unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) > > -- > > 2.7.4 > > > > -- > The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno
WARNING: multiple messages have this Message-ID (diff)
From: Rob Clark <robdclark@gmail.com> To: Sharat Masetty <smasetty@codeaurora.org>, freedreno <freedreno@lists.freedesktop.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, dri-devel@freedesktop.org, linux-arm-msm <linux-arm-msm@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Georgi Djakov <georgi.djakov@linaro.org>, Matthias Kaehlcke <mka@chromium.org> Subject: Re: [Freedreno] [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth Date: Mon, 18 May 2020 09:25:41 -0700 [thread overview] Message-ID: <CAF6AEGtoNwUGX-r7QytGn5hSU-VD4RJZyhcb3WdgAgAFR5BK4A@mail.gmail.com> (raw) In-Reply-To: <20200518142333.GA10796@jcrouse1-lnx.qualcomm.com> On Mon, May 18, 2020 at 7:23 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote: > > This patches replaces the previously used static DDR vote and uses > > dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling > > GPU frequency. > > > > Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> > > --- > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +----- > > 1 file changed, 1 insertion(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > index 2d8124b..79433d3 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > @@ -141,11 +141,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) > > > > gmu->freq = gmu->gpu_freqs[perf_index]; > > > > - /* > > - * Eventually we will want to scale the path vote with the frequency but > > - * for now leave it at max so that the performance is nominal. > > - */ > > - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); > > + dev_pm_opp_set_bw(&gpu->pdev->dev, opp); > > } > > This adds an implicit requirement that all targets need bandwidth settings > defined in the OPP or they won't get a bus vote at all. I would prefer that > there be an default escape valve but if not you'll need to add > bandwidth values for the sdm845 OPP that target doesn't regress. > it looks like we could maybe do something like: ret = dev_pm_opp_set_bw(...); if (ret) { dev_warn_once(dev, "no bandwidth settings"); icc_set_bw(...); } ? BR, -R > Jordan > > > unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) > > -- > > 2.7.4 > > > > -- > The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-05-18 16:25 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-14 10:54 [PATCH 0/6] Add support for GPU DDR BW scaling Sharat Masetty 2020-05-14 10:54 ` Sharat Masetty 2020-05-14 10:54 ` [PATCH 1/6] arm64: dts: qcom: sc7180: Add interconnect bindings for GPU Sharat Masetty 2020-05-14 10:54 ` Sharat Masetty 2020-05-14 23:37 ` Matthias Kaehlcke 2020-05-14 23:37 ` Matthias Kaehlcke 2020-05-14 10:54 ` [PATCH 2/6] arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp Sharat Masetty 2020-05-14 10:54 ` Sharat Masetty 2020-05-14 23:45 ` Matthias Kaehlcke 2020-05-14 23:45 ` Matthias Kaehlcke 2020-05-14 10:54 ` [PATCH 3/6] OPP: Add and export helper to set bandwidth Sharat Masetty 2020-05-14 10:54 ` Sharat Masetty 2020-05-15 0:32 ` Matthias Kaehlcke 2020-05-15 0:32 ` Matthias Kaehlcke 2020-05-14 10:54 ` [PATCH 4/6] drm: msm: a6xx: send opp instead of a frequency Sharat Masetty 2020-05-14 10:54 ` Sharat Masetty 2020-05-15 0:39 ` Matthias Kaehlcke 2020-05-15 0:39 ` Matthias Kaehlcke 2020-05-15 0:58 ` Matthias Kaehlcke 2020-05-15 0:58 ` Matthias Kaehlcke 2020-05-14 10:54 ` [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth Sharat Masetty 2020-05-14 10:54 ` Sharat Masetty 2020-05-15 1:05 ` Matthias Kaehlcke 2020-05-15 1:05 ` Matthias Kaehlcke 2020-05-18 14:23 ` Jordan Crouse 2020-05-18 14:23 ` Jordan Crouse 2020-05-18 16:25 ` Rob Clark [this message] 2020-05-18 16:25 ` [Freedreno] " Rob Clark 2020-05-27 8:47 ` Sharat Masetty 2020-05-27 8:47 ` Sharat Masetty 2020-05-27 15:38 ` Rob Clark 2020-05-27 15:38 ` Rob Clark 2020-05-27 17:31 ` Saravana Kannan 2020-05-27 17:31 ` Saravana Kannan 2020-05-27 20:41 ` Sibi Sankar 2020-05-27 20:41 ` Sibi Sankar 2020-05-27 20:51 ` Jordan Crouse 2020-05-27 20:51 ` Jordan Crouse 2020-05-28 11:02 ` Sharat Masetty 2020-05-28 11:02 ` Sharat Masetty 2020-05-14 10:54 ` [PATCH 6/6] dt-bindings: drm/msm/gpu: Document gpu opp table Sharat Masetty 2020-05-14 10:54 ` Sharat Masetty 2020-05-28 15:14 ` Rob Herring 2020-05-28 15:14 ` Rob Herring 2020-05-14 23:56 ` [PATCH 0/6] Add support for GPU DDR BW scaling Matthias Kaehlcke 2020-05-14 23:56 ` Matthias Kaehlcke
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