[PATCH v7 0/6] arm64: dts: Add sdm845 GPU/GMU and SMMU

[PATCH v7 0/6] arm64: dts: Add sdm845 GPU/GMU and SMMU

[Jordan Crouse]

Now that more of the sdm845 bindings are headed upstream this a refresh of
of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes
for the GPU/GMU and GPU SMMU for sdm845. v7 of this patchset also removes
interrupt-names from the driver and the existing DT changes per feedback from
Rob Herring.

This is based on :
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next

with:
https://lore.kernel.org/patchwork/patch/1018365/

This change requires the following dependencies:

include/dt-bindings/power/qcom-rpmpd.h:
https://patchwork.kernel.org/patch/10711119/

qcom,smmu-v2 binding:
https://patchwork.kernel.org/patch/10581911/

v7: Add patches to remove interrupt-names, add version specific compatible
    string for gmu
v6: Update GPU bindings for a6xx and make the examples match the nodes and vice
 versa.  Clean up types and rebase on
 https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging.
v5: Use symbolic names for the RPMH power levels defined in OPP table,
 move the opp tables as children of their respective nodes and rename
 the iommu device.
v4: Rebase
v3: Split GMU PDC region into two GPU specific sections, fix indentation,
  really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
  change gmu phandle to qcom,gmu per Rob

Jordan Crouse (6):
  drm/msm/gpu: Remove hardcoded interrupt name
  drm/msm: drop interrupt-names
  ARM: dts: qcom: Removed unused interrupt-names from GPU node
  arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU
  dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
  arm64: dts: sdm845: Add gpu and gmu device nodes

 .../devicetree/bindings/display/msm/gmu.txt   |  59 +++++++++
 .../devicetree/bindings/display/msm/gpu.txt   |  43 +++++-
 arch/arm/boot/dts/qcom-apq8064.dtsi           |   1 -
 arch/arm64/boot/dts/qcom/msm8916.dtsi         |   1 -
 arch/arm64/boot/dts/qcom/sdm845.dtsi          | 122 ++++++++++++++++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c       |   1 -
 drivers/gpu/drm/msm/msm_gpu.c                 |   2 +-
 drivers/gpu/drm/msm/msm_gpu.h                 |   1 -
 8 files changed, 221 insertions(+), 9 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt

-- 
2.18.0

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[PATCH v7 0/6] arm64: dts: Add sdm845 GPU/GMU and SMMU

[Jordan Crouse]

Now that more of the sdm845 bindings are headed upstream this a refresh of
of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes
for the GPU/GMU and GPU SMMU for sdm845. v7 of this patchset also removes
interrupt-names from the driver and the existing DT changes per feedback from
Rob Herring.

This is based on :
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next

with:
https://lore.kernel.org/patchwork/patch/1018365/

This change requires the following dependencies:

include/dt-bindings/power/qcom-rpmpd.h:
https://patchwork.kernel.org/patch/10711119/

qcom,smmu-v2 binding:
https://patchwork.kernel.org/patch/10581911/

v7: Add patches to remove interrupt-names, add version specific compatible
    string for gmu
v6: Update GPU bindings for a6xx and make the examples match the nodes and vice
 versa.  Clean up types and rebase on
 https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging.
v5: Use symbolic names for the RPMH power levels defined in OPP table,
 move the opp tables as children of their respective nodes and rename
 the iommu device.
v4: Rebase
v3: Split GMU PDC region into two GPU specific sections, fix indentation,
  really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
  change gmu phandle to qcom,gmu per Rob

Jordan Crouse (6):
  drm/msm/gpu: Remove hardcoded interrupt name
  drm/msm: drop interrupt-names
  ARM: dts: qcom: Removed unused interrupt-names from GPU node
  arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU
  dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
  arm64: dts: sdm845: Add gpu and gmu device nodes

 .../devicetree/bindings/display/msm/gmu.txt   |  59 +++++++++
 .../devicetree/bindings/display/msm/gpu.txt   |  43 +++++-
 arch/arm/boot/dts/qcom-apq8064.dtsi           |   1 -
 arch/arm64/boot/dts/qcom/msm8916.dtsi         |   1 -
 arch/arm64/boot/dts/qcom/sdm845.dtsi          | 122 ++++++++++++++++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c       |   1 -
 drivers/gpu/drm/msm/msm_gpu.c                 |   2 +-
 drivers/gpu/drm/msm/msm_gpu.h                 |   1 -
 8 files changed, 221 insertions(+), 9 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt

-- 
2.18.0


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[PATCH v7 1/6] drm/msm/gpu: Remove hardcoded interrupt name

[Jordan Crouse]

Every GPU core only has one interrupt so there isn't any
value in looking up the interrupt by name. Remove the name (which
is legacy anyway) and use platform_get_irq() instead.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 -
 drivers/gpu/drm/msm/msm_gpu.c           | 2 +-
 drivers/gpu/drm/msm/msm_gpu.h           | 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 93d70f4a2154..bfeea50fca8a 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -713,7 +713,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 	adreno_gpu->rev = config->rev;
 
 	adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
-	adreno_gpu_config.irqname = "kgsl_3d0_irq";
 
 	adreno_gpu_config.va_start = SZ_16M;
 	adreno_gpu_config.va_end = 0xffffffff;
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 11aac8337066..f9de09d14344 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -868,7 +868,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 	}
 
 	/* Get Interrupt: */
-	gpu->irq = platform_get_irq_byname(pdev, config->irqname);
+	gpu->irq = platform_get_irq(pdev, 0);
 	if (gpu->irq < 0) {
 		ret = gpu->irq;
 		dev_err(drm->dev, "failed to get irq: %d\n", ret);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index f82bac086666..fc4040e24a6b 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -31,7 +31,6 @@ struct msm_gpu_state;
 
 struct msm_gpu_config {
 	const char *ioname;
-	const char *irqname;
 	uint64_t va_start;
 	uint64_t va_end;
 	unsigned int nr_rings;
-- 
2.18.0

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[PATCH v7 1/6] drm/msm/gpu: Remove hardcoded interrupt name

[Jordan Crouse]

Every GPU core only has one interrupt so there isn't any
value in looking up the interrupt by name. Remove the name (which
is legacy anyway) and use platform_get_irq() instead.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 -
 drivers/gpu/drm/msm/msm_gpu.c           | 2 +-
 drivers/gpu/drm/msm/msm_gpu.h           | 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 93d70f4a2154..bfeea50fca8a 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -713,7 +713,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 	adreno_gpu->rev = config->rev;
 
 	adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
-	adreno_gpu_config.irqname = "kgsl_3d0_irq";
 
 	adreno_gpu_config.va_start = SZ_16M;
 	adreno_gpu_config.va_end = 0xffffffff;
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 11aac8337066..f9de09d14344 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -868,7 +868,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 	}
 
 	/* Get Interrupt: */
-	gpu->irq = platform_get_irq_byname(pdev, config->irqname);
+	gpu->irq = platform_get_irq(pdev, 0);
 	if (gpu->irq < 0) {
 		ret = gpu->irq;
 		dev_err(drm->dev, "failed to get irq: %d\n", ret);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index f82bac086666..fc4040e24a6b 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -31,7 +31,6 @@ struct msm_gpu_state;
 
 struct msm_gpu_config {
 	const char *ioname;
-	const char *irqname;
 	uint64_t va_start;
 	uint64_t va_end;
 	unsigned int nr_rings;
-- 
2.18.0


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[PATCH v7 2/6] drm/msm: drop interrupt-names

[Jordan Crouse]

Each GPU core only uses one interrupt so we don't to look up
an interrupt by name and thereby we don't need interrupt-names.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 Documentation/devicetree/bindings/display/msm/gpu.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 43fac0fe09bb..4ad5e70e5c3e 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -25,7 +25,6 @@ Example:
 		reg = <0x04300000 0x20000>;
 		reg-names = "kgsl_3d0_reg_memory";
 		interrupts = <GIC_SPI 80 0>;
-		interrupt-names = "kgsl_3d0_irq";
 		clock-names =
 		    "core",
 		    "iface",
-- 
2.18.0

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[PATCH v7 2/6] drm/msm: drop interrupt-names

[Jordan Crouse]

Each GPU core only uses one interrupt so we don't to look up
an interrupt by name and thereby we don't need interrupt-names.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 Documentation/devicetree/bindings/display/msm/gpu.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 43fac0fe09bb..4ad5e70e5c3e 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -25,7 +25,6 @@ Example:
 		reg = <0x04300000 0x20000>;
 		reg-names = "kgsl_3d0_reg_memory";
 		interrupts = <GIC_SPI 80 0>;
-		interrupt-names = "kgsl_3d0_irq";
 		clock-names =
 		    "core",
 		    "iface",
-- 
2.18.0


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[PATCH v7 3/6] ARM: dts: qcom: Removed unused interrupt-names from GPU node

[Jordan Crouse]

'interrupt-names' shouldn't be used in cases when there is only
one interrupt and it is not otherwise used in the driver.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 48c3cf427610..0a9862729c80 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1186,7 +1186,6 @@
 			reg = <0x04300000 0x20000>;
 			reg-names = "kgsl_3d0_reg_memory";
 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "kgsl_3d0_irq";
 			clock-names =
 			    "core_clk",
 			    "iface_clk",
-- 
2.18.0

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[PATCH v7 3/6] ARM: dts: qcom: Removed unused interrupt-names from GPU node

[Jordan Crouse]

'interrupt-names' shouldn't be used in cases when there is only
one interrupt and it is not otherwise used in the driver.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 48c3cf427610..0a9862729c80 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1186,7 +1186,6 @@
 			reg = <0x04300000 0x20000>;
 			reg-names = "kgsl_3d0_reg_memory";
 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "kgsl_3d0_irq";
 			clock-names =
 			    "core_clk",
 			    "iface_clk",
-- 
2.18.0


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[PATCH v7 4/6] arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU

[Jordan Crouse]

'interrupt-names' shouldn't be used in cases when there is only
one interrupt and it is not otherwise used in the driver.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index c5348c3da5a2..846de1043e4d 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -880,7 +880,6 @@
 			reg = <0x01c00000 0x20000>;
 			reg-names = "kgsl_3d0_reg_memory";
 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "kgsl_3d0_irq";
 			clock-names =
 			    "core",
 			    "iface",
-- 
2.18.0

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[PATCH v7 4/6] arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU

[Jordan Crouse]

'interrupt-names' shouldn't be used in cases when there is only
one interrupt and it is not otherwise used in the driver.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index c5348c3da5a2..846de1043e4d 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -880,7 +880,6 @@
 			reg = <0x01c00000 0x20000>;
 			reg-names = "kgsl_3d0_reg_memory";
 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "kgsl_3d0_irq";
 			clock-names =
 			    "core",
 			    "iface",
-- 
2.18.0


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[PATCH v7 5/6] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

[Jordan Crouse]

Update the GPU bindings and document the new bindings for the GMU
device found with Adreno a6xx targets.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---

v7: Updated the GMU compatible string and clarified details about when clocks
can be optional on the GPU

 .../devicetree/bindings/display/msm/gmu.txt   | 59 +++++++++++++++++++
 .../devicetree/bindings/display/msm/gpu.txt   | 42 ++++++++++++-
 2 files changed, 98 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt

diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt
new file mode 100644
index 000000000000..59e6865898f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
@@ -0,0 +1,59 @@
+Qualcomm adreno/snapdragon GMU (Graphics management unit)
+
+The GMU is a programmable power controller for the GPU. the CPU controls the
+GMU which in turn handles power controls for the GPU.
+
+Required properties:
+- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
+    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
+  Note that you need to list the less specific "qcom,adreno-gmu"
+  for generic matches and the more specific identifier to identify
+  the specific device.
+- reg: Physical base address and length of the GMU registers.
+- reg-names: Matching names for the register regions
+  * "gmu"
+  * "gmu_pdc"
+  * "gmu_pdc_seg"
+- interrupts: The interrupt signals from the GMU.
+- interrupt-names: Matching names for the interrupts
+  * "hfi"
+  * "gmu"
+- clocks: phandles to the device clocks
+- clock-names: Matching names for the clocks
+   * "gmu"
+   * "cxo"
+   * "axi"
+   * "mnoc"
+- power-domains: should be <&clock_gpucc GPU_CX_GDSC>
+- iommus: phandle to the adreno iommu
+- operating-points-v2: phandle to the OPP operating points
+
+Example:
+
+/ {
+	...
+
+	gmu: gmu@506a000 {
+		compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
+
+		reg = <0x506a000 0x30000>,
+			<0xb280000 0x10000>,
+			<0xb480000 0x10000>;
+		reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hfi", "gmu";
+
+		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+			<&gpucc GPU_CC_CXO_CLK>,
+			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+			<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+		clock-names = "gmu", "cxo", "axi", "memnoc";
+
+		power-domains = <&gpucc GPU_CX_GDSC>;
+		iommus = <&adreno_smmu 5>;
+
+		operating-points-v2 = <&gmu_opp_table>;
+	};
+};
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 4ad5e70e5c3e..9c89f4fdb8ca 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -8,14 +8,23 @@ Required properties:
   with the chip-id.
 - reg: Physical base address and length of the controller's registers.
 - interrupts: The interrupt signal from the gpu.
-- clocks: device clocks
+- clocks: device clocks (if applicable)
   See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required:
+- clock-names: the following clocks are required by a3xx, a4xx and a5xx
+  cores:
   * "core"
   * "iface"
   * "mem_iface"
+  For GMU attached devices the GPU clocks are not used and are not required. The
+  following devices should not list clocks:
+   - qcom,adreno-630.2
+- iommus: optional phandle to an adreno iommu instance
+- operating-points-v2: optional phandle to the OPP operating points
+- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
+  control the power for the GPU. Applicable targets:
+    - qcom,adreno-630.2
 
-Example:
+Example 3xx/4xx/a5xx:
 
 / {
 	...
@@ -35,3 +44,30 @@ Example:
 		    <&mmcc MMSS_IMEM_AHB_CLK>;
 	};
 };
+
+Example a6xx (with GMU):
+
+/ {
+	...
+
+	gpu@5000000 {
+		compatible = "qcom,adreno-630.2", "qcom,adreno";
+		#stream-id-cells = <16>;
+
+		reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+		reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+		/*
+		 * Look ma, no clocks! The GPU clocks and power are
+		 * controlled entirely by the GMU
+		 */
+
+		interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+		iommus = <&adreno_smmu 0>;
+
+		operating-points-v2 = <&gpu_opp_table>;
+
+		qcom,gmu = <&gmu>;
+	};
+};
-- 
2.18.0

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[PATCH v7 5/6] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

[Jordan Crouse]

Update the GPU bindings and document the new bindings for the GMU
device found with Adreno a6xx targets.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---

v7: Updated the GMU compatible string and clarified details about when clocks
can be optional on the GPU

 .../devicetree/bindings/display/msm/gmu.txt   | 59 +++++++++++++++++++
 .../devicetree/bindings/display/msm/gpu.txt   | 42 ++++++++++++-
 2 files changed, 98 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt

diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt
new file mode 100644
index 000000000000..59e6865898f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
@@ -0,0 +1,59 @@
+Qualcomm adreno/snapdragon GMU (Graphics management unit)
+
+The GMU is a programmable power controller for the GPU. the CPU controls the
+GMU which in turn handles power controls for the GPU.
+
+Required properties:
+- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
+    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
+  Note that you need to list the less specific "qcom,adreno-gmu"
+  for generic matches and the more specific identifier to identify
+  the specific device.
+- reg: Physical base address and length of the GMU registers.
+- reg-names: Matching names for the register regions
+  * "gmu"
+  * "gmu_pdc"
+  * "gmu_pdc_seg"
+- interrupts: The interrupt signals from the GMU.
+- interrupt-names: Matching names for the interrupts
+  * "hfi"
+  * "gmu"
+- clocks: phandles to the device clocks
+- clock-names: Matching names for the clocks
+   * "gmu"
+   * "cxo"
+   * "axi"
+   * "mnoc"
+- power-domains: should be <&clock_gpucc GPU_CX_GDSC>
+- iommus: phandle to the adreno iommu
+- operating-points-v2: phandle to the OPP operating points
+
+Example:
+
+/ {
+	...
+
+	gmu: gmu@506a000 {
+		compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
+
+		reg = <0x506a000 0x30000>,
+			<0xb280000 0x10000>,
+			<0xb480000 0x10000>;
+		reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hfi", "gmu";
+
+		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+			<&gpucc GPU_CC_CXO_CLK>,
+			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+			<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+		clock-names = "gmu", "cxo", "axi", "memnoc";
+
+		power-domains = <&gpucc GPU_CX_GDSC>;
+		iommus = <&adreno_smmu 5>;
+
+		operating-points-v2 = <&gmu_opp_table>;
+	};
+};
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 4ad5e70e5c3e..9c89f4fdb8ca 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -8,14 +8,23 @@ Required properties:
   with the chip-id.
 - reg: Physical base address and length of the controller's registers.
 - interrupts: The interrupt signal from the gpu.
-- clocks: device clocks
+- clocks: device clocks (if applicable)
   See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required:
+- clock-names: the following clocks are required by a3xx, a4xx and a5xx
+  cores:
   * "core"
   * "iface"
   * "mem_iface"
+  For GMU attached devices the GPU clocks are not used and are not required. The
+  following devices should not list clocks:
+   - qcom,adreno-630.2
+- iommus: optional phandle to an adreno iommu instance
+- operating-points-v2: optional phandle to the OPP operating points
+- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
+  control the power for the GPU. Applicable targets:
+    - qcom,adreno-630.2
 
-Example:
+Example 3xx/4xx/a5xx:
 
 / {
 	...
@@ -35,3 +44,30 @@ Example:
 		    <&mmcc MMSS_IMEM_AHB_CLK>;
 	};
 };
+
+Example a6xx (with GMU):
+
+/ {
+	...
+
+	gpu@5000000 {
+		compatible = "qcom,adreno-630.2", "qcom,adreno";
+		#stream-id-cells = <16>;
+
+		reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+		reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+		/*
+		 * Look ma, no clocks! The GPU clocks and power are
+		 * controlled entirely by the GMU
+		 */
+
+		interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+		iommus = <&adreno_smmu 0>;
+
+		operating-points-v2 = <&gpu_opp_table>;
+
+		qcom,gmu = <&gmu>;
+	};
+};
-- 
2.18.0


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[PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes

[Jordan Crouse]

Add the nodes to describe the Adreno GPU and GMU devices.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---

v7: Updated the GMU compatible string and removed interrupt-names

 arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 233a5898ebc2..4779014e4a05 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
@@ -1349,6 +1350,127 @@
 			};
 		};
 
+
+		gpu@5000000 {
+			compatible = "qcom,adreno-630.2", "qcom,adreno";
+			#stream-id-cells = <16>;
+
+			reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+			reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+			/*
+			 * Look ma, no clocks! The GPU clocks and power are
+			 * controlled entirely by the GMU
+			 */
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			qcom,gmu = <&gmu>;
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2-qcom-level";
+
+				opp-710000000 {
+					opp-hz = /bits/ 64 <710000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+				};
+
+				opp-675000000 {
+					opp-hz = /bits/ 64 <675000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+				};
+
+				opp-596000000 {
+					opp-hz = /bits/ 64 <596000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+				};
+
+				opp-520000000 {
+					opp-hz = /bits/ 64 <520000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+				};
+
+				opp-414000000 {
+					opp-hz = /bits/ 64 <414000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+				};
+
+				opp-342000000 {
+					opp-hz = /bits/ 64 <342000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+
+				opp-257000000 {
+					opp-hz = /bits/ 64 <257000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+				};
+			};
+		};
+
+		adreno_smmu: iommu@5040000 {
+			compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
+			reg = <0x5040000 0x10000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <2>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				<&gcc GCC_GPU_CFG_AHB_CLK>;
+			clock-names = "bus", "iface";
+
+			power-domains = <&gpucc GPU_CX_GDSC>;
+		};
+
+		gmu: gmu@506a000 {
+			compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
+
+			reg = <0x506a000 0x30000>,
+				<0xb280000 0x10000>,
+				<0xb480000 0x10000>;
+			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi", "gmu";
+
+			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+				<&gpucc GPU_CC_CXO_CLK>,
+				<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+				<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+			clock-names = "gmu", "cxo", "axi", "memnoc";
+
+			power-domains = <&gpucc GPU_CX_GDSC>;
+			iommus = <&adreno_smmu 5>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2-qcom-level";
+
+				opp-400000000 {
+					opp-hz = /bits/ 64 <400000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				};
+			};
+		};
+
 		gpucc: clock-controller@5090000 {
 			compatible = "qcom,sdm845-gpucc";
 			reg = <0x5090000 0x9000>;
-- 
2.18.0

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[PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes

[Jordan Crouse]

Add the nodes to describe the Adreno GPU and GMU devices.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---

v7: Updated the GMU compatible string and removed interrupt-names

 arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 233a5898ebc2..4779014e4a05 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
@@ -1349,6 +1350,127 @@
 			};
 		};
 
+
+		gpu@5000000 {
+			compatible = "qcom,adreno-630.2", "qcom,adreno";
+			#stream-id-cells = <16>;
+
+			reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+			reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+			/*
+			 * Look ma, no clocks! The GPU clocks and power are
+			 * controlled entirely by the GMU
+			 */
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			qcom,gmu = <&gmu>;
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2-qcom-level";
+
+				opp-710000000 {
+					opp-hz = /bits/ 64 <710000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+				};
+
+				opp-675000000 {
+					opp-hz = /bits/ 64 <675000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+				};
+
+				opp-596000000 {
+					opp-hz = /bits/ 64 <596000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+				};
+
+				opp-520000000 {
+					opp-hz = /bits/ 64 <520000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+				};
+
+				opp-414000000 {
+					opp-hz = /bits/ 64 <414000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+				};
+
+				opp-342000000 {
+					opp-hz = /bits/ 64 <342000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+
+				opp-257000000 {
+					opp-hz = /bits/ 64 <257000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+				};
+			};
+		};
+
+		adreno_smmu: iommu@5040000 {
+			compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
+			reg = <0x5040000 0x10000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <2>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				<&gcc GCC_GPU_CFG_AHB_CLK>;
+			clock-names = "bus", "iface";
+
+			power-domains = <&gpucc GPU_CX_GDSC>;
+		};
+
+		gmu: gmu@506a000 {
+			compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
+
+			reg = <0x506a000 0x30000>,
+				<0xb280000 0x10000>,
+				<0xb480000 0x10000>;
+			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi", "gmu";
+
+			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+				<&gpucc GPU_CC_CXO_CLK>,
+				<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+				<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+			clock-names = "gmu", "cxo", "axi", "memnoc";
+
+			power-domains = <&gpucc GPU_CX_GDSC>;
+			iommus = <&adreno_smmu 5>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2-qcom-level";
+
+				opp-400000000 {
+					opp-hz = /bits/ 64 <400000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					qcom,level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				};
+			};
+		};
+
 		gpucc: clock-controller@5090000 {
 			compatible = "qcom,sdm845-gpucc";
 			reg = <0x5090000 0x9000>;
-- 
2.18.0


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Re: [PATCH v7 2/6] drm/msm: drop interrupt-names

[Rob Herring]

On Tue, 18 Dec 2018 11:32:37 -0700, Jordan Crouse wrote:
> Each GPU core only uses one interrupt so we don't to look up
> an interrupt by name and thereby we don't need interrupt-names.
> 
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/display/msm/gpu.txt | 1 -
>  1 file changed, 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>
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Re: [PATCH v7 2/6] drm/msm: drop interrupt-names

[Rob Herring]

On Tue, 18 Dec 2018 11:32:37 -0700, Jordan Crouse wrote:
> Each GPU core only uses one interrupt so we don't to look up
> an interrupt by name and thereby we don't need interrupt-names.
> 
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/display/msm/gpu.txt | 1 -
>  1 file changed, 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v7 3/6] ARM: dts: qcom: Removed unused interrupt-names from GPU node

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> 'interrupt-names' shouldn't be used in cases when there is only
> one interrupt and it is not otherwise used in the driver.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>  arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
>  1 file changed, 1 deletion(-)

Looks good to me.  It should be noted that Andy shouldn't land this
until he has a tree that contains ("drm/msm/gpu: Remove hardcoded
interrupt name").  ...or he should Ack this and it should go through
the same tree as that patch.

I'm curious: is there a reason you didn't remove it from the other two users?

linuxnext/master:arch/arm/boot/dts/imx51.dtsi:
interrupt-names = "kgsl_3d0_irq";
linuxnext/master:arch/arm/boot/dts/imx53.dtsi:
interrupt-names = "kgsl_3d0_irq";

...also: if this really is only for "apq8064" and not globally for all
qcom devices it'd be nice to mention "apq8064" somewhere in the
subject.

-Doug
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Re: [PATCH v7 3/6] ARM: dts: qcom: Removed unused interrupt-names from GPU node

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> 'interrupt-names' shouldn't be used in cases when there is only
> one interrupt and it is not otherwise used in the driver.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>  arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
>  1 file changed, 1 deletion(-)

Looks good to me.  It should be noted that Andy shouldn't land this
until he has a tree that contains ("drm/msm/gpu: Remove hardcoded
interrupt name").  ...or he should Ack this and it should go through
the same tree as that patch.

I'm curious: is there a reason you didn't remove it from the other two users?

linuxnext/master:arch/arm/boot/dts/imx51.dtsi:
interrupt-names = "kgsl_3d0_irq";
linuxnext/master:arch/arm/boot/dts/imx53.dtsi:
interrupt-names = "kgsl_3d0_irq";

...also: if this really is only for "apq8064" and not globally for all
qcom devices it'd be nice to mention "apq8064" somewhere in the
subject.

-Doug

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Re: [PATCH v7 5/6] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

[Rob Herring]

On Tue, 18 Dec 2018 11:32:40 -0700, Jordan Crouse wrote:
> Update the GPU bindings and document the new bindings for the GMU
> device found with Adreno a6xx targets.
> 
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
> 
> v7: Updated the GMU compatible string and clarified details about when clocks
> can be optional on the GPU
> 
>  .../devicetree/bindings/display/msm/gmu.txt   | 59 +++++++++++++++++++
>  .../devicetree/bindings/display/msm/gpu.txt   | 42 ++++++++++++-
>  2 files changed, 98 insertions(+), 3 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>
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Re: [PATCH v7 5/6] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

[Rob Herring]

On Tue, 18 Dec 2018 11:32:40 -0700, Jordan Crouse wrote:
> Update the GPU bindings and document the new bindings for the GMU
> device found with Adreno a6xx targets.
> 
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
> 
> v7: Updated the GMU compatible string and clarified details about when clocks
> can be optional on the GPU
> 
>  .../devicetree/bindings/display/msm/gmu.txt   | 59 +++++++++++++++++++
>  .../devicetree/bindings/display/msm/gpu.txt   | 42 ++++++++++++-
>  2 files changed, 98 insertions(+), 3 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v7 1/6] drm/msm/gpu: Remove hardcoded interrupt name

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Every GPU core only has one interrupt so there isn't any
> value in looking up the interrupt by name. Remove the name (which
> is legacy anyway) and use platform_get_irq() instead.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 -
>  drivers/gpu/drm/msm/msm_gpu.c           | 2 +-
>  drivers/gpu/drm/msm/msm_gpu.h           | 1 -
>  3 files changed, 1 insertion(+), 3 deletions(-)

Reviewed-by: Douglas Anderson <dianders@chromium.org>
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Re: [PATCH v7 1/6] drm/msm/gpu: Remove hardcoded interrupt name

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Every GPU core only has one interrupt so there isn't any
> value in looking up the interrupt by name. Remove the name (which
> is legacy anyway) and use platform_get_irq() instead.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 -
>  drivers/gpu/drm/msm/msm_gpu.c           | 2 +-
>  drivers/gpu/drm/msm/msm_gpu.h           | 1 -
>  3 files changed, 1 insertion(+), 3 deletions(-)

Reviewed-by: Douglas Anderson <dianders@chromium.org>

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Re: [PATCH v7 4/6] arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> 'interrupt-names' shouldn't be used in cases when there is only
> one interrupt and it is not otherwise used in the driver.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 -
>  1 file changed, 1 deletion(-)

Looks good to me.  It should be noted that Andy shouldn't land this
until he has a tree that contains ("drm/msm/gpu: Remove hardcoded
interrupt name").  ...or he should Ack this and it should go through
the same tree as that patch.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
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Re: [PATCH v7 4/6] arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> 'interrupt-names' shouldn't be used in cases when there is only
> one interrupt and it is not otherwise used in the driver.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 -
>  1 file changed, 1 deletion(-)

Looks good to me.  It should be noted that Andy shouldn't land this
until he has a tree that contains ("drm/msm/gpu: Remove hardcoded
interrupt name").  ...or he should Ack this and it should go through
the same tree as that patch.

Reviewed-by: Douglas Anderson <dianders@chromium.org>

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Re: [PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 10:33 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Add the nodes to describe the Adreno GPU and GMU devices.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>
> v7: Updated the GMU compatible string and removed interrupt-names
>
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++
>  1 file changed, 122 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 233a5898ebc2..4779014e4a05 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -11,6 +11,7 @@
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/phy/phy-qcom-qusb2.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
>  #include <dt-bindings/reset/qcom,sdm845-aoss.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> @@ -1349,6 +1350,127 @@
>                         };
>                 };
>
> +
> +               gpu@5000000 {

Repeating my comments from v6:

nit that you're adding an extra blank line here that you don't need.
Given the quantity of outstanding dts patches though, it's almost
certain that Andy will need to manually resolve conflicts when
applying this patch so presumably he can fix up when he lands.

In any case, feel free to add:

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>


> +                       compatible = "qcom,adreno-630.2", "qcom,adreno";
> +                       #stream-id-cells = <16>;
> +
> +                       reg = <0x5000000 0x40000>, <0x509e000 0x10>;
> +                       reg-names = "kgsl_3d0_reg_memory", "cx_mem";
> +
> +                       /*
> +                        * Look ma, no clocks! The GPU clocks and power are
> +                        * controlled entirely by the GMU
> +                        */
> +
> +                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       iommus = <&adreno_smmu 0>;
> +
> +                       operating-points-v2 = <&gpu_opp_table>;
> +
> +                       qcom,gmu = <&gmu>;
> +
> +                       gpu_opp_table: opp-table {
> +                               compatible = "operating-points-v2-qcom-level";

I believe that the consensus from the v2 comments at
<https://patchwork.kernel.org/patch/10727121/> are that this should
be:

compatible = "operating-points-v2-qcom-level", "operating-points-v2";

...same with the other one below...
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Re: [PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 10:33 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Add the nodes to describe the Adreno GPU and GMU devices.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
>
> v7: Updated the GMU compatible string and removed interrupt-names
>
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++
>  1 file changed, 122 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 233a5898ebc2..4779014e4a05 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -11,6 +11,7 @@
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/phy/phy-qcom-qusb2.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
>  #include <dt-bindings/reset/qcom,sdm845-aoss.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> @@ -1349,6 +1350,127 @@
>                         };
>                 };
>
> +
> +               gpu@5000000 {

Repeating my comments from v6:

nit that you're adding an extra blank line here that you don't need.
Given the quantity of outstanding dts patches though, it's almost
certain that Andy will need to manually resolve conflicts when
applying this patch so presumably he can fix up when he lands.

In any case, feel free to add:

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>


> +                       compatible = "qcom,adreno-630.2", "qcom,adreno";
> +                       #stream-id-cells = <16>;
> +
> +                       reg = <0x5000000 0x40000>, <0x509e000 0x10>;
> +                       reg-names = "kgsl_3d0_reg_memory", "cx_mem";
> +
> +                       /*
> +                        * Look ma, no clocks! The GPU clocks and power are
> +                        * controlled entirely by the GMU
> +                        */
> +
> +                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       iommus = <&adreno_smmu 0>;
> +
> +                       operating-points-v2 = <&gpu_opp_table>;
> +
> +                       qcom,gmu = <&gmu>;
> +
> +                       gpu_opp_table: opp-table {
> +                               compatible = "operating-points-v2-qcom-level";

I believe that the consensus from the v2 comments at
<https://patchwork.kernel.org/patch/10727121/> are that this should
be:

compatible = "operating-points-v2-qcom-level", "operating-points-v2";

...same with the other one below...

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Re: [PATCH v7 3/6] ARM: dts: qcom: Removed unused interrupt-names from GPU node

[Jordan Crouse]

On Tue, Dec 18, 2018 at 02:29:25PM -0800, Doug Anderson wrote:
> Hi,
> 
> On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
> >
> > 'interrupt-names' shouldn't be used in cases when there is only
> > one interrupt and it is not otherwise used in the driver.
> >
> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> > ---
> >  arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
> >  1 file changed, 1 deletion(-)
> 
> Looks good to me.  It should be noted that Andy shouldn't land this
> until he has a tree that contains ("drm/msm/gpu: Remove hardcoded
> interrupt name").  ...or he should Ack this and it should go through
> the same tree as that patch.
> 
> I'm curious: is there a reason you didn't remove it from the other two users?
> 
> linuxnext/master:arch/arm/boot/dts/imx51.dtsi:
> interrupt-names = "kgsl_3d0_irq";
> linuxnext/master:arch/arm/boot/dts/imx53.dtsi:
> interrupt-names = "kgsl_3d0_irq";

Because those aren't in Andy's tree. I suspect after all this lands we'll need
another sweep to clean up the extras. There is also a 8996 dt floating around
somewhere.

Jordan

> ...also: if this really is only for "apq8064" and not globally for all
> qcom devices it'd be nice to mention "apq8064" somewhere in the
> subject.

> -Doug

-- 
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a Linux Foundation Collaborative Project
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Re: [PATCH v7 3/6] ARM: dts: qcom: Removed unused interrupt-names from GPU node

[Jordan Crouse]

On Tue, Dec 18, 2018 at 02:29:25PM -0800, Doug Anderson wrote:
> Hi,
> 
> On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
> >
> > 'interrupt-names' shouldn't be used in cases when there is only
> > one interrupt and it is not otherwise used in the driver.
> >
> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> > ---
> >  arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
> >  1 file changed, 1 deletion(-)
> 
> Looks good to me.  It should be noted that Andy shouldn't land this
> until he has a tree that contains ("drm/msm/gpu: Remove hardcoded
> interrupt name").  ...or he should Ack this and it should go through
> the same tree as that patch.
> 
> I'm curious: is there a reason you didn't remove it from the other two users?
> 
> linuxnext/master:arch/arm/boot/dts/imx51.dtsi:
> interrupt-names = "kgsl_3d0_irq";
> linuxnext/master:arch/arm/boot/dts/imx53.dtsi:
> interrupt-names = "kgsl_3d0_irq";

Because those aren't in Andy's tree. I suspect after all this lands we'll need
another sweep to clean up the extras. There is also a 8996 dt floating around
somewhere.

Jordan

> ...also: if this really is only for "apq8064" and not globally for all
> qcom devices it'd be nice to mention "apq8064" somewhere in the
> subject.

> -Doug

-- 
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a Linux Foundation Collaborative Project

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Re: [PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 2:57 PM Doug Anderson <dianders@chromium.org> wrote:
>
> Hi,
>
> On Tue, Dec 18, 2018 at 10:33 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
> >
> > Add the nodes to describe the Adreno GPU and GMU devices.
> >
> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> > ---
> >
> > v7: Updated the GMU compatible string and removed interrupt-names
> >
> >  arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++
> >  1 file changed, 122 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index 233a5898ebc2..4779014e4a05 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -11,6 +11,7 @@
> >  #include <dt-bindings/clock/qcom,rpmh.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/phy/phy-qcom-qusb2.h>
> > +#include <dt-bindings/power/qcom-rpmpd.h>
> >  #include <dt-bindings/reset/qcom,sdm845-aoss.h>
> >  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> >  #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> > @@ -1349,6 +1350,127 @@
> >                         };
> >                 };
> >
> > +
> > +               gpu@5000000 {
>
> Repeating my comments from v6:
>
> nit that you're adding an extra blank line here that you don't need.
> Given the quantity of outstanding dts patches though, it's almost
> certain that Andy will need to manually resolve conflicts when
> applying this patch so presumably he can fix up when he lands.
>
> In any case, feel free to add:
>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Douglas Anderson <dianders@chromium.org>
>
>
> > +                       compatible = "qcom,adreno-630.2", "qcom,adreno";
> > +                       #stream-id-cells = <16>;
> > +
> > +                       reg = <0x5000000 0x40000>, <0x509e000 0x10>;
> > +                       reg-names = "kgsl_3d0_reg_memory", "cx_mem";
> > +
> > +                       /*
> > +                        * Look ma, no clocks! The GPU clocks and power are
> > +                        * controlled entirely by the GMU
> > +                        */
> > +
> > +                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                       iommus = <&adreno_smmu 0>;
> > +
> > +                       operating-points-v2 = <&gpu_opp_table>;
> > +
> > +                       qcom,gmu = <&gmu>;
> > +
> > +                       gpu_opp_table: opp-table {
> > +                               compatible = "operating-points-v2-qcom-level";
>
> I believe that the consensus from the v2 comments at
> <https://patchwork.kernel.org/patch/10727121/> are that this should
> be:
>
> compatible = "operating-points-v2-qcom-level", "operating-points-v2";
>
> ...same with the other one below...

OK, so I read and re-read all the discussions about this that have
happened since my last email and also had an offline chat with Stephen
and I believe the decision is _not_ to do the "operating-points-v2"
fallback even if your table happens to have "opp-hz" in it.  So
presumably that's resolved.  One reason this works OK for us is that
we have the "operating-points" as a sub-node of the GPU and thus don't
have to worry about the messing with the skip table to prevent a
device from being created (as discussed in the comments of v6) [1]

...but in the meantime Rajendra has had to change his bindings, so you
still need to spin this to account for Rajendra's v9 bindings [2].
Specifically you need to make changes like:

-                               compatible = "operating-points-v2-qcom-level";
+                               compatible = "operating-points-v2-level";

...and:

-                                       qcom,level =
<RPMH_REGULATOR_LEVEL_TURBO_L1>;
+                                       opp-level =
<RPMH_REGULATOR_LEVEL_TURBO_L1>;

...when you spin for this, please make sure you account for the nit
(blank line) I commented about above.

-Doug

[1] https://lore.kernel.org/linux-arm-kernel/7e310416-78d3-b7e5-5013-0bcc8bfd0351@codeaurora.org/
[2] https://lkml.kernel.org/r/20190107100959.14528-2-rnayak@codeaurora.org
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Re: [PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes

[Doug Anderson]

Hi,

On Tue, Dec 18, 2018 at 2:57 PM Doug Anderson <dianders@chromium.org> wrote:
>
> Hi,
>
> On Tue, Dec 18, 2018 at 10:33 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
> >
> > Add the nodes to describe the Adreno GPU and GMU devices.
> >
> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> > ---
> >
> > v7: Updated the GMU compatible string and removed interrupt-names
> >
> >  arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++
> >  1 file changed, 122 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index 233a5898ebc2..4779014e4a05 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -11,6 +11,7 @@
> >  #include <dt-bindings/clock/qcom,rpmh.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/phy/phy-qcom-qusb2.h>
> > +#include <dt-bindings/power/qcom-rpmpd.h>
> >  #include <dt-bindings/reset/qcom,sdm845-aoss.h>
> >  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> >  #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> > @@ -1349,6 +1350,127 @@
> >                         };
> >                 };
> >
> > +
> > +               gpu@5000000 {
>
> Repeating my comments from v6:
>
> nit that you're adding an extra blank line here that you don't need.
> Given the quantity of outstanding dts patches though, it's almost
> certain that Andy will need to manually resolve conflicts when
> applying this patch so presumably he can fix up when he lands.
>
> In any case, feel free to add:
>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Douglas Anderson <dianders@chromium.org>
>
>
> > +                       compatible = "qcom,adreno-630.2", "qcom,adreno";
> > +                       #stream-id-cells = <16>;
> > +
> > +                       reg = <0x5000000 0x40000>, <0x509e000 0x10>;
> > +                       reg-names = "kgsl_3d0_reg_memory", "cx_mem";
> > +
> > +                       /*
> > +                        * Look ma, no clocks! The GPU clocks and power are
> > +                        * controlled entirely by the GMU
> > +                        */
> > +
> > +                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                       iommus = <&adreno_smmu 0>;
> > +
> > +                       operating-points-v2 = <&gpu_opp_table>;
> > +
> > +                       qcom,gmu = <&gmu>;
> > +
> > +                       gpu_opp_table: opp-table {
> > +                               compatible = "operating-points-v2-qcom-level";
>
> I believe that the consensus from the v2 comments at
> <https://patchwork.kernel.org/patch/10727121/> are that this should
> be:
>
> compatible = "operating-points-v2-qcom-level", "operating-points-v2";
>
> ...same with the other one below...

OK, so I read and re-read all the discussions about this that have
happened since my last email and also had an offline chat with Stephen
and I believe the decision is _not_ to do the "operating-points-v2"
fallback even if your table happens to have "opp-hz" in it.  So
presumably that's resolved.  One reason this works OK for us is that
we have the "operating-points" as a sub-node of the GPU and thus don't
have to worry about the messing with the skip table to prevent a
device from being created (as discussed in the comments of v6) [1]

...but in the meantime Rajendra has had to change his bindings, so you
still need to spin this to account for Rajendra's v9 bindings [2].
Specifically you need to make changes like:

-                               compatible = "operating-points-v2-qcom-level";
+                               compatible = "operating-points-v2-level";

...and:

-                                       qcom,level =
<RPMH_REGULATOR_LEVEL_TURBO_L1>;
+                                       opp-level =
<RPMH_REGULATOR_LEVEL_TURBO_L1>;

...when you spin for this, please make sure you account for the nit
(blank line) I commented about above.

-Doug

[1] https://lore.kernel.org/linux-arm-kernel/7e310416-78d3-b7e5-5013-0bcc8bfd0351@codeaurora.org/
[2] https://lkml.kernel.org/r/20190107100959.14528-2-rnayak@codeaurora.org

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Re: [PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes

[Rajendra Nayak]

On 1/9/2019 10:50 AM, Doug Anderson wrote:
> ...but in the meantime Rajendra has had to change his bindings, so you
> still need to spin this to account for Rajendra's v9 bindings [2].
> Specifically you need to make changes like:
> 
> -                               compatible = "operating-points-v2-qcom-level";
> +                               compatible = "operating-points-v2-level";

so there's now a v10 [1] and the new compatible is completely dropped and opp-level
is now an optional property using the default "operating-points-v2"

so the change should be
-                               compatible = "operating-points-v2-qcom-level";
+                               compatible = "operating-points-v2";

[1] https://lkml.org/lkml/2019/1/9/152

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Re: [PATCH v7 6/6] arm64: dts: sdm845: Add gpu and gmu device nodes

[Rajendra Nayak]

On 1/9/2019 10:50 AM, Doug Anderson wrote:
> ...but in the meantime Rajendra has had to change his bindings, so you
> still need to spin this to account for Rajendra's v9 bindings [2].
> Specifically you need to make changes like:
> 
> -                               compatible = "operating-points-v2-qcom-level";
> +                               compatible = "operating-points-v2-level";

so there's now a v10 [1] and the new compatible is completely dropped and opp-level
is now an optional property using the default "operating-points-v2"

so the change should be
-                               compatible = "operating-points-v2-qcom-level";
+                               compatible = "operating-points-v2";

[1] https://lkml.org/lkml/2019/1/9/152

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

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Re: [PATCH v7 0/6] arm64: dts: Add sdm845 GPU/GMU and SMMU

[Doug Anderson]

Hi Rob,

On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Now that more of the sdm845 bindings are headed upstream this a refresh of
> of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes
> for the GPU/GMU and GPU SMMU for sdm845. v7 of this patchset also removes
> interrupt-names from the driver and the existing DT changes per feedback from
> Rob Herring.
>
> This is based on :
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next
>
> with:
> https://lore.kernel.org/patchwork/patch/1018365/
>
> This change requires the following dependencies:
>
> include/dt-bindings/power/qcom-rpmpd.h:
> https://patchwork.kernel.org/patch/10711119/
>
> qcom,smmu-v2 binding:
> https://patchwork.kernel.org/patch/10581911/
>
> v7: Add patches to remove interrupt-names, add version specific compatible
>     string for gmu
> v6: Update GPU bindings for a6xx and make the examples match the nodes and vice
>  versa.  Clean up types and rebase on
>  https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging.
> v5: Use symbolic names for the RPMH power levels defined in OPP table,
>  move the opp tables as children of their respective nodes and rename
>  the iommu device.
> v4: Rebase
> v3: Split GMU PDC region into two GPU specific sections, fix indentation,
>   really use qcom,gmu for the phandle name
> v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
>   change gmu phandle to qcom,gmu per Rob
>
> Jordan Crouse (6):
>   drm/msm/gpu: Remove hardcoded interrupt name
>   drm/msm: drop interrupt-names
>   ARM: dts: qcom: Removed unused interrupt-names from GPU node
>   arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU
>   dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
>   arm64: dts: sdm845: Add gpu and gmu device nodes

I know it's been holidays and everyone (including me) has been on
vacation, but just wanted to make sure the current status of this
series was explicitly called out.  :-)


I believe patches #1 and #2 are ready to land and will go through your tree.

Patches #3 and #4 should probably go through Andy's tree and are not
urgent (they are just cleanup).  They can sit on the back burner until
patches #1 and #2 have hit mainline.  That's a good reason to land #1
and #2 sooner.  ;-)

I think patch #5 is also ready to land.  There's been some
bikeshedding about the exact format for the opp table, but none of
that bikeshedding affects the bindings that Jordan wrote.  If you
agree that this is OK to land, it would also be nice to get in.

...then Jordan can spin patch #6 (once Rob H Acks Rajendra's opp
bindings) alone at a future date.


-Doug
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Re: [PATCH v7 0/6] arm64: dts: Add sdm845 GPU/GMU and SMMU

[Doug Anderson]

Hi Rob,

On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Now that more of the sdm845 bindings are headed upstream this a refresh of
> of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes
> for the GPU/GMU and GPU SMMU for sdm845. v7 of this patchset also removes
> interrupt-names from the driver and the existing DT changes per feedback from
> Rob Herring.
>
> This is based on :
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next
>
> with:
> https://lore.kernel.org/patchwork/patch/1018365/
>
> This change requires the following dependencies:
>
> include/dt-bindings/power/qcom-rpmpd.h:
> https://patchwork.kernel.org/patch/10711119/
>
> qcom,smmu-v2 binding:
> https://patchwork.kernel.org/patch/10581911/
>
> v7: Add patches to remove interrupt-names, add version specific compatible
>     string for gmu
> v6: Update GPU bindings for a6xx and make the examples match the nodes and vice
>  versa.  Clean up types and rebase on
>  https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging.
> v5: Use symbolic names for the RPMH power levels defined in OPP table,
>  move the opp tables as children of their respective nodes and rename
>  the iommu device.
> v4: Rebase
> v3: Split GMU PDC region into two GPU specific sections, fix indentation,
>   really use qcom,gmu for the phandle name
> v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
>   change gmu phandle to qcom,gmu per Rob
>
> Jordan Crouse (6):
>   drm/msm/gpu: Remove hardcoded interrupt name
>   drm/msm: drop interrupt-names
>   ARM: dts: qcom: Removed unused interrupt-names from GPU node
>   arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU
>   dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
>   arm64: dts: sdm845: Add gpu and gmu device nodes

I know it's been holidays and everyone (including me) has been on
vacation, but just wanted to make sure the current status of this
series was explicitly called out.  :-)


I believe patches #1 and #2 are ready to land and will go through your tree.

Patches #3 and #4 should probably go through Andy's tree and are not
urgent (they are just cleanup).  They can sit on the back burner until
patches #1 and #2 have hit mainline.  That's a good reason to land #1
and #2 sooner.  ;-)

I think patch #5 is also ready to land.  There's been some
bikeshedding about the exact format for the opp table, but none of
that bikeshedding affects the bindings that Jordan wrote.  If you
agree that this is OK to land, it would also be nice to get in.

...then Jordan can spin patch #6 (once Rob H Acks Rajendra's opp
bindings) alone at a future date.


-Doug

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Re: [PATCH v7 0/6] arm64: dts: Add sdm845 GPU/GMU and SMMU

[Rob Clark]

On Wed, Jan 9, 2019 at 1:20 PM Doug Anderson <dianders@chromium.org> wrote:
>
> Hi Rob,
>
> On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
> >
> > Now that more of the sdm845 bindings are headed upstream this a refresh of
> > of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes
> > for the GPU/GMU and GPU SMMU for sdm845. v7 of this patchset also removes
> > interrupt-names from the driver and the existing DT changes per feedback from
> > Rob Herring.
> >
> > This is based on :
> > git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next
> >
> > with:
> > https://lore.kernel.org/patchwork/patch/1018365/
> >
> > This change requires the following dependencies:
> >
> > include/dt-bindings/power/qcom-rpmpd.h:
> > https://patchwork.kernel.org/patch/10711119/
> >
> > qcom,smmu-v2 binding:
> > https://patchwork.kernel.org/patch/10581911/
> >
> > v7: Add patches to remove interrupt-names, add version specific compatible
> >     string for gmu
> > v6: Update GPU bindings for a6xx and make the examples match the nodes and vice
> >  versa.  Clean up types and rebase on
> >  https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging.
> > v5: Use symbolic names for the RPMH power levels defined in OPP table,
> >  move the opp tables as children of their respective nodes and rename
> >  the iommu device.
> > v4: Rebase
> > v3: Split GMU PDC region into two GPU specific sections, fix indentation,
> >   really use qcom,gmu for the phandle name
> > v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
> >   change gmu phandle to qcom,gmu per Rob
> >
> > Jordan Crouse (6):
> >   drm/msm/gpu: Remove hardcoded interrupt name
> >   drm/msm: drop interrupt-names
> >   ARM: dts: qcom: Removed unused interrupt-names from GPU node
> >   arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU
> >   dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
> >   arm64: dts: sdm845: Add gpu and gmu device nodes
>
> I know it's been holidays and everyone (including me) has been on
> vacation, but just wanted to make sure the current status of this
> series was explicitly called out.  :-)
>
>
> I believe patches #1 and #2 are ready to land and will go through your tree.
>
> Patches #3 and #4 should probably go through Andy's tree and are not
> urgent (they are just cleanup).  They can sit on the back burner until
> patches #1 and #2 have hit mainline.  That's a good reason to land #1
> and #2 sooner.  ;-)
>
> I think patch #5 is also ready to land.  There's been some
> bikeshedding about the exact format for the opp table, but none of
> that bikeshedding affects the bindings that Jordan wrote.  If you
> agree that this is OK to land, it would also be nice to get in.
>
> ...then Jordan can spin patch #6 (once Rob H Acks Rajendra's opp
> bindings) alone at a future date.
>

I've picked up 1+2 and 5..  I assume it makes more sense for agross to
pick up the rest?

BR,
-R

Re: [PATCH v7 0/6] arm64: dts: Add sdm845 GPU/GMU and SMMU

[Rob Clark]

On Wed, Jan 9, 2019 at 1:20 PM Doug Anderson <dianders@chromium.org> wrote:
>
> Hi Rob,
>
> On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
> >
> > Now that more of the sdm845 bindings are headed upstream this a refresh of
> > of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes
> > for the GPU/GMU and GPU SMMU for sdm845. v7 of this patchset also removes
> > interrupt-names from the driver and the existing DT changes per feedback from
> > Rob Herring.
> >
> > This is based on :
> > git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next
> >
> > with:
> > https://lore.kernel.org/patchwork/patch/1018365/
> >
> > This change requires the following dependencies:
> >
> > include/dt-bindings/power/qcom-rpmpd.h:
> > https://patchwork.kernel.org/patch/10711119/
> >
> > qcom,smmu-v2 binding:
> > https://patchwork.kernel.org/patch/10581911/
> >
> > v7: Add patches to remove interrupt-names, add version specific compatible
> >     string for gmu
> > v6: Update GPU bindings for a6xx and make the examples match the nodes and vice
> >  versa.  Clean up types and rebase on
> >  https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging.
> > v5: Use symbolic names for the RPMH power levels defined in OPP table,
> >  move the opp tables as children of their respective nodes and rename
> >  the iommu device.
> > v4: Rebase
> > v3: Split GMU PDC region into two GPU specific sections, fix indentation,
> >   really use qcom,gmu for the phandle name
> > v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
> >   change gmu phandle to qcom,gmu per Rob
> >
> > Jordan Crouse (6):
> >   drm/msm/gpu: Remove hardcoded interrupt name
> >   drm/msm: drop interrupt-names
> >   ARM: dts: qcom: Removed unused interrupt-names from GPU node
> >   arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU
> >   dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
> >   arm64: dts: sdm845: Add gpu and gmu device nodes
>
> I know it's been holidays and everyone (including me) has been on
> vacation, but just wanted to make sure the current status of this
> series was explicitly called out.  :-)
>
>
> I believe patches #1 and #2 are ready to land and will go through your tree.
>
> Patches #3 and #4 should probably go through Andy's tree and are not
> urgent (they are just cleanup).  They can sit on the back burner until
> patches #1 and #2 have hit mainline.  That's a good reason to land #1
> and #2 sooner.  ;-)
>
> I think patch #5 is also ready to land.  There's been some
> bikeshedding about the exact format for the opp table, but none of
> that bikeshedding affects the bindings that Jordan wrote.  If you
> agree that this is OK to land, it would also be nice to get in.
>
> ...then Jordan can spin patch #6 (once Rob H Acks Rajendra's opp
> bindings) alone at a future date.
>

I've picked up 1+2 and 5..  I assume it makes more sense for agross to
pick up the rest?

BR,
-R

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