From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: gregkh@linuxfoundation.org, hminas@synopsys.com,
balbi@kernel.org, kishon@ti.com,
linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver
Date: Mon, 11 Mar 2019 22:14:27 +0100 [thread overview]
Message-ID: <CAFBinCCHZULDQjVeifiag-rzaPopVY7ir42RCGm9Wn6i9-=Qaw@mail.gmail.com> (raw)
In-Reply-To: <6e8b1935-ba91-d06e-be63-cb2632a19654@baylibre.com>
Hi Neil,
On Thu, Mar 7, 2019 at 9:44 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On 06/03/2019 22:04, Martin Blumenstingl wrote:
> > Hi Neil,
> >
> > On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
> > [...]
> >> +static int phy_g12a_usb3_init(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> + int data, ret;
> >> +
> >> + /* Switch PHY to USB3 */
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_USB3_SWITCH,
> >> + PHY_R0_PCIE_USB3_SWITCH);
> > does this automatically clear PHY_R0_PCIE_POWER_STATE (in case the
> > bootloader incorrectly set that)?
>
> Don't forget it's a static configuration, on the board, only USB3 XOR PCIE
> will be available, if the bootloader sets this and the kernel uses USB3,
> or the reverse, one of them is wrong.
I'm specifically asking is because we've seen various GXL/GXM boards
with a bootloader which is configured for the wrong PHY interface
(RGMII != RMII)
> >
> > [...]
> >> +static int phy_g12a_usb3_pcie_init(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> + int ret;
> >> +
> >> + ret = reset_control_reset(priv->reset);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if (priv->mode == PHY_TYPE_USB3)
> >> + return phy_g12a_usb3_init(phy);
> >> +
> >> + /* Power UP PCIE */
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_POWER_STATE,
> >> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
> > similar to my question above: does this automatically clear
> > PHY_R0_PCIE_USB3_SWITCH (in case the bootloader incorrectly set that)?
>
> Same answer, but I'll investigate to have more details on this register.
>
> It's more an implementation issue, we can change it when PCIe is enabled
> on this platform.
I'm fine with postponing this until we bring up PCIe support on this
platform if you add a comment (preferably marked with "TODO") in the
driver. that makes it obvious to everyone who comes across this in the
PHY driver
with a TODO-comment you can add my:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Regards
Martin
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: gregkh@linuxfoundation.org, hminas@synopsys.com,
balbi@kernel.org, kishon@ti.com,
linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [v2,6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver
Date: Mon, 11 Mar 2019 22:14:27 +0100 [thread overview]
Message-ID: <CAFBinCCHZULDQjVeifiag-rzaPopVY7ir42RCGm9Wn6i9-=Qaw@mail.gmail.com> (raw)
Hi Neil,
On Thu, Mar 7, 2019 at 9:44 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On 06/03/2019 22:04, Martin Blumenstingl wrote:
> > Hi Neil,
> >
> > On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
> > [...]
> >> +static int phy_g12a_usb3_init(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> + int data, ret;
> >> +
> >> + /* Switch PHY to USB3 */
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_USB3_SWITCH,
> >> + PHY_R0_PCIE_USB3_SWITCH);
> > does this automatically clear PHY_R0_PCIE_POWER_STATE (in case the
> > bootloader incorrectly set that)?
>
> Don't forget it's a static configuration, on the board, only USB3 XOR PCIE
> will be available, if the bootloader sets this and the kernel uses USB3,
> or the reverse, one of them is wrong.
I'm specifically asking is because we've seen various GXL/GXM boards
with a bootloader which is configured for the wrong PHY interface
(RGMII != RMII)
> >
> > [...]
> >> +static int phy_g12a_usb3_pcie_init(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> + int ret;
> >> +
> >> + ret = reset_control_reset(priv->reset);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if (priv->mode == PHY_TYPE_USB3)
> >> + return phy_g12a_usb3_init(phy);
> >> +
> >> + /* Power UP PCIE */
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_POWER_STATE,
> >> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
> > similar to my question above: does this automatically clear
> > PHY_R0_PCIE_USB3_SWITCH (in case the bootloader incorrectly set that)?
>
> Same answer, but I'll investigate to have more details on this register.
>
> It's more an implementation issue, we can change it when PCIe is enabled
> on this platform.
I'm fine with postponing this until we bring up PCIe support on this
platform if you add a comment (preferably marked with "TODO") in the
driver. that makes it obvious to everyone who comes across this in the
PHY driver
with a TODO-comment you can add my:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Regards
Martin
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: balbi@kernel.org, gregkh@linuxfoundation.org,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
kishon@ti.com, hminas@synopsys.com,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver
Date: Mon, 11 Mar 2019 22:14:27 +0100 [thread overview]
Message-ID: <CAFBinCCHZULDQjVeifiag-rzaPopVY7ir42RCGm9Wn6i9-=Qaw@mail.gmail.com> (raw)
In-Reply-To: <6e8b1935-ba91-d06e-be63-cb2632a19654@baylibre.com>
Hi Neil,
On Thu, Mar 7, 2019 at 9:44 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On 06/03/2019 22:04, Martin Blumenstingl wrote:
> > Hi Neil,
> >
> > On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
> > [...]
> >> +static int phy_g12a_usb3_init(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> + int data, ret;
> >> +
> >> + /* Switch PHY to USB3 */
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_USB3_SWITCH,
> >> + PHY_R0_PCIE_USB3_SWITCH);
> > does this automatically clear PHY_R0_PCIE_POWER_STATE (in case the
> > bootloader incorrectly set that)?
>
> Don't forget it's a static configuration, on the board, only USB3 XOR PCIE
> will be available, if the bootloader sets this and the kernel uses USB3,
> or the reverse, one of them is wrong.
I'm specifically asking is because we've seen various GXL/GXM boards
with a bootloader which is configured for the wrong PHY interface
(RGMII != RMII)
> >
> > [...]
> >> +static int phy_g12a_usb3_pcie_init(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> + int ret;
> >> +
> >> + ret = reset_control_reset(priv->reset);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if (priv->mode == PHY_TYPE_USB3)
> >> + return phy_g12a_usb3_init(phy);
> >> +
> >> + /* Power UP PCIE */
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_POWER_STATE,
> >> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
> > similar to my question above: does this automatically clear
> > PHY_R0_PCIE_USB3_SWITCH (in case the bootloader incorrectly set that)?
>
> Same answer, but I'll investigate to have more details on this register.
>
> It's more an implementation issue, we can change it when PCIe is enabled
> on this platform.
I'm fine with postponing this until we bring up PCIe support on this
platform if you add a comment (preferably marked with "TODO") in the
driver. that makes it obvious to everyone who comes across this in the
PHY driver
with a TODO-comment you can add my:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Regards
Martin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: balbi@kernel.org, gregkh@linuxfoundation.org,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
kishon@ti.com, hminas@synopsys.com,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver
Date: Mon, 11 Mar 2019 22:14:27 +0100 [thread overview]
Message-ID: <CAFBinCCHZULDQjVeifiag-rzaPopVY7ir42RCGm9Wn6i9-=Qaw@mail.gmail.com> (raw)
In-Reply-To: <6e8b1935-ba91-d06e-be63-cb2632a19654@baylibre.com>
Hi Neil,
On Thu, Mar 7, 2019 at 9:44 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On 06/03/2019 22:04, Martin Blumenstingl wrote:
> > Hi Neil,
> >
> > On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
> > [...]
> >> +static int phy_g12a_usb3_init(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> + int data, ret;
> >> +
> >> + /* Switch PHY to USB3 */
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_USB3_SWITCH,
> >> + PHY_R0_PCIE_USB3_SWITCH);
> > does this automatically clear PHY_R0_PCIE_POWER_STATE (in case the
> > bootloader incorrectly set that)?
>
> Don't forget it's a static configuration, on the board, only USB3 XOR PCIE
> will be available, if the bootloader sets this and the kernel uses USB3,
> or the reverse, one of them is wrong.
I'm specifically asking is because we've seen various GXL/GXM boards
with a bootloader which is configured for the wrong PHY interface
(RGMII != RMII)
> >
> > [...]
> >> +static int phy_g12a_usb3_pcie_init(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> + int ret;
> >> +
> >> + ret = reset_control_reset(priv->reset);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if (priv->mode == PHY_TYPE_USB3)
> >> + return phy_g12a_usb3_init(phy);
> >> +
> >> + /* Power UP PCIE */
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_POWER_STATE,
> >> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
> > similar to my question above: does this automatically clear
> > PHY_R0_PCIE_USB3_SWITCH (in case the bootloader incorrectly set that)?
>
> Same answer, but I'll investigate to have more details on this register.
>
> It's more an implementation issue, we can change it when PCIe is enabled
> on this platform.
I'm fine with postponing this until we bring up PCIe support on this
platform if you add a comment (preferably marked with "TODO") in the
driver. that makes it obvious to everyone who comes across this in the
PHY driver
with a TODO-comment you can add my:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Regards
Martin
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2019-03-11 21:14 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-04 10:38 [PATCH v2 0/8] arm64: meson: Add support for USB on Amlogic G12A Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` [PATCH v2 1/8] dt-bindings: phy: Add Amlogic G12A USB2 PHY Bindings Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` [v2,1/8] " Neil Armstrong
2019-03-04 10:38 ` [PATCH v2 2/8] dt-bindings: phy: Add Amlogic G12A USB3+PCIE Combo " Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` [v2,2/8] " Neil Armstrong
2019-03-04 10:38 ` [PATCH v2 2/8] " Neil Armstrong
2019-03-05 21:42 ` Martin Blumenstingl
2019-03-05 21:42 ` Martin Blumenstingl
2019-03-05 21:42 ` Martin Blumenstingl
2019-03-05 21:42 ` [v2,2/8] " Martin Blumenstingl
2019-03-07 8:35 ` [PATCH v2 2/8] " Neil Armstrong
2019-03-07 8:35 ` Neil Armstrong
2019-03-07 8:35 ` Neil Armstrong
2019-03-07 8:35 ` [v2,2/8] " Neil Armstrong
2019-03-12 18:23 ` [PATCH v2 2/8] " Rob Herring
2019-03-12 18:23 ` Rob Herring
2019-03-12 18:23 ` Rob Herring
2019-03-12 18:23 ` [v2,2/8] " Rob Herring
2019-03-12 18:23 ` [PATCH v2 2/8] " Rob Herring
2019-03-04 10:38 ` [PATCH v2 3/8] dt-bindings: usb: dwc2: Add Amlogic G12A DWC2 Compatible Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` [v2,3/8] " Neil Armstrong
2019-03-04 10:38 ` [PATCH v2 4/8] dt-bindings: usb: dwc3: Add Amlogic G12A DWC3 Glue Bindings Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` [v2,4/8] " Neil Armstrong
2019-03-06 21:27 ` [PATCH v2 4/8] " Martin Blumenstingl
2019-03-06 21:27 ` Martin Blumenstingl
2019-03-06 21:27 ` Martin Blumenstingl
2019-03-06 21:27 ` [v2,4/8] " Martin Blumenstingl
2019-03-07 8:36 ` [PATCH v2 4/8] " Neil Armstrong
2019-03-07 8:36 ` Neil Armstrong
2019-03-07 8:36 ` Neil Armstrong
2019-03-07 8:36 ` [v2,4/8] " Neil Armstrong
2019-03-12 18:29 ` [PATCH v2 4/8] " Rob Herring
2019-03-12 18:29 ` Rob Herring
2019-03-12 18:29 ` Rob Herring
2019-03-12 18:29 ` [v2,4/8] " Rob Herring
2019-03-12 18:29 ` [PATCH v2 4/8] " Rob Herring
2019-03-04 10:38 ` [PATCH v2 5/8] phy: amlogic: add Amlogic G12A USB2 PHY Driver Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` [v2,5/8] " Neil Armstrong
2019-03-06 21:00 ` [PATCH v2 5/8] " Martin Blumenstingl
2019-03-06 21:00 ` Martin Blumenstingl
2019-03-06 21:00 ` Martin Blumenstingl
2019-03-06 21:00 ` [v2,5/8] " Martin Blumenstingl
2019-03-07 8:41 ` [PATCH v2 5/8] " Neil Armstrong
2019-03-07 8:41 ` Neil Armstrong
2019-03-07 8:41 ` Neil Armstrong
2019-03-07 8:41 ` [v2,5/8] " Neil Armstrong
2019-03-11 21:04 ` [PATCH v2 5/8] " Martin Blumenstingl
2019-03-11 21:04 ` Martin Blumenstingl
2019-03-11 21:04 ` Martin Blumenstingl
2019-03-11 21:04 ` [v2,5/8] " Martin Blumenstingl
2019-03-04 10:38 ` [PATCH v2 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo " Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` [v2,6/8] " Neil Armstrong
2019-03-06 21:04 ` [PATCH v2 6/8] " Martin Blumenstingl
2019-03-06 21:04 ` Martin Blumenstingl
2019-03-06 21:04 ` Martin Blumenstingl
2019-03-06 21:04 ` [v2,6/8] " Martin Blumenstingl
2019-03-07 8:44 ` [PATCH v2 6/8] " Neil Armstrong
2019-03-07 8:44 ` Neil Armstrong
2019-03-07 8:44 ` Neil Armstrong
2019-03-07 8:44 ` [v2,6/8] " Neil Armstrong
2019-03-11 21:14 ` Martin Blumenstingl [this message]
2019-03-11 21:14 ` [PATCH v2 6/8] " Martin Blumenstingl
2019-03-11 21:14 ` Martin Blumenstingl
2019-03-11 21:14 ` [v2,6/8] " Martin Blumenstingl
2019-03-04 10:38 ` [PATCH v2 7/8] usb: dwc2: Add Amlogic G12A DWC2 Params Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` [v2,7/8] " Neil Armstrong
2019-03-04 10:38 ` [PATCH v2 8/8] usb: dwc3: Add Amlogic G12A DWC3 glue Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` Neil Armstrong
2019-03-04 10:38 ` [v2,8/8] " Neil Armstrong
2019-03-07 2:02 ` [PATCH v2 8/8] " Chunfeng Yun
2019-03-07 2:02 ` Chunfeng Yun
2019-03-07 2:02 ` Chunfeng Yun
2019-03-07 2:02 ` [v2,8/8] " Chunfeng Yun
2019-03-07 9:45 ` [PATCH v2 8/8] " Neil Armstrong
2019-03-07 9:45 ` Neil Armstrong
2019-03-07 9:45 ` Neil Armstrong
2019-03-07 9:45 ` [v2,8/8] " Neil Armstrong
2019-03-07 11:01 ` [PATCH v2 8/8] " Chunfeng Yun
2019-03-07 11:01 ` Chunfeng Yun
2019-03-07 11:01 ` Chunfeng Yun
2019-03-07 11:01 ` [v2,8/8] " Chunfeng Yun
2019-03-11 21:19 ` [PATCH v2 8/8] " Martin Blumenstingl
2019-03-11 21:19 ` Martin Blumenstingl
2019-03-11 21:19 ` Martin Blumenstingl
2019-03-11 21:19 ` [v2,8/8] " Martin Blumenstingl
2019-03-11 21:56 ` [PATCH v2 8/8] " Martin Blumenstingl
2019-03-11 21:56 ` Martin Blumenstingl
2019-03-11 21:56 ` Martin Blumenstingl
2019-03-11 21:56 ` [v2,8/8] " Martin Blumenstingl
2019-03-13 13:07 ` [PATCH v2 8/8] " Neil Armstrong
2019-03-13 13:07 ` Neil Armstrong
2019-03-13 13:07 ` Neil Armstrong
2019-03-13 13:07 ` [v2,8/8] " Neil Armstrong
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