[PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Punnaiah Choudary Kalluri]

Add bindings documentation for Zynq Quad SPI driver.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
---
 .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   26 ++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
new file mode 100644
index 0000000..88e00f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
@@ -0,0 +1,26 @@
+Xilinx Zynq QSPI controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible		: Should be "xlnx,zynq-qspi-1.0".
+- reg			: Physical base address and size of QSPI registers map.
+- interrupts		: Property with a value describing the interrupt
+			  number.
+- interrupt-parent	: Must be core interrupt controller
+- clock-names		: List of input clock names - "ref_clk", "aper_clk"
+			  (See clock bindings for details).
+- clocks		: Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs		: Number of chip selects used.
+
+Example:
+	qspi@e000d000 {
+		compatible = "xlnx,zynq-qspi-1.0";
+		clock-names = "ref_clk", "aper_clk";
+		clocks = <&clkc 10>, <&clkc 43>;
+		interrupt-parent = <&ps7_scugic_0>;
+		interrupts = <0 19 4>;
+		num-cs = /bits/ 16 <1>;
+		reg = <0xe000d000 0x1000>;
+	};
-- 
1.7.9.5

[PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Punnaiah Choudary Kalluri]

Add bindings documentation for Zynq Quad SPI driver.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   26 ++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
new file mode 100644
index 0000000..88e00f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
@@ -0,0 +1,26 @@
+Xilinx Zynq QSPI controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible		: Should be "xlnx,zynq-qspi-1.0".
+- reg			: Physical base address and size of QSPI registers map.
+- interrupts		: Property with a value describing the interrupt
+			  number.
+- interrupt-parent	: Must be core interrupt controller
+- clock-names		: List of input clock names - "ref_clk", "aper_clk"
+			  (See clock bindings for details).
+- clocks		: Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs		: Number of chip selects used.
+
+Example:
+	qspi@e000d000 {
+		compatible = "xlnx,zynq-qspi-1.0";
+		clock-names = "ref_clk", "aper_clk";
+		clocks = <&clkc 10>, <&clkc 43>;
+		interrupt-parent = <&ps7_scugic_0>;
+		interrupts = <0 19 4>;
+		num-cs = /bits/ 16 <1>;
+		reg = <0xe000d000 0x1000>;
+	};
-- 
1.7.9.5


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[PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Punnaiah Choudary Kalluri]

Add bindings documentation for Zynq Quad SPI driver.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
 .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   26 ++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
new file mode 100644
index 0000000..88e00f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
@@ -0,0 +1,26 @@
+Xilinx Zynq QSPI controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible		: Should be "xlnx,zynq-qspi-1.0".
+- reg			: Physical base address and size of QSPI registers map.
+- interrupts		: Property with a value describing the interrupt
+			  number.
+- interrupt-parent	: Must be core interrupt controller
+- clock-names		: List of input clock names - "ref_clk", "aper_clk"
+			  (See clock bindings for details).
+- clocks		: Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs		: Number of chip selects used.
+
+Example:
+	qspi@e000d000 {
+		compatible = "xlnx,zynq-qspi-1.0";
+		clock-names = "ref_clk", "aper_clk";
+		clocks = <&clkc 10>, <&clkc 43>;
+		interrupt-parent = <&ps7_scugic_0>;
+		interrupts = <0 19 4>;
+		num-cs = /bits/ 16 <1>;
+		reg = <0xe000d000 0x1000>;
+	};
-- 
1.7.9.5


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Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Sören Brinkmann]

Hi Punnaiah,

On Thu, 2014-04-03 at 10:33PM +0530, Punnaiah Choudary Kalluri wrote:
> Add bindings documentation for Zynq Quad SPI driver.
> 
> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> ---
>  .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   26 ++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> new file mode 100644
> index 0000000..88e00f8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> @@ -0,0 +1,26 @@
> +Xilinx Zynq QSPI controller Device Tree Bindings
> +-------------------------------------------------
> +
> +Required properties:
> +- compatible		: Should be "xlnx,zynq-qspi-1.0".
> +- reg			: Physical base address and size of QSPI registers map.
> +- interrupts		: Property with a value describing the interrupt
> +			  number.
> +- interrupt-parent	: Must be core interrupt controller
> +- clock-names		: List of input clock names - "ref_clk", "aper_clk"
> +			  (See clock bindings for details).
> +- clocks		: Clock phandles (see clock bindings for details).
> +
> +Optional properties:
> +- num-cs		: Number of chip selects used.
> +
> +Example:
> +	qspi@e000d000 {
> +		compatible = "xlnx,zynq-qspi-1.0";
> +		clock-names = "ref_clk", "aper_clk";

These seem to be the SOC names of the clocks. Doesn't have the IP its
own naming for these clock inputs?

	Sören

Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Sören Brinkmann]

Hi Punnaiah,

On Thu, 2014-04-03 at 10:33PM +0530, Punnaiah Choudary Kalluri wrote:
> Add bindings documentation for Zynq Quad SPI driver.
> 
> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> ---
>  .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   26 ++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> new file mode 100644
> index 0000000..88e00f8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> @@ -0,0 +1,26 @@
> +Xilinx Zynq QSPI controller Device Tree Bindings
> +-------------------------------------------------
> +
> +Required properties:
> +- compatible		: Should be "xlnx,zynq-qspi-1.0".
> +- reg			: Physical base address and size of QSPI registers map.
> +- interrupts		: Property with a value describing the interrupt
> +			  number.
> +- interrupt-parent	: Must be core interrupt controller
> +- clock-names		: List of input clock names - "ref_clk", "aper_clk"
> +			  (See clock bindings for details).
> +- clocks		: Clock phandles (see clock bindings for details).
> +
> +Optional properties:
> +- num-cs		: Number of chip selects used.
> +
> +Example:
> +	qspi@e000d000 {
> +		compatible = "xlnx,zynq-qspi-1.0";
> +		clock-names = "ref_clk", "aper_clk";

These seem to be the SOC names of the clocks. Doesn't have the IP its
own naming for these clock inputs?

	Sören

Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Harini Katakam]

Hi Soren

On Thu, Apr 3, 2014 at 11:20 PM, Sören Brinkmann
<soren.brinkmann@xilinx.com> wrote:
> Hi Punnaiah,
>
> On Thu, 2014-04-03 at 10:33PM +0530, Punnaiah Choudary Kalluri wrote:
>> Add bindings documentation for Zynq Quad SPI driver.
>>
>> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
>> ---
>>  .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   26 ++++++++++++++++++++
>>  1 file changed, 26 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
>>
>> diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
>> new file mode 100644
>> index 0000000..88e00f8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
>> @@ -0,0 +1,26 @@
>> +Xilinx Zynq QSPI controller Device Tree Bindings
>> +-------------------------------------------------
>> +
>> +Required properties:
>> +- compatible         : Should be "xlnx,zynq-qspi-1.0".
>> +- reg                        : Physical base address and size of QSPI registers map.
>> +- interrupts         : Property with a value describing the interrupt
>> +                       number.
>> +- interrupt-parent   : Must be core interrupt controller
>> +- clock-names                : List of input clock names - "ref_clk", "aper_clk"
>> +                       (See clock bindings for details).
>> +- clocks             : Clock phandles (see clock bindings for details).
>> +
>> +Optional properties:
>> +- num-cs             : Number of chip selects used.
>> +
>> +Example:
>> +     qspi@e000d000 {
>> +             compatible = "xlnx,zynq-qspi-1.0";
>> +             clock-names = "ref_clk", "aper_clk";
>
> These seem to be the SOC names of the clocks. Doesn't have the IP its
> own naming for these clock inputs?
>

The IP design spec uses the name ref_clk.
There is no particular clock name used for for APB clock.
So I think aper_clk is a valid name to use.

Regards,
Harini

Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Sören Brinkmann]

On Fri, 2014-04-04 at 12:15AM +0530, Harini Katakam wrote:
> Hi Soren
> 
> On Thu, Apr 3, 2014 at 11:20 PM, Sören Brinkmann
> <soren.brinkmann@xilinx.com> wrote:
> > Hi Punnaiah,
> >
> > On Thu, 2014-04-03 at 10:33PM +0530, Punnaiah Choudary Kalluri wrote:
> >> Add bindings documentation for Zynq Quad SPI driver.
> >>
> >> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> >> ---
> >>  .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   26 ++++++++++++++++++++
> >>  1 file changed, 26 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> >> new file mode 100644
> >> index 0000000..88e00f8
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> >> @@ -0,0 +1,26 @@
> >> +Xilinx Zynq QSPI controller Device Tree Bindings
> >> +-------------------------------------------------
> >> +
> >> +Required properties:
> >> +- compatible         : Should be "xlnx,zynq-qspi-1.0".
> >> +- reg                        : Physical base address and size of QSPI registers map.
> >> +- interrupts         : Property with a value describing the interrupt
> >> +                       number.
> >> +- interrupt-parent   : Must be core interrupt controller
> >> +- clock-names                : List of input clock names - "ref_clk", "aper_clk"
> >> +                       (See clock bindings for details).
> >> +- clocks             : Clock phandles (see clock bindings for details).
> >> +
> >> +Optional properties:
> >> +- num-cs             : Number of chip selects used.
> >> +
> >> +Example:
> >> +     qspi@e000d000 {
> >> +             compatible = "xlnx,zynq-qspi-1.0";
> >> +             clock-names = "ref_clk", "aper_clk";
> >
> > These seem to be the SOC names of the clocks. Doesn't have the IP its
> > own naming for these clock inputs?
> >
> 
> The IP design spec uses the name ref_clk.
> There is no particular clock name used for for APB clock.
> So I think aper_clk is a valid name to use.

aper is a Zynq-ism, IMHO. I think 'pclk', 'apbclk' or
something like that is more appropriate.

	Sören

Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Sören Brinkmann]

On Fri, 2014-04-04 at 12:15AM +0530, Harini Katakam wrote:
> Hi Soren
> 
> On Thu, Apr 3, 2014 at 11:20 PM, Sören Brinkmann
> <soren.brinkmann@xilinx.com> wrote:
> > Hi Punnaiah,
> >
> > On Thu, 2014-04-03 at 10:33PM +0530, Punnaiah Choudary Kalluri wrote:
> >> Add bindings documentation for Zynq Quad SPI driver.
> >>
> >> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> >> ---
> >>  .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   26 ++++++++++++++++++++
> >>  1 file changed, 26 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> >> new file mode 100644
> >> index 0000000..88e00f8
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> >> @@ -0,0 +1,26 @@
> >> +Xilinx Zynq QSPI controller Device Tree Bindings
> >> +-------------------------------------------------
> >> +
> >> +Required properties:
> >> +- compatible         : Should be "xlnx,zynq-qspi-1.0".
> >> +- reg                        : Physical base address and size of QSPI registers map.
> >> +- interrupts         : Property with a value describing the interrupt
> >> +                       number.
> >> +- interrupt-parent   : Must be core interrupt controller
> >> +- clock-names                : List of input clock names - "ref_clk", "aper_clk"
> >> +                       (See clock bindings for details).
> >> +- clocks             : Clock phandles (see clock bindings for details).
> >> +
> >> +Optional properties:
> >> +- num-cs             : Number of chip selects used.
> >> +
> >> +Example:
> >> +     qspi@e000d000 {
> >> +             compatible = "xlnx,zynq-qspi-1.0";
> >> +             clock-names = "ref_clk", "aper_clk";
> >
> > These seem to be the SOC names of the clocks. Doesn't have the IP its
> > own naming for these clock inputs?
> >
> 
> The IP design spec uses the name ref_clk.
> There is no particular clock name used for for APB clock.
> So I think aper_clk is a valid name to use.

aper is a Zynq-ism, IMHO. I think 'pclk', 'apbclk' or
something like that is more appropriate.

	Sören

Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Mark Brown]

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On Thu, Apr 03, 2014 at 10:33:06PM +0530, Punnaiah Choudary Kalluri wrote:

> +Optional properties:
> +- num-cs		: Number of chip selects used.

What does this translate into?

> +		num-cs = /bits/ 16 <1>;

Why the odd specification in the example - why not just specify it as a
number?

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Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Mark Brown]

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On Thu, Apr 03, 2014 at 10:33:06PM +0530, Punnaiah Choudary Kalluri wrote:

> +Optional properties:
> +- num-cs		: Number of chip selects used.

What does this translate into?

> +		num-cs = /bits/ 16 <1>;

Why the odd specification in the example - why not just specify it as a
number?

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Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Harini Katakam]

Hi Mark,

On Fri, Apr 4, 2014 at 2:31 AM, Mark Brown <broonie@kernel.org> wrote:
> On Thu, Apr 03, 2014 at 10:33:06PM +0530, Punnaiah Choudary Kalluri wrote:
>
>> +Optional properties:
>> +- num-cs             : Number of chip selects used.
>
> What does this translate into?
>
>> +             num-cs = /bits/ 16 <1>;
>
> Why the odd specification in the example - why not just specify it as a
> number?

Same as discussed on SPI cadence thread.

Regards,
Harini

Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Harini Katakam]

Hi Mark,

On Fri, Apr 4, 2014 at 2:31 AM, Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Thu, Apr 03, 2014 at 10:33:06PM +0530, Punnaiah Choudary Kalluri wrote:
>
>> +Optional properties:
>> +- num-cs             : Number of chip selects used.
>
> What does this translate into?
>
>> +             num-cs = /bits/ 16 <1>;
>
> Why the odd specification in the example - why not just specify it as a
> number?

Same as discussed on SPI cadence thread.

Regards,
Harini
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Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Michal Simek]

[-- Attachment #1: Type: text/plain, Size: 1394 bytes --]

Hi Mark and Harini,

On 04/04/2014 05:01 AM, Harini Katakam wrote:
> Hi Mark,
> 
> On Fri, Apr 4, 2014 at 2:31 AM, Mark Brown <broonie@kernel.org> wrote:
>> On Thu, Apr 03, 2014 at 10:33:06PM +0530, Punnaiah Choudary Kalluri wrote:
>>
>>> +Optional properties:
>>> +- num-cs             : Number of chip selects used.
>>
>> What does this translate into?
>>
>>> +             num-cs = /bits/ 16 <1>;
>>
>> Why the odd specification in the example - why not just specify it as a
>> number?
> 
> Same as discussed on SPI cadence thread.

I have discussed this briefly with Rob and it is more up to Mark
if he wants to have this with 16bit width or not. I expect that
"num-cs" is getting to be shared across spi drivers
and maybe in near future you will move "num-cs" of probe to spi core
that's why it should stay 32bit for easier integration.

I have asked Harini some weeks ago to try to do it just with
of_property_read_u16 because you can directly setup
master->num_chipselect and you don't need to read it as u32
and saving to u16.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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Re: [PATCH 1/2] devicetree: Add devicetree bindings documentation for Zynq Quad SPI

[Michal Simek]

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Hi Mark and Harini,

On 04/04/2014 05:01 AM, Harini Katakam wrote:
> Hi Mark,
> 
> On Fri, Apr 4, 2014 at 2:31 AM, Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>> On Thu, Apr 03, 2014 at 10:33:06PM +0530, Punnaiah Choudary Kalluri wrote:
>>
>>> +Optional properties:
>>> +- num-cs             : Number of chip selects used.
>>
>> What does this translate into?
>>
>>> +             num-cs = /bits/ 16 <1>;
>>
>> Why the odd specification in the example - why not just specify it as a
>> number?
> 
> Same as discussed on SPI cadence thread.

I have discussed this briefly with Rob and it is more up to Mark
if he wants to have this with 16bit width or not. I expect that
"num-cs" is getting to be shared across spi drivers
and maybe in near future you will move "num-cs" of probe to spi core
that's why it should stay 32bit for easier integration.

I have asked Harini some weeks ago to try to do it just with
of_property_read_u16 because you can directly setup
master->num_chipselect and you don't need to read it as u32
and saving to u16.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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