[PATCH 00/11] Exynos7: Adding USB 3.0 support

[PATCH 00/11] Exynos7: Adding USB 3.0 support

[Vivek Gautam]

The series has dependency on
a) "[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC"
   http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
b) "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt
   bindings header.
   http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142
c) "tty: serial: samsung: Clean-up selection of number of available UARTs"
   http://www.spinics.net/lists/linux-samsung-soc/msg37418.html
d) "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next)
   https://lkml.org/lkml/2014/10/21/654
e) "Samsung pinctrl patches for v3.19"
   http://www.spinics.net/lists/linux-samsung-soc/msg38744.html

Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies.

Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes
together in this series only so as to avoid having 'n' number of dependencies.

The USB driver patches in this series were part of [1] sent earlier.
[1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
    https://lkml.org/lkml/2014/10/7/191

Vivek Gautam (11):
  pinctrl: exynos: Add BUS1 pin controller for exynos7
  dwc3: exynos: Remove local variable for clock from probe
  dwc3: exynos: Add provision for suspend clock
  dwc3: exynos: Add provision for AXI UpScaler clock on exynos7
  phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support
  phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply
  phy: exynos7-usbdrd: Update dependency for ARCH_EXYNOS
  clk: exynos7: Add required clock tree for USB
  arm64: exynos: Add bus1 pinctrl node on exynos7
  arm64: dts: Enable USB 3.0 controller on exynos7
  arm64: dts: exynos7-espresso: Add regulators for Vbus and Vbus-Boost

 .../devicetree/bindings/phy/samsung-phy.txt        |    6 +
 .../devicetree/bindings/usb/exynos-usb.txt         |    6 +-
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts    |   43 +++++++
 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi    |   26 ++++
 arch/arm64/boot/dts/exynos/exynos7.dtsi            |   42 ++++++
 drivers/clk/samsung/clk-exynos7.c                  |   64 +++++++++
 drivers/phy/Kconfig                                |    2 +-
 drivers/phy/phy-exynos5-usbdrd.c                   |  136 +++++++++++++++++---
 drivers/pinctrl/samsung/pinctrl-exynos.c           |   12 ++
 drivers/usb/dwc3/dwc3-exynos.c                     |   39 +++++-
 include/dt-bindings/clock/exynos7-clk.h            |    9 +-
 11 files changed, 354 insertions(+), 31 deletions(-)

-- 
1.7.10.4

[PATCH 00/11] Exynos7: Adding USB 3.0 support

[Vivek Gautam]

The series has dependency on
a) "[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC"
   http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
b) "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt
   bindings header.
   http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142
c) "tty: serial: samsung: Clean-up selection of number of available UARTs"
   http://www.spinics.net/lists/linux-samsung-soc/msg37418.html
d) "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next)
   https://lkml.org/lkml/2014/10/21/654
e) "Samsung pinctrl patches for v3.19"
   http://www.spinics.net/lists/linux-samsung-soc/msg38744.html

Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies.

Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes
together in this series only so as to avoid having 'n' number of dependencies.

The USB driver patches in this series were part of [1] sent earlier.
[1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
    https://lkml.org/lkml/2014/10/7/191

Vivek Gautam (11):
  pinctrl: exynos: Add BUS1 pin controller for exynos7
  dwc3: exynos: Remove local variable for clock from probe
  dwc3: exynos: Add provision for suspend clock
  dwc3: exynos: Add provision for AXI UpScaler clock on exynos7
  phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support
  phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply
  phy: exynos7-usbdrd: Update dependency for ARCH_EXYNOS
  clk: exynos7: Add required clock tree for USB
  arm64: exynos: Add bus1 pinctrl node on exynos7
  arm64: dts: Enable USB 3.0 controller on exynos7
  arm64: dts: exynos7-espresso: Add regulators for Vbus and Vbus-Boost

 .../devicetree/bindings/phy/samsung-phy.txt        |    6 +
 .../devicetree/bindings/usb/exynos-usb.txt         |    6 +-
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts    |   43 +++++++
 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi    |   26 ++++
 arch/arm64/boot/dts/exynos/exynos7.dtsi            |   42 ++++++
 drivers/clk/samsung/clk-exynos7.c                  |   64 +++++++++
 drivers/phy/Kconfig                                |    2 +-
 drivers/phy/phy-exynos5-usbdrd.c                   |  136 +++++++++++++++++---
 drivers/pinctrl/samsung/pinctrl-exynos.c           |   12 ++
 drivers/usb/dwc3/dwc3-exynos.c                     |   39 +++++-
 include/dt-bindings/clock/exynos7-clk.h            |    9 +-
 11 files changed, 354 insertions(+), 31 deletions(-)

-- 
1.7.10.4

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[PATCH 01/11] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/pinctrl/samsung/pinctrl-exynos.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d5d4cfc..caca5b5 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1300,6 +1300,13 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
 	EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
 };
 
+/* pin banks of exynos7 pin-controller - BUS1 */
+static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
+	EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
+	EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
+	EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
+};
+
 const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
 	{
 		/* pin-controller instance 0 Alive data */
@@ -1342,5 +1349,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
 		.pin_banks	= exynos7_pin_banks7,
 		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks7),
 		.eint_gpio_init = exynos_eint_gpio_init,
+	}, {
+		/* pin-controller instance 8 BUS1 data */
+		.pin_banks	= exynos7_pin_banks8,
+		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks8),
+		.eint_gpio_init = exynos_eint_gpio_init,
 	},
 };
-- 
1.7.10.4

[PATCH 02/11] dwc3: exynos: Remove local variable for clock from probe

[Vivek Gautam]

There's no need to keep one local variable for clock, and
then assign the same to 'clk' member of dwc3_exynos.
Just cleaning it up.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 drivers/usb/dwc3/dwc3-exynos.c |   13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 3951a65..7109de7 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -106,7 +106,6 @@ static int dwc3_exynos_remove_child(struct device *dev, void *unused)
 static int dwc3_exynos_probe(struct platform_device *pdev)
 {
 	struct dwc3_exynos	*exynos;
-	struct clk		*clk;
 	struct device		*dev = &pdev->dev;
 	struct device_node	*node = dev->of_node;
 
@@ -133,15 +132,13 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	clk = devm_clk_get(dev, "usbdrd30");
-	if (IS_ERR(clk)) {
+	exynos->dev	= dev;
+
+	exynos->clk = devm_clk_get(dev, "usbdrd30");
+	if (IS_ERR(exynos->clk)) {
 		dev_err(dev, "couldn't get clock\n");
 		return -EINVAL;
 	}
-
-	exynos->dev	= dev;
-	exynos->clk	= clk;
-
 	clk_prepare_enable(exynos->clk);
 
 	exynos->vdd33 = devm_regulator_get(dev, "vdd33");
@@ -185,7 +182,7 @@ err4:
 err3:
 	regulator_disable(exynos->vdd33);
 err2:
-	clk_disable_unprepare(clk);
+	clk_disable_unprepare(exynos->clk);
 	return ret;
 }
 
-- 
1.7.10.4

[PATCH 03/11] dwc3: exynos: Add provision for suspend clock

[Vivek Gautam]

DWC3 controller on Exynos SoC series have separate control for
suspend clock which replaces pipe3_rx_pclk as clock source to
a small part of DWC3 core that operates when SS PHY is in its
lowest power state (P3) in states SS.disabled and U3.

Suggested-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 drivers/usb/dwc3/dwc3-exynos.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 7109de7..af15ab3 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -35,6 +35,8 @@ struct dwc3_exynos {
 	struct device		*dev;
 
 	struct clk		*clk;
+	struct clk		*susp_clk;
+
 	struct regulator	*vdd33;
 	struct regulator	*vdd10;
 };
@@ -141,6 +143,13 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
 	}
 	clk_prepare_enable(exynos->clk);
 
+	exynos->susp_clk = devm_clk_get(dev, "usbdrd30_susp_clk");
+	if (IS_ERR(exynos->susp_clk)) {
+		dev_dbg(dev, "no suspend clk specified\n");
+		exynos->susp_clk = NULL;
+	}
+	clk_prepare_enable(exynos->susp_clk);
+
 	exynos->vdd33 = devm_regulator_get(dev, "vdd33");
 	if (IS_ERR(exynos->vdd33)) {
 		ret = PTR_ERR(exynos->vdd33);
@@ -182,6 +191,7 @@ err4:
 err3:
 	regulator_disable(exynos->vdd33);
 err2:
+	clk_disable_unprepare(exynos->susp_clk);
 	clk_disable_unprepare(exynos->clk);
 	return ret;
 }
@@ -194,6 +204,7 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
 	platform_device_unregister(exynos->usb2_phy);
 	platform_device_unregister(exynos->usb3_phy);
 
+	clk_disable_unprepare(exynos->susp_clk);
 	clk_disable_unprepare(exynos->clk);
 
 	regulator_disable(exynos->vdd33);
-- 
1.7.10.4

[PATCH 03/11] dwc3: exynos: Add provision for suspend clock

[Vivek Gautam]

DWC3 controller on Exynos SoC series have separate control for
suspend clock which replaces pipe3_rx_pclk as clock source to
a small part of DWC3 core that operates when SS PHY is in its
lowest power state (P3) in states SS.disabled and U3.

Suggested-by: Anton Tikhomirov <av.tikhomirov-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 drivers/usb/dwc3/dwc3-exynos.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 7109de7..af15ab3 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -35,6 +35,8 @@ struct dwc3_exynos {
 	struct device		*dev;
 
 	struct clk		*clk;
+	struct clk		*susp_clk;
+
 	struct regulator	*vdd33;
 	struct regulator	*vdd10;
 };
@@ -141,6 +143,13 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
 	}
 	clk_prepare_enable(exynos->clk);
 
+	exynos->susp_clk = devm_clk_get(dev, "usbdrd30_susp_clk");
+	if (IS_ERR(exynos->susp_clk)) {
+		dev_dbg(dev, "no suspend clk specified\n");
+		exynos->susp_clk = NULL;
+	}
+	clk_prepare_enable(exynos->susp_clk);
+
 	exynos->vdd33 = devm_regulator_get(dev, "vdd33");
 	if (IS_ERR(exynos->vdd33)) {
 		ret = PTR_ERR(exynos->vdd33);
@@ -182,6 +191,7 @@ err4:
 err3:
 	regulator_disable(exynos->vdd33);
 err2:
+	clk_disable_unprepare(exynos->susp_clk);
 	clk_disable_unprepare(exynos->clk);
 	return ret;
 }
@@ -194,6 +204,7 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
 	platform_device_unregister(exynos->usb2_phy);
 	platform_device_unregister(exynos->usb3_phy);
 
+	clk_disable_unprepare(exynos->susp_clk);
 	clk_disable_unprepare(exynos->clk);
 
 	regulator_disable(exynos->vdd33);
-- 
1.7.10.4

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[PATCH 04/11] dwc3: exynos: Add provision for AXI UpScaler clock on exynos7

[Vivek Gautam]

DWC3 controller on Exynos7 SoC has separate control for
AXI UpScaler which connects DWC3 DRD controller to AXI bus.
Get the gate clock for the same to control it across power
cycles.

Suggested-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 Documentation/devicetree/bindings/usb/exynos-usb.txt |    6 ++++--
 drivers/usb/dwc3/dwc3-exynos.c                       |   17 +++++++++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index a3b5990..9b4dbe3 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -82,8 +82,10 @@ Example:
 
 DWC3
 Required properties:
- - compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3
-	       controller.
+ - compatible: should be one of the following -
+	       "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
+					    Exynos5250/5420.
+	       "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
  - #address-cells, #size-cells : should be '1' if the device has sub-nodes
 				 with 'reg' property.
  - ranges: allows valid 1:1 translation between child's address space and
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index af15ab3..6ae8fe5 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -36,6 +36,7 @@ struct dwc3_exynos {
 
 	struct clk		*clk;
 	struct clk		*susp_clk;
+	struct clk		*axius_clk;
 
 	struct regulator	*vdd33;
 	struct regulator	*vdd10;
@@ -150,6 +151,17 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
 	}
 	clk_prepare_enable(exynos->susp_clk);
 
+	if (of_device_is_compatible(node, "samsung,exynos7-dwusb3")) {
+		exynos->axius_clk = devm_clk_get(dev, "usbdrd30_axius_clk");
+		if (IS_ERR(exynos->axius_clk)) {
+			dev_err(dev, "no AXI UpScaler clk specified\n");
+			return -ENODEV;
+		}
+		clk_prepare_enable(exynos->axius_clk);
+	} else {
+		exynos->axius_clk = NULL;
+	}
+
 	exynos->vdd33 = devm_regulator_get(dev, "vdd33");
 	if (IS_ERR(exynos->vdd33)) {
 		ret = PTR_ERR(exynos->vdd33);
@@ -191,6 +203,7 @@ err4:
 err3:
 	regulator_disable(exynos->vdd33);
 err2:
+	clk_disable_unprepare(exynos->axius_clk);
 	clk_disable_unprepare(exynos->susp_clk);
 	clk_disable_unprepare(exynos->clk);
 	return ret;
@@ -204,6 +217,7 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
 	platform_device_unregister(exynos->usb2_phy);
 	platform_device_unregister(exynos->usb3_phy);
 
+	clk_disable_unprepare(exynos->axius_clk);
 	clk_disable_unprepare(exynos->susp_clk);
 	clk_disable_unprepare(exynos->clk);
 
@@ -216,6 +230,7 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
 #ifdef CONFIG_OF
 static const struct of_device_id exynos_dwc3_match[] = {
 	{ .compatible = "samsung,exynos5250-dwusb3" },
+	{ .compatible = "samsung,exynos7-dwusb3" },
 	{},
 };
 MODULE_DEVICE_TABLE(of, exynos_dwc3_match);
@@ -226,6 +241,7 @@ static int dwc3_exynos_suspend(struct device *dev)
 {
 	struct dwc3_exynos *exynos = dev_get_drvdata(dev);
 
+	clk_disable(exynos->axius_clk);
 	clk_disable(exynos->clk);
 
 	regulator_disable(exynos->vdd33);
@@ -251,6 +267,7 @@ static int dwc3_exynos_resume(struct device *dev)
 	}
 
 	clk_enable(exynos->clk);
+	clk_enable(exynos->axius_clk);
 
 	/* runtime set active to reflect active state. */
 	pm_runtime_disable(dev);
-- 
1.7.10.4

[PATCH 05/11] phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support

[Vivek Gautam]

Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
Additionally, separate gate control is available for the clock
used for ITP (Isochronous Transfer Packet) generation.

So get the same and control in the phy-exynos5-usbdrd driver.

Suggested-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 .../devicetree/bindings/phy/samsung-phy.txt        |    6 ++
 drivers/phy/phy-exynos5-usbdrd.c                   |  104 ++++++++++++++++----
 2 files changed, 92 insertions(+), 18 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 15e0f2c..d5bad92 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -128,6 +128,7 @@ Required properties:
 - compatible : Should be set to one of the following supported values:
 	- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
 	- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
+	- "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
 - reg : Register offset and length of USB DRD PHY register set;
 - clocks: Clock IDs array as required by the controller
 - clock-names: names of clocks correseponding to IDs in the clock property;
@@ -138,6 +139,11 @@ Required properties:
 	       PHY operations, associated by phy name. It is used to
 	       determine bit values for clock settings register.
 	       For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
+	- optional clocks: Exynos7 SoC has now following additional
+			   gate clocks available:
+			   - phy_pipe: for PIPE3 phy
+			   - phy_utmi: for UTMI+ phy
+			   - itp: for ITP generation
 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
 		      control pmu registers for power isolation.
 - #phy-cells : from the generic PHY bindings, must be 1;
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index f756aca..3654712 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -141,6 +141,7 @@ struct exynos5_usbdrd_phy_drvdata {
 	const struct exynos5_usbdrd_phy_config *phy_cfg;
 	u32 pmu_offset_usbdrd0_phy;
 	u32 pmu_offset_usbdrd1_phy;
+	bool has_common_clk_gate;
 };
 
 /**
@@ -148,6 +149,9 @@ struct exynos5_usbdrd_phy_drvdata {
  * @dev: pointer to device instance of this platform device
  * @reg_phy: usb phy controller register memory base
  * @clk: phy clock for register access
+ * @pipeclk: clock for pipe3 phy
+ * @utmiclk: clock for utmi+ phy
+ * @itpclk: clock for ITP generation
  * @drv_data: pointer to SoC level driver data structure
  * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
  *	    instances each with its 'phy' and 'phy_cfg'.
@@ -155,12 +159,14 @@ struct exynos5_usbdrd_phy_drvdata {
  *	       reference clocks' for SS and HS operations
  * @ref_clk: reference clock to PHY block from which PHY's
  *	     operational clocks are derived
- * @ref_rate: rate of above reference clock
  */
 struct exynos5_usbdrd_phy {
 	struct device *dev;
 	void __iomem *reg_phy;
 	struct clk *clk;
+	struct clk *pipeclk;
+	struct clk *utmiclk;
+	struct clk *itpclk;
 	const struct exynos5_usbdrd_phy_drvdata *drv_data;
 	struct phy_usb_instance {
 		struct phy *phy;
@@ -447,6 +453,11 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
 	dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
 
 	clk_prepare_enable(phy_drd->ref_clk);
+	if (!phy_drd->drv_data->has_common_clk_gate) {
+		clk_prepare_enable(phy_drd->pipeclk);
+		clk_prepare_enable(phy_drd->utmiclk);
+		clk_prepare_enable(phy_drd->itpclk);
+	}
 
 	/* Enable VBUS supply */
 	if (phy_drd->vbus) {
@@ -464,6 +475,11 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
 
 fail_vbus:
 	clk_disable_unprepare(phy_drd->ref_clk);
+	if (!phy_drd->drv_data->has_common_clk_gate) {
+		clk_disable_unprepare(phy_drd->itpclk);
+		clk_disable_unprepare(phy_drd->utmiclk);
+		clk_disable_unprepare(phy_drd->pipeclk);
+	}
 
 	return ret;
 }
@@ -483,6 +499,11 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
 		regulator_disable(phy_drd->vbus);
 
 	clk_disable_unprepare(phy_drd->ref_clk);
+	if (!phy_drd->drv_data->has_common_clk_gate) {
+		clk_disable_unprepare(phy_drd->itpclk);
+		clk_disable_unprepare(phy_drd->pipeclk);
+		clk_disable_unprepare(phy_drd->utmiclk);
+	}
 
 	return 0;
 }
@@ -506,6 +527,57 @@ static struct phy_ops exynos5_usbdrd_phy_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
+{
+	unsigned long ref_rate;
+	int ret;
+
+	phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
+	if (IS_ERR(phy_drd->clk)) {
+		dev_err(phy_drd->dev, "Failed to get phy clock\n");
+		return PTR_ERR(phy_drd->clk);
+	}
+
+	phy_drd->ref_clk = devm_clk_get(phy_drd->dev, "ref");
+	if (IS_ERR(phy_drd->ref_clk)) {
+		dev_err(phy_drd->dev, "Failed to get phy reference clock\n");
+		return PTR_ERR(phy_drd->ref_clk);
+	}
+	ref_rate = clk_get_rate(phy_drd->ref_clk);
+
+	ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
+	if (ret) {
+		dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
+			ref_rate);
+		return ret;
+	}
+
+	if (!phy_drd->drv_data->has_common_clk_gate) {
+		phy_drd->pipeclk = devm_clk_get(phy_drd->dev, "phy_pipe");
+		if (IS_ERR(phy_drd->pipeclk)) {
+			dev_info(phy_drd->dev,
+				 "PIPE3 phy operational clock not specified\n");
+			phy_drd->pipeclk = NULL;
+		}
+
+		phy_drd->utmiclk = devm_clk_get(phy_drd->dev, "phy_utmi");
+		if (IS_ERR(phy_drd->utmiclk)) {
+			dev_info(phy_drd->dev,
+				 "UTMI phy operational clock not specified\n");
+			phy_drd->utmiclk = NULL;
+		}
+
+		phy_drd->itpclk = devm_clk_get(phy_drd->dev, "itp");
+		if (IS_ERR(phy_drd->itpclk)) {
+			dev_info(phy_drd->dev,
+				 "ITP clock from main OSC not specified\n");
+			phy_drd->itpclk = NULL;
+		}
+	}
+
+	return 0;
+}
+
 static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
 	{
 		.id		= EXYNOS5_DRDPHY_UTMI,
@@ -525,11 +597,19 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
 	.phy_cfg		= phy_cfg_exynos5,
 	.pmu_offset_usbdrd0_phy	= EXYNOS5_USBDRD_PHY_CONTROL,
 	.pmu_offset_usbdrd1_phy	= EXYNOS5420_USBDRD1_PHY_CONTROL,
+	.has_common_clk_gate	= true,
 };
 
 static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
 	.phy_cfg		= phy_cfg_exynos5,
 	.pmu_offset_usbdrd0_phy	= EXYNOS5_USBDRD_PHY_CONTROL,
+	.has_common_clk_gate	= true,
+};
+
+static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
+	.phy_cfg		= phy_cfg_exynos5,
+	.pmu_offset_usbdrd0_phy	= EXYNOS5_USBDRD_PHY_CONTROL,
+	.has_common_clk_gate	= false,
 };
 
 static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
@@ -539,6 +619,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
 	}, {
 		.compatible = "samsung,exynos5420-usbdrd-phy",
 		.data = &exynos5420_usbdrd_phy
+	}, {
+		.compatible = "samsung,exynos7-usbdrd-phy",
+		.data = &exynos7_usbdrd_phy
 	},
 	{ },
 };
@@ -555,7 +638,6 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
 	const struct exynos5_usbdrd_phy_drvdata *drv_data;
 	struct regmap *reg_pmu;
 	u32 pmu_offset;
-	unsigned long ref_rate;
 	int i, ret;
 	int channel;
 
@@ -576,23 +658,9 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
 	drv_data = match->data;
 	phy_drd->drv_data = drv_data;
 
-	phy_drd->clk = devm_clk_get(dev, "phy");
-	if (IS_ERR(phy_drd->clk)) {
-		dev_err(dev, "Failed to get clock of phy controller\n");
-		return PTR_ERR(phy_drd->clk);
-	}
-
-	phy_drd->ref_clk = devm_clk_get(dev, "ref");
-	if (IS_ERR(phy_drd->ref_clk)) {
-		dev_err(dev, "Failed to get reference clock of usbdrd phy\n");
-		return PTR_ERR(phy_drd->ref_clk);
-	}
-	ref_rate = clk_get_rate(phy_drd->ref_clk);
-
-	ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
+	ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
 	if (ret) {
-		dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
-			ref_rate);
+		dev_err(dev, "Failed to initialize clocks\n");
 		return ret;
 	}
 
-- 
1.7.10.4

[PATCH 05/11] phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support

[Vivek Gautam]

Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
Additionally, separate gate control is available for the clock
used for ITP (Isochronous Transfer Packet) generation.

So get the same and control in the phy-exynos5-usbdrd driver.

Suggested-by: Anton Tikhomirov <av.tikhomirov-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/phy/samsung-phy.txt        |    6 ++
 drivers/phy/phy-exynos5-usbdrd.c                   |  104 ++++++++++++++++----
 2 files changed, 92 insertions(+), 18 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 15e0f2c..d5bad92 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -128,6 +128,7 @@ Required properties:
 - compatible : Should be set to one of the following supported values:
 	- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
 	- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
+	- "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
 - reg : Register offset and length of USB DRD PHY register set;
 - clocks: Clock IDs array as required by the controller
 - clock-names: names of clocks correseponding to IDs in the clock property;
@@ -138,6 +139,11 @@ Required properties:
 	       PHY operations, associated by phy name. It is used to
 	       determine bit values for clock settings register.
 	       For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
+	- optional clocks: Exynos7 SoC has now following additional
+			   gate clocks available:
+			   - phy_pipe: for PIPE3 phy
+			   - phy_utmi: for UTMI+ phy
+			   - itp: for ITP generation
 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
 		      control pmu registers for power isolation.
 - #phy-cells : from the generic PHY bindings, must be 1;
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index f756aca..3654712 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -141,6 +141,7 @@ struct exynos5_usbdrd_phy_drvdata {
 	const struct exynos5_usbdrd_phy_config *phy_cfg;
 	u32 pmu_offset_usbdrd0_phy;
 	u32 pmu_offset_usbdrd1_phy;
+	bool has_common_clk_gate;
 };
 
 /**
@@ -148,6 +149,9 @@ struct exynos5_usbdrd_phy_drvdata {
  * @dev: pointer to device instance of this platform device
  * @reg_phy: usb phy controller register memory base
  * @clk: phy clock for register access
+ * @pipeclk: clock for pipe3 phy
+ * @utmiclk: clock for utmi+ phy
+ * @itpclk: clock for ITP generation
  * @drv_data: pointer to SoC level driver data structure
  * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
  *	    instances each with its 'phy' and 'phy_cfg'.
@@ -155,12 +159,14 @@ struct exynos5_usbdrd_phy_drvdata {
  *	       reference clocks' for SS and HS operations
  * @ref_clk: reference clock to PHY block from which PHY's
  *	     operational clocks are derived
- * @ref_rate: rate of above reference clock
  */
 struct exynos5_usbdrd_phy {
 	struct device *dev;
 	void __iomem *reg_phy;
 	struct clk *clk;
+	struct clk *pipeclk;
+	struct clk *utmiclk;
+	struct clk *itpclk;
 	const struct exynos5_usbdrd_phy_drvdata *drv_data;
 	struct phy_usb_instance {
 		struct phy *phy;
@@ -447,6 +453,11 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
 	dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
 
 	clk_prepare_enable(phy_drd->ref_clk);
+	if (!phy_drd->drv_data->has_common_clk_gate) {
+		clk_prepare_enable(phy_drd->pipeclk);
+		clk_prepare_enable(phy_drd->utmiclk);
+		clk_prepare_enable(phy_drd->itpclk);
+	}
 
 	/* Enable VBUS supply */
 	if (phy_drd->vbus) {
@@ -464,6 +475,11 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
 
 fail_vbus:
 	clk_disable_unprepare(phy_drd->ref_clk);
+	if (!phy_drd->drv_data->has_common_clk_gate) {
+		clk_disable_unprepare(phy_drd->itpclk);
+		clk_disable_unprepare(phy_drd->utmiclk);
+		clk_disable_unprepare(phy_drd->pipeclk);
+	}
 
 	return ret;
 }
@@ -483,6 +499,11 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
 		regulator_disable(phy_drd->vbus);
 
 	clk_disable_unprepare(phy_drd->ref_clk);
+	if (!phy_drd->drv_data->has_common_clk_gate) {
+		clk_disable_unprepare(phy_drd->itpclk);
+		clk_disable_unprepare(phy_drd->pipeclk);
+		clk_disable_unprepare(phy_drd->utmiclk);
+	}
 
 	return 0;
 }
@@ -506,6 +527,57 @@ static struct phy_ops exynos5_usbdrd_phy_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
+{
+	unsigned long ref_rate;
+	int ret;
+
+	phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
+	if (IS_ERR(phy_drd->clk)) {
+		dev_err(phy_drd->dev, "Failed to get phy clock\n");
+		return PTR_ERR(phy_drd->clk);
+	}
+
+	phy_drd->ref_clk = devm_clk_get(phy_drd->dev, "ref");
+	if (IS_ERR(phy_drd->ref_clk)) {
+		dev_err(phy_drd->dev, "Failed to get phy reference clock\n");
+		return PTR_ERR(phy_drd->ref_clk);
+	}
+	ref_rate = clk_get_rate(phy_drd->ref_clk);
+
+	ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
+	if (ret) {
+		dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
+			ref_rate);
+		return ret;
+	}
+
+	if (!phy_drd->drv_data->has_common_clk_gate) {
+		phy_drd->pipeclk = devm_clk_get(phy_drd->dev, "phy_pipe");
+		if (IS_ERR(phy_drd->pipeclk)) {
+			dev_info(phy_drd->dev,
+				 "PIPE3 phy operational clock not specified\n");
+			phy_drd->pipeclk = NULL;
+		}
+
+		phy_drd->utmiclk = devm_clk_get(phy_drd->dev, "phy_utmi");
+		if (IS_ERR(phy_drd->utmiclk)) {
+			dev_info(phy_drd->dev,
+				 "UTMI phy operational clock not specified\n");
+			phy_drd->utmiclk = NULL;
+		}
+
+		phy_drd->itpclk = devm_clk_get(phy_drd->dev, "itp");
+		if (IS_ERR(phy_drd->itpclk)) {
+			dev_info(phy_drd->dev,
+				 "ITP clock from main OSC not specified\n");
+			phy_drd->itpclk = NULL;
+		}
+	}
+
+	return 0;
+}
+
 static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
 	{
 		.id		= EXYNOS5_DRDPHY_UTMI,
@@ -525,11 +597,19 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
 	.phy_cfg		= phy_cfg_exynos5,
 	.pmu_offset_usbdrd0_phy	= EXYNOS5_USBDRD_PHY_CONTROL,
 	.pmu_offset_usbdrd1_phy	= EXYNOS5420_USBDRD1_PHY_CONTROL,
+	.has_common_clk_gate	= true,
 };
 
 static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
 	.phy_cfg		= phy_cfg_exynos5,
 	.pmu_offset_usbdrd0_phy	= EXYNOS5_USBDRD_PHY_CONTROL,
+	.has_common_clk_gate	= true,
+};
+
+static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
+	.phy_cfg		= phy_cfg_exynos5,
+	.pmu_offset_usbdrd0_phy	= EXYNOS5_USBDRD_PHY_CONTROL,
+	.has_common_clk_gate	= false,
 };
 
 static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
@@ -539,6 +619,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
 	}, {
 		.compatible = "samsung,exynos5420-usbdrd-phy",
 		.data = &exynos5420_usbdrd_phy
+	}, {
+		.compatible = "samsung,exynos7-usbdrd-phy",
+		.data = &exynos7_usbdrd_phy
 	},
 	{ },
 };
@@ -555,7 +638,6 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
 	const struct exynos5_usbdrd_phy_drvdata *drv_data;
 	struct regmap *reg_pmu;
 	u32 pmu_offset;
-	unsigned long ref_rate;
 	int i, ret;
 	int channel;
 
@@ -576,23 +658,9 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
 	drv_data = match->data;
 	phy_drd->drv_data = drv_data;
 
-	phy_drd->clk = devm_clk_get(dev, "phy");
-	if (IS_ERR(phy_drd->clk)) {
-		dev_err(dev, "Failed to get clock of phy controller\n");
-		return PTR_ERR(phy_drd->clk);
-	}
-
-	phy_drd->ref_clk = devm_clk_get(dev, "ref");
-	if (IS_ERR(phy_drd->ref_clk)) {
-		dev_err(dev, "Failed to get reference clock of usbdrd phy\n");
-		return PTR_ERR(phy_drd->ref_clk);
-	}
-	ref_rate = clk_get_rate(phy_drd->ref_clk);
-
-	ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
+	ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
 	if (ret) {
-		dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
-			ref_rate);
+		dev_err(dev, "Failed to initialize clocks\n");
 		return ret;
 	}
 
-- 
1.7.10.4

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[PATCH 06/11] phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply

[Vivek Gautam]

Some Exynos boards have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 drivers/phy/phy-exynos5-usbdrd.c |   32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index 3654712..1f54639 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -159,6 +159,8 @@ struct exynos5_usbdrd_phy_drvdata {
  *	       reference clocks' for SS and HS operations
  * @ref_clk: reference clock to PHY block from which PHY's
  *	     operational clocks are derived
+ * vbus: VBUS regulator for phy
+ * vbus_boost: Boost regulator for VBUS present on few Exynos boards
  */
 struct exynos5_usbdrd_phy {
 	struct device *dev;
@@ -178,6 +180,7 @@ struct exynos5_usbdrd_phy {
 	u32 extrefclk;
 	struct clk *ref_clk;
 	struct regulator *vbus;
+	struct regulator *vbus_boost;
 };
 
 static inline
@@ -460,11 +463,20 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
 	}
 
 	/* Enable VBUS supply */
+	if (phy_drd->vbus_boost) {
+		ret = regulator_enable(phy_drd->vbus_boost);
+		if (ret) {
+			dev_err(phy_drd->dev,
+				"Failed to enable VBUS boost supply\n");
+			goto fail_vbus;
+		}
+	}
+
 	if (phy_drd->vbus) {
 		ret = regulator_enable(phy_drd->vbus);
 		if (ret) {
 			dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
-			goto fail_vbus;
+			goto fail_vbus_boost;
 		}
 	}
 
@@ -473,6 +485,10 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
 
 	return 0;
 
+fail_vbus_boost:
+	if (phy_drd->vbus_boost)
+		regulator_disable(phy_drd->vbus_boost);
+
 fail_vbus:
 	clk_disable_unprepare(phy_drd->ref_clk);
 	if (!phy_drd->drv_data->has_common_clk_gate) {
@@ -497,6 +513,8 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
 	/* Disable VBUS supply */
 	if (phy_drd->vbus)
 		regulator_disable(phy_drd->vbus);
+	if (phy_drd->vbus_boost)
+		regulator_disable(phy_drd->vbus_boost);
 
 	clk_disable_unprepare(phy_drd->ref_clk);
 	if (!phy_drd->drv_data->has_common_clk_gate) {
@@ -690,7 +708,7 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
 		break;
 	}
 
-	/* Get Vbus regulator */
+	/* Get Vbus regulators */
 	phy_drd->vbus = devm_regulator_get(dev, "vbus");
 	if (IS_ERR(phy_drd->vbus)) {
 		ret = PTR_ERR(phy_drd->vbus);
@@ -701,6 +719,16 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
 		phy_drd->vbus = NULL;
 	}
 
+	phy_drd->vbus_boost = devm_regulator_get(dev, "vbus-boost");
+	if (IS_ERR(phy_drd->vbus_boost)) {
+		ret = PTR_ERR(phy_drd->vbus_boost);
+		if (ret == -EPROBE_DEFER)
+			return ret;
+
+		dev_warn(dev, "Failed to get VBUS boost supply regulator\n");
+		phy_drd->vbus_boost = NULL;
+	}
+
 	dev_vdbg(dev, "Creating usbdrd_phy phy\n");
 
 	for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
-- 
1.7.10.4

[PATCH 07/11] phy: exynos7-usbdrd: Update dependency for ARCH_EXYNOS

[Vivek Gautam]

This PHY controller is also present on Exynos7 platform
in arch-exynos family.
So PHY_EXYNOS5_USBDRD should now depend on ARCH_EXYNOS.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 drivers/phy/Kconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2a436e6..1514e40 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -193,7 +193,7 @@ config PHY_EXYNOS5250_USB2
 
 config PHY_EXYNOS5_USBDRD
 	tristate "Exynos5 SoC series USB DRD PHY driver"
-	depends on ARCH_EXYNOS5 && OF
+	depends on ARCH_EXYNOS && OF
 	depends on HAS_IOMEM
 	depends on USB_DWC3_EXYNOS
 	select GENERIC_PHY
-- 
1.7.10.4

[PATCH 08/11] clk: exynos7: Add required clock tree for USB

[Vivek Gautam]

Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   64 +++++++++++++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h |    9 ++++-
 2 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index ea4483b..3128593 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -343,6 +343,8 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
 	MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
 
 	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+	MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
+		MUX_SEL_TOP1_FSYS0, 28, 2),
 
 	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
 	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
@@ -356,6 +358,8 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
 
 	DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
 		DIV_TOP1_FSYS0, 24, 4),
+	DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
+		DIV_TOP1_FSYS0, 28, 4),
 
 	DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
 		DIV_TOP1_FSYS1, 24, 4),
@@ -366,6 +370,8 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
 static struct samsung_gate_clock top1_gate_clks[] __initdata = {
 	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
 		ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
+	GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
+		ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
 
 	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
 		ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
@@ -647,7 +653,12 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
 #define MUX_SEL_FSYS00			0x0200
 #define MUX_SEL_FSYS01			0x0204
+#define MUX_SEL_FSYS02			0x0208
+#define ENABLE_ACLK_FSYS00		0x0800
 #define ENABLE_ACLK_FSYS01		0x0804
+#define ENABLE_SCLK_FSYS01		0x0A04
+#define ENABLE_SCLK_FSYS02		0x0A08
+#define ENABLE_SCLK_FSYS04		0x0A10
 
 /*
  * List of parent clocks for Muxes in CMU_FSYS0
@@ -655,10 +666,29 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 PNAME(mout_aclk_fsys0_200_p)	= { "fin_pll", "dout_aclk_fsys0_200" };
 PNAME(mout_sclk_mmc2_p)		= { "fin_pll", "sclk_mmc2" };
 
+PNAME(mout_sclk_usbdrd300_p)	= { "fin_pll", "sclk_usbdrd300" };
+PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p)	= { "fin_pll",
+				"phyclk_usbdrd300_udrd30_phyclock" };
+PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p)	= { "fin_pll",
+				"phyclk_usbdrd300_udrd30_pipe_pclk" };
+
+/* fixed rate clocks used in the FSYS0 block */
+struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
+	FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL,
+		CLK_IS_ROOT, 60000000),
+	FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL,
+		CLK_IS_ROOT, 125000000),
+};
+
 static unsigned long fsys0_clk_regs[] __initdata = {
 	MUX_SEL_FSYS00,
 	MUX_SEL_FSYS01,
+	MUX_SEL_FSYS02,
+	ENABLE_ACLK_FSYS00,
 	ENABLE_ACLK_FSYS01,
+	ENABLE_SCLK_FSYS01,
+	ENABLE_SCLK_FSYS02,
+	ENABLE_SCLK_FSYS04,
 };
 
 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
@@ -666,11 +696,45 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
 		MUX_SEL_FSYS00, 24, 1),
 
 	MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
+	MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
+		MUX_SEL_FSYS01, 28, 1),
+
+	MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
+		mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
+		MUX_SEL_FSYS02, 24, 1),
+	MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
+		mout_phyclk_usbdrd300_udrd30_phyclk_p,
+		MUX_SEL_FSYS02, 28, 1),
 };
 
 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
+	GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
+		"mout_aclk_fsys0_200_user",
+		ENABLE_ACLK_FSYS00, 19, 0, 0),
+
+	GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
+		ENABLE_ACLK_FSYS01, 29, 0, 0),
 	GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
 		ENABLE_ACLK_FSYS01, 31, 0, 0),
+
+	GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
+		"mout_sclk_usbdrd300_user",
+		ENABLE_SCLK_FSYS01, 4, 0, 0),
+	GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
+		ENABLE_SCLK_FSYS01, 8, 0, 0),
+
+	GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
+		"phyclk_usbdrd300_udrd30_pipe_pclk_user",
+		"mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
+		ENABLE_SCLK_FSYS02, 24, 0, 0),
+	GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
+		"phyclk_usbdrd300_udrd30_phyclk_user",
+		"mout_phyclk_usbdrd300_udrd30_phyclk_user",
+		ENABLE_SCLK_FSYS02, 28, 0, 0),
+
+	GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
+		"fin_pll",
+		ENABLE_SCLK_FSYS04, 28, 0, 0),
 };
 
 static struct samsung_cmu_info fsys0_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 8e4681b..eef2116 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -82,7 +82,14 @@
 
 /* FSYS0 */
 #define ACLK_MMC2			1
-#define FSYS0_NR_CLK			2
+#define ACLK_AXIUS_USBDRD30X_FSYS0X	2
+#define ACLK_USBDRD300			3
+#define SCLK_USBDRD300_SUSPENDCLK	4
+#define SCLK_USBDRD300_REFCLK		5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY		8
+#define FSYS0_NR_CLK			9
 
 /* FSYS1 */
 #define ACLK_MMC1			1
-- 
1.7.10.4

[PATCH 08/11] clk: exynos7: Add required clock tree for USB

[Vivek Gautam]

Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.

Signed-off-by: Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 drivers/clk/samsung/clk-exynos7.c       |   64 +++++++++++++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h |    9 ++++-
 2 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index ea4483b..3128593 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -343,6 +343,8 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
 	MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
 
 	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+	MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
+		MUX_SEL_TOP1_FSYS0, 28, 2),
 
 	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
 	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
@@ -356,6 +358,8 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
 
 	DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
 		DIV_TOP1_FSYS0, 24, 4),
+	DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
+		DIV_TOP1_FSYS0, 28, 4),
 
 	DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
 		DIV_TOP1_FSYS1, 24, 4),
@@ -366,6 +370,8 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
 static struct samsung_gate_clock top1_gate_clks[] __initdata = {
 	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
 		ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
+	GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
+		ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
 
 	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
 		ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
@@ -647,7 +653,12 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
 #define MUX_SEL_FSYS00			0x0200
 #define MUX_SEL_FSYS01			0x0204
+#define MUX_SEL_FSYS02			0x0208
+#define ENABLE_ACLK_FSYS00		0x0800
 #define ENABLE_ACLK_FSYS01		0x0804
+#define ENABLE_SCLK_FSYS01		0x0A04
+#define ENABLE_SCLK_FSYS02		0x0A08
+#define ENABLE_SCLK_FSYS04		0x0A10
 
 /*
  * List of parent clocks for Muxes in CMU_FSYS0
@@ -655,10 +666,29 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 PNAME(mout_aclk_fsys0_200_p)	= { "fin_pll", "dout_aclk_fsys0_200" };
 PNAME(mout_sclk_mmc2_p)		= { "fin_pll", "sclk_mmc2" };
 
+PNAME(mout_sclk_usbdrd300_p)	= { "fin_pll", "sclk_usbdrd300" };
+PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p)	= { "fin_pll",
+				"phyclk_usbdrd300_udrd30_phyclock" };
+PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p)	= { "fin_pll",
+				"phyclk_usbdrd300_udrd30_pipe_pclk" };
+
+/* fixed rate clocks used in the FSYS0 block */
+struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
+	FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL,
+		CLK_IS_ROOT, 60000000),
+	FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL,
+		CLK_IS_ROOT, 125000000),
+};
+
 static unsigned long fsys0_clk_regs[] __initdata = {
 	MUX_SEL_FSYS00,
 	MUX_SEL_FSYS01,
+	MUX_SEL_FSYS02,
+	ENABLE_ACLK_FSYS00,
 	ENABLE_ACLK_FSYS01,
+	ENABLE_SCLK_FSYS01,
+	ENABLE_SCLK_FSYS02,
+	ENABLE_SCLK_FSYS04,
 };
 
 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
@@ -666,11 +696,45 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
 		MUX_SEL_FSYS00, 24, 1),
 
 	MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
+	MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
+		MUX_SEL_FSYS01, 28, 1),
+
+	MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
+		mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
+		MUX_SEL_FSYS02, 24, 1),
+	MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
+		mout_phyclk_usbdrd300_udrd30_phyclk_p,
+		MUX_SEL_FSYS02, 28, 1),
 };
 
 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
+	GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
+		"mout_aclk_fsys0_200_user",
+		ENABLE_ACLK_FSYS00, 19, 0, 0),
+
+	GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
+		ENABLE_ACLK_FSYS01, 29, 0, 0),
 	GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
 		ENABLE_ACLK_FSYS01, 31, 0, 0),
+
+	GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
+		"mout_sclk_usbdrd300_user",
+		ENABLE_SCLK_FSYS01, 4, 0, 0),
+	GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
+		ENABLE_SCLK_FSYS01, 8, 0, 0),
+
+	GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
+		"phyclk_usbdrd300_udrd30_pipe_pclk_user",
+		"mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
+		ENABLE_SCLK_FSYS02, 24, 0, 0),
+	GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
+		"phyclk_usbdrd300_udrd30_phyclk_user",
+		"mout_phyclk_usbdrd300_udrd30_phyclk_user",
+		ENABLE_SCLK_FSYS02, 28, 0, 0),
+
+	GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
+		"fin_pll",
+		ENABLE_SCLK_FSYS04, 28, 0, 0),
 };
 
 static struct samsung_cmu_info fsys0_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 8e4681b..eef2116 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -82,7 +82,14 @@
 
 /* FSYS0 */
 #define ACLK_MMC2			1
-#define FSYS0_NR_CLK			2
+#define ACLK_AXIUS_USBDRD30X_FSYS0X	2
+#define ACLK_USBDRD300			3
+#define SCLK_USBDRD300_SUSPENDCLK	4
+#define SCLK_USBDRD300_REFCLK		5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY		8
+#define FSYS0_NR_CLK			9
 
 /* FSYS1 */
 #define ACLK_MMC1			1
-- 
1.7.10.4

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[PATCH 09/11] arm64: exynos: Add bus1 pinctrl node on exynos7

[Vivek Gautam]

BUS1 pinctrl provides gpios for usb and power regulator
available on exynos7-espresso board. So add relevant device
node for pinctrl-bus1.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi |   26 +++++++++++++++++++++++
 arch/arm64/boot/dts/exynos/exynos7.dtsi         |    7 ++++++
 2 files changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index 2eef4a2..9648e03 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -335,6 +335,32 @@
 	};
 };
 
+&pinctrl_bus1 {
+	gpf0: gpf0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf4: gpf4 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gph1: gph1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
 &pinctrl_nfc {
 	gpj0: gpj0 {
 		gpio-controller;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index d7a37c3..90048b2 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -26,6 +26,7 @@
 		pinctrl5 = &pinctrl_ese;
 		pinctrl6 = &pinctrl_fsys0;
 		pinctrl7 = &pinctrl_fsys1;
+		pinctrl8 = &pinctrl_bus1;
 	};
 
 	cpus {
@@ -242,6 +243,12 @@
 			interrupts = <0 383 0>;
 		};
 
+		pinctrl_bus1: pinctrl@14870000 {
+			compatible = "samsung,exynos7-pinctrl";
+			reg = <0x14870000 0x1000>;
+			interrupts = <0 384 0>;
+		};
+
 		pinctrl_nfc: pinctrl@14cd0000 {
 			compatible = "samsung,exynos7-pinctrl";
 			reg = <0x14cd0000 0x1000>;
-- 
1.7.10.4

[PATCH 10/11] arm64: dts: Enable USB 3.0 controller on exynos7

[Vivek Gautam]

Adding USB 3.0 DRD controller device node, with its clock
and phy information to enable using the same on Exynos7.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos7.dtsi |   35 +++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 90048b2..e633b02 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -531,6 +531,41 @@
 			clocks = <&clock_peric0 PCLK_PWM>;
 			clock-names = "timers";
 		};
+
+		usbdrd3: usb@15400000 {
+			compatible = "samsung,exynos7-dwusb3";
+			clocks = <&clock_fsys0 ACLK_USBDRD300>,
+				 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
+				 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
+			clock-names = "usbdrd30", "usbdrd30_susp_clk",
+				      "usbdrd30_axius_clk";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			dwc3 {
+				compatible = "snps,dwc3";
+				reg = <0x15400000 0x10000>;
+				interrupts = <0 223 0>;
+				phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		usbdrd_phy: phy@15500000 {
+			compatible = "samsung,exynos7-usbdrd-phy";
+			reg = <0x15500000 0x100>;
+			clocks =
+			  <&clock_fsys0 ACLK_USBDRD300>,
+			  <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
+			  <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
+			  <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
+			  <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
+			clock-names = "phy", "ref", "phy_pipe", "phy_utmi",
+				      "itp";
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			#phy-cells = <1>;
+		};
 	};
 };
 
-- 
1.7.10.4

[PATCH 11/11] arm64: dts: exynos7-espresso: Add regulators for Vbus and Vbus-Boost

[Vivek Gautam]

Adding fixed voltage regulators for Vbus and Vbus-boost required
by USB 3.0 DRD controller on Exynos7-espresso board.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos7-espresso.dts |   43 +++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 5424cc4..2dedd5e 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -30,6 +30,28 @@
 		device_type = "memory";
 		reg = <0x0 0x40000000 0x0 0xC0000000>;
 	};
+
+	usb30_vbus_reg: regulator-usb30 {
+		compatible = "regulator-fixed";
+		regulator-name = "VBUS_5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gph1 1 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb30_vbus_en>;
+		enable-active-high;
+	};
+
+	usb3drd_vboost_5v: regulator-usb3drd-vboost {
+		compatible = "regulator-fixed";
+		regulator-name = "VUSB_VBUS_5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpf4 1 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3drd_vboost_en>;
+		enable-active-high;
+	};
 };
 
 &fin_pll {
@@ -40,6 +62,22 @@
 	status = "okay";
 };
 
+&pinctrl_bus1 {
+	usb30_vbus_en: usb30-vbus-en {
+		samsung,pins = "gph1-1";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <0>;
+	};
+
+	usb3drd_vboost_en: usb3drd-vboost-en {
+		samsung,pins = "gpf4-1";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <0>;
+	};
+};
+
 &rtc {
 	status = "okay";
 };
@@ -82,3 +120,8 @@
 	bus-width = <4>;
 	disable-wp;
 };
+
+&usbdrd_phy {
+	vbus-supply = <&usb30_vbus_reg>;
+	vbus-boost-supply = <&usb3drd_vboost_5v>;
+};
-- 
1.7.10.4

Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1259 bytes --]

On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
> The series has dependency on
> a) "[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC"
>    http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
> b) "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt
>    bindings header.
>    http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142
> c) "tty: serial: samsung: Clean-up selection of number of available UARTs"
>    http://www.spinics.net/lists/linux-samsung-soc/msg37418.html
> d) "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next)
>    https://lkml.org/lkml/2014/10/21/654
> e) "Samsung pinctrl patches for v3.19"
>    http://www.spinics.net/lists/linux-samsung-soc/msg38744.html
> 
> Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies.
> 
> Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes
> together in this series only so as to avoid having 'n' number of dependencies.
> 
> The USB driver patches in this series were part of [1] sent earlier.
> [1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
>     https://lkml.org/lkml/2014/10/7/191

I took dwc3 driver patches.

-- 
balbi

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Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1259 bytes --]

On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
> The series has dependency on
> a) "[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC"
>    http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
> b) "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt
>    bindings header.
>    http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142
> c) "tty: serial: samsung: Clean-up selection of number of available UARTs"
>    http://www.spinics.net/lists/linux-samsung-soc/msg37418.html
> d) "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next)
>    https://lkml.org/lkml/2014/10/21/654
> e) "Samsung pinctrl patches for v3.19"
>    http://www.spinics.net/lists/linux-samsung-soc/msg38744.html
> 
> Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies.
> 
> Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes
> together in this series only so as to avoid having 'n' number of dependencies.
> 
> The USB driver patches in this series were part of [1] sent earlier.
> [1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
>     https://lkml.org/lkml/2014/10/7/191

I took dwc3 driver patches.

-- 
balbi

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Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support

[Kishon Vijay Abraham I]

On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
> On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
>> The series has dependency on
>> a) "[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC"
>>    http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
>> b) "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt
>>    bindings header.
>>    http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142
>> c) "tty: serial: samsung: Clean-up selection of number of available UARTs"
>>    http://www.spinics.net/lists/linux-samsung-soc/msg37418.html
>> d) "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next)
>>    https://lkml.org/lkml/2014/10/21/654
>> e) "Samsung pinctrl patches for v3.19"
>>    http://www.spinics.net/lists/linux-samsung-soc/msg38744.html
>>
>> Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies.
>>
>> Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes
>> together in this series only so as to avoid having 'n' number of dependencies.
>>
>> The USB driver patches in this series were part of [1] sent earlier.
>> [1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
>>     https://lkml.org/lkml/2014/10/7/191
> 
> I took dwc3 driver patches.

I took the phy patches.

Thanks
Kishon

Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support

[Kishon Vijay Abraham I]

On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
> On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
>> The series has dependency on
>> a) "[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC"
>>    http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
>> b) "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt
>>    bindings header.
>>    http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142
>> c) "tty: serial: samsung: Clean-up selection of number of available UARTs"
>>    http://www.spinics.net/lists/linux-samsung-soc/msg37418.html
>> d) "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next)
>>    https://lkml.org/lkml/2014/10/21/654
>> e) "Samsung pinctrl patches for v3.19"
>>    http://www.spinics.net/lists/linux-samsung-soc/msg38744.html
>>
>> Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies.
>>
>> Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes
>> together in this series only so as to avoid having 'n' number of dependencies.
>>
>> The USB driver patches in this series were part of [1] sent earlier.
>> [1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
>>     https://lkml.org/lkml/2014/10/7/191
> 
> I took dwc3 driver patches.

I took the phy patches.

Thanks
Kishon

Re: [PATCH 01/11] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Alim Akhtar]

Hi Vivek,

On Fri, Nov 21, 2014 at 7:05 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> USB and Power regulator on Exynos7 require gpios available
> in BUS1 pin controller block.
> So adding the BUS1 pinctrl support.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c |   12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index d5d4cfc..caca5b5 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -1300,6 +1300,13 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>  };
>
> +/* pin banks of exynos7 pin-controller - BUS1 */
> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
> +};
> +
Looks like you are just trying to touch pin banks only related to USB
stuffs, but as this patch does not have any dependencies on other
patches in this series, will you consider adding other pin banks of
BUS1, just for completeness of BUS1 pin-controller.

>  const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>         {
>                 /* pin-controller instance 0 Alive data */
> @@ -1342,5 +1349,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>                 .pin_banks      = exynos7_pin_banks7,
>                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
>                 .eint_gpio_init = exynos_eint_gpio_init,
> +       }, {
> +               /* pin-controller instance 8 BUS1 data */
> +               .pin_banks      = exynos7_pin_banks8,
> +               .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
> +               .eint_gpio_init = exynos_eint_gpio_init,
>         },
>  };
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Regards,
Alim

Re: [PATCH 01/11] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Alim Akhtar]

Hi Vivek,

On Fri, Nov 21, 2014 at 7:05 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> USB and Power regulator on Exynos7 require gpios available
> in BUS1 pin controller block.
> So adding the BUS1 pinctrl support.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c |   12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index d5d4cfc..caca5b5 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -1300,6 +1300,13 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>  };
>
> +/* pin banks of exynos7 pin-controller - BUS1 */
> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
> +};
> +
Looks like you are just trying to touch pin banks only related to USB
stuffs, but as this patch does not have any dependencies on other
patches in this series, will you consider adding other pin banks of
BUS1, just for completeness of BUS1 pin-controller.

>  const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>         {
>                 /* pin-controller instance 0 Alive data */
> @@ -1342,5 +1349,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>                 .pin_banks      = exynos7_pin_banks7,
>                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
>                 .eint_gpio_init = exynos_eint_gpio_init,
> +       }, {
> +               /* pin-controller instance 8 BUS1 data */
> +               .pin_banks      = exynos7_pin_banks8,
> +               .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
> +               .eint_gpio_init = exynos_eint_gpio_init,
>         },
>  };
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Regards,
Alim

Re: [PATCH 09/11] arm64: exynos: Add bus1 pinctrl node on exynos7

[Alim Akhtar]

Hi Vivek,

On Fri, Nov 21, 2014 at 7:05 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> BUS1 pinctrl provides gpios for usb and power regulator
> available on exynos7-espresso board. So add relevant device
> node for pinctrl-bus1.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi |   26 +++++++++++++++++++++++
>  arch/arm64/boot/dts/exynos/exynos7.dtsi         |    7 ++++++
>  2 files changed, 33 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> index 2eef4a2..9648e03 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> @@ -335,6 +335,32 @@
>         };
>  };
>
> +&pinctrl_bus1 {
> +       gpf0: gpf0 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf4: gpf4 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gph1: gph1 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> +
See my comment on patch 01/11, accordingly you can modify this.

>  &pinctrl_nfc {
>         gpj0: gpj0 {
>                 gpio-controller;
> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index d7a37c3..90048b2 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -26,6 +26,7 @@
>                 pinctrl5 = &pinctrl_ese;
>                 pinctrl6 = &pinctrl_fsys0;
>                 pinctrl7 = &pinctrl_fsys1;
> +               pinctrl8 = &pinctrl_bus1;
>         };
>
>         cpus {
> @@ -242,6 +243,12 @@
>                         interrupts = <0 383 0>;
>                 };
>
> +               pinctrl_bus1: pinctrl@14870000 {
> +                       compatible = "samsung,exynos7-pinctrl";
> +                       reg = <0x14870000 0x1000>;
> +                       interrupts = <0 384 0>;
> +               };
> +
>                 pinctrl_nfc: pinctrl@14cd0000 {
>                         compatible = "samsung,exynos7-pinctrl";
>                         reg = <0x14cd0000 0x1000>;
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
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-- 
Regards,
Alim

Re: [PATCH 09/11] arm64: exynos: Add bus1 pinctrl node on exynos7

[Alim Akhtar]

Hi Vivek,

On Fri, Nov 21, 2014 at 7:05 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> BUS1 pinctrl provides gpios for usb and power regulator
> available on exynos7-espresso board. So add relevant device
> node for pinctrl-bus1.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi |   26 +++++++++++++++++++++++
>  arch/arm64/boot/dts/exynos/exynos7.dtsi         |    7 ++++++
>  2 files changed, 33 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> index 2eef4a2..9648e03 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> @@ -335,6 +335,32 @@
>         };
>  };
>
> +&pinctrl_bus1 {
> +       gpf0: gpf0 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf4: gpf4 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gph1: gph1 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> +
See my comment on patch 01/11, accordingly you can modify this.

>  &pinctrl_nfc {
>         gpj0: gpj0 {
>                 gpio-controller;
> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index d7a37c3..90048b2 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -26,6 +26,7 @@
>                 pinctrl5 = &pinctrl_ese;
>                 pinctrl6 = &pinctrl_fsys0;
>                 pinctrl7 = &pinctrl_fsys1;
> +               pinctrl8 = &pinctrl_bus1;
>         };
>
>         cpus {
> @@ -242,6 +243,12 @@
>                         interrupts = <0 383 0>;
>                 };
>
> +               pinctrl_bus1: pinctrl@14870000 {
> +                       compatible = "samsung,exynos7-pinctrl";
> +                       reg = <0x14870000 0x1000>;
> +                       interrupts = <0 384 0>;
> +               };
> +
>                 pinctrl_nfc: pinctrl@14cd0000 {
>                         compatible = "samsung,exynos7-pinctrl";
>                         reg = <0x14cd0000 0x1000>;
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Regards,
Alim

Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support

[Kukjin Kim]

On 11/22/14 17:40, Kishon Vijay Abraham I wrote:
> 
> On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
>> On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
>>> The series has dependency on
>>> a) "[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC"
>>>    http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
>>> b) "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt
>>>    bindings header.
>>>    http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142
>>> c) "tty: serial: samsung: Clean-up selection of number of available UARTs"
>>>    http://www.spinics.net/lists/linux-samsung-soc/msg37418.html
>>> d) "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next)
>>>    https://lkml.org/lkml/2014/10/21/654
>>> e) "Samsung pinctrl patches for v3.19"
>>>    http://www.spinics.net/lists/linux-samsung-soc/msg38744.html
>>>
>>> Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies.
>>>
>>> Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes
>>> together in this series only so as to avoid having 'n' number of dependencies.
>>>
>>> The USB driver patches in this series were part of [1] sent earlier.
>>> [1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
>>>     https://lkml.org/lkml/2014/10/7/191
>>
>> I took dwc3 driver patches.
> 
> I took the phy patches.
> 
I'll take DT changes once exynos7 is landing into samsung tree :)

Thanks,
Kukjin

Re: [PATCH 01/11] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

Hi Alim,


On Sat, Nov 22, 2014 at 7:07 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
> Hi Vivek,
>
> On Fri, Nov 21, 2014 at 7:05 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>> USB and Power regulator on Exynos7 require gpios available
>> in BUS1 pin controller block.
>> So adding the BUS1 pinctrl support.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> ---
>>  drivers/pinctrl/samsung/pinctrl-exynos.c |   12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> index d5d4cfc..caca5b5 100644
>> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> @@ -1300,6 +1300,13 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>>  };
>>
>> +/* pin banks of exynos7 pin-controller - BUS1 */
>> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
>> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
>> +};
>> +
> Looks like you are just trying to touch pin banks only related to USB
> stuffs, but as this patch does not have any dependencies on other
> patches in this series, will you consider adding other pin banks of
> BUS1, just for completeness of BUS1 pin-controller.

True, this just touches the USB related pinctrl.
Will add the rest pin banks of BUS1 for completeness.
Thanks for pointing out. :-)

[snip]



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH 01/11] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

Hi Alim,


On Sat, Nov 22, 2014 at 7:07 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
> Hi Vivek,
>
> On Fri, Nov 21, 2014 at 7:05 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>> USB and Power regulator on Exynos7 require gpios available
>> in BUS1 pin controller block.
>> So adding the BUS1 pinctrl support.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> ---
>>  drivers/pinctrl/samsung/pinctrl-exynos.c |   12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> index d5d4cfc..caca5b5 100644
>> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> @@ -1300,6 +1300,13 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>>  };
>>
>> +/* pin banks of exynos7 pin-controller - BUS1 */
>> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
>> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
>> +};
>> +
> Looks like you are just trying to touch pin banks only related to USB
> stuffs, but as this patch does not have any dependencies on other
> patches in this series, will you consider adding other pin banks of
> BUS1, just for completeness of BUS1 pin-controller.

True, this just touches the USB related pinctrl.
Will add the rest pin banks of BUS1 for completeness.
Thanks for pointing out. :-)

[snip]



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

[PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
---

This patch was part of series:
"[PATCH 00/11] Exynos7: Adding USB 3.0 support"
 https://lkml.org/lkml/2014/11/21/247

Changes since V1:
 - Added support for all pin banks which are part of BUS1 pin controller.

 drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d5d4cfc..44e60dc 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1300,6 +1300,20 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
 	EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
 };
 
+/* pin banks of exynos7 pin-controller - BUS1 */
+static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
+	EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
+	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
+	EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
+	EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
+	EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
+	EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
+	EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
+	EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
+	EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
+	EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
+};
+
 const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
 	{
 		/* pin-controller instance 0 Alive data */
@@ -1342,5 +1356,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
 		.pin_banks	= exynos7_pin_banks7,
 		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks7),
 		.eint_gpio_init = exynos_eint_gpio_init,
+	}, {
+		/* pin-controller instance 8 BUS1 data */
+		.pin_banks	= exynos7_pin_banks8,
+		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks8),
+		.eint_gpio_init = exynos_eint_gpio_init,
 	},
 };
-- 
1.7.10.4

[PATCH V2 2/2] arm64: exynos: Add bus1 pinctrl node on exynos7

[Vivek Gautam]

BUS1 pinctrl provides gpios for usb and power regulator
available on exynos7-espresso board. So add relevant device
node for pinctrl-bus1.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---

This patch was part of series:
"[PATCH 00/11] Exynos7: Adding USB 3.0 support"
 https://lkml.org/lkml/2014/11/21/247

Changes since V1:
 - Added support for all pin banks which are part of BUS1 pin controller.

 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi |   82 +++++++++++++++++++++++
 arch/arm64/boot/dts/exynos/exynos7.dtsi         |    7 ++
 2 files changed, 89 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index 2eef4a2..c367f0a 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -335,6 +335,88 @@
 	};
 };
 
+&pinctrl_bus1 {
+	gpf0: gpf0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf1: gpf1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf2: gpf2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf3: gpf3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf4: gpf4 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf5: gpf5 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg1: gpg1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg2: gpg2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gph1: gph1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpv6: gpv6 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
 &pinctrl_nfc {
 	gpj0: gpj0 {
 		gpio-controller;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 1d9e4c9..e633b02 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -26,6 +26,7 @@
 		pinctrl5 = &pinctrl_ese;
 		pinctrl6 = &pinctrl_fsys0;
 		pinctrl7 = &pinctrl_fsys1;
+		pinctrl8 = &pinctrl_bus1;
 	};
 
 	cpus {
@@ -242,6 +243,12 @@
 			interrupts = <0 383 0>;
 		};
 
+		pinctrl_bus1: pinctrl@14870000 {
+			compatible = "samsung,exynos7-pinctrl";
+			reg = <0x14870000 0x1000>;
+			interrupts = <0 384 0>;
+		};
+
 		pinctrl_nfc: pinctrl@14cd0000 {
 			compatible = "samsung,exynos7-pinctrl";
 			reg = <0x14cd0000 0x1000>;
-- 
1.7.10.4

Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support

[Vivek Gautam]

Hi Sylwester,


On Sat, Nov 22, 2014 at 8:42 PM, Kukjin Kim <kgene@kernel.org> wrote:
> On 11/22/14 17:40, Kishon Vijay Abraham I wrote:
>>
>> On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
>>> On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
>>>> The series has dependency on
>>>> a) "[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC"
>>>>    http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
>>>> b) "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt
>>>>    bindings header.
>>>>    http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142
>>>> c) "tty: serial: samsung: Clean-up selection of number of available UARTs"
>>>>    http://www.spinics.net/lists/linux-samsung-soc/msg37418.html
>>>> d) "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next)
>>>>    https://lkml.org/lkml/2014/10/21/654
>>>> e) "Samsung pinctrl patches for v3.19"
>>>>    http://www.spinics.net/lists/linux-samsung-soc/msg38744.html
>>>>
>>>> Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies.
>>>>
>>>> Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes
>>>> together in this series only so as to avoid having 'n' number of dependencies.
>>>>
>>>> The USB driver patches in this series were part of [1] sent earlier.
>>>> [1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
>>>>     https://lkml.org/lkml/2014/10/7/191
>>>
>>> I took dwc3 driver patches.
>>
>> I took the phy patches.
>>
> I'll take DT changes once exynos7 is landing into samsung tree :)
>

You too may want to pick the sole clock driver patch in this series
for 3.19 ? :-)
"clk: exynos7: Add required clock tree for USB"

Please let me know if the merge window is still open on your side so
that you can
pick this patch.


-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support

[Vivek Gautam]

Hi Sylwester,


On Sat, Nov 22, 2014 at 8:42 PM, Kukjin Kim <kgene@kernel.org> wrote:
> On 11/22/14 17:40, Kishon Vijay Abraham I wrote:
>>
>> On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
>>> On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
>>>> The series has dependency on
>>>> a) "[PATCH v7 0/7] Enable support for Samsung Exynos7 SoC"
>>>>    http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
>>>> b) "[GIT PULL] Samsung clock changes for 3.19" - specifically the clock dt
>>>>    bindings header.
>>>>    http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142
>>>> c) "tty: serial: samsung: Clean-up selection of number of available UARTs"
>>>>    http://www.spinics.net/lists/linux-samsung-soc/msg37418.html
>>>> d) "dts, kbuild: Implement support for dtb vendor subdirs"(merged in linux-next)
>>>>    https://lkml.org/lkml/2014/10/21/654
>>>> e) "Samsung pinctrl patches for v3.19"
>>>>    http://www.spinics.net/lists/linux-samsung-soc/msg38744.html
>>>>
>>>> Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies.
>>>>
>>>> Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes
>>>> together in this series only so as to avoid having 'n' number of dependencies.
>>>>
>>>> The USB driver patches in this series were part of [1] sent earlier.
>>>> [1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
>>>>     https://lkml.org/lkml/2014/10/7/191
>>>
>>> I took dwc3 driver patches.
>>
>> I took the phy patches.
>>
> I'll take DT changes once exynos7 is landing into samsung tree :)
>

You too may want to pick the sole clock driver patch in this series
for 3.19 ? :-)
"clk: exynos7: Add required clock tree for USB"

Please let me know if the merge window is still open on your side so
that you can
pick this patch.


-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 2/2] arm64: exynos: Add bus1 pinctrl node on exynos7

[Alim Akhtar]

Hi Vivek,

On Mon, Nov 24, 2014 at 6:36 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> BUS1 pinctrl provides gpios for usb and power regulator
> available on exynos7-espresso board. So add relevant device
> node for pinctrl-bus1.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> ---
>
Looks good to me.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> This patch was part of series:
> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>  https://lkml.org/lkml/2014/11/21/247
>
> Changes since V1:
>  - Added support for all pin banks which are part of BUS1 pin controller.
>
>  arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi |   82 +++++++++++++++++++++++
>  arch/arm64/boot/dts/exynos/exynos7.dtsi         |    7 ++
>  2 files changed, 89 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> index 2eef4a2..c367f0a 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> @@ -335,6 +335,88 @@
>         };
>  };
>
> +&pinctrl_bus1 {
> +       gpf0: gpf0 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf1: gpf1 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf2: gpf2 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf3: gpf3 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf4: gpf4 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf5: gpf5 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpg1: gpg1 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpg2: gpg2 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gph1: gph1 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpv6: gpv6 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> +
>  &pinctrl_nfc {
>         gpj0: gpj0 {
>                 gpio-controller;
> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index 1d9e4c9..e633b02 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -26,6 +26,7 @@
>                 pinctrl5 = &pinctrl_ese;
>                 pinctrl6 = &pinctrl_fsys0;
>                 pinctrl7 = &pinctrl_fsys1;
> +               pinctrl8 = &pinctrl_bus1;
>         };
>
>         cpus {
> @@ -242,6 +243,12 @@
>                         interrupts = <0 383 0>;
>                 };
>
> +               pinctrl_bus1: pinctrl@14870000 {
> +                       compatible = "samsung,exynos7-pinctrl";
> +                       reg = <0x14870000 0x1000>;
> +                       interrupts = <0 384 0>;
> +               };
> +
>                 pinctrl_nfc: pinctrl@14cd0000 {
>                         compatible = "samsung,exynos7-pinctrl";
>                         reg = <0x14cd0000 0x1000>;
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Regards,
Alim

Re: [PATCH V2 2/2] arm64: exynos: Add bus1 pinctrl node on exynos7

[Alim Akhtar]

Hi Vivek,

On Mon, Nov 24, 2014 at 6:36 PM, Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> BUS1 pinctrl provides gpios for usb and power regulator
> available on exynos7-espresso board. So add relevant device
> node for pinctrl-bus1.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
>
Looks good to me.
Reviewed-by: Alim Akhtar <alim.akhtar-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

> This patch was part of series:
> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>  https://lkml.org/lkml/2014/11/21/247
>
> Changes since V1:
>  - Added support for all pin banks which are part of BUS1 pin controller.
>
>  arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi |   82 +++++++++++++++++++++++
>  arch/arm64/boot/dts/exynos/exynos7.dtsi         |    7 ++
>  2 files changed, 89 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> index 2eef4a2..c367f0a 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> @@ -335,6 +335,88 @@
>         };
>  };
>
> +&pinctrl_bus1 {
> +       gpf0: gpf0 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf1: gpf1 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf2: gpf2 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf3: gpf3 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf4: gpf4 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpf5: gpf5 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpg1: gpg1 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpg2: gpg2 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gph1: gph1 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpv6: gpv6 {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> +
>  &pinctrl_nfc {
>         gpj0: gpj0 {
>                 gpio-controller;
> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index 1d9e4c9..e633b02 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -26,6 +26,7 @@
>                 pinctrl5 = &pinctrl_ese;
>                 pinctrl6 = &pinctrl_fsys0;
>                 pinctrl7 = &pinctrl_fsys1;
> +               pinctrl8 = &pinctrl_bus1;
>         };
>
>         cpus {
> @@ -242,6 +243,12 @@
>                         interrupts = <0 383 0>;
>                 };
>
> +               pinctrl_bus1: pinctrl@14870000 {
> +                       compatible = "samsung,exynos7-pinctrl";
> +                       reg = <0x14870000 0x1000>;
> +                       interrupts = <0 384 0>;
> +               };
> +
>                 pinctrl_nfc: pinctrl@14cd0000 {
>                         compatible = "samsung,exynos7-pinctrl";
>                         reg = <0x14cd0000 0x1000>;
> --
> 1.7.10.4
>
> --
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> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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-- 
Regards,
Alim
--
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Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Alim Akhtar]

Hi Vivek,

On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> USB and Power regulator on Exynos7 require gpios available
> in BUS1 pin controller block.
> So adding the BUS1 pinctrl support.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
Looks good to me.
Thanks!

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>
> This patch was part of series:
> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>  https://lkml.org/lkml/2014/11/21/247
>
> Changes since V1:
>  - Added support for all pin banks which are part of BUS1 pin controller.
>
>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index d5d4cfc..44e60dc 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -1300,6 +1300,20 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>  };
>
> +/* pin banks of exynos7 pin-controller - BUS1 */
> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
> +       EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
> +       EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
> +       EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
> +       EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
> +       EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
> +       EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
> +       EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
> +};
> +
>  const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>         {
>                 /* pin-controller instance 0 Alive data */
> @@ -1342,5 +1356,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>                 .pin_banks      = exynos7_pin_banks7,
>                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
>                 .eint_gpio_init = exynos_eint_gpio_init,
> +       }, {
> +               /* pin-controller instance 8 BUS1 data */
> +               .pin_banks      = exynos7_pin_banks8,
> +               .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
> +               .eint_gpio_init = exynos_eint_gpio_init,
>         },
>  };
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
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-- 
Regards,
Alim

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Alim Akhtar]

Hi Vivek,

On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> USB and Power regulator on Exynos7 require gpios available
> in BUS1 pin controller block.
> So adding the BUS1 pinctrl support.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
Looks good to me.
Thanks!

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>
> This patch was part of series:
> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>  https://lkml.org/lkml/2014/11/21/247
>
> Changes since V1:
>  - Added support for all pin banks which are part of BUS1 pin controller.
>
>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index d5d4cfc..44e60dc 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -1300,6 +1300,20 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>  };
>
> +/* pin banks of exynos7 pin-controller - BUS1 */
> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
> +       EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
> +       EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
> +       EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
> +       EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
> +       EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
> +       EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
> +       EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
> +};
> +
>  const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>         {
>                 /* pin-controller instance 0 Alive data */
> @@ -1342,5 +1356,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>                 .pin_banks      = exynos7_pin_banks7,
>                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
>                 .eint_gpio_init = exynos_eint_gpio_init,
> +       }, {
> +               /* pin-controller instance 8 BUS1 data */
> +               .pin_banks      = exynos7_pin_banks8,
> +               .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
> +               .eint_gpio_init = exynos_eint_gpio_init,
>         },
>  };
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Regards,
Alim

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

Hi Alim,


On Wed, Nov 26, 2014 at 7:03 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
> Hi Vivek,
>
> On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>> USB and Power regulator on Exynos7 require gpios available
>> in BUS1 pin controller block.
>> So adding the BUS1 pinctrl support.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> ---
> Looks good to me.
> Thanks!
>
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

Thanks for the review.

>
>>
>> This patch was part of series:
>> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>>  https://lkml.org/lkml/2014/11/21/247
>>
>> Changes since V1:
>>  - Added support for all pin banks which are part of BUS1 pin controller.
>>
>>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>>
>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> index d5d4cfc..44e60dc 100644
>> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> @@ -1300,6 +1300,20 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>>  };
>>
>> +/* pin banks of exynos7 pin-controller - BUS1 */
>> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
>> +       EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
>> +       EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
>> +       EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
>> +       EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
>> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
>> +       EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
>> +};
>> +
>>  const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>>         {
>>                 /* pin-controller instance 0 Alive data */
>> @@ -1342,5 +1356,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>>                 .pin_banks      = exynos7_pin_banks7,
>>                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
>>                 .eint_gpio_init = exynos_eint_gpio_init,
>> +       }, {
>> +               /* pin-controller instance 8 BUS1 data */
>> +               .pin_banks      = exynos7_pin_banks8,
>> +               .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
>> +               .eint_gpio_init = exynos_eint_gpio_init,
>>         },
>>  };
>> --
>> 1.7.10.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Regards,
> Alim
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

Hi Alim,


On Wed, Nov 26, 2014 at 7:03 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
> Hi Vivek,
>
> On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>> USB and Power regulator on Exynos7 require gpios available
>> in BUS1 pin controller block.
>> So adding the BUS1 pinctrl support.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> ---
> Looks good to me.
> Thanks!
>
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

Thanks for the review.

>
>>
>> This patch was part of series:
>> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>>  https://lkml.org/lkml/2014/11/21/247
>>
>> Changes since V1:
>>  - Added support for all pin banks which are part of BUS1 pin controller.
>>
>>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>>
>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> index d5d4cfc..44e60dc 100644
>> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> @@ -1300,6 +1300,20 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>>  };
>>
>> +/* pin banks of exynos7 pin-controller - BUS1 */
>> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
>> +       EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
>> +       EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
>> +       EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
>> +       EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
>> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
>> +       EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
>> +};
>> +
>>  const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>>         {
>>                 /* pin-controller instance 0 Alive data */
>> @@ -1342,5 +1356,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>>                 .pin_banks      = exynos7_pin_banks7,
>>                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
>>                 .eint_gpio_init = exynos_eint_gpio_init,
>> +       }, {
>> +               /* pin-controller instance 8 BUS1 data */
>> +               .pin_banks      = exynos7_pin_banks8,
>> +               .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
>> +               .eint_gpio_init = exynos_eint_gpio_init,
>>         },
>>  };
>> --
>> 1.7.10.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Regards,
> Alim
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

Hi Linus,


On Fri, Nov 28, 2014 at 9:05 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
> Hi Alim,
>
>
> On Wed, Nov 26, 2014 at 7:03 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
>> Hi Vivek,
>>
>> On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>>> USB and Power regulator on Exynos7 require gpios available
>>> in BUS1 pin controller block.
>>> So adding the BUS1 pinctrl support.
>>>
>>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>>> Cc: Linus Walleij <linus.walleij@linaro.org>

If the change looks good, will it be possible to pick it fo 3.19-rc1 ?
That will really help enabling USB IP on exynos7.

>>> ---
>> Looks good to me.
>> Thanks!
>>
>> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
>
> Thanks for the review.
>
>>
>>>
>>> This patch was part of series:
>>> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>>>  https://lkml.org/lkml/2014/11/21/247
>>>
>>> Changes since V1:
>>>  - Added support for all pin banks which are part of BUS1 pin controller.
>>>
>>>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>>>  1 file changed, 19 insertions(+)
>>>
>>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
>>> index d5d4cfc..44e60dc 100644
>>> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
>>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
>>> @@ -1300,6 +1300,20 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>>>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>>>  };
>>>
>>> +/* pin banks of exynos7 pin-controller - BUS1 */
>>> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
>>> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
>>> +       EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
>>> +       EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
>>> +       EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
>>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
>>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
>>> +       EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
>>> +       EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
>>> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
>>> +       EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
>>> +};
>>> +
>>>  const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>>>         {
>>>                 /* pin-controller instance 0 Alive data */
>>> @@ -1342,5 +1356,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>>>                 .pin_banks      = exynos7_pin_banks7,
>>>                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
>>>                 .eint_gpio_init = exynos_eint_gpio_init,
>>> +       }, {
>>> +               /* pin-controller instance 8 BUS1 data */
>>> +               .pin_banks      = exynos7_pin_banks8,
>>> +               .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
>>> +               .eint_gpio_init = exynos_eint_gpio_init,
>>>         },
>>>  };
>>> --
>>> 1.7.10.4
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>>
>>
>> --
>> Regards,
>> Alim
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Best Regards
> Vivek Gautam
> Samsung R&D Institute, Bangalore
> India



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

Hi Linus,


On Fri, Nov 28, 2014 at 9:05 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
> Hi Alim,
>
>
> On Wed, Nov 26, 2014 at 7:03 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
>> Hi Vivek,
>>
>> On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>>> USB and Power regulator on Exynos7 require gpios available
>>> in BUS1 pin controller block.
>>> So adding the BUS1 pinctrl support.
>>>
>>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>>> Cc: Linus Walleij <linus.walleij@linaro.org>

If the change looks good, will it be possible to pick it fo 3.19-rc1 ?
That will really help enabling USB IP on exynos7.

>>> ---
>> Looks good to me.
>> Thanks!
>>
>> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
>
> Thanks for the review.
>
>>
>>>
>>> This patch was part of series:
>>> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>>>  https://lkml.org/lkml/2014/11/21/247
>>>
>>> Changes since V1:
>>>  - Added support for all pin banks which are part of BUS1 pin controller.
>>>
>>>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>>>  1 file changed, 19 insertions(+)
>>>
>>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
>>> index d5d4cfc..44e60dc 100644
>>> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
>>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
>>> @@ -1300,6 +1300,20 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>>>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>>>  };
>>>
>>> +/* pin banks of exynos7 pin-controller - BUS1 */
>>> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
>>> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
>>> +       EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
>>> +       EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
>>> +       EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
>>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
>>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
>>> +       EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
>>> +       EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
>>> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
>>> +       EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
>>> +};
>>> +
>>>  const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>>>         {
>>>                 /* pin-controller instance 0 Alive data */
>>> @@ -1342,5 +1356,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
>>>                 .pin_banks      = exynos7_pin_banks7,
>>>                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
>>>                 .eint_gpio_init = exynos_eint_gpio_init,
>>> +       }, {
>>> +               /* pin-controller instance 8 BUS1 data */
>>> +               .pin_banks      = exynos7_pin_banks8,
>>> +               .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
>>> +               .eint_gpio_init = exynos_eint_gpio_init,
>>>         },
>>>  };
>>> --
>>> 1.7.10.4
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>>
>>
>> --
>> Regards,
>> Alim
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Best Regards
> Vivek Gautam
> Samsung R&D Institute, Bangalore
> India



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 2/2] arm64: exynos: Add bus1 pinctrl node on exynos7

[Vivek Gautam]

Hi Kukjin,


On Wed, Nov 26, 2014 at 6:59 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
> Hi Vivek,
>
> On Mon, Nov 24, 2014 at 6:36 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>> BUS1 pinctrl provides gpios for usb and power regulator
>> available on exynos7-espresso board. So add relevant device
>> node for pinctrl-bus1.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> ---

We can pick this up for 3.19 rc1 ?

>>
> Looks good to me.
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
>
>> This patch was part of series:
>> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>>  https://lkml.org/lkml/2014/11/21/247
>>
>> Changes since V1:
>>  - Added support for all pin banks which are part of BUS1 pin controller.
>>
>>  arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi |   82 +++++++++++++++++++++++
>>  arch/arm64/boot/dts/exynos/exynos7.dtsi         |    7 ++
>>  2 files changed, 89 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
>> index 2eef4a2..c367f0a 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
>> @@ -335,6 +335,88 @@
>>         };
>>  };
>>
>> +&pinctrl_bus1 {
>> +       gpf0: gpf0 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf1: gpf1 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf2: gpf2 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf3: gpf3 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf4: gpf4 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf5: gpf5 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpg1: gpg1 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpg2: gpg2 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gph1: gph1 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpv6: gpv6 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +};
>> +
>>  &pinctrl_nfc {
>>         gpj0: gpj0 {
>>                 gpio-controller;
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> index 1d9e4c9..e633b02 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> @@ -26,6 +26,7 @@
>>                 pinctrl5 = &pinctrl_ese;
>>                 pinctrl6 = &pinctrl_fsys0;
>>                 pinctrl7 = &pinctrl_fsys1;
>> +               pinctrl8 = &pinctrl_bus1;
>>         };
>>
>>         cpus {
>> @@ -242,6 +243,12 @@
>>                         interrupts = <0 383 0>;
>>                 };
>>
>> +               pinctrl_bus1: pinctrl@14870000 {
>> +                       compatible = "samsung,exynos7-pinctrl";
>> +                       reg = <0x14870000 0x1000>;
>> +                       interrupts = <0 384 0>;
>> +               };
>> +
>>                 pinctrl_nfc: pinctrl@14cd0000 {
>>                         compatible = "samsung,exynos7-pinctrl";
>>                         reg = <0x14cd0000 0x1000>;
>> --
>> 1.7.10.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Regards,
> Alim
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 2/2] arm64: exynos: Add bus1 pinctrl node on exynos7

[Vivek Gautam]

Hi Kukjin,


On Wed, Nov 26, 2014 at 6:59 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
> Hi Vivek,
>
> On Mon, Nov 24, 2014 at 6:36 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>> BUS1 pinctrl provides gpios for usb and power regulator
>> available on exynos7-espresso board. So add relevant device
>> node for pinctrl-bus1.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> ---

We can pick this up for 3.19 rc1 ?

>>
> Looks good to me.
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
>
>> This patch was part of series:
>> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>>  https://lkml.org/lkml/2014/11/21/247
>>
>> Changes since V1:
>>  - Added support for all pin banks which are part of BUS1 pin controller.
>>
>>  arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi |   82 +++++++++++++++++++++++
>>  arch/arm64/boot/dts/exynos/exynos7.dtsi         |    7 ++
>>  2 files changed, 89 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
>> index 2eef4a2..c367f0a 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
>> @@ -335,6 +335,88 @@
>>         };
>>  };
>>
>> +&pinctrl_bus1 {
>> +       gpf0: gpf0 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf1: gpf1 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf2: gpf2 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf3: gpf3 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf4: gpf4 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpf5: gpf5 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpg1: gpg1 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpg2: gpg2 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gph1: gph1 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       gpv6: gpv6 {
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +};
>> +
>>  &pinctrl_nfc {
>>         gpj0: gpj0 {
>>                 gpio-controller;
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> index 1d9e4c9..e633b02 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> @@ -26,6 +26,7 @@
>>                 pinctrl5 = &pinctrl_ese;
>>                 pinctrl6 = &pinctrl_fsys0;
>>                 pinctrl7 = &pinctrl_fsys1;
>> +               pinctrl8 = &pinctrl_bus1;
>>         };
>>
>>         cpus {
>> @@ -242,6 +243,12 @@
>>                         interrupts = <0 383 0>;
>>                 };
>>
>> +               pinctrl_bus1: pinctrl@14870000 {
>> +                       compatible = "samsung,exynos7-pinctrl";
>> +                       reg = <0x14870000 0x1000>;
>> +                       interrupts = <0 384 0>;
>> +               };
>> +
>>                 pinctrl_nfc: pinctrl@14cd0000 {
>>                         compatible = "samsung,exynos7-pinctrl";
>>                         reg = <0x14cd0000 0x1000>;
>> --
>> 1.7.10.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Regards,
> Alim
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Linus Walleij]

On Fri, Nov 28, 2014 at 4:39 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
> On Fri, Nov 28, 2014 at 9:05 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:

>>> On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>>>> USB and Power regulator on Exynos7 require gpios available
>>>> in BUS1 pin controller block.
>>>> So adding the BUS1 pinctrl support.
>>>>
>>>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>>>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>>>> Cc: Linus Walleij <linus.walleij@linaro.org>
>
> If the change looks good, will it be possible to pick it fo 3.19-rc1 ?
> That will really help enabling USB IP on exynos7.

As you know the Exynos driver has a maintainer, Tomasz Figa, I will not
merge patches without his ACK.

Apart from that, there are *again* a lot of Exynos patches flying around and
I start to loose track of them. If they do not apply together and start to
conflict I will just ask Tomasz to stack them and provide a pull request
again.

Yours,
Linus Walleij

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Linus Walleij]

On Fri, Nov 28, 2014 at 4:39 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
> On Fri, Nov 28, 2014 at 9:05 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:

>>> On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>>>> USB and Power regulator on Exynos7 require gpios available
>>>> in BUS1 pin controller block.
>>>> So adding the BUS1 pinctrl support.
>>>>
>>>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>>>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>>>> Cc: Linus Walleij <linus.walleij@linaro.org>
>
> If the change looks good, will it be possible to pick it fo 3.19-rc1 ?
> That will really help enabling USB IP on exynos7.

As you know the Exynos driver has a maintainer, Tomasz Figa, I will not
merge patches without his ACK.

Apart from that, there are *again* a lot of Exynos patches flying around and
I start to loose track of them. If they do not apply together and start to
conflict I will just ask Tomasz to stack them and provide a pull request
again.

Yours,
Linus Walleij

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

On Fri, Nov 28, 2014 at 9:15 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Fri, Nov 28, 2014 at 4:39 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
>> On Fri, Nov 28, 2014 at 9:05 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
>
>>>> On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>>>>> USB and Power regulator on Exynos7 require gpios available
>>>>> in BUS1 pin controller block.
>>>>> So adding the BUS1 pinctrl support.
>>>>>
>>>>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>>>>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>>>>> Cc: Linus Walleij <linus.walleij@linaro.org>
>>
>> If the change looks good, will it be possible to pick it fo 3.19-rc1 ?
>> That will really help enabling USB IP on exynos7.
>
> As you know the Exynos driver has a maintainer, Tomasz Figa, I will not
> merge patches without his ACK.
>
> Apart from that, there are *again* a lot of Exynos patches flying around and
> I start to loose track of them. If they do not apply together and start to
> conflict I will just ask Tomasz to stack them and provide a pull request
> again.

True, this merge cycle has surely got number of exynos7 related
patches in flight,
which are difficult to keep track of.
Thanks for asking Tomasz.



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

On Fri, Nov 28, 2014 at 9:15 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Fri, Nov 28, 2014 at 4:39 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
>> On Fri, Nov 28, 2014 at 9:05 AM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
>
>>>> On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>>>>> USB and Power regulator on Exynos7 require gpios available
>>>>> in BUS1 pin controller block.
>>>>> So adding the BUS1 pinctrl support.
>>>>>
>>>>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>>>>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>>>>> Cc: Linus Walleij <linus.walleij@linaro.org>
>>
>> If the change looks good, will it be possible to pick it fo 3.19-rc1 ?
>> That will really help enabling USB IP on exynos7.
>
> As you know the Exynos driver has a maintainer, Tomasz Figa, I will not
> merge patches without his ACK.
>
> Apart from that, there are *again* a lot of Exynos patches flying around and
> I start to loose track of them. If they do not apply together and start to
> conflict I will just ask Tomasz to stack them and provide a pull request
> again.

True, this merge cycle has surely got number of exynos7 related
patches in flight,
which are difficult to keep track of.
Thanks for asking Tomasz.



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Tomasz Figa]

Hi Vivek,

Please see my comments below.

2014-11-24 22:02 GMT+09:00 Vivek Gautam <gautam.vivek@samsung.com>:
> USB and Power regulator on Exynos7 require gpios available
> in BUS1 pin controller block.
> So adding the BUS1 pinctrl support.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
>
> This patch was part of series:
> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>  https://lkml.org/lkml/2014/11/21/247
>
> Changes since V1:
>  - Added support for all pin banks which are part of BUS1 pin controller.
>
>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)

I have missed this with previous patch, but DT bindings documentation
should list all aliases for all supported compatible strings, because
they are required for correct operation. There is a small section
about aliases in [1] already, so please add there information about
aliases for Exynos7 pin controllers along with their names, e.g.

Aliases for controllers compatible with "samsung,exynos7-pinctrl":
 - pinctrl0: pin controller of ALIVE block,
 - pinctrl1: pin controller of BUS0 block,
 [...]
 - pinctrl8: pin controller of BUS1 block.

[1] Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt

I guess you can do this in separate patch or respin this one with this added.

Best regards,
Tomasz

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Tomasz Figa]

Hi Vivek,

Please see my comments below.

2014-11-24 22:02 GMT+09:00 Vivek Gautam <gautam.vivek@samsung.com>:
> USB and Power regulator on Exynos7 require gpios available
> in BUS1 pin controller block.
> So adding the BUS1 pinctrl support.
>
> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
>
> This patch was part of series:
> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>  https://lkml.org/lkml/2014/11/21/247
>
> Changes since V1:
>  - Added support for all pin banks which are part of BUS1 pin controller.
>
>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)

I have missed this with previous patch, but DT bindings documentation
should list all aliases for all supported compatible strings, because
they are required for correct operation. There is a small section
about aliases in [1] already, so please add there information about
aliases for Exynos7 pin controllers along with their names, e.g.

Aliases for controllers compatible with "samsung,exynos7-pinctrl":
 - pinctrl0: pin controller of ALIVE block,
 - pinctrl1: pin controller of BUS0 block,
 [...]
 - pinctrl8: pin controller of BUS1 block.

[1] Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt

I guess you can do this in separate patch or respin this one with this added.

Best regards,
Tomasz

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Linus Walleij]

On Mon, Dec 1, 2014 at 3:21 PM, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
> On Fri, Nov 28, 2014 at 9:15 PM, Linus Walleij <linus.walleij@linaro.org> wrote:

>> Apart from that, there are *again* a lot of Exynos patches flying around and
>> I start to loose track of them. If they do not apply together and start to
>> conflict I will just ask Tomasz to stack them and provide a pull request
>> again.
>
> True, this merge cycle has surely got number of exynos7 related
> patches in flight,
> which are difficult to keep track of.
> Thanks for asking Tomasz.

I will probably not take any more Exynos patches for this merge cycle and
ask Tomasz to queue the Exynos pinctrl patches for v3.20 after v3.19
merge cycle is complete, so make sure to include Tomasz on reviews.

Tomasz: OK?

Yours,
Linus Walleij

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Linus Walleij]

On Mon, Dec 1, 2014 at 3:21 PM, Vivek Gautam <gautamvivek1987-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Fri, Nov 28, 2014 at 9:15 PM, Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:

>> Apart from that, there are *again* a lot of Exynos patches flying around and
>> I start to loose track of them. If they do not apply together and start to
>> conflict I will just ask Tomasz to stack them and provide a pull request
>> again.
>
> True, this merge cycle has surely got number of exynos7 related
> patches in flight,
> which are difficult to keep track of.
> Thanks for asking Tomasz.

I will probably not take any more Exynos patches for this merge cycle and
ask Tomasz to queue the Exynos pinctrl patches for v3.20 after v3.19
merge cycle is complete, so make sure to include Tomasz on reviews.

Tomasz: OK?

Yours,
Linus Walleij
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Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

Hi Tomasz,


On Mon, Dec 1, 2014 at 9:37 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Vivek,
>
> Please see my comments below.
>
> 2014-11-24 22:02 GMT+09:00 Vivek Gautam <gautam.vivek@samsung.com>:
>> USB and Power regulator on Exynos7 require gpios available
>> in BUS1 pin controller block.
>> So adding the BUS1 pinctrl support.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> ---
>>
>> This patch was part of series:
>> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>>  https://lkml.org/lkml/2014/11/21/247
>>
>> Changes since V1:
>>  - Added support for all pin banks which are part of BUS1 pin controller.
>>
>>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>
> I have missed this with previous patch, but DT bindings documentation
> should list all aliases for all supported compatible strings, because
> they are required for correct operation. There is a small section
> about aliases in [1] already, so please add there information about
> aliases for Exynos7 pin controllers along with their names, e.g.
>
> Aliases for controllers compatible with "samsung,exynos7-pinctrl":
>  - pinctrl0: pin controller of ALIVE block,
>  - pinctrl1: pin controller of BUS0 block,
>  [...]
>  - pinctrl8: pin controller of BUS1 block.
>
> [1] Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>
> I guess you can do this in separate patch or respin this one with this added.

Sure, i will add the aliases in a separate patch.
I missed to update the patch in this cycle :-(
So we can queue up the reworked version for 3.20.



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH V2 1/2] pinctrl: exynos: Add BUS1 pin controller for exynos7

[Vivek Gautam]

Hi Tomasz,


On Mon, Dec 1, 2014 at 9:37 PM, Tomasz Figa <tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Hi Vivek,
>
> Please see my comments below.
>
> 2014-11-24 22:02 GMT+09:00 Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>:
>> USB and Power regulator on Exynos7 require gpios available
>> in BUS1 pin controller block.
>> So adding the BUS1 pinctrl support.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> Signed-off-by: Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> ---
>>
>> This patch was part of series:
>> "[PATCH 00/11] Exynos7: Adding USB 3.0 support"
>>  https://lkml.org/lkml/2014/11/21/247
>>
>> Changes since V1:
>>  - Added support for all pin banks which are part of BUS1 pin controller.
>>
>>  drivers/pinctrl/samsung/pinctrl-exynos.c |   19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>
> I have missed this with previous patch, but DT bindings documentation
> should list all aliases for all supported compatible strings, because
> they are required for correct operation. There is a small section
> about aliases in [1] already, so please add there information about
> aliases for Exynos7 pin controllers along with their names, e.g.
>
> Aliases for controllers compatible with "samsung,exynos7-pinctrl":
>  - pinctrl0: pin controller of ALIVE block,
>  - pinctrl1: pin controller of BUS0 block,
>  [...]
>  - pinctrl8: pin controller of BUS1 block.
>
> [1] Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>
> I guess you can do this in separate patch or respin this one with this added.

Sure, i will add the aliases in a separate patch.
I missed to update the patch in this cycle :-(
So we can queue up the reworked version for 3.20.



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India
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Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support

[Sylwester Nawrocki]

Hi Vivek,

On 25/11/14 12:48, Vivek Gautam wrote:
> On Sat, Nov 22, 2014 at 8:42 PM, Kukjin Kim <kgene@kernel.org> wrote:
>> > On 11/22/14 17:40, Kishon Vijay Abraham I wrote:
>>> >> On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
...
>>>> >>> I took dwc3 driver patches.
>>> >>
>>> >> I took the phy patches.
>>> >>
>> > I'll take DT changes once exynos7 is landing into samsung tree :)
>> >
> You too may want to pick the sole clock driver patch in this series
> for 3.19 ? :-)
> "clk: exynos7: Add required clock tree for USB"
> 
> Please let me know if the merge window is still open on your side so
> that you can pick this patch.

My apologies, it seems I have missed this patch. :/
Feel free to ping me off the list in future if there is no response
for more than week.
I queued this patch now for 3.20.  I'm putting all the exynos7 clk
patches on a separate branch which could then be pulled into samsung
arm tree for the dependant dts changes.

-- 
Thanks,
Sylwester

Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support

[Sylwester Nawrocki]

Hi Vivek,

On 25/11/14 12:48, Vivek Gautam wrote:
> On Sat, Nov 22, 2014 at 8:42 PM, Kukjin Kim <kgene@kernel.org> wrote:
>> > On 11/22/14 17:40, Kishon Vijay Abraham I wrote:
>>> >> On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
...
>>>> >>> I took dwc3 driver patches.
>>> >>
>>> >> I took the phy patches.
>>> >>
>> > I'll take DT changes once exynos7 is landing into samsung tree :)
>> >
> You too may want to pick the sole clock driver patch in this series
> for 3.19 ? :-)
> "clk: exynos7: Add required clock tree for USB"
> 
> Please let me know if the merge window is still open on your side so
> that you can pick this patch.

My apologies, it seems I have missed this patch. :/
Feel free to ping me off the list in future if there is no response
for more than week.
I queued this patch now for 3.20.  I'm putting all the exynos7 clk
patches on a separate branch which could then be pulled into samsung
arm tree for the dependant dts changes.

-- 
Thanks,
Sylwester