From: Daniel Palmer <daniel@0x0f.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Marc Zyngier <maz@kernel.org>, DTML <devicetree@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Romain Perier <romain.perier@gmail.com>
Subject: Re: [PATCH 2/3] irqchip: SigmaStar SSD20xD gpi
Date: Fri, 1 Oct 2021 21:33:13 +0900 [thread overview]
Message-ID: <CAFr9PX=VqbQw-6H0GKdVgWYFGiQ+nnUXOWqsFRMJ14o285Sy-A@mail.gmail.com> (raw)
In-Reply-To: <CACRpkdY-G5cN1Bn0yTi+867X93K9kBsV5543d8LoXzk9W-yCOg@mail.gmail.com>
Hi Linus,
On Fri, 1 Oct 2021 at 01:13, Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Thu, Sep 30, 2021 at 3:37 PM Daniel Palmer <daniel@0x0f.com> wrote:
> To me this looks like your IRQ handler is firing for unused IRQs, i.e.
> you are getting spurious IRQs.
>
> Are you missing to disable all IRQs as part of the set-up before
> registering the GPIO chip? (Usually some registers need to
> be written with zeroes.)
I don't think it's something like the wrong IRQ firing as the same
driver was previously working with EOI to clear the interrupt instead
of ACK.
I'll double check though.
Cheers,
Daniel
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Palmer <daniel@0x0f.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Marc Zyngier <maz@kernel.org>, DTML <devicetree@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Romain Perier <romain.perier@gmail.com>
Subject: Re: [PATCH 2/3] irqchip: SigmaStar SSD20xD gpi
Date: Fri, 1 Oct 2021 21:33:13 +0900 [thread overview]
Message-ID: <CAFr9PX=VqbQw-6H0GKdVgWYFGiQ+nnUXOWqsFRMJ14o285Sy-A@mail.gmail.com> (raw)
In-Reply-To: <CACRpkdY-G5cN1Bn0yTi+867X93K9kBsV5543d8LoXzk9W-yCOg@mail.gmail.com>
Hi Linus,
On Fri, 1 Oct 2021 at 01:13, Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Thu, Sep 30, 2021 at 3:37 PM Daniel Palmer <daniel@0x0f.com> wrote:
> To me this looks like your IRQ handler is firing for unused IRQs, i.e.
> you are getting spurious IRQs.
>
> Are you missing to disable all IRQs as part of the set-up before
> registering the GPIO chip? (Usually some registers need to
> be written with zeroes.)
I don't think it's something like the wrong IRQ firing as the same
driver was previously working with EOI to clear the interrupt instead
of ACK.
I'll double check though.
Cheers,
Daniel
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-01 12:31 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-14 10:04 [PATCH 0/3] SigmaStar SSD20XD GPIO interrupt controller Daniel Palmer
2021-09-14 10:04 ` Daniel Palmer
2021-09-14 10:04 ` [PATCH 1/3] dt-bindings: interrupt-controller: Add SigmaStar SSD20xD gpi Daniel Palmer
2021-09-14 10:04 ` Daniel Palmer
2021-09-21 20:36 ` Rob Herring
2021-09-21 20:36 ` Rob Herring
2021-09-14 10:04 ` [PATCH 2/3] irqchip: " Daniel Palmer
2021-09-14 10:04 ` Daniel Palmer
2021-09-20 9:45 ` Marc Zyngier
2021-09-20 9:45 ` Marc Zyngier
2021-09-20 10:05 ` Daniel Palmer
2021-09-20 10:05 ` Daniel Palmer
2021-09-20 11:24 ` Marc Zyngier
2021-09-20 11:24 ` Marc Zyngier
2021-09-21 4:16 ` Daniel Palmer
2021-09-21 4:16 ` Daniel Palmer
2021-09-21 8:27 ` Marc Zyngier
2021-09-21 8:27 ` Marc Zyngier
2021-09-21 18:23 ` Linus Walleij
2021-09-21 18:23 ` Linus Walleij
2021-09-30 12:39 ` Daniel Palmer
2021-09-30 12:39 ` Daniel Palmer
2021-09-30 13:07 ` Marc Zyngier
2021-09-30 13:07 ` Marc Zyngier
2021-09-30 13:10 ` Daniel Palmer
2021-09-30 13:10 ` Daniel Palmer
2021-09-30 13:06 ` Marc Zyngier
2021-09-30 13:06 ` Marc Zyngier
2021-09-30 13:36 ` Daniel Palmer
2021-09-30 13:36 ` Daniel Palmer
2021-09-30 13:53 ` Marc Zyngier
2021-09-30 13:53 ` Marc Zyngier
2021-09-30 13:59 ` Daniel Palmer
2021-09-30 13:59 ` Daniel Palmer
2021-09-30 14:11 ` Marc Zyngier
2021-09-30 14:11 ` Marc Zyngier
2021-09-30 16:10 ` Linus Walleij
2021-09-30 16:10 ` Linus Walleij
2021-09-30 16:13 ` Linus Walleij
2021-09-30 16:13 ` Linus Walleij
2021-10-01 12:33 ` Daniel Palmer [this message]
2021-10-01 12:33 ` Daniel Palmer
2021-10-02 3:08 ` Daniel Palmer
2021-10-02 3:08 ` Daniel Palmer
2021-09-21 6:11 ` Daniel Palmer
2021-09-21 6:11 ` Daniel Palmer
2021-09-14 10:04 ` [PATCH 3/3] ARM: dts: mstar: Add gpi interrupt controller to i2m Daniel Palmer
2021-09-14 10:04 ` Daniel Palmer
2021-09-14 15:59 ` [PATCH 0/3] SigmaStar SSD20XD GPIO interrupt controller Andrew Lunn
2021-09-14 15:59 ` Andrew Lunn
2021-09-15 9:06 ` Daniel Palmer
2021-09-15 9:06 ` Daniel Palmer
2021-09-15 20:34 ` Andrew Lunn
2021-09-15 20:34 ` Andrew Lunn
2021-09-20 8:36 ` Daniel Palmer
2021-09-20 8:36 ` Daniel Palmer
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