[U-Boot] [PATCH 0/6] sunxi: update Pine64/A64 DTs

[U-Boot] [PATCH 0/6] sunxi: update Pine64/A64 DTs

[Andre Przywara]

Hi,

in the wake of the sunxi DM enablement series it became apparent that
the current device tree files for the A64 SoC and its board are outdated.

Since Linux v4.10-rc1 there are now basic .dts files for the Allwinner
A64 SoC and the Pine64 boards in the mainline kernel.
Linux v4.11-rc1 added MMC and USB support.
Because our preliminary device trees used in U-Boot differ significantly,
let's update our copy with what's in the current Linus' master tree.
Since in contrast to U-Boot the kernel still lacks support for Ethernet,
we keep our preliminary nodes for that IP, but adjust it slightly to
match the new clocks and reset bindings.

As the sun8i-emac driver is actually using the DT for the pinmux setup,
we teach it how to cope with the new pinctrl bindings in the first two
patches. This is probably becoming somewhat obsolete very soon (with
DM GPIO support on the list already), however I consider these two
patches as merely fixes for the existing driver to maintain bisectability.
It would make sense to merge the new DTs before the DM patches, so we
need to have something in place which works meanwhile.

Let me know what you think.

Cheers,
Andre.

Andre Przywara (6):
  sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()
  net: sun8i-emac: use new, generic GPIO setup routine
  sunxi: dts: update sun50i-a64.dtsi from Linux
  sunxi: dts: update Pine64 .dts
  sunxi: dts: remove now obsolete pine64-common.dtsi
  sunxi: dts: add Bananapi M64 .dts

 arch/arm/dts/Makefile                      |   3 +-
 arch/arm/dts/sun50i-a64-bananapi-m64.dts   | 135 +++++++
 arch/arm/dts/sun50i-a64-pine64-common.dtsi |  93 -----
 arch/arm/dts/sun50i-a64-pine64-plus.dts    |  16 +-
 arch/arm/dts/sun50i-a64-pine64.dts         |  72 +++-
 arch/arm/dts/sun50i-a64.dtsi               | 615 +++++++++--------------------
 arch/arm/include/asm/arch-sunxi/gpio.h     |   4 +
 arch/arm/mach-sunxi/pinmux.c               |  77 ++++
 drivers/net/sun8i_emac.c                   |  38 +-
 include/dt-bindings/clock/sun50i-a64-ccu.h | 134 +++++++
 include/dt-bindings/reset/sun50i-a64-ccu.h |  98 +++++
 11 files changed, 706 insertions(+), 579 deletions(-)
 create mode 100644 arch/arm/dts/sun50i-a64-bananapi-m64.dts
 delete mode 100644 arch/arm/dts/sun50i-a64-pine64-common.dtsi
 create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h

-- 
2.8.2

[U-Boot] [PATCH 1/6] sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()

[Andre Przywara]

Instead of hard-coding GPIO pins used for a certain peripheral, we
should just use the pinctrl information from the DT.
The sun8i-emac driver has some simple implementation of that, so
let's just generalize this and move the code into a more common
location.
On the way we add support for the new, generic pinctrl binding now
used by all Allwinner SoCs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/include/asm/arch-sunxi/gpio.h |  4 ++
 arch/arm/mach-sunxi/pinmux.c           | 77 ++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 85a4ec3..ba8c661 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -239,4 +239,8 @@ int axp_gpio_init(void);
 static inline int axp_gpio_init(void) { return 0; }
 #endif
 
+int sunxi_gpio_parse_pin_name(const char *pin_name);
+int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
+			     const char * mux_name, int mux_sel);
+
 #endif /* _SUNXI_GPIO_H */
diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
index b026f78..f1e1e8f 100644
--- a/arch/arm/mach-sunxi/pinmux.c
+++ b/arch/arm/mach-sunxi/pinmux.c
@@ -9,6 +9,9 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
 {
@@ -69,3 +72,77 @@ int sunxi_gpio_set_pull(u32 pin, u32 val)
 
 	return 0;
 }
+
+int sunxi_gpio_parse_pin_name(const char *pin_name)
+{
+	int pin;
+
+	if (pin_name[0] != 'P')
+		return -1;
+
+	if (pin_name[1] < 'A' || pin_name[1] > 'Z')
+		return -1;
+
+	pin = (pin_name[1] - 'A') << 5;
+	pin += simple_strtol(&pin_name[2], NULL, 10);
+
+	return pin;
+}
+
+int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
+			     const char * mux_name, int mux_sel)
+{
+	int drive, pull, pin, i;
+	const char *pin_name;
+	int offset;
+
+	offset = fdtdec_lookup_phandle(fdt_blob, node, "pinctrl-0");
+	if (offset < 0)
+		return offset;
+
+	drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
+					     "drive-strength", 0);
+	if (drive) {
+		if (drive <= 10)
+			drive = SUN4I_PINCTRL_10_MA;
+		else if (drive <= 20)
+			drive = SUN4I_PINCTRL_20_MA;
+		else if (drive <= 30)
+			drive = SUN4I_PINCTRL_30_MA;
+		else
+			drive = SUN4I_PINCTRL_40_MA;
+	} else {
+		drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
+						     "allwinner,drive", 4);
+	}
+
+	if (fdt_get_property(fdt_blob, offset, "bias-pull-up", NULL))
+		pull = SUN4I_PINCTRL_PULL_UP;
+	else if (fdt_get_property(fdt_blob, offset, "bias-disable", NULL))
+		pull = SUN4I_PINCTRL_NO_PULL;
+	else if (fdt_get_property(fdt_blob, offset, "bias-pull-down", NULL))
+		pull = SUN4I_PINCTRL_PULL_DOWN;
+	else
+		pull = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
+						    "allwinner,pull", 0);
+
+	for (i = 0; ; i++) {
+		pin_name = fdt_stringlist_get(fdt_blob, offset,
+					      "allwinner,pins", i, NULL);
+		if (!pin_name) {
+			pin_name = fdt_stringlist_get(fdt_blob, offset,
+						      "pins", i, NULL);
+			if (!pin_name)
+				break;
+		}
+		pin = sunxi_gpio_parse_pin_name(pin_name);
+		if (pin < 0)
+			continue;
+
+		sunxi_gpio_set_cfgpin(pin, mux_sel);
+		sunxi_gpio_set_drv(pin, drive);
+		sunxi_gpio_set_pull(pin, pull);
+	}
+
+	return i;
+}
-- 
2.8.2

[U-Boot] [PATCH 2/6] net: sun8i-emac: use new, generic GPIO setup routine

[Andre Przywara]

Instead of open-coding the fairly generic pinmux setup in the sun8i-emac
driver, let's just use the new common implementation of that.
This has also the advantage of supporting the newpinctrl bindings, so
the driver can cope with the upstream Linux DTs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/net/sun8i_emac.c | 38 ++++++--------------------------------
 1 file changed, 6 insertions(+), 32 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index abdfada..8a1ea55 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -438,42 +438,16 @@ static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
 
 static int parse_phy_pins(struct udevice *dev)
 {
-	int offset;
-	const char *pin_name;
-	int drive, pull, i;
+	int ret = sunxi_gpio_setup_dt_pins(gd->fdt_blob, dev->of_offset,
+					   "emac", SUN8I_GPD8_GMAC);
 
-	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
-				       "pinctrl-0");
-	if (offset < 0) {
+	if (ret < 0) {
 		printf("WARNING: emac: cannot find pinctrl-0 node\n");
-		return offset;
+		return ret;
 	}
 
-	drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
-					     "allwinner,drive", 4);
-	pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
-					    "allwinner,pull", 0);
-	for (i = 0; ; i++) {
-		int pin;
-
-		pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
-					      "allwinner,pins", i, NULL);
-		if (!pin_name)
-			break;
-		if (pin_name[0] != 'P')
-			continue;
-		pin = (pin_name[1] - 'A') << 5;
-		if (pin >= 26 << 5)
-			continue;
-		pin += simple_strtol(&pin_name[2], NULL, 10);
-
-		sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
-		sunxi_gpio_set_drv(pin, drive);
-		sunxi_gpio_set_pull(pin, pull);
-	}
-
-	if (!i) {
-		printf("WARNING: emac: cannot find allwinner,pins property\n");
+	if (!ret) {
+		printf("WARNING: emac: cannot find pins property\n");
 		return -2;
 	}
 
-- 
2.8.2

[U-Boot] [PATCH 3/6] sunxi: dts: update sun50i-a64.dtsi from Linux

[Andre Przywara]

Now with USB and MMC for the A64 supported in mainline Linux, let's
sync our DT with what's in the official Linux repository.
This completely changes the clock representation, but U-Boot doesn't
use this anyway.
Also it switches to a new pinctrl binding, which uses generic property
names.
The only user of that was the sun8i-emac, which has just learned
how to deal with this. Since mainline Linux does not support this
Ethernet IP yet, let's copy over our previous DT nodes for that,
adjusting them to match the new clock and pinctrl bindings.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/dts/sun50i-a64-pine64-common.dtsi |   2 +-
 arch/arm/dts/sun50i-a64.dtsi               | 615 +++++++++--------------------
 include/dt-bindings/clock/sun50i-a64-ccu.h | 134 +++++++
 include/dt-bindings/reset/sun50i-a64-ccu.h |  98 +++++
 4 files changed, 411 insertions(+), 438 deletions(-)
 create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h

diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
index 9ec81c6..a42b0fa 100644
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -61,7 +61,7 @@
 
 &mmc0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
+	pinctrl-0 = <&mmc0_pins>;
 	vmmc-supply = <&reg_vcc3v3>;
 	cd-gpios = <&pio 5 6 0>;
 	cd-inverted;
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index bef0d00..3a5515f 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -42,8 +42,9 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/clock/sun50i-a64-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -54,28 +55,28 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu at 0 {
+		cpu0: cpu at 0 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			reg = <0>;
 			enable-method = "psci";
 		};
 
-		cpu at 1 {
+		cpu1: cpu at 1 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			reg = <1>;
 			enable-method = "psci";
 		};
 
-		cpu at 2 {
+		cpu2: cpu at 2 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			reg = <2>;
 			enable-method = "psci";
 		};
 
-		cpu at 3 {
+		cpu3: cpu at 3 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			reg = <3>;
@@ -83,28 +84,23 @@
 		};
 	};
 
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
+	osc24M: osc24M_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "osc24M";
 	};
 
-	memory {
-		device_type = "memory";
-		reg = <0x40000000 0>;
+	osc32k: osc32k_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "osc32k";
 	};
 
-	gic: interrupt-controller at 1c81000 {
-		compatible = "arm,gic-400";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-
-		reg = <0x01c81000 0x1000>,
-		      <0x01c82000 0x2000>,
-		      <0x01c84000 0x2000>,
-		      <0x01c86000 0x2000>;
-		interrupts = <GIC_PPI 9
-		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
 	};
 
 	timer {
@@ -119,199 +115,6 @@
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		osc24M: osc24M_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <24000000>;
-			clock-output-names = "osc24M";
-		};
-
-		osc32k: osc32k_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <32768>;
-			clock-output-names = "osc32k";
-		};
-
-		pll1: pll1_clk at 1c20000 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun8i-a23-pll1-clk";
-			reg = <0x01c20000 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll1";
-		};
-
-		pll6: pll6_clk at 1c20028 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun6i-a31-pll6-clk";
-			reg = <0x01c20028 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll6", "pll6x2";
-		};
-
-		pll6d2: pll6d2_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-factor-clock";
-			clock-div = <2>;
-			clock-mult = <1>;
-			clocks = <&pll6 0>;
-			clock-output-names = "pll6d2";
-		};
-
-		pll7: pll7_clk at 1c2002c {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun6i-a31-pll6-clk";
-			reg = <0x01c2002c 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll7", "pll7x2";
-		};
-
-		cpu: cpu_clk at 1c20050 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-cpu-clk";
-			reg = <0x01c20050 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
-			clock-output-names = "cpu";
-			critical-clocks = <0>;
-		};
-
-		axi: axi_clk at 1c20050 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-axi-clk";
-			reg = <0x01c20050 0x4>;
-			clocks = <&cpu>;
-			clock-output-names = "axi";
-		};
-
-		ahb1: ahb1_clk at 1c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun6i-a31-ahb1-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
-			clock-output-names = "ahb1";
-		};
-
-		ahb2: ahb2_clk at 1c2005c {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun8i-h3-ahb2-clk";
-			reg = <0x01c2005c 0x4>;
-			clocks = <&ahb1>, <&pll6d2>;
-			clock-output-names = "ahb2";
-		};
-
-		apb1: apb1_clk at 1c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-apb0-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&ahb1>;
-			clock-output-names = "apb1";
-		};
-
-		apb2: apb2_clk at 1c20058 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-apb1-clk";
-			reg = <0x01c20058 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
-			clock-output-names = "apb2";
-		};
-
-		bus_gates: bus_gates_clk at 1c20060 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun50i-a64-bus-gates-clk",
-				     "allwinner,sunxi-multi-bus-gates-clk";
-			reg = <0x01c20060 0x14>;
-			ahb1_parent {
-				clocks = <&ahb1>;
-				clock-indices = <1>, <5>,
-						<6>, <8>,
-						<9>, <10>,
-						<13>, <14>,
-						<18>, <19>,
-						<20>, <21>,
-						<23>, <24>,
-						<25>, <28>,
-						<32>, <35>,
-						<36>, <37>,
-						<40>, <43>,
-						<44>, <52>,
-						<53>, <54>,
-						<135>;
-				clock-output-names = "bus_mipidsi", "bus_ce",
-						"bus_dma", "bus_mmc0",
-						"bus_mmc1", "bus_mmc2",
-						"bus_nand", "bus_sdram",
-						"bus_ts", "bus_hstimer",
-						"bus_spi0", "bus_spi1",
-						"bus_otg", "bus_otg_ehci0",
-						"bus_ehci0", "bus_otg_ohci0",
-						"bus_ve", "bus_lcd0",
-						"bus_lcd1", "bus_deint",
-						"bus_csi", "bus_hdmi",
-						"bus_de", "bus_gpu",
-						"bus_msgbox", "bus_spinlock",
-						"bus_dbg";
-			};
-			ahb2_parent {
-				clocks = <&ahb2>;
-				clock-indices = <17>, <29>;
-				clock-output-names = "bus_gmac", "bus_ohci0";
-			};
-			apb1_parent {
-				clocks = <&apb1>;
-				clock-indices = <64>, <65>,
-						<69>, <72>,
-						<76>, <77>,
-						<78>;
-				clock-output-names = "bus_codec", "bus_spdif",
-						"bus_pio", "bus_ths",
-						"bus_i2s0", "bus_i2s1",
-						"bus_i2s2";
-			};
-			abp2_parent {
-				clocks = <&apb2>;
-				clock-indices = <96>, <97>,
-						<98>, <101>,
-						<112>, <113>,
-						<114>, <115>,
-						<116>;
-				clock-output-names = "bus_i2c0", "bus_i2c1",
-						"bus_i2c2", "bus_scr",
-						"bus_uart0", "bus_uart1",
-						"bus_uart2", "bus_uart3",
-						"bus_uart4";
-			};
-		};
-
-		mmc0_clk: mmc0_clk at 1c20088 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
-			clock-output-names = "mmc0";
-                };
-
-		mmc1_clk: mmc1_clk at 1c2008c {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
-			clock-output-names = "mmc1";
-		};
-
-		mmc2_clk: mmc2_clk at 1c20090 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
-			clock-output-names = "mmc2";
-		};
-	};
-
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -319,240 +122,196 @@
 		ranges;
 
 		mmc0: mmc at 1c0f000 {
-			compatible = "allwinner,sun50i-a64-mmc",
-				     "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun50i-a64-mmc";
 			reg = <0x01c0f000 0x1000>;
-			clocks = <&bus_gates 8>, <&mmc0_clk>,
-				 <&mmc0_clk>, <&mmc0_clk>;
-			clock-names = "ahb", "mmc",
-				      "output", "sample";
-			resets = <&ahb_rst 8>;
+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC0>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <150000000>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
 		mmc1: mmc at 1c10000 {
-			compatible = "allwinner,sun50i-a64-mmc",
-				     "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun50i-a64-mmc";
 			reg = <0x01c10000 0x1000>;
-			clocks = <&bus_gates 9>, <&mmc1_clk>,
-				 <&mmc1_clk>, <&mmc1_clk>;
-			clock-names = "ahb", "mmc",
-				      "output", "sample";
-			resets = <&ahb_rst 9>;
+			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC1>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <150000000>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
 		mmc2: mmc at 1c11000 {
-			compatible = "allwinner,sun50i-a64-mmc",
-				     "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun50i-a64-emmc";
 			reg = <0x01c11000 0x1000>;
-			clocks = <&bus_gates 10>, <&mmc2_clk>,
-				 <&mmc2_clk>, <&mmc2_clk>;
-			clock-names = "ahb", "mmc",
-				      "output", "sample";
-			resets = <&ahb_rst 10>;
+			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC2>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <200000000>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
+		usb_otg: usb at 01c19000 {
+			compatible = "allwinner,sun8i-a33-musb";
+			reg = <0x01c19000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			status = "disabled";
+		};
+
+		usbphy: phy at 01c19400 {
+			compatible = "allwinner,sun50i-a64-usb-phy";
+			reg = <0x01c19400 0x14>,
+			      <0x01c1b800 0x4>;
+			reg-names = "phy_ctrl",
+				    "pmu1";
+			clocks = <&ccu CLK_USB_PHY0>,
+				 <&ccu CLK_USB_PHY1>;
+			clock-names = "usb0_phy",
+				      "usb1_phy";
+			resets = <&ccu RST_USB_PHY0>,
+				 <&ccu RST_USB_PHY1>;
+			reset-names = "usb0_reset",
+				      "usb1_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
+		ehci1: usb at 01c1b000 {
+			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+			reg = <0x01c1b000 0x100>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_BUS_EHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>,
+				 <&ccu RST_BUS_EHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci1: usb at 01c1b400 {
+			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+			reg = <0x01c1b400 0x100>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ccu: clock at 01c20000 {
+			compatible = "allwinner,sun50i-a64-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		pio: pinctrl at 1c20800 {
 			compatible = "allwinner,sun50i-a64-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&bus_gates 69>;
+			clocks = <&ccu 58>;
 			gpio-controller;
 			#gpio-cells = <3>;
 			interrupt-controller;
-			#interrupt-cells = <2>;
-
-			uart0_pins_a: uart0 at 0 {
-				allwinner,pins = "PB8", "PB9";
-				allwinner,function = "uart0";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart0_pins_b: uart0 at 1 {
-				allwinner,pins = "PF2", "PF3";
-				allwinner,function = "uart0";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart1_2pins: uart1_2 at 0 {
-				allwinner,pins = "PG6", "PG7";
-				allwinner,function = "uart1";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart1_4pins: uart1_4 at 0 {
-				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
-				allwinner,function = "uart1";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart2_2pins: uart2_2 at 0 {
-				allwinner,pins = "PB0", "PB1";
-				allwinner,function = "uart2";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart2_4pins: uart2_4 at 0 {
-				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
-				allwinner,function = "uart2";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart3_pins_a: uart3 at 0 {
-				allwinner,pins = "PD0", "PD1";
-				allwinner,function = "uart3";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart3_2pins_b: uart3_2 at 1 {
-				allwinner,pins = "PH4", "PH5";
-				allwinner,function = "uart3";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart3_4pins_b: uart3_4 at 1 {
-				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
-				allwinner,function = "uart3";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart4_2pins: uart4_2 at 0 {
-				allwinner,pins = "PD2", "PD3";
-				allwinner,function = "uart4";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart4_4pins: uart4_4 at 0 {
-				allwinner,pins = "PD2", "PD3", "PD4", "PD5";
-				allwinner,function = "uart4";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
+			#interrupt-cells = <3>;
 
-			mmc0_pins: mmc0 at 0 {
-				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
-						 "PF4", "PF5";
-				allwinner,function = "mmc0";
-				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			i2c1_pins: i2c1_pins {
+				pins = "PH2", "PH3";
+				function = "i2c1";
 			};
 
-			mmc0_default_cd_pin: mmc0_cd_pin at 0 {
-				allwinner,pins = "PF6";
-				allwinner,function = "gpio_in";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3",
+				       "PF4", "PF5";
+				function = "mmc0";
+				drive-strength = <30>;
+				bias-pull-up;
 			};
 
-			mmc1_pins: mmc1 at 0 {
-				allwinner,pins = "PG0", "PG1", "PG2", "PG3",
-						 "PG4", "PG5";
-				allwinner,function = "mmc1";
-				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			mmc1_pins: mmc1-pins {
+				pins = "PG0", "PG1", "PG2", "PG3",
+				       "PG4", "PG5";
+				function = "mmc1";
+				drive-strength = <30>;
+				bias-pull-up;
 			};
 
-			mmc2_pins: mmc2 at 0 {
-				allwinner,pins = "PC1", "PC5", "PC6", "PC8",
-						 "PC9", "PC10";
-				allwinner,function = "mmc2";
-				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			mmc2_pins: mmc2-pins {
+				pins = "PC1", "PC5", "PC6", "PC8", "PC9",
+				       "PC10","PC11", "PC12", "PC13",
+				       "PC14", "PC15", "PC16";
+				function = "mmc2";
+				drive-strength = <30>;
+				bias-pull-up;
 			};
 
-			i2c0_pins: i2c0_pins {
-				allwinner,pins = "PH0", "PH1";
-				allwinner,function = "i2c0";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			rmii_pins: rmii_pins {
+				pins = "PD10", "PD11", "PD13", "PD14",
+				       "PD17", "PD18", "PD19", "PD20",
+				       "PD22", "PD23";
+				function = "emac";
+				drive-strength = <40>;
 			};
 
-			i2c1_pins: i2c1_pins {
-				allwinner,pins = "PH2", "PH3";
-				allwinner,function = "i2c1";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			rgmii_pins: rgmii_pins {
+				pins = "PD8", "PD9", "PD10", "PD11",
+				       "PD12", "PD13", "PD15",
+				       "PD16", "PD17", "PD18", "PD19",
+				       "PD20", "PD21", "PD22", "PD23";
+				function = "emac";
+				drive-strength = <40>;
 			};
 
-			i2c2_pins: i2c2_pins {
-				allwinner,pins = "PE14", "PE15";
-				allwinner,function = "i2c2";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			uart0_pins_a: uart0 at 0 {
+				pins = "PB8", "PB9";
+				function = "uart0";
 			};
 
-			rmii_pins: rmii_pins {
-				allwinner,pins = "PD10", "PD11", "PD13", "PD14",
-						 "PD17", "PD18", "PD19", "PD20",
-						 "PD22", "PD23";
-				allwinner,function = "emac";
-				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			uart1_pins: uart1_pins {
+				pins = "PG6", "PG7";
+				function = "uart1";
 			};
 
-			rgmii_pins: rgmii_pins {
-				allwinner,pins = "PD8", "PD9", "PD10", "PD11",
-						 "PD12", "PD13", "PD15",
-						 "PD16", "PD17", "PD18", "PD19",
-						 "PD20", "PD21", "PD22", "PD23";
-				allwinner,function = "emac";
-				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			uart1_rts_cts_pins: uart1_rts_cts_pins {
+				pins = "PG8", "PG9";
+				function = "uart1";
 			};
 		};
 
-		ahb_rst: reset at 1c202c0 {
-			#reset-cells = <1>;
-			compatible = "allwinner,sun6i-a31-clock-reset";
-			reg = <0x01c202c0 0xc>;
-		};
-
-		apb1_rst: reset at 1c202d0 {
-			#reset-cells = <1>;
-			compatible = "allwinner,sun6i-a31-clock-reset";
-			reg = <0x01c202d0 0x4>;
-		};
-
-		apb2_rst: reset at 1c202d8 {
-			#reset-cells = <1>;
-			compatible = "allwinner,sun6i-a31-clock-reset";
-			reg = <0x01c202d8 0x4>;
-		};
-
 		uart0: serial at 1c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&bus_gates 112>;
-			resets = <&apb2_rst 16>;
+			clocks = <&ccu 67>;
+			resets = <&ccu 46>;
 			status = "disabled";
 		};
 
@@ -562,8 +321,8 @@
 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&bus_gates 113>;
-			resets = <&apb2_rst 17>;
+			clocks = <&ccu 68>;
+			resets = <&ccu 47>;
 			status = "disabled";
 		};
 
@@ -573,8 +332,8 @@
 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&bus_gates 114>;
-			resets = <&apb2_rst 18>;
+			clocks = <&ccu 69>;
+			resets = <&ccu 48>;
 			status = "disabled";
 		};
 
@@ -584,8 +343,8 @@
 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&bus_gates 115>;
-			resets = <&apb2_rst 19>;
+			clocks = <&ccu 70>;
+			resets = <&ccu 49>;
 			status = "disabled";
 		};
 
@@ -595,24 +354,17 @@
 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&bus_gates 116>;
-			resets = <&apb2_rst 20>;
+			clocks = <&ccu 71>;
+			resets = <&ccu 50>;
 			status = "disabled";
 		};
 
-		rtc: rtc at 1f00000 {
-			compatible = "allwinner,sun6i-a31-rtc";
-			reg = <0x01f00000 0x54>;
-			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
 		i2c0: i2c at 1c2ac00 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2ac00 0x400>;
 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&bus_gates 96>;
-			resets = <&apb2_rst 0>;
+			clocks = <&ccu 63>;
+			resets = <&ccu 42>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -622,8 +374,8 @@
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2b000 0x400>;
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&bus_gates 97>;
-			resets = <&apb2_rst 1>;
+			clocks = <&ccu 64>;
+			resets = <&ccu 43>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -633,8 +385,8 @@
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2b400 0x400>;
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&bus_gates 98>;
-			resets = <&apb2_rst 2>;
+			clocks = <&ccu 65>;
+			resets = <&ccu 44>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -645,42 +397,31 @@
 			reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
 			reg-names = "emac", "syscon";
 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&ahb_rst 17>;
+			resets = <&ccu RST_BUS_EMAC>;
 			reset-names = "ahb";
-			clocks = <&bus_gates 17>;
+			clocks = <&ccu CLK_BUS_EMAC>;
 			clock-names = "ahb";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
-		usbphy: phy at 1c1b810 {
-			compatible = "allwinner,sun50i-a64-usb-phy",
-				     "allwinner,sun8i-a33-usb-phy";
-			reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>;
-			reg-names = "phy_ctrl", "pmu1";
-			status = "disabled";
-			#phy-cells = <1>;
-		};
-
-		ehci1: usb at 01c1b000 {
-			compatible = "allwinner,sun50i-a64-ehci",
-				     "generic-ehci";
-			reg = <0x01c1b000 0x100>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&usbphy 1>;
-			phy-names = "usb";
-			status = "disabled";
+		gic: interrupt-controller at 1c81000 {
+			compatible = "arm,gic-400";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x2000>,
+			      <0x01c84000 0x2000>,
+			      <0x01c86000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
 		};
 
-		ohci1: usb at 01c1b400 {
-			compatible = "allwinner,sun50i-a64-ohci",
-				     "generic-ohci";
-			reg = <0x01c1b400 0x100>;
-			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&usbphy 1>;
-			phy-names = "usb";
-			status = "enabled";
+		rtc: rtc at 1f00000 {
+			compatible = "allwinner,sun6i-a31-rtc";
+			reg = <0x01f00000 0x54>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
 };
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
new file mode 100644
index 0000000..370c0a0
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
+#define _DT_BINDINGS_CLK_SUN50I_A64_H_
+
+#define CLK_BUS_MIPI_DSI	28
+#define CLK_BUS_CE		29
+#define CLK_BUS_DMA		30
+#define CLK_BUS_MMC0		31
+#define CLK_BUS_MMC1		32
+#define CLK_BUS_MMC2		33
+#define CLK_BUS_NAND		34
+#define CLK_BUS_DRAM		35
+#define CLK_BUS_EMAC		36
+#define CLK_BUS_TS		37
+#define CLK_BUS_HSTIMER		38
+#define CLK_BUS_SPI0		39
+#define CLK_BUS_SPI1		40
+#define CLK_BUS_OTG		41
+#define CLK_BUS_EHCI0		42
+#define CLK_BUS_EHCI1		43
+#define CLK_BUS_OHCI0		44
+#define CLK_BUS_OHCI1		45
+#define CLK_BUS_VE		46
+#define CLK_BUS_TCON0		47
+#define CLK_BUS_TCON1		48
+#define CLK_BUS_DEINTERLACE	49
+#define CLK_BUS_CSI		50
+#define CLK_BUS_HDMI		51
+#define CLK_BUS_DE		52
+#define CLK_BUS_GPU		53
+#define CLK_BUS_MSGBOX		54
+#define CLK_BUS_SPINLOCK	55
+#define CLK_BUS_CODEC		56
+#define CLK_BUS_SPDIF		57
+#define CLK_BUS_PIO		58
+#define CLK_BUS_THS		59
+#define CLK_BUS_I2S0		60
+#define CLK_BUS_I2S1		61
+#define CLK_BUS_I2S2		62
+#define CLK_BUS_I2C0		63
+#define CLK_BUS_I2C1		64
+#define CLK_BUS_I2C2		65
+#define CLK_BUS_SCR		66
+#define CLK_BUS_UART0		67
+#define CLK_BUS_UART1		68
+#define CLK_BUS_UART2		69
+#define CLK_BUS_UART3		70
+#define CLK_BUS_UART4		71
+#define CLK_BUS_DBG		72
+#define CLK_THS			73
+#define CLK_NAND		74
+#define CLK_MMC0		75
+#define CLK_MMC1		76
+#define CLK_MMC2		77
+#define CLK_TS			78
+#define CLK_CE			79
+#define CLK_SPI0		80
+#define CLK_SPI1		81
+#define CLK_I2S0		82
+#define CLK_I2S1		83
+#define CLK_I2S2		84
+#define CLK_SPDIF		85
+#define CLK_USB_PHY0		86
+#define CLK_USB_PHY1		87
+#define CLK_USB_HSIC		88
+#define CLK_USB_HSIC_12M	89
+
+#define CLK_USB_OHCI0		91
+
+#define CLK_USB_OHCI1		93
+
+#define CLK_DRAM_VE		95
+#define CLK_DRAM_CSI		96
+#define CLK_DRAM_DEINTERLACE	97
+#define CLK_DRAM_TS		98
+#define CLK_DE			99
+#define CLK_TCON0		100
+#define CLK_TCON1		101
+#define CLK_DEINTERLACE		102
+#define CLK_CSI_MISC		103
+#define CLK_CSI_SCLK		104
+#define CLK_CSI_MCLK		105
+#define CLK_VE			106
+#define CLK_AC_DIG		107
+#define CLK_AC_DIG_4X		108
+#define CLK_AVS			109
+#define CLK_HDMI		110
+#define CLK_HDMI_DDC		111
+
+#define CLK_DSI_DPHY		113
+#define CLK_GPU			114
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */
diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h
new file mode 100644
index 0000000..db60b29
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-a64-ccu.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
+#define _DT_BINDINGS_RST_SUN50I_A64_H_
+
+#define RST_USB_PHY0		0
+#define RST_USB_PHY1		1
+#define RST_USB_HSIC		2
+#define RST_DRAM		3
+#define RST_MBUS		4
+#define RST_BUS_MIPI_DSI	5
+#define RST_BUS_CE		6
+#define RST_BUS_DMA		7
+#define RST_BUS_MMC0		8
+#define RST_BUS_MMC1		9
+#define RST_BUS_MMC2		10
+#define RST_BUS_NAND		11
+#define RST_BUS_DRAM		12
+#define RST_BUS_EMAC		13
+#define RST_BUS_TS		14
+#define RST_BUS_HSTIMER		15
+#define RST_BUS_SPI0		16
+#define RST_BUS_SPI1		17
+#define RST_BUS_OTG		18
+#define RST_BUS_EHCI0		19
+#define RST_BUS_EHCI1		20
+#define RST_BUS_OHCI0		21
+#define RST_BUS_OHCI1		22
+#define RST_BUS_VE		23
+#define RST_BUS_TCON0		24
+#define RST_BUS_TCON1		25
+#define RST_BUS_DEINTERLACE	26
+#define RST_BUS_CSI		27
+#define RST_BUS_HDMI0		28
+#define RST_BUS_HDMI1		29
+#define RST_BUS_DE		30
+#define RST_BUS_GPU		31
+#define RST_BUS_MSGBOX		32
+#define RST_BUS_SPINLOCK	33
+#define RST_BUS_DBG		34
+#define RST_BUS_LVDS		35
+#define RST_BUS_CODEC		36
+#define RST_BUS_SPDIF		37
+#define RST_BUS_THS		38
+#define RST_BUS_I2S0		39
+#define RST_BUS_I2S1		40
+#define RST_BUS_I2S2		41
+#define RST_BUS_I2C0		42
+#define RST_BUS_I2C1		43
+#define RST_BUS_I2C2		44
+#define RST_BUS_SCR		45
+#define RST_BUS_UART0		46
+#define RST_BUS_UART1		47
+#define RST_BUS_UART2		48
+#define RST_BUS_UART3		49
+#define RST_BUS_UART4		50
+
+#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */
-- 
2.8.2

[U-Boot] [PATCH 4/6] sunxi: dts: update Pine64 .dts

[Andre Przywara]

Update the two .dts files for the Pine64 boards with those used in the
kernel. This switches from using a -common.dtsi to including the .dts
for the non-plus model in the -plus file.
Again we keep our EMAC driver nodes in, which are not yet in mainline
Linux.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/dts/sun50i-a64-pine64-plus.dts | 16 ++------
 arch/arm/dts/sun50i-a64-pine64.dts      | 72 +++++++++++++++++++++++++++++++--
 2 files changed, 72 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts
index 389c609..65c698c 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus.dts
+++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts
@@ -40,22 +40,13 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/dts-v1/;
-
-#include "sun50i-a64-pine64-common.dtsi"
+#include "sun50i-a64-pine64.dts"
 
 / {
 	model = "Pine64+";
 	compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
 
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	/* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
-	memory {
-		reg = <0x40000000 0x40000000>;
-	};
+	/* TODO: Camera, Ethernet PHY, touchscreen, etc. */
 };
 
 &emac {
@@ -66,7 +57,6 @@
 	status = "okay";
 
 	phy1: ethernet-phy at 1 {
-	reg = <1>;
+		reg = <1>;
 	};
 };
-
diff --git a/arch/arm/dts/sun50i-a64-pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts
index ebe029e..006aa04 100644
--- a/arch/arm/dts/sun50i-a64-pine64.dts
+++ b/arch/arm/dts/sun50i-a64-pine64.dts
@@ -42,17 +42,83 @@
 
 /dts-v1/;
 
-#include "sun50i-a64-pine64-common.dtsi"
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Pine64";
 	compatible = "pine64,pine64", "allwinner,sun50i-a64";
 
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &emac;
+	};
+
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
-		reg = <0x40000000 0x20000000>;
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rmii_pins>;
+	phy-mode = "rmii";
+	phy = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy at 1 {
+		reg = <1>;
 	};
 };
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+&i2c1_pins {
+	bias-pull-up;
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&reg_vcc3v3>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+	disable-wp;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
-- 
2.8.2

[U-Boot] [PATCH 5/6] sunxi: dts: remove now obsolete pine64-common.dtsi

[Andre Przywara]

Now since the common DT nodes between the two Pine64 boards have been
moved into the .dts for the non-plus model, we no longer need the
extra -common.dtsi.
Let's just remove it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/dts/sun50i-a64-pine64-common.dtsi | 93 ------------------------------
 1 file changed, 93 deletions(-)
 delete mode 100644 arch/arm/dts/sun50i-a64-pine64-common.dtsi

diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
deleted file mode 100644
index a42b0fa..0000000
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016 ARM Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "sun50i-a64.dtsi"
-
-/ {
-
-	aliases {
-		serial0 = &uart0;
-		ethernet0 = &emac;
-	};
-
-	soc {
-		reg_vcc3v3: vcc3v3 {
-			compatible = "regulator-fixed";
-			regulator-name = "vcc3v3";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-		};
-	};
-};
-
-&mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>;
-	vmmc-supply = <&reg_vcc3v3>;
-	cd-gpios = <&pio 5 6 0>;
-	cd-inverted;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
-	status = "okay";
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-	status = "okay";
-};
-
-&usbphy {
-       status = "okay";
-};
-
-&ohci1 {
-       status = "okay";
-};
-
-&ehci1 {
-       status = "okay";
-};
-- 
2.8.2

[U-Boot] [PATCH 6/6] sunxi: dts: add Bananapi M64 .dts

[Andre Przywara]

Since mainline Linux gained support for the BananaPi-M64, let's just
copy this DT to prepare the U-Boot support for that board.
Again add the required DT nodes for the Ethernet IP.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/dts/Makefile                    |   3 +-
 arch/arm/dts/sun50i-a64-bananapi-m64.dts | 135 +++++++++++++++++++++++++++++++
 2 files changed, 137 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-a64-bananapi-m64.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eeaa9e0..ffe1a9e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -299,7 +299,8 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-orangepi-pc2.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-pine64-plus.dtb \
-	sun50i-a64-pine64.dtb
+	sun50i-a64-pine64.dtb \
+	sun50i-a64-bananapi-m64.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
new file mode 100644
index 0000000..943b303
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "BananaPi-M64";
+	compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		ethernet0 = &emac;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+&i2c1_pins {
+	bias-pull-up;
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&reg_vcc3v3>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+	disable-wp;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+	status = "okay";
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii";
+
+	allwinner,leds-active-low;
+	status = "okay";
+
+	phy1: ethernet-phy at 1 {
+		reg = <1>;
+	};
+};
-- 
2.8.2

[U-Boot] [PATCH 0/6] sunxi: update Pine64/A64 DTs

[Chen-Yu Tsai]

On Mon, Feb 27, 2017 at 8:26 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Hi,
>
> in the wake of the sunxi DM enablement series it became apparent that
> the current device tree files for the A64 SoC and its board are outdated.
>
> Since Linux v4.10-rc1 there are now basic .dts files for the Allwinner
> A64 SoC and the Pine64 boards in the mainline kernel.
> Linux v4.11-rc1 added MMC and USB support.
> Because our preliminary device trees used in U-Boot differ significantly,
> let's update our copy with what's in the current Linus' master tree.
> Since in contrast to U-Boot the kernel still lacks support for Ethernet,
> we keep our preliminary nodes for that IP, but adjust it slightly to
> match the new clocks and reset bindings.
>
> As the sun8i-emac driver is actually using the DT for the pinmux setup,
> we teach it how to cope with the new pinctrl bindings in the first two
> patches. This is probably becoming somewhat obsolete very soon (with
> DM GPIO support on the list already), however I consider these two
> patches as merely fixes for the existing driver to maintain bisectability.
> It would make sense to merge the new DTs before the DM patches, so we
> need to have something in place which works meanwhile.
>
> Let me know what you think.
>
> Cheers,
> Andre.
>
> Andre Przywara (6):
>   sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()
>   net: sun8i-emac: use new, generic GPIO setup routine
>   sunxi: dts: update sun50i-a64.dtsi from Linux
>   sunxi: dts: update Pine64 .dts
>   sunxi: dts: remove now obsolete pine64-common.dtsi
>   sunxi: dts: add Bananapi M64 .dts

Could we keep this simple, and just do a "sync with the kernel" commit for
sun50i, which also keeps the sun8i-emac specific bits. And also explicitly
mention the git commit or tag you are syncing to.

ChenYu

>
>  arch/arm/dts/Makefile                      |   3 +-
>  arch/arm/dts/sun50i-a64-bananapi-m64.dts   | 135 +++++++
>  arch/arm/dts/sun50i-a64-pine64-common.dtsi |  93 -----
>  arch/arm/dts/sun50i-a64-pine64-plus.dts    |  16 +-
>  arch/arm/dts/sun50i-a64-pine64.dts         |  72 +++-
>  arch/arm/dts/sun50i-a64.dtsi               | 615 +++++++++--------------------
>  arch/arm/include/asm/arch-sunxi/gpio.h     |   4 +
>  arch/arm/mach-sunxi/pinmux.c               |  77 ++++
>  drivers/net/sun8i_emac.c                   |  38 +-
>  include/dt-bindings/clock/sun50i-a64-ccu.h | 134 +++++++
>  include/dt-bindings/reset/sun50i-a64-ccu.h |  98 +++++
>  11 files changed, 706 insertions(+), 579 deletions(-)
>  create mode 100644 arch/arm/dts/sun50i-a64-bananapi-m64.dts
>  delete mode 100644 arch/arm/dts/sun50i-a64-pine64-common.dtsi
>  create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
>
> --
> 2.8.2
>

[U-Boot] [PATCH 1/6] sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()

[Chen-Yu Tsai]

On Mon, Feb 27, 2017 at 8:26 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Instead of hard-coding GPIO pins used for a certain peripheral, we
> should just use the pinctrl information from the DT.
> The sun8i-emac driver has some simple implementation of that, so
> let's just generalize this and move the code into a more common
> location.
> On the way we add support for the new, generic pinctrl binding now
> used by all Allwinner SoCs.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/include/asm/arch-sunxi/gpio.h |  4 ++
>  arch/arm/mach-sunxi/pinmux.c           | 77 ++++++++++++++++++++++++++++++++++
>  2 files changed, 81 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 85a4ec3..ba8c661 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -239,4 +239,8 @@ int axp_gpio_init(void);
>  static inline int axp_gpio_init(void) { return 0; }
>  #endif
>
> +int sunxi_gpio_parse_pin_name(const char *pin_name);
> +int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
> +                            const char * mux_name, int mux_sel);
> +
>  #endif /* _SUNXI_GPIO_H */
> diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
> index b026f78..f1e1e8f 100644
> --- a/arch/arm/mach-sunxi/pinmux.c
> +++ b/arch/arm/mach-sunxi/pinmux.c
> @@ -9,6 +9,9 @@
>  #include <common.h>
>  #include <asm/io.h>
>  #include <asm/arch/gpio.h>
> +#include <fdtdec.h>
> +#include <fdt_support.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>
>  void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
>  {
> @@ -69,3 +72,77 @@ int sunxi_gpio_set_pull(u32 pin, u32 val)
>
>         return 0;
>  }
> +
> +int sunxi_gpio_parse_pin_name(const char *pin_name)
> +{
> +       int pin;
> +
> +       if (pin_name[0] != 'P')
> +               return -1;
> +
> +       if (pin_name[1] < 'A' || pin_name[1] > 'Z')
> +               return -1;
> +
> +       pin = (pin_name[1] - 'A') << 5;
> +       pin += simple_strtol(&pin_name[2], NULL, 10);
> +
> +       return pin;
> +}
> +
> +int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
> +                            const char * mux_name, int mux_sel)
> +{
> +       int drive, pull, pin, i;
> +       const char *pin_name;
> +       int offset;
> +
> +       offset = fdtdec_lookup_phandle(fdt_blob, node, "pinctrl-0");
> +       if (offset < 0)
> +               return offset;
> +
> +       drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
> +                                            "drive-strength", 0);
> +       if (drive) {
> +               if (drive <= 10)
> +                       drive = SUN4I_PINCTRL_10_MA;
> +               else if (drive <= 20)
> +                       drive = SUN4I_PINCTRL_20_MA;
> +               else if (drive <= 30)
> +                       drive = SUN4I_PINCTRL_30_MA;
> +               else
> +                       drive = SUN4I_PINCTRL_40_MA;
> +       } else {
> +               drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
> +                                                    "allwinner,drive", 4);

You should use a different default, something invalid.


> +       }
> +
> +       if (fdt_get_property(fdt_blob, offset, "bias-pull-up", NULL))
> +               pull = SUN4I_PINCTRL_PULL_UP;
> +       else if (fdt_get_property(fdt_blob, offset, "bias-disable", NULL))
> +               pull = SUN4I_PINCTRL_NO_PULL;
> +       else if (fdt_get_property(fdt_blob, offset, "bias-pull-down", NULL))
> +               pull = SUN4I_PINCTRL_PULL_DOWN;
> +       else
> +               pull = fdt_getprop_u32_default_node(fdt_blob, offset, 0,
> +                                                   "allwinner,pull", 0);

Same here.

> +
> +       for (i = 0; ; i++) {
> +               pin_name = fdt_stringlist_get(fdt_blob, offset,
> +                                             "allwinner,pins", i, NULL);
> +               if (!pin_name) {
> +                       pin_name = fdt_stringlist_get(fdt_blob, offset,
> +                                                     "pins", i, NULL);
> +                       if (!pin_name)
> +                               break;
> +               }
> +               pin = sunxi_gpio_parse_pin_name(pin_name);
> +               if (pin < 0)
> +                       continue;
> +
> +               sunxi_gpio_set_cfgpin(pin, mux_sel);
> +               sunxi_gpio_set_drv(pin, drive);
> +               sunxi_gpio_set_pull(pin, pull);

As the defaults implied by the bindings are to not touch the settings
if they aren't specified, as in "whatever the hardware was set to".
This applies to both drive strength and bias/pull.

Regards
ChenYu

> +       }
> +
> +       return i;
> +}
> --
> 2.8.2
>

[U-Boot] [PATCH 0/6] sunxi: update Pine64/A64 DTs

[Andre Przywara]

Hi,

On 27/02/17 03:30, Chen-Yu Tsai wrote:
> On Mon, Feb 27, 2017 at 8:26 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>> Hi,
>>
>> in the wake of the sunxi DM enablement series it became apparent that
>> the current device tree files for the A64 SoC and its board are outdated.
>>
>> Since Linux v4.10-rc1 there are now basic .dts files for the Allwinner
>> A64 SoC and the Pine64 boards in the mainline kernel.
>> Linux v4.11-rc1 added MMC and USB support.
>> Because our preliminary device trees used in U-Boot differ significantly,
>> let's update our copy with what's in the current Linus' master tree.
>> Since in contrast to U-Boot the kernel still lacks support for Ethernet,
>> we keep our preliminary nodes for that IP, but adjust it slightly to
>> match the new clocks and reset bindings.
>>
>> As the sun8i-emac driver is actually using the DT for the pinmux setup,
>> we teach it how to cope with the new pinctrl bindings in the first two
>> patches. This is probably becoming somewhat obsolete very soon (with
>> DM GPIO support on the list already), however I consider these two
>> patches as merely fixes for the existing driver to maintain bisectability.
>> It would make sense to merge the new DTs before the DM patches, so we
>> need to have something in place which works meanwhile.
>>
>> Let me know what you think.
>>
>> Cheers,
>> Andre.
>>
>> Andre Przywara (6):
>>   sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()
>>   net: sun8i-emac: use new, generic GPIO setup routine
>>   sunxi: dts: update sun50i-a64.dtsi from Linux
>>   sunxi: dts: update Pine64 .dts
>>   sunxi: dts: remove now obsolete pine64-common.dtsi
>>   sunxi: dts: add Bananapi M64 .dts
> 
> Could we keep this simple, and just do a "sync with the kernel" commit for
> sun50i, which also keeps the sun8i-emac specific bits. And also explicitly
> mention the git commit or tag you are syncing to.

So you mean to drop patch 1 and 2 and keep the old style pinctrl
bindings around for the EMAC node?
I can certainly do this (if others agree), but didn't want to dodge a
more proper solution in the first place.

Another alternative would be to squash the functionality of patch 1
directly into sun8i_emac.c, so without the moving to pinmux.c. This
would mean dropping patch 1/6 and just having a fix for the sun8i_emac.

Let me know what's the preferred solution here.

Cheers,
Andre.

>>  arch/arm/dts/Makefile                      |   3 +-
>>  arch/arm/dts/sun50i-a64-bananapi-m64.dts   | 135 +++++++
>>  arch/arm/dts/sun50i-a64-pine64-common.dtsi |  93 -----
>>  arch/arm/dts/sun50i-a64-pine64-plus.dts    |  16 +-
>>  arch/arm/dts/sun50i-a64-pine64.dts         |  72 +++-
>>  arch/arm/dts/sun50i-a64.dtsi               | 615 +++++++++--------------------
>>  arch/arm/include/asm/arch-sunxi/gpio.h     |   4 +
>>  arch/arm/mach-sunxi/pinmux.c               |  77 ++++
>>  drivers/net/sun8i_emac.c                   |  38 +-
>>  include/dt-bindings/clock/sun50i-a64-ccu.h | 134 +++++++
>>  include/dt-bindings/reset/sun50i-a64-ccu.h |  98 +++++
>>  11 files changed, 706 insertions(+), 579 deletions(-)
>>  create mode 100644 arch/arm/dts/sun50i-a64-bananapi-m64.dts
>>  delete mode 100644 arch/arm/dts/sun50i-a64-pine64-common.dtsi
>>  create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
>>  create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
>>
>> --
>> 2.8.2
>>

[U-Boot] [PATCH 1/6] sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()

[Maxime Ripard]

On Mon, Feb 27, 2017 at 12:26:40AM +0000, Andre Przywara wrote:
> Instead of hard-coding GPIO pins used for a certain peripheral, we
> should just use the pinctrl information from the DT.
> The sun8i-emac driver has some simple implementation of that, so
> let's just generalize this and move the code into a more common
> location.
> On the way we add support for the new, generic pinctrl binding now
> used by all Allwinner SoCs.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/include/asm/arch-sunxi/gpio.h |  4 ++
>  arch/arm/mach-sunxi/pinmux.c           | 77 ++++++++++++++++++++++++++++++++++
>  2 files changed, 81 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 85a4ec3..ba8c661 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -239,4 +239,8 @@ int axp_gpio_init(void);
>  static inline int axp_gpio_init(void) { return 0; }
>  #endif
>  
> +int sunxi_gpio_parse_pin_name(const char *pin_name);
> +int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
> +			     const char * mux_name, int mux_sel);
> +
>  #endif /* _SUNXI_GPIO_H */
> diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
> index b026f78..f1e1e8f 100644
> --- a/arch/arm/mach-sunxi/pinmux.c
> +++ b/arch/arm/mach-sunxi/pinmux.c
> @@ -9,6 +9,9 @@
>  #include <common.h>
>  #include <asm/io.h>
>  #include <asm/arch/gpio.h>
> +#include <fdtdec.h>
> +#include <fdt_support.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>  
>  void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
>  {
> @@ -69,3 +72,77 @@ int sunxi_gpio_set_pull(u32 pin, u32 val)
>  
>  	return 0;
>  }
> +
> +int sunxi_gpio_parse_pin_name(const char *pin_name)
> +{
> +	int pin;
> +
> +	if (pin_name[0] != 'P')
> +		return -1;
> +
> +	if (pin_name[1] < 'A' || pin_name[1] > 'Z')
> +		return -1;
> +
> +	pin = (pin_name[1] - 'A') << 5;
> +	pin += simple_strtol(&pin_name[2], NULL, 10);
> +
> +	return pin;
> +}

That function already exists, sunxi_name_to_gpio.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 801 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170227/de627360/attachment.sig>

[U-Boot] [PATCH 1/6] sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()

[Andre Przywara]

Hi,

On 27/02/17 10:07, Maxime Ripard wrote:
> On Mon, Feb 27, 2017 at 12:26:40AM +0000, Andre Przywara wrote:
>> Instead of hard-coding GPIO pins used for a certain peripheral, we
>> should just use the pinctrl information from the DT.
>> The sun8i-emac driver has some simple implementation of that, so
>> let's just generalize this and move the code into a more common
>> location.
>> On the way we add support for the new, generic pinctrl binding now
>> used by all Allwinner SoCs.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>>  arch/arm/include/asm/arch-sunxi/gpio.h |  4 ++
>>  arch/arm/mach-sunxi/pinmux.c           | 77 ++++++++++++++++++++++++++++++++++
>>  2 files changed, 81 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
>> index 85a4ec3..ba8c661 100644
>> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
>> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
>> @@ -239,4 +239,8 @@ int axp_gpio_init(void);
>>  static inline int axp_gpio_init(void) { return 0; }
>>  #endif
>>  
>> +int sunxi_gpio_parse_pin_name(const char *pin_name);
>> +int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node,
>> +			     const char * mux_name, int mux_sel);
>> +
>>  #endif /* _SUNXI_GPIO_H */
>> diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
>> index b026f78..f1e1e8f 100644
>> --- a/arch/arm/mach-sunxi/pinmux.c
>> +++ b/arch/arm/mach-sunxi/pinmux.c
>> @@ -9,6 +9,9 @@
>>  #include <common.h>
>>  #include <asm/io.h>
>>  #include <asm/arch/gpio.h>
>> +#include <fdtdec.h>
>> +#include <fdt_support.h>
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>>  
>>  void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
>>  {
>> @@ -69,3 +72,77 @@ int sunxi_gpio_set_pull(u32 pin, u32 val)
>>  
>>  	return 0;
>>  }
>> +
>> +int sunxi_gpio_parse_pin_name(const char *pin_name)
>> +{
>> +	int pin;
>> +
>> +	if (pin_name[0] != 'P')
>> +		return -1;
>> +
>> +	if (pin_name[1] < 'A' || pin_name[1] > 'Z')
>> +		return -1;
>> +
>> +	pin = (pin_name[1] - 'A') << 5;
>> +	pin += simple_strtol(&pin_name[2], NULL, 10);
>> +
>> +	return pin;
>> +}
> 
> That function already exists, sunxi_name_to_gpio.

Indeed, I found this yesterday _after_ sending the patches ;-)
For some reasons I missed that when I originally wrote the patches,
sorry for that.

Cheers,
Andre.

[U-Boot] [PATCH 0/6] sunxi: update Pine64/A64 DTs

[Chen-Yu Tsai]

Hi,

On Mon, Feb 27, 2017 at 5:53 PM, Andre Przywara <andre.przywara@arm.com> wrote:
> Hi,
>
> On 27/02/17 03:30, Chen-Yu Tsai wrote:
>> On Mon, Feb 27, 2017 at 8:26 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>>> Hi,
>>>
>>> in the wake of the sunxi DM enablement series it became apparent that
>>> the current device tree files for the A64 SoC and its board are outdated.
>>>
>>> Since Linux v4.10-rc1 there are now basic .dts files for the Allwinner
>>> A64 SoC and the Pine64 boards in the mainline kernel.
>>> Linux v4.11-rc1 added MMC and USB support.
>>> Because our preliminary device trees used in U-Boot differ significantly,
>>> let's update our copy with what's in the current Linus' master tree.
>>> Since in contrast to U-Boot the kernel still lacks support for Ethernet,
>>> we keep our preliminary nodes for that IP, but adjust it slightly to
>>> match the new clocks and reset bindings.
>>>
>>> As the sun8i-emac driver is actually using the DT for the pinmux setup,
>>> we teach it how to cope with the new pinctrl bindings in the first two
>>> patches. This is probably becoming somewhat obsolete very soon (with
>>> DM GPIO support on the list already), however I consider these two
>>> patches as merely fixes for the existing driver to maintain bisectability.
>>> It would make sense to merge the new DTs before the DM patches, so we
>>> need to have something in place which works meanwhile.
>>>
>>> Let me know what you think.
>>>
>>> Cheers,
>>> Andre.
>>>
>>> Andre Przywara (6):
>>>   sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()
>>>   net: sun8i-emac: use new, generic GPIO setup routine
>>>   sunxi: dts: update sun50i-a64.dtsi from Linux
>>>   sunxi: dts: update Pine64 .dts
>>>   sunxi: dts: remove now obsolete pine64-common.dtsi
>>>   sunxi: dts: add Bananapi M64 .dts
>>
>> Could we keep this simple, and just do a "sync with the kernel" commit for
>> sun50i, which also keeps the sun8i-emac specific bits. And also explicitly
>> mention the git commit or tag you are syncing to.
>
> So you mean to drop patch 1 and 2 and keep the old style pinctrl
> bindings around for the EMAC node?
> I can certainly do this (if others agree), but didn't want to dodge a
> more proper solution in the first place.

I've actually no preference on this. What I meant was you don't need
four patches to do the sync-up, just one, i.e. copy sun50i*.{dts,dtsi}
from the kernel, and patch back whatever the emac needs, since it's
not in mainline yet.

I guess you could update sun8i-emac to deal with generic pinconf,
or update the gpio driver, but that would be a separate series.

ChenYu

> Another alternative would be to squash the functionality of patch 1
> directly into sun8i_emac.c, so without the moving to pinmux.c. This
> would mean dropping patch 1/6 and just having a fix for the sun8i_emac.
>
> Let me know what's the preferred solution here.
>
> Cheers,
> Andre.
>
>>>  arch/arm/dts/Makefile                      |   3 +-
>>>  arch/arm/dts/sun50i-a64-bananapi-m64.dts   | 135 +++++++
>>>  arch/arm/dts/sun50i-a64-pine64-common.dtsi |  93 -----
>>>  arch/arm/dts/sun50i-a64-pine64-plus.dts    |  16 +-
>>>  arch/arm/dts/sun50i-a64-pine64.dts         |  72 +++-
>>>  arch/arm/dts/sun50i-a64.dtsi               | 615 +++++++++--------------------
>>>  arch/arm/include/asm/arch-sunxi/gpio.h     |   4 +
>>>  arch/arm/mach-sunxi/pinmux.c               |  77 ++++
>>>  drivers/net/sun8i_emac.c                   |  38 +-
>>>  include/dt-bindings/clock/sun50i-a64-ccu.h | 134 +++++++
>>>  include/dt-bindings/reset/sun50i-a64-ccu.h |  98 +++++
>>>  11 files changed, 706 insertions(+), 579 deletions(-)
>>>  create mode 100644 arch/arm/dts/sun50i-a64-bananapi-m64.dts
>>>  delete mode 100644 arch/arm/dts/sun50i-a64-pine64-common.dtsi
>>>  create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
>>>  create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
>>>
>>> --
>>> 2.8.2
>>>

[U-Boot] [PATCH 0/6] sunxi: update Pine64/A64 DTs

[Jagan Teki]

On Mon, Feb 27, 2017 at 6:09 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> Hi,
>
> On Mon, Feb 27, 2017 at 5:53 PM, Andre Przywara <andre.przywara@arm.com> wrote:
>> Hi,
>>
>> On 27/02/17 03:30, Chen-Yu Tsai wrote:
>>> On Mon, Feb 27, 2017 at 8:26 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>>>> Hi,
>>>>
>>>> in the wake of the sunxi DM enablement series it became apparent that
>>>> the current device tree files for the A64 SoC and its board are outdated.
>>>>
>>>> Since Linux v4.10-rc1 there are now basic .dts files for the Allwinner
>>>> A64 SoC and the Pine64 boards in the mainline kernel.
>>>> Linux v4.11-rc1 added MMC and USB support.
>>>> Because our preliminary device trees used in U-Boot differ significantly,
>>>> let's update our copy with what's in the current Linus' master tree.
>>>> Since in contrast to U-Boot the kernel still lacks support for Ethernet,
>>>> we keep our preliminary nodes for that IP, but adjust it slightly to
>>>> match the new clocks and reset bindings.
>>>>
>>>> As the sun8i-emac driver is actually using the DT for the pinmux setup,
>>>> we teach it how to cope with the new pinctrl bindings in the first two
>>>> patches. This is probably becoming somewhat obsolete very soon (with
>>>> DM GPIO support on the list already), however I consider these two
>>>> patches as merely fixes for the existing driver to maintain bisectability.
>>>> It would make sense to merge the new DTs before the DM patches, so we
>>>> need to have something in place which works meanwhile.
>>>>
>>>> Let me know what you think.
>>>>
>>>> Cheers,
>>>> Andre.
>>>>
>>>> Andre Przywara (6):
>>>>   sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins()
>>>>   net: sun8i-emac: use new, generic GPIO setup routine
>>>>   sunxi: dts: update sun50i-a64.dtsi from Linux
>>>>   sunxi: dts: update Pine64 .dts
>>>>   sunxi: dts: remove now obsolete pine64-common.dtsi
>>>>   sunxi: dts: add Bananapi M64 .dts
>>>
>>> Could we keep this simple, and just do a "sync with the kernel" commit for
>>> sun50i, which also keeps the sun8i-emac specific bits. And also explicitly
>>> mention the git commit or tag you are syncing to.
>>
>> So you mean to drop patch 1 and 2 and keep the old style pinctrl
>> bindings around for the EMAC node?
>> I can certainly do this (if others agree), but didn't want to dodge a
>> more proper solution in the first place.
>
> I've actually no preference on this. What I meant was you don't need
> four patches to do the sync-up, just one, i.e. copy sun50i*.{dts,dtsi}
> from the kernel, and patch back whatever the emac needs, since it's
> not in mainline yet.
>
> I guess you could update sun8i-emac to deal with generic pinconf,
> or update the gpio driver, but that would be a separate series.

Agree with ChenYu, and will update the status on this on patchwork as
"Superseded"

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.