* [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-23 10:28 ` rajnesh.kanwal49 0 siblings, 0 replies; 19+ messages in thread From: rajnesh.kanwal49 @ 2020-02-23 10:28 UTC (permalink / raw) To: qemu-riscv; +Cc: palmerdabbelt, alistair.francis, qemu-devel From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> Currently riscv_cpu_local_irq_pending is used to find out pending interrupt and VS mode interrupts are being shifted to represent S mode interrupts in this function. So when the cause returned by this function is passed to riscv_cpu_do_interrupt to actually forward the interrupt, the VS mode forwarding check does not work as intended and interrupt is actually forwarded to hypervisor. This patch fixes this issue. Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> --- target/riscv/cpu_helper.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b9e90dfd9a..59535ecba6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) target_ulong pending = env->mip & env->mie & ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); target_ulong vspending = (env->mip & env->mie & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* + * See if we need to adjust cause. Yes if its VS mode interrupt + * no if hypervisor has delegated one of hs mode's interrupt + */ + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || + cause == IRQ_VS_EXT) + cause = cause - 1; /* Trap to VS mode */ } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-23 10:28 ` rajnesh.kanwal49 0 siblings, 0 replies; 19+ messages in thread From: rajnesh.kanwal49 @ 2020-02-23 10:28 UTC (permalink / raw) To: qemu-riscv; +Cc: alistair.francis, palmerdabbelt, qemu-devel From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> Currently riscv_cpu_local_irq_pending is used to find out pending interrupt and VS mode interrupts are being shifted to represent S mode interrupts in this function. So when the cause returned by this function is passed to riscv_cpu_do_interrupt to actually forward the interrupt, the VS mode forwarding check does not work as intended and interrupt is actually forwarded to hypervisor. This patch fixes this issue. Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> --- target/riscv/cpu_helper.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b9e90dfd9a..59535ecba6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) target_ulong pending = env->mip & env->mie & ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); target_ulong vspending = (env->mip & env->mie & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* + * See if we need to adjust cause. Yes if its VS mode interrupt + * no if hypervisor has delegated one of hs mode's interrupt + */ + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || + cause == IRQ_VS_EXT) + cause = cause - 1; /* Trap to VS mode */ } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. 2020-02-23 10:28 ` rajnesh.kanwal49 @ 2020-02-23 14:40 ` Jose Martins -1 siblings, 0 replies; 19+ messages in thread From: Jose Martins @ 2020-02-23 14:40 UTC (permalink / raw) To: rajnesh.kanwal49; +Cc: alistair.francis, palmerdabbelt, qemu-riscv, qemu-devel Hello rajnesh, I had already submitted almost this exact patch a few weeks ago. Jose On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > Currently riscv_cpu_local_irq_pending is used to find out pending > interrupt and VS mode interrupts are being shifted to represent > S mode interrupts in this function. So when the cause returned by > this function is passed to riscv_cpu_do_interrupt to actually > forward the interrupt, the VS mode forwarding check does not work > as intended and interrupt is actually forwarded to hypervisor. This > patch fixes this issue. > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > --- > target/riscv/cpu_helper.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index b9e90dfd9a..59535ecba6 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) > target_ulong pending = env->mip & env->mie & > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > target_ulong vspending = (env->mip & env->mie & > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > > target_ulong mie = env->priv < PRV_M || > (env->priv == PRV_M && mstatus_mie); > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && > !force_hs_execp) { > + /* > + * See if we need to adjust cause. Yes if its VS mode interrupt > + * no if hypervisor has delegated one of hs mode's interrupt > + */ > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > + cause == IRQ_VS_EXT) > + cause = cause - 1; > /* Trap to VS mode */ > } else if (riscv_cpu_virt_enabled(env)) { > /* Trap into HS mode, from virt */ > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-23 14:40 ` Jose Martins 0 siblings, 0 replies; 19+ messages in thread From: Jose Martins @ 2020-02-23 14:40 UTC (permalink / raw) To: rajnesh.kanwal49; +Cc: qemu-riscv, palmerdabbelt, alistair.francis, qemu-devel Hello rajnesh, I had already submitted almost this exact patch a few weeks ago. Jose On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > Currently riscv_cpu_local_irq_pending is used to find out pending > interrupt and VS mode interrupts are being shifted to represent > S mode interrupts in this function. So when the cause returned by > this function is passed to riscv_cpu_do_interrupt to actually > forward the interrupt, the VS mode forwarding check does not work > as intended and interrupt is actually forwarded to hypervisor. This > patch fixes this issue. > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > --- > target/riscv/cpu_helper.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index b9e90dfd9a..59535ecba6 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) > target_ulong pending = env->mip & env->mie & > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > target_ulong vspending = (env->mip & env->mie & > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > > target_ulong mie = env->priv < PRV_M || > (env->priv == PRV_M && mstatus_mie); > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && > !force_hs_execp) { > + /* > + * See if we need to adjust cause. Yes if its VS mode interrupt > + * no if hypervisor has delegated one of hs mode's interrupt > + */ > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > + cause == IRQ_VS_EXT) > + cause = cause - 1; > /* Trap to VS mode */ > } else if (riscv_cpu_virt_enabled(env)) { > /* Trap into HS mode, from virt */ > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. 2020-02-23 14:40 ` Jose Martins @ 2020-02-23 15:10 ` Rajnesh Kanwal -1 siblings, 0 replies; 19+ messages in thread From: Rajnesh Kanwal @ 2020-02-23 15:10 UTC (permalink / raw) To: Jose Martins; +Cc: alistair.francis, palmerdabbelt, qemu-riscv, qemu-devel [-- Attachment #1: Type: text/plain, Size: 2801 bytes --] Hello Jose, Sorry I didn't see that as it hadn't became a part of the port. I don't know how they proceed with same patches. Just to add, there is a minor problem with your patch. The cause value should only be decremented by one for VS mode interrupts. In case if hypervisor has delegated S mode interrupts then we should not decrement cause for those interrupts. Regards, Rajnesh On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <josemartins90@gmail.com> wrote: > Hello rajnesh, > > I had already submitted almost this exact patch a few weeks ago. > > Jose > > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > > > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > > > Currently riscv_cpu_local_irq_pending is used to find out pending > > interrupt and VS mode interrupts are being shifted to represent > > S mode interrupts in this function. So when the cause returned by > > this function is passed to riscv_cpu_do_interrupt to actually > > forward the interrupt, the VS mode forwarding check does not work > > as intended and interrupt is actually forwarded to hypervisor. This > > patch fixes this issue. > > > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > --- > > target/riscv/cpu_helper.c | 9 ++++++++- > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index b9e90dfd9a..59535ecba6 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState > *env) > > target_ulong pending = env->mip & env->mie & > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > > target_ulong vspending = (env->mip & env->mie & > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > > > > target_ulong mie = env->priv < PRV_M || > > (env->priv == PRV_M && mstatus_mie); > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) > && > > !force_hs_execp) { > > + /* > > + * See if we need to adjust cause. Yes if its VS mode > interrupt > > + * no if hypervisor has delegated one of hs mode's > interrupt > > + */ > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > > + cause == IRQ_VS_EXT) > > + cause = cause - 1; > > /* Trap to VS mode */ > > } else if (riscv_cpu_virt_enabled(env)) { > > /* Trap into HS mode, from virt */ > > -- > > 2.17.1 > > > > > [-- Attachment #2: Type: text/html, Size: 4004 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-23 15:10 ` Rajnesh Kanwal 0 siblings, 0 replies; 19+ messages in thread From: Rajnesh Kanwal @ 2020-02-23 15:10 UTC (permalink / raw) To: Jose Martins; +Cc: qemu-riscv, palmerdabbelt, alistair.francis, qemu-devel [-- Attachment #1: Type: text/plain, Size: 2801 bytes --] Hello Jose, Sorry I didn't see that as it hadn't became a part of the port. I don't know how they proceed with same patches. Just to add, there is a minor problem with your patch. The cause value should only be decremented by one for VS mode interrupts. In case if hypervisor has delegated S mode interrupts then we should not decrement cause for those interrupts. Regards, Rajnesh On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <josemartins90@gmail.com> wrote: > Hello rajnesh, > > I had already submitted almost this exact patch a few weeks ago. > > Jose > > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > > > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > > > Currently riscv_cpu_local_irq_pending is used to find out pending > > interrupt and VS mode interrupts are being shifted to represent > > S mode interrupts in this function. So when the cause returned by > > this function is passed to riscv_cpu_do_interrupt to actually > > forward the interrupt, the VS mode forwarding check does not work > > as intended and interrupt is actually forwarded to hypervisor. This > > patch fixes this issue. > > > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > --- > > target/riscv/cpu_helper.c | 9 ++++++++- > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index b9e90dfd9a..59535ecba6 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState > *env) > > target_ulong pending = env->mip & env->mie & > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > > target_ulong vspending = (env->mip & env->mie & > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > > > > target_ulong mie = env->priv < PRV_M || > > (env->priv == PRV_M && mstatus_mie); > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) > && > > !force_hs_execp) { > > + /* > > + * See if we need to adjust cause. Yes if its VS mode > interrupt > > + * no if hypervisor has delegated one of hs mode's > interrupt > > + */ > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > > + cause == IRQ_VS_EXT) > > + cause = cause - 1; > > /* Trap to VS mode */ > > } else if (riscv_cpu_virt_enabled(env)) { > > /* Trap into HS mode, from virt */ > > -- > > 2.17.1 > > > > > [-- Attachment #2: Type: text/html, Size: 4004 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. 2020-02-23 15:10 ` Rajnesh Kanwal @ 2020-02-23 15:39 ` Jose Martins -1 siblings, 0 replies; 19+ messages in thread From: Jose Martins @ 2020-02-23 15:39 UTC (permalink / raw) To: Rajnesh Kanwal; +Cc: alistair.francis, palmerdabbelt, qemu-riscv, qemu-devel No problem. But I'm failing to see what you mean. My reasoning was: the specification mandates that only VS mode interrupt bits are writable in hideleg, all the others must be hardwired to zero. This means the hypervisor can't really delegate S mode interrupts as you are saying. So, if this is implemented correctly, you will never get inside that if condition because of an HS interrupt. And all delegatable asynchronous exception values must be decremented. So, checking if this is an async exception should do the job. Jose On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> wrote: > > Hello Jose, > > Sorry I didn't see that as it hadn't became a part of the port. I don't know how > they proceed with same patches. > > Just to add, there is a minor problem with your patch. The cause value should > only be decremented by one for VS mode interrupts. In case if hypervisor has > delegated S mode interrupts then we should not decrement cause for those > interrupts. > > Regards, > Rajnesh > > > On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <josemartins90@gmail.com> wrote: >> >> Hello rajnesh, >> >> I had already submitted almost this exact patch a few weeks ago. >> >> Jose >> >> On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: >> > >> > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >> > >> > Currently riscv_cpu_local_irq_pending is used to find out pending >> > interrupt and VS mode interrupts are being shifted to represent >> > S mode interrupts in this function. So when the cause returned by >> > this function is passed to riscv_cpu_do_interrupt to actually >> > forward the interrupt, the VS mode forwarding check does not work >> > as intended and interrupt is actually forwarded to hypervisor. This >> > patch fixes this issue. >> > >> > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >> > --- >> > target/riscv/cpu_helper.c | 9 ++++++++- >> > 1 file changed, 8 insertions(+), 1 deletion(-) >> > >> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> > index b9e90dfd9a..59535ecba6 100644 >> > --- a/target/riscv/cpu_helper.c >> > +++ b/target/riscv/cpu_helper.c >> > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) >> > target_ulong pending = env->mip & env->mie & >> > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); >> > target_ulong vspending = (env->mip & env->mie & >> > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; >> > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); >> > >> > target_ulong mie = env->priv < PRV_M || >> > (env->priv == PRV_M && mstatus_mie); >> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) >> > >> > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && >> > !force_hs_execp) { >> > + /* >> > + * See if we need to adjust cause. Yes if its VS mode interrupt >> > + * no if hypervisor has delegated one of hs mode's interrupt >> > + */ >> > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || >> > + cause == IRQ_VS_EXT) >> > + cause = cause - 1; >> > /* Trap to VS mode */ >> > } else if (riscv_cpu_virt_enabled(env)) { >> > /* Trap into HS mode, from virt */ >> > -- >> > 2.17.1 >> > >> > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-23 15:39 ` Jose Martins 0 siblings, 0 replies; 19+ messages in thread From: Jose Martins @ 2020-02-23 15:39 UTC (permalink / raw) To: Rajnesh Kanwal; +Cc: qemu-riscv, palmerdabbelt, alistair.francis, qemu-devel No problem. But I'm failing to see what you mean. My reasoning was: the specification mandates that only VS mode interrupt bits are writable in hideleg, all the others must be hardwired to zero. This means the hypervisor can't really delegate S mode interrupts as you are saying. So, if this is implemented correctly, you will never get inside that if condition because of an HS interrupt. And all delegatable asynchronous exception values must be decremented. So, checking if this is an async exception should do the job. Jose On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> wrote: > > Hello Jose, > > Sorry I didn't see that as it hadn't became a part of the port. I don't know how > they proceed with same patches. > > Just to add, there is a minor problem with your patch. The cause value should > only be decremented by one for VS mode interrupts. In case if hypervisor has > delegated S mode interrupts then we should not decrement cause for those > interrupts. > > Regards, > Rajnesh > > > On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <josemartins90@gmail.com> wrote: >> >> Hello rajnesh, >> >> I had already submitted almost this exact patch a few weeks ago. >> >> Jose >> >> On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: >> > >> > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >> > >> > Currently riscv_cpu_local_irq_pending is used to find out pending >> > interrupt and VS mode interrupts are being shifted to represent >> > S mode interrupts in this function. So when the cause returned by >> > this function is passed to riscv_cpu_do_interrupt to actually >> > forward the interrupt, the VS mode forwarding check does not work >> > as intended and interrupt is actually forwarded to hypervisor. This >> > patch fixes this issue. >> > >> > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >> > --- >> > target/riscv/cpu_helper.c | 9 ++++++++- >> > 1 file changed, 8 insertions(+), 1 deletion(-) >> > >> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> > index b9e90dfd9a..59535ecba6 100644 >> > --- a/target/riscv/cpu_helper.c >> > +++ b/target/riscv/cpu_helper.c >> > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) >> > target_ulong pending = env->mip & env->mie & >> > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); >> > target_ulong vspending = (env->mip & env->mie & >> > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; >> > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); >> > >> > target_ulong mie = env->priv < PRV_M || >> > (env->priv == PRV_M && mstatus_mie); >> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) >> > >> > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && >> > !force_hs_execp) { >> > + /* >> > + * See if we need to adjust cause. Yes if its VS mode interrupt >> > + * no if hypervisor has delegated one of hs mode's interrupt >> > + */ >> > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || >> > + cause == IRQ_VS_EXT) >> > + cause = cause - 1; >> > /* Trap to VS mode */ >> > } else if (riscv_cpu_virt_enabled(env)) { >> > /* Trap into HS mode, from virt */ >> > -- >> > 2.17.1 >> > >> > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. 2020-02-23 15:39 ` Jose Martins @ 2020-02-24 10:13 ` Rajnesh Kanwal -1 siblings, 0 replies; 19+ messages in thread From: Rajnesh Kanwal @ 2020-02-24 10:13 UTC (permalink / raw) To: Jose Martins; +Cc: alistair.francis, palmerdabbelt, qemu-riscv, qemu-devel [-- Attachment #1: Type: text/plain, Size: 4125 bytes --] Nice catch. You are right. I was a bit confused after looking at current xvisor and KVM port. They are delegating S mode interrupts to VS mode, as per my understanding after looking at https://github.com/kvm-riscv/linux/blob/riscv_kvm_master/arch/riscv/kvm/main.c line no. 34. I will see if there is a way to decline a patch. Thanks for pointing that out. Regards, Rajnesh On Sun, Feb 23, 2020 at 8:40 PM Jose Martins <josemartins90@gmail.com> wrote: > No problem. But I'm failing to see what you mean. My reasoning was: > the specification mandates that only VS mode interrupt bits are > writable in hideleg, all the others must be hardwired to zero. This > means the hypervisor can't really delegate S mode interrupts as you > are saying. So, if this is implemented correctly, you will never get > inside that if condition because of an HS interrupt. And all > delegatable asynchronous exception values must be decremented. So, > checking if this is an async exception should do the job. > > Jose > > On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > wrote: > > > > Hello Jose, > > > > Sorry I didn't see that as it hadn't became a part of the port. I don't > know how > > they proceed with same patches. > > > > Just to add, there is a minor problem with your patch. The cause value > should > > only be decremented by one for VS mode interrupts. In case if hypervisor > has > > delegated S mode interrupts then we should not decrement cause for those > > interrupts. > > > > Regards, > > Rajnesh > > > > > > On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <josemartins90@gmail.com> > wrote: > >> > >> Hello rajnesh, > >> > >> I had already submitted almost this exact patch a few weeks ago. > >> > >> Jose > >> > >> On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > >> > > >> > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > >> > > >> > Currently riscv_cpu_local_irq_pending is used to find out pending > >> > interrupt and VS mode interrupts are being shifted to represent > >> > S mode interrupts in this function. So when the cause returned by > >> > this function is passed to riscv_cpu_do_interrupt to actually > >> > forward the interrupt, the VS mode forwarding check does not work > >> > as intended and interrupt is actually forwarded to hypervisor. This > >> > patch fixes this issue. > >> > > >> > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > >> > --- > >> > target/riscv/cpu_helper.c | 9 ++++++++- > >> > 1 file changed, 8 insertions(+), 1 deletion(-) > >> > > >> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > >> > index b9e90dfd9a..59535ecba6 100644 > >> > --- a/target/riscv/cpu_helper.c > >> > +++ b/target/riscv/cpu_helper.c > >> > @@ -46,7 +46,7 @@ static int > riscv_cpu_local_irq_pending(CPURISCVState *env) > >> > target_ulong pending = env->mip & env->mie & > >> > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > >> > target_ulong vspending = (env->mip & env->mie & > >> > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) > >> 1; > >> > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > >> > > >> > target_ulong mie = env->priv < PRV_M || > >> > (env->priv == PRV_M && mstatus_mie); > >> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > >> > > >> > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & > 1) && > >> > !force_hs_execp) { > >> > + /* > >> > + * See if we need to adjust cause. Yes if its VS > mode interrupt > >> > + * no if hypervisor has delegated one of hs mode's > interrupt > >> > + */ > >> > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > >> > + cause == IRQ_VS_EXT) > >> > + cause = cause - 1; > >> > /* Trap to VS mode */ > >> > } else if (riscv_cpu_virt_enabled(env)) { > >> > /* Trap into HS mode, from virt */ > >> > -- > >> > 2.17.1 > >> > > >> > > [-- Attachment #2: Type: text/html, Size: 5925 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-24 10:13 ` Rajnesh Kanwal 0 siblings, 0 replies; 19+ messages in thread From: Rajnesh Kanwal @ 2020-02-24 10:13 UTC (permalink / raw) To: Jose Martins; +Cc: qemu-riscv, palmerdabbelt, alistair.francis, qemu-devel [-- Attachment #1: Type: text/plain, Size: 4125 bytes --] Nice catch. You are right. I was a bit confused after looking at current xvisor and KVM port. They are delegating S mode interrupts to VS mode, as per my understanding after looking at https://github.com/kvm-riscv/linux/blob/riscv_kvm_master/arch/riscv/kvm/main.c line no. 34. I will see if there is a way to decline a patch. Thanks for pointing that out. Regards, Rajnesh On Sun, Feb 23, 2020 at 8:40 PM Jose Martins <josemartins90@gmail.com> wrote: > No problem. But I'm failing to see what you mean. My reasoning was: > the specification mandates that only VS mode interrupt bits are > writable in hideleg, all the others must be hardwired to zero. This > means the hypervisor can't really delegate S mode interrupts as you > are saying. So, if this is implemented correctly, you will never get > inside that if condition because of an HS interrupt. And all > delegatable asynchronous exception values must be decremented. So, > checking if this is an async exception should do the job. > > Jose > > On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > wrote: > > > > Hello Jose, > > > > Sorry I didn't see that as it hadn't became a part of the port. I don't > know how > > they proceed with same patches. > > > > Just to add, there is a minor problem with your patch. The cause value > should > > only be decremented by one for VS mode interrupts. In case if hypervisor > has > > delegated S mode interrupts then we should not decrement cause for those > > interrupts. > > > > Regards, > > Rajnesh > > > > > > On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <josemartins90@gmail.com> > wrote: > >> > >> Hello rajnesh, > >> > >> I had already submitted almost this exact patch a few weeks ago. > >> > >> Jose > >> > >> On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > >> > > >> > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > >> > > >> > Currently riscv_cpu_local_irq_pending is used to find out pending > >> > interrupt and VS mode interrupts are being shifted to represent > >> > S mode interrupts in this function. So when the cause returned by > >> > this function is passed to riscv_cpu_do_interrupt to actually > >> > forward the interrupt, the VS mode forwarding check does not work > >> > as intended and interrupt is actually forwarded to hypervisor. This > >> > patch fixes this issue. > >> > > >> > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > >> > --- > >> > target/riscv/cpu_helper.c | 9 ++++++++- > >> > 1 file changed, 8 insertions(+), 1 deletion(-) > >> > > >> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > >> > index b9e90dfd9a..59535ecba6 100644 > >> > --- a/target/riscv/cpu_helper.c > >> > +++ b/target/riscv/cpu_helper.c > >> > @@ -46,7 +46,7 @@ static int > riscv_cpu_local_irq_pending(CPURISCVState *env) > >> > target_ulong pending = env->mip & env->mie & > >> > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > >> > target_ulong vspending = (env->mip & env->mie & > >> > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) > >> 1; > >> > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > >> > > >> > target_ulong mie = env->priv < PRV_M || > >> > (env->priv == PRV_M && mstatus_mie); > >> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > >> > > >> > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & > 1) && > >> > !force_hs_execp) { > >> > + /* > >> > + * See if we need to adjust cause. Yes if its VS > mode interrupt > >> > + * no if hypervisor has delegated one of hs mode's > interrupt > >> > + */ > >> > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > >> > + cause == IRQ_VS_EXT) > >> > + cause = cause - 1; > >> > /* Trap to VS mode */ > >> > } else if (riscv_cpu_virt_enabled(env)) { > >> > /* Trap into HS mode, from virt */ > >> > -- > >> > 2.17.1 > >> > > >> > > [-- Attachment #2: Type: text/html, Size: 5925 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. 2020-02-24 10:13 ` Rajnesh Kanwal @ 2020-02-24 11:05 ` Anup Patel -1 siblings, 0 replies; 19+ messages in thread From: Anup Patel @ 2020-02-24 11:05 UTC (permalink / raw) To: Rajnesh Kanwal, Jose Martins Cc: qemu-riscv, palmerdabbelt, Alistair Francis, qemu-devel Hi, Yes, indeed this has to be fixed in QEMU, Xvisor and KVM. Before fixing Xvisor and KVM, we have to first fix this in QEMU. For Xvisor RISC-V, feel free to send patch to Xvisor-devel@googlegroups.com For KVM RISC-V, I will update it in v11 patch series and KVM RISC-V git repo as well. Regards, Anup From: Qemu-riscv <qemu-riscv-bounces+anup.patel=wdc.com@nongnu.org> On Behalf Of Rajnesh Kanwal Sent: Monday, February 24, 2020 3:44 PM To: Jose Martins <josemartins90@gmail.com> Cc: Alistair Francis <Alistair.Francis@wdc.com>; palmerdabbelt@google.com; qemu-riscv@nongnu.org; qemu-devel@nongnu.org Subject: Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. Nice catch. You are right. I was a bit confused after looking at current xvisor and KVM port. They are delegating S mode interrupts to VS mode, as per my understanding after looking at https://github.com/kvm-riscv/linux/blob/riscv_kvm_master/arch/riscv/kvm/main.c line no. 34. I will see if there is a way to decline a patch. Thanks for pointing that out. Regards, Rajnesh On Sun, Feb 23, 2020 at 8:40 PM Jose Martins <mailto:josemartins90@gmail.com> wrote: No problem. But I'm failing to see what you mean. My reasoning was: the specification mandates that only VS mode interrupt bits are writable in hideleg, all the others must be hardwired to zero. This means the hypervisor can't really delegate S mode interrupts as you are saying. So, if this is implemented correctly, you will never get inside that if condition because of an HS interrupt. And all delegatable asynchronous exception values must be decremented. So, checking if this is an async exception should do the job. Jose On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal <mailto:rajnesh.kanwal49@gmail.com> wrote: > > Hello Jose, > > Sorry I didn't see that as it hadn't became a part of the port. I don't know how > they proceed with same patches. > > Just to add, there is a minor problem with your patch. The cause value should > only be decremented by one for VS mode interrupts. In case if hypervisor has > delegated S mode interrupts then we should not decrement cause for those > interrupts. > > Regards, > Rajnesh > > > On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <mailto:josemartins90@gmail.com> wrote: >> >> Hello rajnesh, >> >> I had already submitted almost this exact patch a few weeks ago. >> >> Jose >> >> On Sun, 23 Feb 2020 at 13:51, <mailto:rajnesh.kanwal49@gmail.com> wrote: >> > >> > From: Rajnesh Kanwal <mailto:rajnesh.kanwal49@gmail.com> >> > >> > Currently riscv_cpu_local_irq_pending is used to find out pending >> > interrupt and VS mode interrupts are being shifted to represent >> > S mode interrupts in this function. So when the cause returned by >> > this function is passed to riscv_cpu_do_interrupt to actually >> > forward the interrupt, the VS mode forwarding check does not work >> > as intended and interrupt is actually forwarded to hypervisor. This >> > patch fixes this issue. >> > >> > Signed-off-by: Rajnesh Kanwal <mailto:rajnesh.kanwal49@gmail.com> >> > --- >> > target/riscv/cpu_helper.c | 9 ++++++++- >> > 1 file changed, 8 insertions(+), 1 deletion(-) >> > >> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> > index b9e90dfd9a..59535ecba6 100644 >> > --- a/target/riscv/cpu_helper.c >> > +++ b/target/riscv/cpu_helper.c >> > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) >> > target_ulong pending = env->mip & env->mie & >> > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); >> > target_ulong vspending = (env->mip & env->mie & >> > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; >> > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); >> > >> > target_ulong mie = env->priv < PRV_M || >> > (env->priv == PRV_M && mstatus_mie); >> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) >> > >> > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && >> > !force_hs_execp) { >> > + /* >> > + * See if we need to adjust cause. Yes if its VS mode interrupt >> > + * no if hypervisor has delegated one of hs mode's interrupt >> > + */ >> > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || >> > + cause == IRQ_VS_EXT) >> > + cause = cause - 1; >> > /* Trap to VS mode */ >> > } else if (riscv_cpu_virt_enabled(env)) { >> > /* Trap into HS mode, from virt */ >> > -- >> > 2.17.1 >> > >> > ^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-24 11:05 ` Anup Patel 0 siblings, 0 replies; 19+ messages in thread From: Anup Patel @ 2020-02-24 11:05 UTC (permalink / raw) To: Rajnesh Kanwal, Jose Martins Cc: Alistair Francis, palmerdabbelt, qemu-riscv, qemu-devel Hi, Yes, indeed this has to be fixed in QEMU, Xvisor and KVM. Before fixing Xvisor and KVM, we have to first fix this in QEMU. For Xvisor RISC-V, feel free to send patch to Xvisor-devel@googlegroups.com For KVM RISC-V, I will update it in v11 patch series and KVM RISC-V git repo as well. Regards, Anup From: Qemu-riscv <qemu-riscv-bounces+anup.patel=wdc.com@nongnu.org> On Behalf Of Rajnesh Kanwal Sent: Monday, February 24, 2020 3:44 PM To: Jose Martins <josemartins90@gmail.com> Cc: Alistair Francis <Alistair.Francis@wdc.com>; palmerdabbelt@google.com; qemu-riscv@nongnu.org; qemu-devel@nongnu.org Subject: Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. Nice catch. You are right. I was a bit confused after looking at current xvisor and KVM port. They are delegating S mode interrupts to VS mode, as per my understanding after looking at https://github.com/kvm-riscv/linux/blob/riscv_kvm_master/arch/riscv/kvm/main.c line no. 34. I will see if there is a way to decline a patch. Thanks for pointing that out. Regards, Rajnesh On Sun, Feb 23, 2020 at 8:40 PM Jose Martins <mailto:josemartins90@gmail.com> wrote: No problem. But I'm failing to see what you mean. My reasoning was: the specification mandates that only VS mode interrupt bits are writable in hideleg, all the others must be hardwired to zero. This means the hypervisor can't really delegate S mode interrupts as you are saying. So, if this is implemented correctly, you will never get inside that if condition because of an HS interrupt. And all delegatable asynchronous exception values must be decremented. So, checking if this is an async exception should do the job. Jose On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal <mailto:rajnesh.kanwal49@gmail.com> wrote: > > Hello Jose, > > Sorry I didn't see that as it hadn't became a part of the port. I don't know how > they proceed with same patches. > > Just to add, there is a minor problem with your patch. The cause value should > only be decremented by one for VS mode interrupts. In case if hypervisor has > delegated S mode interrupts then we should not decrement cause for those > interrupts. > > Regards, > Rajnesh > > > On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <mailto:josemartins90@gmail.com> wrote: >> >> Hello rajnesh, >> >> I had already submitted almost this exact patch a few weeks ago. >> >> Jose >> >> On Sun, 23 Feb 2020 at 13:51, <mailto:rajnesh.kanwal49@gmail.com> wrote: >> > >> > From: Rajnesh Kanwal <mailto:rajnesh.kanwal49@gmail.com> >> > >> > Currently riscv_cpu_local_irq_pending is used to find out pending >> > interrupt and VS mode interrupts are being shifted to represent >> > S mode interrupts in this function. So when the cause returned by >> > this function is passed to riscv_cpu_do_interrupt to actually >> > forward the interrupt, the VS mode forwarding check does not work >> > as intended and interrupt is actually forwarded to hypervisor. This >> > patch fixes this issue. >> > >> > Signed-off-by: Rajnesh Kanwal <mailto:rajnesh.kanwal49@gmail.com> >> > --- >> > target/riscv/cpu_helper.c | 9 ++++++++- >> > 1 file changed, 8 insertions(+), 1 deletion(-) >> > >> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> > index b9e90dfd9a..59535ecba6 100644 >> > --- a/target/riscv/cpu_helper.c >> > +++ b/target/riscv/cpu_helper.c >> > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) >> > target_ulong pending = env->mip & env->mie & >> > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); >> > target_ulong vspending = (env->mip & env->mie & >> > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; >> > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); >> > >> > target_ulong mie = env->priv < PRV_M || >> > (env->priv == PRV_M && mstatus_mie); >> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) >> > >> > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && >> > !force_hs_execp) { >> > + /* >> > + * See if we need to adjust cause. Yes if its VS mode interrupt >> > + * no if hypervisor has delegated one of hs mode's interrupt >> > + */ >> > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || >> > + cause == IRQ_VS_EXT) >> > + cause = cause - 1; >> > /* Trap to VS mode */ >> > } else if (riscv_cpu_virt_enabled(env)) { >> > /* Trap into HS mode, from virt */ >> > -- >> > 2.17.1 >> > >> > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. 2020-02-23 14:40 ` Jose Martins @ 2020-02-24 18:59 ` Alistair Francis -1 siblings, 0 replies; 19+ messages in thread From: Alistair Francis @ 2020-02-24 18:59 UTC (permalink / raw) To: Jose Martins Cc: Palmer Dabbelt, open list:RISC-V, rajnesh.kanwal49, Alistair Francis, qemu-devel@nongnu.org Developers On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> wrote: > > Hello rajnesh, > > I had already submitted almost this exact patch a few weeks ago. To QEMU? I don't see the patch. Alistair > > Jose > > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > > > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > > > Currently riscv_cpu_local_irq_pending is used to find out pending > > interrupt and VS mode interrupts are being shifted to represent > > S mode interrupts in this function. So when the cause returned by > > this function is passed to riscv_cpu_do_interrupt to actually > > forward the interrupt, the VS mode forwarding check does not work > > as intended and interrupt is actually forwarded to hypervisor. This > > patch fixes this issue. > > > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > --- > > target/riscv/cpu_helper.c | 9 ++++++++- > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index b9e90dfd9a..59535ecba6 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) > > target_ulong pending = env->mip & env->mie & > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > > target_ulong vspending = (env->mip & env->mie & > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > > > > target_ulong mie = env->priv < PRV_M || > > (env->priv == PRV_M && mstatus_mie); > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && > > !force_hs_execp) { > > + /* > > + * See if we need to adjust cause. Yes if its VS mode interrupt > > + * no if hypervisor has delegated one of hs mode's interrupt > > + */ > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > > + cause == IRQ_VS_EXT) > > + cause = cause - 1; > > /* Trap to VS mode */ > > } else if (riscv_cpu_virt_enabled(env)) { > > /* Trap into HS mode, from virt */ > > -- > > 2.17.1 > > > > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-24 18:59 ` Alistair Francis 0 siblings, 0 replies; 19+ messages in thread From: Alistair Francis @ 2020-02-24 18:59 UTC (permalink / raw) To: Jose Martins Cc: rajnesh.kanwal49, Alistair Francis, Palmer Dabbelt, open list:RISC-V, qemu-devel@nongnu.org Developers On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> wrote: > > Hello rajnesh, > > I had already submitted almost this exact patch a few weeks ago. To QEMU? I don't see the patch. Alistair > > Jose > > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > > > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > > > Currently riscv_cpu_local_irq_pending is used to find out pending > > interrupt and VS mode interrupts are being shifted to represent > > S mode interrupts in this function. So when the cause returned by > > this function is passed to riscv_cpu_do_interrupt to actually > > forward the interrupt, the VS mode forwarding check does not work > > as intended and interrupt is actually forwarded to hypervisor. This > > patch fixes this issue. > > > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > --- > > target/riscv/cpu_helper.c | 9 ++++++++- > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index b9e90dfd9a..59535ecba6 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) > > target_ulong pending = env->mip & env->mie & > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > > target_ulong vspending = (env->mip & env->mie & > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > > > > target_ulong mie = env->priv < PRV_M || > > (env->priv == PRV_M && mstatus_mie); > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && > > !force_hs_execp) { > > + /* > > + * See if we need to adjust cause. Yes if its VS mode interrupt > > + * no if hypervisor has delegated one of hs mode's interrupt > > + */ > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > > + cause == IRQ_VS_EXT) > > + cause = cause - 1; > > /* Trap to VS mode */ > > } else if (riscv_cpu_virt_enabled(env)) { > > /* Trap into HS mode, from virt */ > > -- > > 2.17.1 > > > > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. 2020-02-24 18:59 ` Alistair Francis @ 2020-02-26 8:52 ` Rajnesh Kanwal -1 siblings, 0 replies; 19+ messages in thread From: Rajnesh Kanwal @ 2020-02-26 8:52 UTC (permalink / raw) To: Alistair Francis Cc: Jose Martins, open list:RISC-V, Palmer Dabbelt, Alistair Francis, qemu-devel@nongnu.org Developers [-- Attachment #1: Type: text/plain, Size: 2780 bytes --] Here is the link to the patch https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html -Rajnesh On Tue, Feb 25, 2020 at 12:06 AM Alistair Francis <alistair23@gmail.com> wrote: > On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> > wrote: > > > > Hello rajnesh, > > > > I had already submitted almost this exact patch a few weeks ago. > > To QEMU? I don't see the patch. > > Alistair > > > > > Jose > > > > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > > > > > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > > > > > Currently riscv_cpu_local_irq_pending is used to find out pending > > > interrupt and VS mode interrupts are being shifted to represent > > > S mode interrupts in this function. So when the cause returned by > > > this function is passed to riscv_cpu_do_interrupt to actually > > > forward the interrupt, the VS mode forwarding check does not work > > > as intended and interrupt is actually forwarded to hypervisor. This > > > patch fixes this issue. > > > > > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > > --- > > > target/riscv/cpu_helper.c | 9 ++++++++- > > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > > index b9e90dfd9a..59535ecba6 100644 > > > --- a/target/riscv/cpu_helper.c > > > +++ b/target/riscv/cpu_helper.c > > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState > *env) > > > target_ulong pending = env->mip & env->mie & > > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > > > target_ulong vspending = (env->mip & env->mie & > > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> > 1; > > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > > > > > > target_ulong mie = env->priv < PRV_M || > > > (env->priv == PRV_M && mstatus_mie); > > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > > > > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & > 1) && > > > !force_hs_execp) { > > > + /* > > > + * See if we need to adjust cause. Yes if its VS mode > interrupt > > > + * no if hypervisor has delegated one of hs mode's > interrupt > > > + */ > > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > > > + cause == IRQ_VS_EXT) > > > + cause = cause - 1; > > > /* Trap to VS mode */ > > > } else if (riscv_cpu_virt_enabled(env)) { > > > /* Trap into HS mode, from virt */ > > > -- > > > 2.17.1 > > > > > > > > > [-- Attachment #2: Type: text/html, Size: 4194 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-26 8:52 ` Rajnesh Kanwal 0 siblings, 0 replies; 19+ messages in thread From: Rajnesh Kanwal @ 2020-02-26 8:52 UTC (permalink / raw) To: Alistair Francis Cc: Jose Martins, Alistair Francis, Palmer Dabbelt, open list:RISC-V, qemu-devel@nongnu.org Developers [-- Attachment #1: Type: text/plain, Size: 2780 bytes --] Here is the link to the patch https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html -Rajnesh On Tue, Feb 25, 2020 at 12:06 AM Alistair Francis <alistair23@gmail.com> wrote: > On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> > wrote: > > > > Hello rajnesh, > > > > I had already submitted almost this exact patch a few weeks ago. > > To QEMU? I don't see the patch. > > Alistair > > > > > Jose > > > > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: > > > > > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > > > > > Currently riscv_cpu_local_irq_pending is used to find out pending > > > interrupt and VS mode interrupts are being shifted to represent > > > S mode interrupts in this function. So when the cause returned by > > > this function is passed to riscv_cpu_do_interrupt to actually > > > forward the interrupt, the VS mode forwarding check does not work > > > as intended and interrupt is actually forwarded to hypervisor. This > > > patch fixes this issue. > > > > > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> > > > --- > > > target/riscv/cpu_helper.c | 9 ++++++++- > > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > > index b9e90dfd9a..59535ecba6 100644 > > > --- a/target/riscv/cpu_helper.c > > > +++ b/target/riscv/cpu_helper.c > > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState > *env) > > > target_ulong pending = env->mip & env->mie & > > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > > > target_ulong vspending = (env->mip & env->mie & > > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> > 1; > > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > > > > > > target_ulong mie = env->priv < PRV_M || > > > (env->priv == PRV_M && mstatus_mie); > > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > > > > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & > 1) && > > > !force_hs_execp) { > > > + /* > > > + * See if we need to adjust cause. Yes if its VS mode > interrupt > > > + * no if hypervisor has delegated one of hs mode's > interrupt > > > + */ > > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || > > > + cause == IRQ_VS_EXT) > > > + cause = cause - 1; > > > /* Trap to VS mode */ > > > } else if (riscv_cpu_virt_enabled(env)) { > > > /* Trap into HS mode, from virt */ > > > -- > > > 2.17.1 > > > > > > > > > [-- Attachment #2: Type: text/html, Size: 4194 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. 2020-02-26 8:52 ` Rajnesh Kanwal @ 2020-02-26 17:55 ` Alistair Francis -1 siblings, 0 replies; 19+ messages in thread From: Alistair Francis @ 2020-02-26 17:55 UTC (permalink / raw) To: Rajnesh Kanwal Cc: Jose Martins, open list:RISC-V, Palmer Dabbelt, Alistair Francis, qemu-devel@nongnu.org Developers On Wed, Feb 26, 2020 at 12:54 AM Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> wrote: > > Here is the link to the patch > https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html Ah, it doesn't look like it made it to the QEMU-devel list. Can you re-send it to QEMU-devel? Alistair > > -Rajnesh > > On Tue, Feb 25, 2020 at 12:06 AM Alistair Francis <alistair23@gmail.com> wrote: >> >> On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> wrote: >> > >> > Hello rajnesh, >> > >> > I had already submitted almost this exact patch a few weeks ago. >> >> To QEMU? I don't see the patch. >> >> Alistair >> >> > >> > Jose >> > >> > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: >> > > >> > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >> > > >> > > Currently riscv_cpu_local_irq_pending is used to find out pending >> > > interrupt and VS mode interrupts are being shifted to represent >> > > S mode interrupts in this function. So when the cause returned by >> > > this function is passed to riscv_cpu_do_interrupt to actually >> > > forward the interrupt, the VS mode forwarding check does not work >> > > as intended and interrupt is actually forwarded to hypervisor. This >> > > patch fixes this issue. >> > > >> > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >> > > --- >> > > target/riscv/cpu_helper.c | 9 ++++++++- >> > > 1 file changed, 8 insertions(+), 1 deletion(-) >> > > >> > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> > > index b9e90dfd9a..59535ecba6 100644 >> > > --- a/target/riscv/cpu_helper.c >> > > +++ b/target/riscv/cpu_helper.c >> > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) >> > > target_ulong pending = env->mip & env->mie & >> > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); >> > > target_ulong vspending = (env->mip & env->mie & >> > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; >> > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); >> > > >> > > target_ulong mie = env->priv < PRV_M || >> > > (env->priv == PRV_M && mstatus_mie); >> > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) >> > > >> > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && >> > > !force_hs_execp) { >> > > + /* >> > > + * See if we need to adjust cause. Yes if its VS mode interrupt >> > > + * no if hypervisor has delegated one of hs mode's interrupt >> > > + */ >> > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || >> > > + cause == IRQ_VS_EXT) >> > > + cause = cause - 1; >> > > /* Trap to VS mode */ >> > > } else if (riscv_cpu_virt_enabled(env)) { >> > > /* Trap into HS mode, from virt */ >> > > -- >> > > 2.17.1 >> > > >> > > >> > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. @ 2020-02-26 17:55 ` Alistair Francis 0 siblings, 0 replies; 19+ messages in thread From: Alistair Francis @ 2020-02-26 17:55 UTC (permalink / raw) To: Rajnesh Kanwal Cc: Jose Martins, Alistair Francis, Palmer Dabbelt, open list:RISC-V, qemu-devel@nongnu.org Developers On Wed, Feb 26, 2020 at 12:54 AM Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> wrote: > > Here is the link to the patch > https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html Ah, it doesn't look like it made it to the QEMU-devel list. Can you re-send it to QEMU-devel? Alistair > > -Rajnesh > > On Tue, Feb 25, 2020 at 12:06 AM Alistair Francis <alistair23@gmail.com> wrote: >> >> On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> wrote: >> > >> > Hello rajnesh, >> > >> > I had already submitted almost this exact patch a few weeks ago. >> >> To QEMU? I don't see the patch. >> >> Alistair >> >> > >> > Jose >> > >> > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: >> > > >> > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >> > > >> > > Currently riscv_cpu_local_irq_pending is used to find out pending >> > > interrupt and VS mode interrupts are being shifted to represent >> > > S mode interrupts in this function. So when the cause returned by >> > > this function is passed to riscv_cpu_do_interrupt to actually >> > > forward the interrupt, the VS mode forwarding check does not work >> > > as intended and interrupt is actually forwarded to hypervisor. This >> > > patch fixes this issue. >> > > >> > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >> > > --- >> > > target/riscv/cpu_helper.c | 9 ++++++++- >> > > 1 file changed, 8 insertions(+), 1 deletion(-) >> > > >> > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> > > index b9e90dfd9a..59535ecba6 100644 >> > > --- a/target/riscv/cpu_helper.c >> > > +++ b/target/riscv/cpu_helper.c >> > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) >> > > target_ulong pending = env->mip & env->mie & >> > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); >> > > target_ulong vspending = (env->mip & env->mie & >> > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; >> > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); >> > > >> > > target_ulong mie = env->priv < PRV_M || >> > > (env->priv == PRV_M && mstatus_mie); >> > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) >> > > >> > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && >> > > !force_hs_execp) { >> > > + /* >> > > + * See if we need to adjust cause. Yes if its VS mode interrupt >> > > + * no if hypervisor has delegated one of hs mode's interrupt >> > > + */ >> > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || >> > > + cause == IRQ_VS_EXT) >> > > + cause = cause - 1; >> > > /* Trap to VS mode */ >> > > } else if (riscv_cpu_virt_enabled(env)) { >> > > /* Trap into HS mode, from virt */ >> > > -- >> > > 2.17.1 >> > > >> > > >> > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding. 2020-02-26 17:55 ` Alistair Francis (?) @ 2020-03-06 17:31 ` Palmer Dabbelt -1 siblings, 0 replies; 19+ messages in thread From: Palmer Dabbelt @ 2020-03-06 17:31 UTC (permalink / raw) To: alistair23 Cc: rajnesh.kanwal49, josemartins90, qemu-riscv, Alistair Francis, qemu-devel On Wed, 26 Feb 2020 09:55:34 PST (-0800), alistair23@gmail.com wrote: > On Wed, Feb 26, 2020 at 12:54 AM Rajnesh Kanwal > <rajnesh.kanwal49@gmail.com> wrote: >> >> Here is the link to the patch >> https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html > > Ah, it doesn't look like it made it to the QEMU-devel list. Can you > re-send it to QEMU-devel? I can't find the older patch in my inbox, so I'm just taking this one. > > Alistair > >> >> -Rajnesh >> >> On Tue, Feb 25, 2020 at 12:06 AM Alistair Francis <alistair23@gmail.com> wrote: >>> >>> On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> wrote: >>> > >>> > Hello rajnesh, >>> > >>> > I had already submitted almost this exact patch a few weeks ago. >>> >>> To QEMU? I don't see the patch. >>> >>> Alistair >>> >>> > >>> > Jose >>> > >>> > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote: >>> > > >>> > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >>> > > >>> > > Currently riscv_cpu_local_irq_pending is used to find out pending >>> > > interrupt and VS mode interrupts are being shifted to represent >>> > > S mode interrupts in this function. So when the cause returned by >>> > > this function is passed to riscv_cpu_do_interrupt to actually >>> > > forward the interrupt, the VS mode forwarding check does not work >>> > > as intended and interrupt is actually forwarded to hypervisor. This >>> > > patch fixes this issue. >>> > > >>> > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> >>> > > --- >>> > > target/riscv/cpu_helper.c | 9 ++++++++- >>> > > 1 file changed, 8 insertions(+), 1 deletion(-) >>> > > >>> > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >>> > > index b9e90dfd9a..59535ecba6 100644 >>> > > --- a/target/riscv/cpu_helper.c >>> > > +++ b/target/riscv/cpu_helper.c >>> > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) >>> > > target_ulong pending = env->mip & env->mie & >>> > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); >>> > > target_ulong vspending = (env->mip & env->mie & >>> > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; >>> > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); >>> > > >>> > > target_ulong mie = env->priv < PRV_M || >>> > > (env->priv == PRV_M && mstatus_mie); >>> > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) >>> > > >>> > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && >>> > > !force_hs_execp) { >>> > > + /* >>> > > + * See if we need to adjust cause. Yes if its VS mode interrupt >>> > > + * no if hypervisor has delegated one of hs mode's interrupt >>> > > + */ >>> > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || >>> > > + cause == IRQ_VS_EXT) >>> > > + cause = cause - 1; >>> > > /* Trap to VS mode */ >>> > > } else if (riscv_cpu_virt_enabled(env)) { >>> > > /* Trap into HS mode, from virt */ >>> > > -- >>> > > 2.17.1 >>> > > >>> > > >>> > ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2020-03-06 17:40 UTC | newest] Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-23 10:28 [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding rajnesh.kanwal49 2020-02-23 10:28 ` rajnesh.kanwal49 2020-02-23 14:40 ` Jose Martins 2020-02-23 14:40 ` Jose Martins 2020-02-23 15:10 ` Rajnesh Kanwal 2020-02-23 15:10 ` Rajnesh Kanwal 2020-02-23 15:39 ` Jose Martins 2020-02-23 15:39 ` Jose Martins 2020-02-24 10:13 ` Rajnesh Kanwal 2020-02-24 10:13 ` Rajnesh Kanwal 2020-02-24 11:05 ` Anup Patel 2020-02-24 11:05 ` Anup Patel 2020-02-24 18:59 ` Alistair Francis 2020-02-24 18:59 ` Alistair Francis 2020-02-26 8:52 ` Rajnesh Kanwal 2020-02-26 8:52 ` Rajnesh Kanwal 2020-02-26 17:55 ` Alistair Francis 2020-02-26 17:55 ` Alistair Francis 2020-03-06 17:31 ` Palmer Dabbelt
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