* [PATCH 1/2] usb: dwc3: Rename .select_dr_mode to .glue_configure
@ 2022-04-01 14:31 Marek Vasut
2022-04-01 14:31 ` [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP Marek Vasut
0 siblings, 1 reply; 9+ messages in thread
From: Marek Vasut @ 2022-04-01 14:31 UTC (permalink / raw)
To: u-boot
Cc: Marek Vasut, Angus Ainslie, Bin Meng, Fabio Estevam,
Kunihiko Hayashi, Michal Simek, Peng Fan, Stefano Babic
Rename the select_dr_mode callback to glue_configure, the callback is
used for more than enforcing controller mode even on the TI chips, so
change the name to a more generic one. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Angus Ainslie <angus@akkea.ca>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
drivers/usb/dwc3/dwc3-generic.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 01bd0ca190e..7e3814207e4 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -219,11 +219,11 @@ U_BOOT_DRIVER(dwc3_generic_host) = {
#endif
struct dwc3_glue_ops {
- void (*select_dr_mode)(struct udevice *dev, int index,
+ void (*glue_configure)(struct udevice *dev, int index,
enum usb_dr_mode mode);
};
-void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
+void dwc3_ti_glue_configure(struct udevice *dev, int index,
enum usb_dr_mode mode)
{
#define USBOTGSS_UTMI_OTG_STATUS 0x0084
@@ -304,7 +304,7 @@ enum dwc3_omap_utmi_mode {
}
struct dwc3_glue_ops ti_ops = {
- .select_dr_mode = dwc3_ti_select_dr_mode,
+ .glue_configure = dwc3_ti_glue_configure,
};
static int dwc3_glue_bind(struct udevice *parent)
@@ -435,8 +435,8 @@ static int dwc3_glue_probe(struct udevice *dev)
dr_mode = usb_get_dr_mode(dev_ofnode(child));
device_find_next_child(&child);
- if (ops && ops->select_dr_mode)
- ops->select_dr_mode(dev, index, dr_mode);
+ if (ops && ops->glue_configure)
+ ops->glue_configure(dev, index, dr_mode);
index++;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
2022-04-01 14:31 [PATCH 1/2] usb: dwc3: Rename .select_dr_mode to .glue_configure Marek Vasut
@ 2022-04-01 14:31 ` Marek Vasut
2022-04-01 21:28 ` Tim Harvey
2022-04-07 22:22 ` Tim Harvey
0 siblings, 2 replies; 9+ messages in thread
From: Marek Vasut @ 2022-04-01 14:31 UTC (permalink / raw)
To: u-boot
Cc: Marek Vasut, Angus Ainslie, Bin Meng, Fabio Estevam,
Kunihiko Hayashi, Michal Simek, Peng Fan, Stefano Babic
The i.MX8MP glue needs to be configured based on a couple of DT
properties, implement .glue_configure callback to parse those DT
properties and configure the glue accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Angus Ainslie <angus@akkea.ca>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 7e3814207e4..6cf844cb483 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -223,6 +223,57 @@ struct dwc3_glue_ops {
enum usb_dr_mode mode);
};
+void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
+ enum usb_dr_mode mode)
+{
+/* USB glue registers */
+#define USB_CTRL0 0x00
+#define USB_CTRL1 0x04
+
+#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
+#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
+#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
+
+#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
+#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
+ fdt_addr_t regs = dev_read_addr_index(dev, 1);
+ void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
+ u32 value;
+
+ value = readl(base + USB_CTRL0);
+
+ if (dev_read_bool(dev, "fsl,permanently-attached"))
+ value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+ else
+ value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+
+ if (dev_read_bool(dev, "fsl,disable-port-power-control"))
+ value &= ~(USB_CTRL0_PORTPWR_EN);
+ else
+ value |= USB_CTRL0_PORTPWR_EN;
+
+ writel(value, base + USB_CTRL0);
+
+ value = readl(base + USB_CTRL1);
+ if (dev_read_bool(dev, "fsl,over-current-active-low"))
+ value |= USB_CTRL1_OC_POLARITY;
+ else
+ value &= ~USB_CTRL1_OC_POLARITY;
+
+ if (dev_read_bool(dev, "fsl,power-active-low"))
+ value |= USB_CTRL1_PWR_POLARITY;
+ else
+ value &= ~USB_CTRL1_PWR_POLARITY;
+
+ writel(value, base + USB_CTRL1);
+
+ unmap_physmem(base, MAP_NOCACHE);
+}
+
+struct dwc3_glue_ops imx8mp_ops = {
+ .glue_configure = dwc3_imx8mp_glue_configure,
+};
+
void dwc3_ti_glue_configure(struct udevice *dev, int index,
enum usb_dr_mode mode)
{
@@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "qcom,dwc3" },
+ { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
{ }
--
2.35.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
2022-04-01 14:31 ` [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP Marek Vasut
@ 2022-04-01 21:28 ` Tim Harvey
2022-04-02 0:48 ` Marek Vasut
2022-04-07 22:22 ` Tim Harvey
1 sibling, 1 reply; 9+ messages in thread
From: Tim Harvey @ 2022-04-01 21:28 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, Angus Ainslie, Bin Meng, Fabio Estevam, Kunihiko Hayashi,
Michal Simek, Peng Fan, Stefano Babic
On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut <marex@denx.de> wrote:
>
> The i.MX8MP glue needs to be configured based on a couple of DT
> properties, implement .glue_configure callback to parse those DT
> properties and configure the glue accordingly.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Angus Ainslie <angus@akkea.ca>
> Cc: Bin Meng <bmeng.cn@gmail.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Cc: Michal Simek <michal.simek@xilinx.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> index 7e3814207e4..6cf844cb483 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
> enum usb_dr_mode mode);
> };
>
> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
> + enum usb_dr_mode mode)
> +{
> +/* USB glue registers */
> +#define USB_CTRL0 0x00
> +#define USB_CTRL1 0x04
> +
> +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
> +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
> +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
> +
> +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
> + fdt_addr_t regs = dev_read_addr_index(dev, 1);
> + void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
> + u32 value;
> +
> + value = readl(base + USB_CTRL0);
> +
> + if (dev_read_bool(dev, "fsl,permanently-attached"))
> + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> + else
> + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> +
> + if (dev_read_bool(dev, "fsl,disable-port-power-control"))
> + value &= ~(USB_CTRL0_PORTPWR_EN);
> + else
> + value |= USB_CTRL0_PORTPWR_EN;
> +
> + writel(value, base + USB_CTRL0);
> +
> + value = readl(base + USB_CTRL1);
> + if (dev_read_bool(dev, "fsl,over-current-active-low"))
> + value |= USB_CTRL1_OC_POLARITY;
> + else
> + value &= ~USB_CTRL1_OC_POLARITY;
> +
> + if (dev_read_bool(dev, "fsl,power-active-low"))
> + value |= USB_CTRL1_PWR_POLARITY;
> + else
> + value &= ~USB_CTRL1_PWR_POLARITY;
> +
> + writel(value, base + USB_CTRL1);
> +
> + unmap_physmem(base, MAP_NOCACHE);
> +}
> +
> +struct dwc3_glue_ops imx8mp_ops = {
> + .glue_configure = dwc3_imx8mp_glue_configure,
> +};
> +
> void dwc3_ti_glue_configure(struct udevice *dev, int index,
> enum usb_dr_mode mode)
> {
> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
> { .compatible = "rockchip,rk3328-dwc3" },
> { .compatible = "rockchip,rk3399-dwc3" },
> { .compatible = "qcom,dwc3" },
> + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
> { .compatible = "fsl,imx8mq-dwc3" },
> { .compatible = "intel,tangier-dwc3" },
> { }
> --
> 2.35.1
>
Marek,
Looks like your working on IMX8MP USB support - thanks for that!
I'm working on bring-up of an IMX8MP board and can test your
power-domain and USB patches but I'm having trouble getting some of
your patches to apply - do you have a repo I can pull from?
Best Regards,
Tim
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
2022-04-01 21:28 ` Tim Harvey
@ 2022-04-02 0:48 ` Marek Vasut
2022-04-04 18:51 ` Tim Harvey
0 siblings, 1 reply; 9+ messages in thread
From: Marek Vasut @ 2022-04-02 0:48 UTC (permalink / raw)
To: Tim Harvey
Cc: u-boot, Angus Ainslie, Bin Meng, Fabio Estevam, Kunihiko Hayashi,
Michal Simek, Peng Fan, Stefano Babic
On 4/1/22 23:28, Tim Harvey wrote:
> On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut <marex@denx.de> wrote:
>>
>> The i.MX8MP glue needs to be configured based on a couple of DT
>> properties, implement .glue_configure callback to parse those DT
>> properties and configure the glue accordingly.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Angus Ainslie <angus@akkea.ca>
>> Cc: Bin Meng <bmeng.cn@gmail.com>
>> Cc: Fabio Estevam <festevam@gmail.com>
>> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
>> Cc: Michal Simek <michal.simek@xilinx.com>
>> Cc: Peng Fan <peng.fan@nxp.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>> ---
>> drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
>> 1 file changed, 52 insertions(+)
>>
>> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
>> index 7e3814207e4..6cf844cb483 100644
>> --- a/drivers/usb/dwc3/dwc3-generic.c
>> +++ b/drivers/usb/dwc3/dwc3-generic.c
>> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
>> enum usb_dr_mode mode);
>> };
>>
>> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
>> + enum usb_dr_mode mode)
>> +{
>> +/* USB glue registers */
>> +#define USB_CTRL0 0x00
>> +#define USB_CTRL1 0x04
>> +
>> +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
>> +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
>> +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
>> +
>> +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
>> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
>> + fdt_addr_t regs = dev_read_addr_index(dev, 1);
>> + void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
>> + u32 value;
>> +
>> + value = readl(base + USB_CTRL0);
>> +
>> + if (dev_read_bool(dev, "fsl,permanently-attached"))
>> + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
>> + else
>> + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
>> +
>> + if (dev_read_bool(dev, "fsl,disable-port-power-control"))
>> + value &= ~(USB_CTRL0_PORTPWR_EN);
>> + else
>> + value |= USB_CTRL0_PORTPWR_EN;
>> +
>> + writel(value, base + USB_CTRL0);
>> +
>> + value = readl(base + USB_CTRL1);
>> + if (dev_read_bool(dev, "fsl,over-current-active-low"))
>> + value |= USB_CTRL1_OC_POLARITY;
>> + else
>> + value &= ~USB_CTRL1_OC_POLARITY;
>> +
>> + if (dev_read_bool(dev, "fsl,power-active-low"))
>> + value |= USB_CTRL1_PWR_POLARITY;
>> + else
>> + value &= ~USB_CTRL1_PWR_POLARITY;
>> +
>> + writel(value, base + USB_CTRL1);
>> +
>> + unmap_physmem(base, MAP_NOCACHE);
>> +}
>> +
>> +struct dwc3_glue_ops imx8mp_ops = {
>> + .glue_configure = dwc3_imx8mp_glue_configure,
>> +};
>> +
>> void dwc3_ti_glue_configure(struct udevice *dev, int index,
>> enum usb_dr_mode mode)
>> {
>> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
>> { .compatible = "rockchip,rk3328-dwc3" },
>> { .compatible = "rockchip,rk3399-dwc3" },
>> { .compatible = "qcom,dwc3" },
>> + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
>> { .compatible = "fsl,imx8mq-dwc3" },
>> { .compatible = "intel,tangier-dwc3" },
>> { }
>> --
>> 2.35.1
>>
>
> Marek,
>
> Looks like your working on IMX8MP USB support - thanks for that!
>
> I'm working on bring-up of an IMX8MP board and can test your
> power-domain and USB patches but I'm having trouble getting some of
> your patches to apply - do you have a repo I can pull from?
https://source.denx.de/u-boot/custodians/u-boot-usb/-/commits/imx-8mp
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
2022-04-02 0:48 ` Marek Vasut
@ 2022-04-04 18:51 ` Tim Harvey
2022-04-04 19:11 ` Marek Vasut
0 siblings, 1 reply; 9+ messages in thread
From: Tim Harvey @ 2022-04-04 18:51 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, Angus Ainslie, Bin Meng, Fabio Estevam, Kunihiko Hayashi,
Michal Simek, Peng Fan, Stefano Babic
On Fri, Apr 1, 2022 at 5:48 PM Marek Vasut <marex@denx.de> wrote:
>
> On 4/1/22 23:28, Tim Harvey wrote:
> > On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut <marex@denx.de> wrote:
> >>
> >> The i.MX8MP glue needs to be configured based on a couple of DT
> >> properties, implement .glue_configure callback to parse those DT
> >> properties and configure the glue accordingly.
> >>
> >> Signed-off-by: Marek Vasut <marex@denx.de>
> >> Cc: Angus Ainslie <angus@akkea.ca>
> >> Cc: Bin Meng <bmeng.cn@gmail.com>
> >> Cc: Fabio Estevam <festevam@gmail.com>
> >> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> >> Cc: Michal Simek <michal.simek@xilinx.com>
> >> Cc: Peng Fan <peng.fan@nxp.com>
> >> Cc: Stefano Babic <sbabic@denx.de>
> >> ---
> >> drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
> >> 1 file changed, 52 insertions(+)
> >>
> >> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> >> index 7e3814207e4..6cf844cb483 100644
> >> --- a/drivers/usb/dwc3/dwc3-generic.c
> >> +++ b/drivers/usb/dwc3/dwc3-generic.c
> >> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
> >> enum usb_dr_mode mode);
> >> };
> >>
> >> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
> >> + enum usb_dr_mode mode)
> >> +{
> >> +/* USB glue registers */
> >> +#define USB_CTRL0 0x00
> >> +#define USB_CTRL1 0x04
> >> +
> >> +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
> >> +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
> >> +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
> >> +
> >> +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
> >> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
> >> + fdt_addr_t regs = dev_read_addr_index(dev, 1);
> >> + void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
> >> + u32 value;
> >> +
> >> + value = readl(base + USB_CTRL0);
> >> +
> >> + if (dev_read_bool(dev, "fsl,permanently-attached"))
> >> + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> >> + else
> >> + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> >> +
> >> + if (dev_read_bool(dev, "fsl,disable-port-power-control"))
> >> + value &= ~(USB_CTRL0_PORTPWR_EN);
> >> + else
> >> + value |= USB_CTRL0_PORTPWR_EN;
> >> +
> >> + writel(value, base + USB_CTRL0);
> >> +
> >> + value = readl(base + USB_CTRL1);
> >> + if (dev_read_bool(dev, "fsl,over-current-active-low"))
> >> + value |= USB_CTRL1_OC_POLARITY;
> >> + else
> >> + value &= ~USB_CTRL1_OC_POLARITY;
> >> +
> >> + if (dev_read_bool(dev, "fsl,power-active-low"))
> >> + value |= USB_CTRL1_PWR_POLARITY;
> >> + else
> >> + value &= ~USB_CTRL1_PWR_POLARITY;
> >> +
> >> + writel(value, base + USB_CTRL1);
> >> +
> >> + unmap_physmem(base, MAP_NOCACHE);
> >> +}
> >> +
> >> +struct dwc3_glue_ops imx8mp_ops = {
> >> + .glue_configure = dwc3_imx8mp_glue_configure,
> >> +};
> >> +
> >> void dwc3_ti_glue_configure(struct udevice *dev, int index,
> >> enum usb_dr_mode mode)
> >> {
> >> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
> >> { .compatible = "rockchip,rk3328-dwc3" },
> >> { .compatible = "rockchip,rk3399-dwc3" },
> >> { .compatible = "qcom,dwc3" },
> >> + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
> >> { .compatible = "fsl,imx8mq-dwc3" },
> >> { .compatible = "intel,tangier-dwc3" },
> >> { }
> >> --
> >> 2.35.1
> >>
> >
> > Marek,
> >
> > Looks like your working on IMX8MP USB support - thanks for that!
> >
> > I'm working on bring-up of an IMX8MP board and can test your
> > power-domain and USB patches but I'm having trouble getting some of
> > your patches to apply - do you have a repo I can pull from?
>
> https://source.denx.de/u-boot/custodians/u-boot-usb/-/commits/imx-8mp
Marek,
Thanks. I've thrown my board patches on top but don't get very far
with regards to USB due to clk:
U-Boot 2022.04-rc5-00085-gce6842669a59-dirty (Apr 04 2022 - 11:32:45 -0700)
CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 38C
Reset cause: POR
Model: Gateworks Venice GW74xx i.MX8MP board
DRAM: 1 GiB
clk_register: failed to get osc_32k device (parent of usb_root_clk)
Core: 210 devices, 23 uclasses, devicetree: separate
WDT: Started watchdog@30280000 with servicing (60s timeout)
MMC: FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from nowhere... OK
In: serial@30890000
Out: serial@30890000
Err: serial@30890000
u-boot=> usb start
starting USB...
Bus usb@38100000: Port not available.
Bus usb@38200000: Port not available.
I see 'clk_register: failed to get osc_32k device (parent of
usb_root_clk)' above yet clock-osc-32k seems to be there:
u-boot=> clk dump
Rate Usecnt Name
------------------------------------------
32768 0 |-- clock-osc-32k
24000000 4 |-- clock-osc-24m
24000000 0 | |-- dram_pll_ref_sel
750000000 0 | | `-- dram_pll
750000000 0 | | `-- dram_pll_bypass
750000000 0 | | `-- dram_pll_out
750000000 0 | | `-- dram_core_clk
750000000 0 | | `-- dram1_root_clk
24000000 0 | |-- arm_pll_ref_sel
1200000000 0 | | `-- arm_pll
1200000000 0 | | `-- arm_pll_bypass
1200000000 0 | | `-- arm_pll_out
24000000 1 | |-- sys_pll1_ref_sel
800000000 1 | | `-- sys_pll1
800000000 1 | | `-- sys_pll1_bypass
800000000 2 | | `-- sys_pll1_out
40000000 0 | | |-- sys_pll1_40m
80000000 0 | | |-- sys_pll1_80m
100000000 0 | | |-- sys_pll1_100m
100000000 0 | | | `-- dram_alt
25000000 0 | | | `-- dram_alt_root
133333333 0 | | |-- sys_pll1_133m
133333333 0 | | | `-- ahb_root
66666667 0 | | | `-- ipg_root
66666667 0 | | | |--
gpio1_root_clk
66666667 0 | | | |--
gpio2_root_clk
66666667 0 | | | |--
gpio3_root_clk
66666667 0 | | | |--
gpio4_root_clk
66666667 0 | | | |--
gpio5_root_clk
66666667 0 | | | `-- hsio_root_clk
160000000 0 | | |-- sys_pll1_160m
200000000 0 | | |-- sys_pll1_200m
266666666 1 | | |-- sys_pll1_266m
266666666 0 | | | |-- nand_usdhc_bus
266666666 4 | | | `-- enet_axi
266666666 2 | | | |-- enet1_root_clk
266666666 2 | | | `-- sim_enet_root_clk
400000000 2 | | |-- sys_pll1_400m
400000000 0 | | | |-- qspi
400000000 0 | | | | `-- qspi_root_clk
400000000 2 | | | |-- usdhc1
400000000 2 | | | | `-- usdhc1_root_clk
200000000 0 | | | |-- usdhc2
200000000 0 | | | | `-- usdhc2_root_clk
400000000 2 | | | `-- usdhc3
400000000 2 | | | `-- usdhc3_root_clk
800000000 0 | | `-- sys_pll1_800m
400000000 0 | | |-- hsio_axi
400000000 0 | | |-- main_axi
800000000 0 | | |-- noc
160000000 0 | | |-- dram_apb
400000000 0 | | `-- gic
24000000 1 | |-- sys_pll2_ref_sel
1000000000 1 | | `-- sys_pll2
1000000000 1 | | `-- sys_pll2_bypass
1000000000 3 | | `-- sys_pll2_out
50000000 2 | | |-- sys_pll2_50m
50000000 2 | | | `-- enet_phy_ref
100000000 2 | | |-- sys_pll2_100m
100000000 2 | | | `-- enet_timer
125000000 2 | | |-- sys_pll2_125m
125000000 2 | | | `-- enet_ref
166666666 0 | | |-- sys_pll2_166m
200000000 0 | | |-- sys_pll2_200m
250000000 0 | | |-- sys_pll2_250m
333333333 0 | | |-- sys_pll2_333m
500000000 0 | | |-- sys_pll2_500m
500000000 0 | | | `-- arm_a53_src
500000000 0 | | | `-- arm_a53_cg
500000000 0 | | | `-- arm_a53_div
1000000000 0 | | `-- sys_pll2_1000m
24000000 0 | |-- sys_pll3_ref_sel
600000000 0 | | `-- sys_pll3
600000000 0 | | `-- sys_pll3_bypass
600000000 0 | | `-- sys_pll3_out
600000000 0 | | `-- noc_io
24000000 0 | |-- i2c5
24000000 0 | | `-- i2c5_root_clk
24000000 0 | |-- i2c6
24000000 0 | | `-- i2c6_root_clk
24000000 2 | |-- i2c1
24000000 2 | | `-- i2c1_root_clk
24000000 2 | |-- i2c2
24000000 2 | | `-- i2c2_root_clk
24000000 0 | |-- i2c3
24000000 0 | | `-- i2c3_root_clk
24000000 0 | |-- i2c4
24000000 0 | | `-- i2c4_root_clk
24000000 0 | |-- uart1
24000000 0 | | `-- uart1_root_clk
24000000 0 | |-- uart2
24000000 0 | | `-- uart2_root_clk
24000000 0 | |-- uart3
24000000 0 | | `-- uart3_root_clk
24000000 0 | |-- uart4
24000000 0 | | `-- uart4_root_clk
24000000 0 | |-- usb_core_ref
24000000 0 | |-- usb_phy_ref
24000000 0 | | `-- usb_phy_root_clk
24000000 0 | `-- wdog
24000000 0 | |-- wdog1_root_clk
24000000 0 | |-- wdog2_root_clk
24000000 0 | `-- wdog3_root_clk
4294967277 0 |-- usb_root_clk
u-boot=> dm tree
Class Index Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
clk 0 [ + ] fixed_clock |-- clock-osc-32k
clk 1 [ + ] fixed_clock |-- clock-osc-24m
clk 8 [ + ] ccf_clk_mux | |-- dram_pll_ref_sel
clk 13 [ + ] imx_clk_pll1443x | | `-- dram_pll
clk 18 [ + ] ccf_clk_mux | | `-- dram_pll_bypass
clk 23 [ + ] clk_gate | | `-- dram_pll_out
clk 81 [ + ] ccf_clk_mux | |
`-- dram_core_clk
clk 82 [ ] imx_clk_gate2 | |
`-- dram1_root_clk
clk 9 [ + ] ccf_clk_mux | |-- arm_pll_ref_sel
clk 14 [ + ] imx_clk_pll1416x | | `-- arm_pll
clk 19 [ + ] ccf_clk_mux | | `-- arm_pll_bypass
clk 24 [ ] clk_gate | | `-- arm_pll_out
clk 10 [ + ] ccf_clk_mux | |-- sys_pll1_ref_sel
clk 15 [ + ] imx_clk_pll1416x | | `-- sys_pll1
clk 20 [ + ] ccf_clk_mux | | `-- sys_pll1_bypass
clk 25 [ + ] clk_gate | | `-- sys_pll1_out
clk 28 [ ] ccf_clk_fixed_factor | |
|-- sys_pll1_40m
clk 29 [ ] ccf_clk_fixed_factor | |
|-- sys_pll1_80m
clk 30 [ + ] ccf_clk_fixed_factor | |
|-- sys_pll1_100m
clk 57 [ + ] clk_composite | | |
`-- dram_alt
clk 80 [ ] ccf_clk_fixed_factor | | |
`-- dram_alt_root
clk 31 [ + ] ccf_clk_fixed_factor | |
|-- sys_pll1_133m
clk 55 [ + ] clk_composite | | |
`-- ahb_root
clk 56 [ + ] ccf_clk_divider | | |
`-- ipg_root
clk 84 [ ] imx_clk_gate2 | | |
|-- gpio1_root_clk
clk 85 [ ] imx_clk_gate2 | | |
|-- gpio2_root_clk
clk 86 [ ] imx_clk_gate2 | | |
|-- gpio3_root_clk
clk 87 [ ] imx_clk_gate2 | | |
|-- gpio4_root_clk
clk 88 [ ] imx_clk_gate2 | | |
|-- gpio5_root_clk
clk 108 [ ] imx_clk_gate2 | | |
`-- hsio_root_clk
clk 32 [ ] ccf_clk_fixed_factor | |
|-- sys_pll1_160m
clk 33 [ ] ccf_clk_fixed_factor | |
|-- sys_pll1_200m
clk 34 [ + ] ccf_clk_fixed_factor | |
|-- sys_pll1_266m
clk 52 [ ] clk_composite | | |
|-- nand_usdhc_bus
clk 51 [ + ] clk_composite | | |
`-- enet_axi
clk 83 [ ] imx_clk_gate2 | | |
|-- enet1_root_clk
clk 96 [ ] imx_clk_gate2 | | |
`-- sim_enet_root_clk
clk 35 [ + ] ccf_clk_fixed_factor | |
|-- sys_pll1_400m
clk 64 [ + ] clk_composite | | | |-- qspi
clk 93 [ ] imx_clk_gate2 | | |
| `-- qspi_root_clk
clk 65 [ + ] clk_composite | | |
|-- usdhc1
clk 103 [ ] imx_clk_gate2 | | |
| `-- usdhc1_root_clk
clk 66 [ + ] clk_composite | | |
|-- usdhc2
clk 104 [ ] imx_clk_gate2 | | |
| `-- usdhc2_root_clk
clk 79 [ + ] clk_composite | | |
`-- usdhc3
clk 109 [ ] imx_clk_gate2 | | |
`-- usdhc3_root_clk
clk 36 [ + ] ccf_clk_fixed_factor | |
`-- sys_pll1_800m
clk 49 [ ] clk_composite | |
|-- hsio_axi
clk 50 [ ] clk_composite | |
|-- main_axi
clk 53 [ ] clk_composite | | |-- noc
clk 58 [ ] clk_composite | |
|-- dram_apb
clk 77 [ ] clk_composite | | `-- gic
clk 11 [ + ] ccf_clk_mux | |-- sys_pll2_ref_sel
clk 16 [ + ] imx_clk_pll1416x | | `-- sys_pll2
clk 21 [ + ] ccf_clk_mux | | `-- sys_pll2_bypass
clk 26 [ + ] clk_gate | | `-- sys_pll2_out
clk 37 [ ] ccf_clk_fixed_factor | |
|-- sys_pll2_50m
clk 63 [ ] clk_composite | | |
`-- enet_phy_ref
clk 38 [ ] ccf_clk_fixed_factor | |
|-- sys_pll2_100m
clk 62 [ ] clk_composite | | |
`-- enet_timer
clk 39 [ ] ccf_clk_fixed_factor | |
|-- sys_pll2_125m
clk 61 [ ] clk_composite | | |
`-- enet_ref
clk 40 [ ] ccf_clk_fixed_factor | |
|-- sys_pll2_166m
clk 41 [ ] ccf_clk_fixed_factor | |
|-- sys_pll2_200m
clk 42 [ ] ccf_clk_fixed_factor | |
|-- sys_pll2_250m
clk 43 [ ] ccf_clk_fixed_factor | |
|-- sys_pll2_333m
clk 44 [ + ] ccf_clk_fixed_factor | |
|-- sys_pll2_500m
clk 46 [ + ] ccf_clk_mux | | |
`-- arm_a53_src
clk 47 [ + ] clk_gate | | |
`-- arm_a53_cg
clk 48 [ ] ccf_clk_divider | | |
`-- arm_a53_div
clk 45 [ ] ccf_clk_fixed_factor | |
`-- sys_pll2_1000m
clk 12 [ + ] ccf_clk_mux | |-- sys_pll3_ref_sel
clk 17 [ + ] imx_clk_pll1416x | | `-- sys_pll3
clk 22 [ + ] ccf_clk_mux | | `-- sys_pll3_bypass
clk 27 [ + ] clk_gate | | `-- sys_pll3_out
clk 54 [ ] clk_composite | | `-- noc_io
clk 59 [ + ] clk_composite | |-- i2c5
clk 94 [ ] imx_clk_gate2 | | `-- i2c5_root_clk
clk 60 [ + ] clk_composite | |-- i2c6
clk 95 [ ] imx_clk_gate2 | | `-- i2c6_root_clk
clk 67 [ + ] clk_composite | |-- i2c1
clk 89 [ ] imx_clk_gate2 | | `-- i2c1_root_clk
clk 68 [ + ] clk_composite | |-- i2c2
clk 90 [ ] imx_clk_gate2 | | `-- i2c2_root_clk
clk 69 [ + ] clk_composite | |-- i2c3
clk 91 [ ] imx_clk_gate2 | | `-- i2c3_root_clk
clk 70 [ + ] clk_composite | |-- i2c4
clk 92 [ ] imx_clk_gate2 | | `-- i2c4_root_clk
clk 71 [ + ] clk_composite | |-- uart1
clk 97 [ ] imx_clk_gate2 | | `-- uart1_root_clk
clk 72 [ + ] clk_composite | |-- uart2
clk 98 [ ] imx_clk_gate2 | | `-- uart2_root_clk
clk 73 [ + ] clk_composite | |-- uart3
clk 99 [ ] imx_clk_gate2 | | `-- uart3_root_clk
clk 74 [ + ] clk_composite | |-- uart4
clk 100 [ ] imx_clk_gate2 | | `-- uart4_root_clk
clk 75 [ ] clk_composite | |-- usb_core_ref
clk 76 [ + ] clk_composite | |-- usb_phy_ref
clk 102 [ ] imx_clk_gate2 | | `-- usb_phy_root_clk
clk 78 [ + ] clk_composite | `-- wdog
clk 105 [ ] imx_clk_gate2 | |-- wdog1_root_clk
clk 106 [ ] imx_clk_gate2 | |-- wdog2_root_clk
clk 107 [ ] imx_clk_gate2 | `-- wdog3_root_clk
clk 2 [ ] fixed_clock |-- clock-ext1
clk 3 [ ] fixed_clock |-- clock-ext2
clk 4 [ ] fixed_clock |-- clock-ext3
clk 5 [ ] fixed_clock |-- clock-ext4
firmware 0 [ ] psci |-- psci
sysreset 0 [ ] psci-sysreset | `-- psci-sysreset
simple_bus 0 [ + ] simple_bus |-- soc@0
simple_bus 1 [ + ] simple_bus | |-- bus@30000000
gpio 0 [ + ] gpio_mxc | | |-- gpio@30200000
nop 0 [ + ] gpio_hog | | | |-- dio0
nop 1 [ + ] gpio_hog | | | `-- dio1
gpio 1 [ + ] gpio_mxc | | |-- gpio@30210000
nop 2 [ + ] gpio_hog | | | |-- pcie1_wdis#
nop 3 [ + ] gpio_hog | | | |-- pcie2_wdis#
nop 4 [ + ] gpio_hog | | | `-- pcie3_wdis#
gpio 2 [ + ] gpio_mxc | | |-- gpio@30220000
nop 5 [ + ] gpio_hog | | | |-- m2_gdis#
nop 6 [ + ] gpio_hog | | | |-- m2_rst#
nop 7 [ + ] gpio_hog | | | `-- m2_off#
gpio 3 [ + ] gpio_mxc | | |-- gpio@30230000
nop 8 [ + ] gpio_hog | | | |-- m2_wdis#
nop 9 [ + ] gpio_hog | | | `-- uart_rs485
gpio 4 [ + ] gpio_mxc | | |-- gpio@30240000
nop 10 [ + ] gpio_hog | | | |-- uart_half
nop 11 [ + ] gpio_hog | | | `-- uart_term
thermal 0 [ ] imx_tmu | | |-- tmu@30260000
thermal 1 [ ] imx_tmu | | | |-- cpu-thermal
thermal 2 [ ] imx_tmu | | | `-- soc-thermal
watchdog 0 [ + ] imx_wdt | | |-- watchdog@30280000
pinctrl 0 [ + ] imx8mq-pinctrl | | |-- pinctrl@30330000
pinconfig 0 [ + ] pinconfig | | | |-- hoggrp
pinconfig 1 [ ] pinconfig | | | |-- accelgrp
pinconfig 2 [ + ] pinconfig | | | |-- eqosgrp
pinconfig 3 [ + ] pinconfig | | | |-- fecgrp
pinconfig 4 [ ] pinconfig | | | |-- flexcan2grp
pinconfig 5 [ ] pinconfig | | | |-- gscgrp
pinconfig 6 [ + ] pinconfig | | | |-- i2c1grp
pinconfig 7 [ + ] pinconfig | | | |-- i2c2grp
pinconfig 8 [ ] pinconfig | | | |-- i2c3grp
pinconfig 9 [ ] pinconfig | | | |-- i2c4grp
pinconfig 10 [ ] pinconfig | | | |-- kszgrp
pinconfig 11 [ + ] pinconfig | | | |-- ledgrp
pinconfig 12 [ ] pinconfig | | | |-- pciegrp
pinconfig 13 [ ] pinconfig | | | |-- pmicgrp
pinconfig 14 [ ] pinconfig | | | |-- ppsgrp
pinconfig 15 [ ] pinconfig | | | |-- regcangrp
pinconfig 16 [ ] pinconfig | | | |-- regwifigrp
pinconfig 17 [ ] pinconfig | | | |-- regusb1grp
pinconfig 18 [ ] pinconfig | | | |-- regusb2grp
pinconfig 19 [ ] pinconfig | | | |-- sai2grp
pinconfig 20 [ ] pinconfig | | | |-- spi2grp
pinconfig 21 [ ] pinconfig | | | |-- uart1grp
pinconfig 22 [ + ] pinconfig | | | |-- uart2grp
pinconfig 23 [ ] pinconfig | | | |-- uart3grp
pinconfig 24 [ ] pinconfig | | | |-- uart3gpiogrp
pinconfig 25 [ ] pinconfig | | | |-- uart4grp
pinconfig 26 [ + ] pinconfig | | | |-- usdhc1grp
pinconfig 27 [ + ] pinconfig | | | |-- usdhc3grp
pinconfig 28 [ ] pinconfig | | | |-- usdhc3-100mhzgrp
pinconfig 29 [ ] pinconfig | | | |-- usdhc3-200mhzgrp
pinconfig 30 [ + ] pinconfig | | | `-- wdoggrp
simple_bus 2 [ ] simple_bus | | |-- snvs@30370000
clk 6 [ + ] clk_imx8mp | | |--
clock-controller@30380000
power_doma 0 [ ] imx8m_power_domain | | `-- gpc@303a0000
power_doma 1 [ ] imx8m_power_domain | | |-- power-domain@1
power_doma 2 [ ] imx8m_power_domain | | |-- power-domain@2
power_doma 3 [ ] imx8m_power_domain | | |-- power-domain@3
power_doma 4 [ ] imx8m_power_domain | | `-- power-domains@17
simple_bus 3 [ ] simple_bus | |-- bus@30400000
simple_bus 4 [ + ] simple_bus | |-- bus@30800000
serial 0 [ ] serial_mxc | | |-- serial@30860000
serial 1 [ ] serial_mxc | | |-- serial@30880000
serial 2 [ + ] serial_mxc | | |-- serial@30890000
i2c 0 [ + ] i2c_mxc | | |-- i2c@30a20000
misc 0 [ ] gsc | | | `-- gsc@20
i2c 1 [ + ] i2c_mxc | | |-- i2c@30a30000
dsa 0 [ + ] ksz-switch | | | `-- switch@5f
ethernet 0 [ + ] dsa-port | | | |-- lan1
ethernet 1 [ + ] dsa-port | | | |-- lan2
ethernet 2 [ + ] dsa-port | | | |-- lan3
ethernet 3 [ + ] dsa-port | | | |-- lan4
ethernet 4 [ + ] dsa-port | | | |-- lan5
mdio 0 [ + ] ksz_mdio | | | `-- ksz-mdio-0
i2c 2 [ ] i2c_mxc | | |-- i2c@30a40000
i2c 3 [ ] i2c_mxc | | |-- i2c@30a50000
serial 3 [ ] serial_mxc | | |-- serial@30a60000
mmc 0 [ + ] fsl_esdhc | | |-- mmc@30b40000
blk 0 [ ] mmc_blk | | | `-- mmc@30b40000.blk
mmc 1 [ + ] fsl_esdhc | | |-- mmc@30b60000
blk 1 [ ] mmc_blk | | | `-- mmc@30b60000.blk
ethernet 5 [ + ] fecmxc | | |-- ethernet@30be0000
ethernet 6 [ + ] eth_eqos | | `-- ethernet@30bf0000
eth_phy_ge 0 [ + ] eth_phy_generic_drv | | `-- ethernet-phy@0
simple_bus 5 [ ] simple_bus | |-- bus@32c00000
nop 12 [ ] dwc3-generic-wrapper | |-- usb@32f10100
usb 0 [ ] dwc3-generic-host | | `-- usb@38100000
nop 13 [ ] dwc3-generic-wrapper | `-- usb@32f10108
usb 1 [ ] dwc3-generic-host | `-- usb@38200000
led 0 [ + ] gpio_led |-- led-controller
led 1 [ + ] gpio_led | |-- led-0
led 2 [ + ] gpio_led | `-- led-1
clk 7 [ ] fixed_clock |-- pcie0-refclk
regulator 0 [ ] regulator_fixed |-- regulator-usb1
regulator 1 [ ] regulator_fixed |-- regulator-usb2
regulator 2 [ ] regulator_fixed |-- regulator-can2-stby
regulator 3 [ ] regulator_fixed |-- regulator-wifi-en
sysreset 1 [ ] wdt_reboot `-- wdt-reboot
I've got the following in my config:
CONFIG_CLK_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y
...
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
...
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
Any ideas?
Best Regards,
Tim
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
2022-04-04 18:51 ` Tim Harvey
@ 2022-04-04 19:11 ` Marek Vasut
2022-04-04 20:15 ` Tim Harvey
0 siblings, 1 reply; 9+ messages in thread
From: Marek Vasut @ 2022-04-04 19:11 UTC (permalink / raw)
To: Tim Harvey
Cc: u-boot, Angus Ainslie, Bin Meng, Fabio Estevam, Kunihiko Hayashi,
Michal Simek, Peng Fan, Stefano Babic
On 4/4/22 20:51, Tim Harvey wrote:
> On Fri, Apr 1, 2022 at 5:48 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 4/1/22 23:28, Tim Harvey wrote:
>>> On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> The i.MX8MP glue needs to be configured based on a couple of DT
>>>> properties, implement .glue_configure callback to parse those DT
>>>> properties and configure the glue accordingly.
>>>>
>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>> Cc: Angus Ainslie <angus@akkea.ca>
>>>> Cc: Bin Meng <bmeng.cn@gmail.com>
>>>> Cc: Fabio Estevam <festevam@gmail.com>
>>>> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
>>>> Cc: Michal Simek <michal.simek@xilinx.com>
>>>> Cc: Peng Fan <peng.fan@nxp.com>
>>>> Cc: Stefano Babic <sbabic@denx.de>
>>>> ---
>>>> drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
>>>> 1 file changed, 52 insertions(+)
>>>>
>>>> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
>>>> index 7e3814207e4..6cf844cb483 100644
>>>> --- a/drivers/usb/dwc3/dwc3-generic.c
>>>> +++ b/drivers/usb/dwc3/dwc3-generic.c
>>>> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
>>>> enum usb_dr_mode mode);
>>>> };
>>>>
>>>> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
>>>> + enum usb_dr_mode mode)
>>>> +{
>>>> +/* USB glue registers */
>>>> +#define USB_CTRL0 0x00
>>>> +#define USB_CTRL1 0x04
>>>> +
>>>> +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
>>>> +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
>>>> +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
>>>> +
>>>> +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
>>>> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
>>>> + fdt_addr_t regs = dev_read_addr_index(dev, 1);
>>>> + void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
>>>> + u32 value;
>>>> +
>>>> + value = readl(base + USB_CTRL0);
>>>> +
>>>> + if (dev_read_bool(dev, "fsl,permanently-attached"))
>>>> + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
>>>> + else
>>>> + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
>>>> +
>>>> + if (dev_read_bool(dev, "fsl,disable-port-power-control"))
>>>> + value &= ~(USB_CTRL0_PORTPWR_EN);
>>>> + else
>>>> + value |= USB_CTRL0_PORTPWR_EN;
>>>> +
>>>> + writel(value, base + USB_CTRL0);
>>>> +
>>>> + value = readl(base + USB_CTRL1);
>>>> + if (dev_read_bool(dev, "fsl,over-current-active-low"))
>>>> + value |= USB_CTRL1_OC_POLARITY;
>>>> + else
>>>> + value &= ~USB_CTRL1_OC_POLARITY;
>>>> +
>>>> + if (dev_read_bool(dev, "fsl,power-active-low"))
>>>> + value |= USB_CTRL1_PWR_POLARITY;
>>>> + else
>>>> + value &= ~USB_CTRL1_PWR_POLARITY;
>>>> +
>>>> + writel(value, base + USB_CTRL1);
>>>> +
>>>> + unmap_physmem(base, MAP_NOCACHE);
>>>> +}
>>>> +
>>>> +struct dwc3_glue_ops imx8mp_ops = {
>>>> + .glue_configure = dwc3_imx8mp_glue_configure,
>>>> +};
>>>> +
>>>> void dwc3_ti_glue_configure(struct udevice *dev, int index,
>>>> enum usb_dr_mode mode)
>>>> {
>>>> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
>>>> { .compatible = "rockchip,rk3328-dwc3" },
>>>> { .compatible = "rockchip,rk3399-dwc3" },
>>>> { .compatible = "qcom,dwc3" },
>>>> + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
>>>> { .compatible = "fsl,imx8mq-dwc3" },
>>>> { .compatible = "intel,tangier-dwc3" },
>>>> { }
>>>> --
>>>> 2.35.1
>>>>
>>>
>>> Marek,
>>>
>>> Looks like your working on IMX8MP USB support - thanks for that!
>>>
>>> I'm working on bring-up of an IMX8MP board and can test your
>>> power-domain and USB patches but I'm having trouble getting some of
>>> your patches to apply - do you have a repo I can pull from?
>>
>> https://source.denx.de/u-boot/custodians/u-boot-usb/-/commits/imx-8mp
>
> Marek,
>
> Thanks. I've thrown my board patches on top but don't get very far
> with regards to USB due to clk:
> U-Boot 2022.04-rc5-00085-gce6842669a59-dirty (Apr 04 2022 - 11:32:45 -0700)
>
> CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
> CPU: Industrial temperature grade (-40C to 105C) at 38C
> Reset cause: POR
> Model: Gateworks Venice GW74xx i.MX8MP board
> DRAM: 1 GiB
> clk_register: failed to get osc_32k device (parent of usb_root_clk)
> Core: 210 devices, 23 uclasses, devicetree: separate
> WDT: Started watchdog@30280000 with servicing (60s timeout)
> MMC: FSL_SDHC: 0, FSL_SDHC: 2
> Loading Environment from nowhere... OK
> In: serial@30890000
> Out: serial@30890000
> Err: serial@30890000
>
> u-boot=> usb start
> starting USB...
> Bus usb@38100000: Port not available.
> Bus usb@38200000: Port not available.
>
> I see 'clk_register: failed to get osc_32k device (parent of
> usb_root_clk)' above yet clock-osc-32k seems to be there:
[...]
> I've got the following in my config:
> CONFIG_CLK_CCF=y
> CONFIG_CLK_COMPOSITE_CCF=y
> CONFIG_CLK_IMX8MP=y
> ...
> CONFIG_USB_XHCI_DWC3=y
> CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
> CONFIG_USB_DWC3=y
> CONFIG_USB_DWC3_GENERIC=y
> ...
> CONFIG_POWER_DOMAIN=y
> CONFIG_IMX8M_POWER_DOMAIN=y
>
> Any ideas?
"Port not available" means device_probe() returns -ENODEV in usb uclass,
maybe you're still missing some regulator driver or some such ? You'd
have to dig into that.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
2022-04-04 19:11 ` Marek Vasut
@ 2022-04-04 20:15 ` Tim Harvey
2022-04-04 21:00 ` Marek Vasut
0 siblings, 1 reply; 9+ messages in thread
From: Tim Harvey @ 2022-04-04 20:15 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, Angus Ainslie, Bin Meng, Fabio Estevam, Kunihiko Hayashi,
Michal Simek, Peng Fan, Stefano Babic
On Mon, Apr 4, 2022 at 12:11 PM Marek Vasut <marex@denx.de> wrote:
>
> On 4/4/22 20:51, Tim Harvey wrote:
> > On Fri, Apr 1, 2022 at 5:48 PM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 4/1/22 23:28, Tim Harvey wrote:
> >>> On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut <marex@denx.de> wrote:
> >>>>
> >>>> The i.MX8MP glue needs to be configured based on a couple of DT
> >>>> properties, implement .glue_configure callback to parse those DT
> >>>> properties and configure the glue accordingly.
> >>>>
> >>>> Signed-off-by: Marek Vasut <marex@denx.de>
> >>>> Cc: Angus Ainslie <angus@akkea.ca>
> >>>> Cc: Bin Meng <bmeng.cn@gmail.com>
> >>>> Cc: Fabio Estevam <festevam@gmail.com>
> >>>> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> >>>> Cc: Michal Simek <michal.simek@xilinx.com>
> >>>> Cc: Peng Fan <peng.fan@nxp.com>
> >>>> Cc: Stefano Babic <sbabic@denx.de>
> >>>> ---
> >>>> drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
> >>>> 1 file changed, 52 insertions(+)
> >>>>
> >>>> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> >>>> index 7e3814207e4..6cf844cb483 100644
> >>>> --- a/drivers/usb/dwc3/dwc3-generic.c
> >>>> +++ b/drivers/usb/dwc3/dwc3-generic.c
> >>>> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
> >>>> enum usb_dr_mode mode);
> >>>> };
> >>>>
> >>>> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
> >>>> + enum usb_dr_mode mode)
> >>>> +{
> >>>> +/* USB glue registers */
> >>>> +#define USB_CTRL0 0x00
> >>>> +#define USB_CTRL1 0x04
> >>>> +
> >>>> +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
> >>>> +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
> >>>> +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
> >>>> +
> >>>> +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
> >>>> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
> >>>> + fdt_addr_t regs = dev_read_addr_index(dev, 1);
> >>>> + void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
> >>>> + u32 value;
> >>>> +
> >>>> + value = readl(base + USB_CTRL0);
> >>>> +
> >>>> + if (dev_read_bool(dev, "fsl,permanently-attached"))
> >>>> + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> >>>> + else
> >>>> + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> >>>> +
> >>>> + if (dev_read_bool(dev, "fsl,disable-port-power-control"))
> >>>> + value &= ~(USB_CTRL0_PORTPWR_EN);
> >>>> + else
> >>>> + value |= USB_CTRL0_PORTPWR_EN;
> >>>> +
> >>>> + writel(value, base + USB_CTRL0);
> >>>> +
> >>>> + value = readl(base + USB_CTRL1);
> >>>> + if (dev_read_bool(dev, "fsl,over-current-active-low"))
> >>>> + value |= USB_CTRL1_OC_POLARITY;
> >>>> + else
> >>>> + value &= ~USB_CTRL1_OC_POLARITY;
> >>>> +
> >>>> + if (dev_read_bool(dev, "fsl,power-active-low"))
> >>>> + value |= USB_CTRL1_PWR_POLARITY;
> >>>> + else
> >>>> + value &= ~USB_CTRL1_PWR_POLARITY;
> >>>> +
> >>>> + writel(value, base + USB_CTRL1);
> >>>> +
> >>>> + unmap_physmem(base, MAP_NOCACHE);
> >>>> +}
> >>>> +
> >>>> +struct dwc3_glue_ops imx8mp_ops = {
> >>>> + .glue_configure = dwc3_imx8mp_glue_configure,
> >>>> +};
> >>>> +
> >>>> void dwc3_ti_glue_configure(struct udevice *dev, int index,
> >>>> enum usb_dr_mode mode)
> >>>> {
> >>>> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
> >>>> { .compatible = "rockchip,rk3328-dwc3" },
> >>>> { .compatible = "rockchip,rk3399-dwc3" },
> >>>> { .compatible = "qcom,dwc3" },
> >>>> + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
> >>>> { .compatible = "fsl,imx8mq-dwc3" },
> >>>> { .compatible = "intel,tangier-dwc3" },
> >>>> { }
> >>>> --
> >>>> 2.35.1
> >>>>
> >>>
> >>> Marek,
> >>>
> >>> Looks like your working on IMX8MP USB support - thanks for that!
> >>>
> >>> I'm working on bring-up of an IMX8MP board and can test your
> >>> power-domain and USB patches but I'm having trouble getting some of
> >>> your patches to apply - do you have a repo I can pull from?
> >>
> >> https://source.denx.de/u-boot/custodians/u-boot-usb/-/commits/imx-8mp
> >
> > Marek,
> >
> > Thanks. I've thrown my board patches on top but don't get very far
> > with regards to USB due to clk:
> > U-Boot 2022.04-rc5-00085-gce6842669a59-dirty (Apr 04 2022 - 11:32:45 -0700)
> >
> > CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
> > CPU: Industrial temperature grade (-40C to 105C) at 38C
> > Reset cause: POR
> > Model: Gateworks Venice GW74xx i.MX8MP board
> > DRAM: 1 GiB
> > clk_register: failed to get osc_32k device (parent of usb_root_clk)
> > Core: 210 devices, 23 uclasses, devicetree: separate
> > WDT: Started watchdog@30280000 with servicing (60s timeout)
> > MMC: FSL_SDHC: 0, FSL_SDHC: 2
> > Loading Environment from nowhere... OK
> > In: serial@30890000
> > Out: serial@30890000
> > Err: serial@30890000
> >
> > u-boot=> usb start
> > starting USB...
> > Bus usb@38100000: Port not available.
> > Bus usb@38200000: Port not available.
> >
> > I see 'clk_register: failed to get osc_32k device (parent of
> > usb_root_clk)' above yet clock-osc-32k seems to be there:
>
> [...]
>
> > I've got the following in my config:
> > CONFIG_CLK_CCF=y
> > CONFIG_CLK_COMPOSITE_CCF=y
> > CONFIG_CLK_IMX8MP=y
> > ...
> > CONFIG_USB_XHCI_DWC3=y
> > CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
> > CONFIG_USB_DWC3=y
> > CONFIG_USB_DWC3_GENERIC=y
> > ...
> > CONFIG_POWER_DOMAIN=y
> > CONFIG_IMX8M_POWER_DOMAIN=y
> >
> > Any ideas?
>
> "Port not available" means device_probe() returns -ENODEV in usb uclass,
> maybe you're still missing some regulator driver or some such ? You'd
> have to dig into that.
Marek,
Thanks - I was missing CONFIG_IMX8MP_HSIOMIX_BLKCTRL. IMX8MP USB is
working now. I will respond to the individual patches you have.
Best Regards,
Tim
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
2022-04-04 20:15 ` Tim Harvey
@ 2022-04-04 21:00 ` Marek Vasut
0 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2022-04-04 21:00 UTC (permalink / raw)
To: Tim Harvey
Cc: u-boot, Angus Ainslie, Bin Meng, Fabio Estevam, Kunihiko Hayashi,
Michal Simek, Peng Fan, Stefano Babic
On 4/4/22 22:15, Tim Harvey wrote:
> On Mon, Apr 4, 2022 at 12:11 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 4/4/22 20:51, Tim Harvey wrote:
>>> On Fri, Apr 1, 2022 at 5:48 PM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 4/1/22 23:28, Tim Harvey wrote:
>>>>> On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut <marex@denx.de> wrote:
>>>>>>
>>>>>> The i.MX8MP glue needs to be configured based on a couple of DT
>>>>>> properties, implement .glue_configure callback to parse those DT
>>>>>> properties and configure the glue accordingly.
>>>>>>
>>>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>>>> Cc: Angus Ainslie <angus@akkea.ca>
>>>>>> Cc: Bin Meng <bmeng.cn@gmail.com>
>>>>>> Cc: Fabio Estevam <festevam@gmail.com>
>>>>>> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
>>>>>> Cc: Michal Simek <michal.simek@xilinx.com>
>>>>>> Cc: Peng Fan <peng.fan@nxp.com>
>>>>>> Cc: Stefano Babic <sbabic@denx.de>
>>>>>> ---
>>>>>> drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
>>>>>> 1 file changed, 52 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
>>>>>> index 7e3814207e4..6cf844cb483 100644
>>>>>> --- a/drivers/usb/dwc3/dwc3-generic.c
>>>>>> +++ b/drivers/usb/dwc3/dwc3-generic.c
>>>>>> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
>>>>>> enum usb_dr_mode mode);
>>>>>> };
>>>>>>
>>>>>> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
>>>>>> + enum usb_dr_mode mode)
>>>>>> +{
>>>>>> +/* USB glue registers */
>>>>>> +#define USB_CTRL0 0x00
>>>>>> +#define USB_CTRL1 0x04
>>>>>> +
>>>>>> +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
>>>>>> +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
>>>>>> +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
>>>>>> +
>>>>>> +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
>>>>>> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
>>>>>> + fdt_addr_t regs = dev_read_addr_index(dev, 1);
>>>>>> + void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
>>>>>> + u32 value;
>>>>>> +
>>>>>> + value = readl(base + USB_CTRL0);
>>>>>> +
>>>>>> + if (dev_read_bool(dev, "fsl,permanently-attached"))
>>>>>> + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
>>>>>> + else
>>>>>> + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
>>>>>> +
>>>>>> + if (dev_read_bool(dev, "fsl,disable-port-power-control"))
>>>>>> + value &= ~(USB_CTRL0_PORTPWR_EN);
>>>>>> + else
>>>>>> + value |= USB_CTRL0_PORTPWR_EN;
>>>>>> +
>>>>>> + writel(value, base + USB_CTRL0);
>>>>>> +
>>>>>> + value = readl(base + USB_CTRL1);
>>>>>> + if (dev_read_bool(dev, "fsl,over-current-active-low"))
>>>>>> + value |= USB_CTRL1_OC_POLARITY;
>>>>>> + else
>>>>>> + value &= ~USB_CTRL1_OC_POLARITY;
>>>>>> +
>>>>>> + if (dev_read_bool(dev, "fsl,power-active-low"))
>>>>>> + value |= USB_CTRL1_PWR_POLARITY;
>>>>>> + else
>>>>>> + value &= ~USB_CTRL1_PWR_POLARITY;
>>>>>> +
>>>>>> + writel(value, base + USB_CTRL1);
>>>>>> +
>>>>>> + unmap_physmem(base, MAP_NOCACHE);
>>>>>> +}
>>>>>> +
>>>>>> +struct dwc3_glue_ops imx8mp_ops = {
>>>>>> + .glue_configure = dwc3_imx8mp_glue_configure,
>>>>>> +};
>>>>>> +
>>>>>> void dwc3_ti_glue_configure(struct udevice *dev, int index,
>>>>>> enum usb_dr_mode mode)
>>>>>> {
>>>>>> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
>>>>>> { .compatible = "rockchip,rk3328-dwc3" },
>>>>>> { .compatible = "rockchip,rk3399-dwc3" },
>>>>>> { .compatible = "qcom,dwc3" },
>>>>>> + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
>>>>>> { .compatible = "fsl,imx8mq-dwc3" },
>>>>>> { .compatible = "intel,tangier-dwc3" },
>>>>>> { }
>>>>>> --
>>>>>> 2.35.1
>>>>>>
>>>>>
>>>>> Marek,
>>>>>
>>>>> Looks like your working on IMX8MP USB support - thanks for that!
>>>>>
>>>>> I'm working on bring-up of an IMX8MP board and can test your
>>>>> power-domain and USB patches but I'm having trouble getting some of
>>>>> your patches to apply - do you have a repo I can pull from?
>>>>
>>>> https://source.denx.de/u-boot/custodians/u-boot-usb/-/commits/imx-8mp
>>>
>>> Marek,
>>>
>>> Thanks. I've thrown my board patches on top but don't get very far
>>> with regards to USB due to clk:
>>> U-Boot 2022.04-rc5-00085-gce6842669a59-dirty (Apr 04 2022 - 11:32:45 -0700)
>>>
>>> CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
>>> CPU: Industrial temperature grade (-40C to 105C) at 38C
>>> Reset cause: POR
>>> Model: Gateworks Venice GW74xx i.MX8MP board
>>> DRAM: 1 GiB
>>> clk_register: failed to get osc_32k device (parent of usb_root_clk)
>>> Core: 210 devices, 23 uclasses, devicetree: separate
>>> WDT: Started watchdog@30280000 with servicing (60s timeout)
>>> MMC: FSL_SDHC: 0, FSL_SDHC: 2
>>> Loading Environment from nowhere... OK
>>> In: serial@30890000
>>> Out: serial@30890000
>>> Err: serial@30890000
>>>
>>> u-boot=> usb start
>>> starting USB...
>>> Bus usb@38100000: Port not available.
>>> Bus usb@38200000: Port not available.
>>>
>>> I see 'clk_register: failed to get osc_32k device (parent of
>>> usb_root_clk)' above yet clock-osc-32k seems to be there:
>>
>> [...]
>>
>>> I've got the following in my config:
>>> CONFIG_CLK_CCF=y
>>> CONFIG_CLK_COMPOSITE_CCF=y
>>> CONFIG_CLK_IMX8MP=y
>>> ...
>>> CONFIG_USB_XHCI_DWC3=y
>>> CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
>>> CONFIG_USB_DWC3=y
>>> CONFIG_USB_DWC3_GENERIC=y
>>> ...
>>> CONFIG_POWER_DOMAIN=y
>>> CONFIG_IMX8M_POWER_DOMAIN=y
>>>
>>> Any ideas?
>>
>> "Port not available" means device_probe() returns -ENODEV in usb uclass,
>> maybe you're still missing some regulator driver or some such ? You'd
>> have to dig into that.
>
> Marek,
>
> Thanks - I was missing CONFIG_IMX8MP_HSIOMIX_BLKCTRL. IMX8MP USB is
> working now. I will respond to the individual patches you have.
Nice.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP
2022-04-01 14:31 ` [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP Marek Vasut
2022-04-01 21:28 ` Tim Harvey
@ 2022-04-07 22:22 ` Tim Harvey
1 sibling, 0 replies; 9+ messages in thread
From: Tim Harvey @ 2022-04-07 22:22 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, Angus Ainslie, Bin Meng, Fabio Estevam, Kunihiko Hayashi,
Michal Simek, Peng Fan, Stefano Babic
On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut <marex@denx.de> wrote:
>
> The i.MX8MP glue needs to be configured based on a couple of DT
> properties, implement .glue_configure callback to parse those DT
> properties and configure the glue accordingly.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Angus Ainslie <angus@akkea.ca>
> Cc: Bin Meng <bmeng.cn@gmail.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Cc: Michal Simek <michal.simek@xilinx.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> index 7e3814207e4..6cf844cb483 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
> enum usb_dr_mode mode);
> };
>
> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
> + enum usb_dr_mode mode)
> +{
> +/* USB glue registers */
> +#define USB_CTRL0 0x00
> +#define USB_CTRL1 0x04
> +
> +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
> +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
> +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
> +
> +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
> + fdt_addr_t regs = dev_read_addr_index(dev, 1);
> + void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
> + u32 value;
> +
> + value = readl(base + USB_CTRL0);
> +
> + if (dev_read_bool(dev, "fsl,permanently-attached"))
> + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> + else
> + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> +
> + if (dev_read_bool(dev, "fsl,disable-port-power-control"))
> + value &= ~(USB_CTRL0_PORTPWR_EN);
> + else
> + value |= USB_CTRL0_PORTPWR_EN;
> +
> + writel(value, base + USB_CTRL0);
> +
> + value = readl(base + USB_CTRL1);
> + if (dev_read_bool(dev, "fsl,over-current-active-low"))
> + value |= USB_CTRL1_OC_POLARITY;
> + else
> + value &= ~USB_CTRL1_OC_POLARITY;
> +
> + if (dev_read_bool(dev, "fsl,power-active-low"))
> + value |= USB_CTRL1_PWR_POLARITY;
> + else
> + value &= ~USB_CTRL1_PWR_POLARITY;
> +
> + writel(value, base + USB_CTRL1);
> +
> + unmap_physmem(base, MAP_NOCACHE);
> +}
> +
> +struct dwc3_glue_ops imx8mp_ops = {
> + .glue_configure = dwc3_imx8mp_glue_configure,
> +};
> +
> void dwc3_ti_glue_configure(struct udevice *dev, int index,
> enum usb_dr_mode mode)
> {
> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
> { .compatible = "rockchip,rk3328-dwc3" },
> { .compatible = "rockchip,rk3399-dwc3" },
> { .compatible = "qcom,dwc3" },
> + { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
> { .compatible = "fsl,imx8mq-dwc3" },
> { .compatible = "intel,tangier-dwc3" },
> { }
> --
> 2.35.1
>
Thanks for working on this!
This helps get DWC3 USB working on IMX8MP.
For both patches in this series:
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
Best Regards,
Tim
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-04-07 22:22 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-01 14:31 [PATCH 1/2] usb: dwc3: Rename .select_dr_mode to .glue_configure Marek Vasut
2022-04-01 14:31 ` [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP Marek Vasut
2022-04-01 21:28 ` Tim Harvey
2022-04-02 0:48 ` Marek Vasut
2022-04-04 18:51 ` Tim Harvey
2022-04-04 19:11 ` Marek Vasut
2022-04-04 20:15 ` Tim Harvey
2022-04-04 21:00 ` Marek Vasut
2022-04-07 22:22 ` Tim Harvey
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