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From: Mike Leach <mike.leach@linaro.org>
To: Tanmay Jagdale <tanmay@marvell.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>,
	"Suzuki K. Poulose" <suzuki.poulose@arm.com>,
	Leo Yan <leo.yan@linaro.org>, Rob Herring <robh+dt@kernel.org>,
	Coresight ML <coresight@lists.linaro.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	devicetree@vger.kernel.org, Al Grant <al.grant@arm.com>,
	Sunil Kovvuri Goutham <sgoutham@marvell.com>,
	Linu Cherian <lcherian@marvell.com>,
	Bharat Bhushan <bbhushan2@marvell.com>
Subject: Re: [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC
Date: Thu, 2 Sep 2021 17:27:31 +0100	[thread overview]
Message-ID: <CAJ9a7Vhh_0_D9_59At38D-okpLkARWmTpq=U6K=eRTEzoOEhMw@mail.gmail.com> (raw)
In-Reply-To: <20210901131049.1365367-2-tanmay@marvell.com>

On Wed, 1 Sept 2021 at 14:12, Tanmay Jagdale <tanmay@marvell.com> wrote:
>
> Add "arm,max-burst-size" optional property for TMC ETR.
> If specified, this value indicates the maximum burst size
> that can be initiated by TMC on the AXI bus.
>
> Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
> ---
>  Documentation/devicetree/bindings/arm/coresight.txt | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 7f9c1ca87487..7971f8dba2ee 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -127,6 +127,11 @@ its hardware characteristcs.
>         * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
>           use the SG mode on this system.
>
> +       * arm,max-burst-size: The maximum burst size initiated by TMC on the
> +         AXI master interface. The burst size can be in the range [0..15],
> +         the setting supports one data transfer per burst upto a maximum of
> +         16 data transfers per burst.
> +
>  * Optional property for CATU :
>         * interrupts : Exactly one SPI may be listed for reporting the address
>           error
> --
> 2.25.1
>

Reviewed-by: Mike Leach <mike.leach@linaro.org>

-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

WARNING: multiple messages have this Message-ID (diff)
From: Mike Leach <mike.leach@linaro.org>
To: Tanmay Jagdale <tanmay@marvell.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>,
	 "Suzuki K. Poulose" <suzuki.poulose@arm.com>,
	Leo Yan <leo.yan@linaro.org>,  Rob Herring <robh+dt@kernel.org>,
	Coresight ML <coresight@lists.linaro.org>,
	 linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	devicetree@vger.kernel.org,  Al Grant <al.grant@arm.com>,
	Sunil Kovvuri Goutham <sgoutham@marvell.com>,
	 Linu Cherian <lcherian@marvell.com>,
	Bharat Bhushan <bbhushan2@marvell.com>
Subject: Re: [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC
Date: Thu, 2 Sep 2021 17:27:31 +0100	[thread overview]
Message-ID: <CAJ9a7Vhh_0_D9_59At38D-okpLkARWmTpq=U6K=eRTEzoOEhMw@mail.gmail.com> (raw)
In-Reply-To: <20210901131049.1365367-2-tanmay@marvell.com>

On Wed, 1 Sept 2021 at 14:12, Tanmay Jagdale <tanmay@marvell.com> wrote:
>
> Add "arm,max-burst-size" optional property for TMC ETR.
> If specified, this value indicates the maximum burst size
> that can be initiated by TMC on the AXI bus.
>
> Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
> ---
>  Documentation/devicetree/bindings/arm/coresight.txt | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 7f9c1ca87487..7971f8dba2ee 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -127,6 +127,11 @@ its hardware characteristcs.
>         * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
>           use the SG mode on this system.
>
> +       * arm,max-burst-size: The maximum burst size initiated by TMC on the
> +         AXI master interface. The burst size can be in the range [0..15],
> +         the setting supports one data transfer per burst upto a maximum of
> +         16 data transfers per burst.
> +
>  * Optional property for CATU :
>         * interrupts : Exactly one SPI may be listed for reporting the address
>           error
> --
> 2.25.1
>

Reviewed-by: Mike Leach <mike.leach@linaro.org>

-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-09-02 16:27 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-01 13:10 [PATCH 0/2] coresight: tmc: Add support to configure AXI burst size Tanmay Jagdale
2021-09-01 13:10 ` Tanmay Jagdale
2021-09-01 13:10 ` [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC Tanmay Jagdale
2021-09-01 13:10   ` Tanmay Jagdale
2021-09-02 16:27   ` Mike Leach [this message]
2021-09-02 16:27     ` Mike Leach
2021-09-03 19:54   ` Rob Herring
2021-09-03 19:54     ` Rob Herring
2021-09-01 13:10 ` [PATCH 2/2] coresight: tmc: Configure AXI write burst size Tanmay Jagdale
2021-09-01 13:10   ` Tanmay Jagdale
2021-09-02 16:29   ` Mike Leach
2021-09-02 16:29     ` Mike Leach
2021-09-02 16:32 ` [PATCH 0/2] coresight: tmc: Add support to configure AXI " Mike Leach
2021-09-02 16:32   ` Mike Leach
2021-09-07 17:17 ` Mathieu Poirier
2021-09-07 17:17   ` Mathieu Poirier

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