From: Guo Ren <guoren@kernel.org>
To: Greentime Hu <greentime.hu@sifive.com>
Cc: Guo Ren <guoren@linux.alibaba.com>,
Vincent Chen <vincent.chen@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Oleg Nesterov <oleg@redhat.com>
Subject: Re: [RFC PATCH v4 05/13] riscv: Add new csr defines related to vector extension
Date: Mon, 1 Jun 2020 17:03:47 +0800 [thread overview]
Message-ID: <CAJF2gTQ=S+tbxVOoL3w3DjQ1H0UP6L7F++i-OAcaeY+QNmd=mw@mail.gmail.com> (raw)
In-Reply-To: <fe966314eae51a5089033f7186ac86c39719e0a0.1590474856.git.greentime.hu@sifive.com>
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu <greentime.hu@sifive.com> wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Follow the riscv vector spec to add new csr number.
>
> [greentime.hu@sifive.com: update the defined value based on new spec and
> remove unused ones]
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> ---
> arch/riscv/include/asm/csr.h | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 8e18d2c64399..cc13626c4bbe 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -24,6 +24,12 @@
> #define SR_FS_CLEAN _AC(0x00004000, UL)
> #define SR_FS_DIRTY _AC(0x00006000, UL)
>
> +#define SR_VS _AC(0x00000600, UL) /* Vector Status */
> +#define SR_VS_OFF _AC(0x00000000, UL)
> +#define SR_VS_INITIAL _AC(0x00000200, UL)
> +#define SR_VS_CLEAN _AC(0x00000400, UL)
> +#define SR_VS_DIRTY _AC(0x00000600, UL)
> +
> #define SR_XS _AC(0x00018000, UL) /* Extension Status */
> #define SR_XS_OFF _AC(0x00000000, UL)
> #define SR_XS_INITIAL _AC(0x00008000, UL)
> @@ -31,9 +37,9 @@
> #define SR_XS_DIRTY _AC(0x00018000, UL)
>
> #ifndef CONFIG_64BIT
> -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
> +#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */
> #else
> -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
> +#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
> #endif
>
> /* SATP flags */
> @@ -114,6 +120,12 @@
> #define CSR_PMPADDR0 0x3b0
> #define CSR_MHARTID 0xf14
>
> +#define CSR_VSTART 0x8
> +#define CSR_VCSR 0xf
> +#define CSR_VL 0xc20
> +#define CSR_VTYPE 0xc21
> +#define CSR_VLENB 0xc22
> +
> #ifdef CONFIG_RISCV_M_MODE
> # define CSR_STATUS CSR_MSTATUS
> # define CSR_IE CSR_MIE
> --
> 2.26.2
>
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org>
To: Greentime Hu <greentime.hu@sifive.com>
Cc: Guo Ren <guoren@linux.alibaba.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Oleg Nesterov <oleg@redhat.com>,
Vincent Chen <vincent.chen@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv <linux-riscv@lists.infradead.org>
Subject: Re: [RFC PATCH v4 05/13] riscv: Add new csr defines related to vector extension
Date: Mon, 1 Jun 2020 17:03:47 +0800 [thread overview]
Message-ID: <CAJF2gTQ=S+tbxVOoL3w3DjQ1H0UP6L7F++i-OAcaeY+QNmd=mw@mail.gmail.com> (raw)
In-Reply-To: <fe966314eae51a5089033f7186ac86c39719e0a0.1590474856.git.greentime.hu@sifive.com>
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu <greentime.hu@sifive.com> wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Follow the riscv vector spec to add new csr number.
>
> [greentime.hu@sifive.com: update the defined value based on new spec and
> remove unused ones]
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> ---
> arch/riscv/include/asm/csr.h | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 8e18d2c64399..cc13626c4bbe 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -24,6 +24,12 @@
> #define SR_FS_CLEAN _AC(0x00004000, UL)
> #define SR_FS_DIRTY _AC(0x00006000, UL)
>
> +#define SR_VS _AC(0x00000600, UL) /* Vector Status */
> +#define SR_VS_OFF _AC(0x00000000, UL)
> +#define SR_VS_INITIAL _AC(0x00000200, UL)
> +#define SR_VS_CLEAN _AC(0x00000400, UL)
> +#define SR_VS_DIRTY _AC(0x00000600, UL)
> +
> #define SR_XS _AC(0x00018000, UL) /* Extension Status */
> #define SR_XS_OFF _AC(0x00000000, UL)
> #define SR_XS_INITIAL _AC(0x00008000, UL)
> @@ -31,9 +37,9 @@
> #define SR_XS_DIRTY _AC(0x00018000, UL)
>
> #ifndef CONFIG_64BIT
> -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
> +#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */
> #else
> -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
> +#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
> #endif
>
> /* SATP flags */
> @@ -114,6 +120,12 @@
> #define CSR_PMPADDR0 0x3b0
> #define CSR_MHARTID 0xf14
>
> +#define CSR_VSTART 0x8
> +#define CSR_VCSR 0xf
> +#define CSR_VL 0xc20
> +#define CSR_VTYPE 0xc21
> +#define CSR_VLENB 0xc22
> +
> #ifdef CONFIG_RISCV_M_MODE
> # define CSR_STATUS CSR_MSTATUS
> # define CSR_IE CSR_MIE
> --
> 2.26.2
>
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
next prev parent reply other threads:[~2020-06-01 9:04 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-26 7:02 [RFC PATCH v4 00/13] riscv: Add vector ISA support Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 01/13] ptrace: Use regset_size() for dynamic regset size Greentime Hu
2020-05-26 14:00 ` Oleg Nesterov
2020-05-26 14:00 ` Oleg Nesterov
2020-05-27 6:34 ` Greentime Hu
2020-05-27 6:34 ` Greentime Hu
2020-05-27 11:31 ` Oleg Nesterov
2020-05-27 11:31 ` Oleg Nesterov
2020-05-26 7:02 ` [RFC PATCH v4 02/13] riscv: Separate patch for cflags and aflags Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 03/13] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 04/13] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 05/13] riscv: Add new csr defines related to vector extension Greentime Hu
2020-05-31 1:56 ` Guo Ren
2020-05-31 1:56 ` Guo Ren
2020-06-01 8:15 ` Greentime Hu
2020-06-01 8:15 ` Greentime Hu
2020-06-01 8:59 ` Guo Ren
2020-06-01 8:59 ` Guo Ren
2020-06-01 9:03 ` Guo Ren [this message]
2020-06-01 9:03 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 06/13] riscv: Add vector feature to compile Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 07/13] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-05-31 0:58 ` Guo Ren
2020-05-31 0:58 ` Guo Ren
2020-06-01 8:07 ` Greentime Hu
2020-06-01 8:07 ` Greentime Hu
2020-06-01 9:13 ` Guo Ren
2020-06-01 9:13 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 08/13] riscv: Reset vector register Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 09/13] riscv: Add vector struct and assembler definitions Greentime Hu
2020-06-01 9:12 ` Guo Ren
2020-06-01 9:12 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 10/13] riscv: Add task switch support for vector Greentime Hu
2020-05-31 15:29 ` Guo Ren
2020-05-31 15:29 ` Guo Ren
2020-05-31 16:08 ` Guo Ren
2020-05-31 16:08 ` Guo Ren
2020-06-01 9:12 ` Guo Ren
2020-06-01 9:12 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 11/13] riscv: Add ptrace vector support Greentime Hu
2020-06-01 9:14 ` Guo Ren
2020-06-01 9:14 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 12/13] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-05-31 15:28 ` Guo Ren
2020-05-31 15:28 ` Guo Ren
2020-06-01 9:13 ` Guo Ren
2020-06-01 9:13 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 13/13] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2020-05-31 15:52 ` [RFC PATCH v4 00/13] riscv: Add vector ISA support Guo Ren
2020-05-31 15:52 ` Guo Ren
2020-06-02 2:21 ` Greentime Hu
2020-06-02 2:21 ` Greentime Hu
2020-06-02 3:08 ` Guo Ren
2020-06-02 3:08 ` Guo Ren
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