From: Guo Ren <guoren@kernel.org> To: Peter Zijlstra <peterz@infradead.org> Cc: linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-csky@vger.kernel.org, linux-arch <linux-arch@vger.kernel.org>, Guo Ren <guoren@linux.alibaba.com>, Will Deacon <will@kernel.org>, Ingo Molnar <mingo@redhat.com>, Waiman Long <longman@redhat.com>, Arnd Bergmann <arnd@arndb.de>, Anup Patel <anup@brainfault.org> Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 Date: Mon, 29 Mar 2021 20:01:41 +0800 [thread overview] Message-ID: <CAJF2gTQUe237NY-kh+4_Yk4DTFJmA5_xgNQ5+BMpFZpUDUEYdw@mail.gmail.com> (raw) In-Reply-To: <YGG5c4QGq6q+lKZI@hirez.programming.kicks-ass.net> On Mon, Mar 29, 2021 at 7:26 PM Peter Zijlstra <peterz@infradead.org> wrote: > > On Mon, Mar 29, 2021 at 07:19:29PM +0800, Guo Ren wrote: > > On Mon, Mar 29, 2021 at 3:50 PM Peter Zijlstra <peterz@infradead.org> wrote: > > > > > > On Sat, Mar 27, 2021 at 06:06:38PM +0000, guoren@kernel.org wrote: > > > > From: Guo Ren <guoren@linux.alibaba.com> > > > > > > > > Some architectures don't have sub-word swap atomic instruction, > > > > they only have the full word's one. > > > > > > > > The sub-word swap only improve the performance when: > > > > NR_CPUS < 16K > > > > * 0- 7: locked byte > > > > * 8: pending > > > > * 9-15: not used > > > > * 16-17: tail index > > > > * 18-31: tail cpu (+1) > > > > > > > > The 9-15 bits are wasted to use xchg16 in xchg_tail. > > > > > > > > Please let architecture select xchg16/xchg32 to implement > > > > xchg_tail. > > > > > > So I really don't like this, this pushes complexity into the generic > > > code for something that's really not needed. > > > > > > Lots of RISC already implement sub-word atomics using word ll/sc. > > > Obviously they're not sharing code like they should be :/ See for > > > example arch/mips/kernel/cmpxchg.c. > > I see, we've done two versions of this: > > - Using cmpxchg codes from MIPS by Michael > > - Re-write with assembly codes by Guo > > > > But using the full-word atomic xchg instructions implement xchg16 has > > the semantic risk for atomic operations. > > What? -ENOPARSE u32 a = 0x55aa66bb; u16 *ptr = &a; CPU0 CPU1 ========= ========= xchg16(ptr, new) while(1) WRITE_ONCE(*(ptr + 1), x); When we use lr.w/sc.w implement xchg16, it'll cause CPU0 deadlock. > > > > Also, I really do think doing ticket locks first is a far more sensible > > > step. > > NACK by Anup > > Who's he when he's not sending NAKs ? We've talked before: https://lore.kernel.org/linux-riscv/CAAhSdy1JHLUFwu7RuCaQ+RUWRBks2KsDva7EpRt8--4ZfofSUQ@mail.gmail.com/T/#t -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org> To: Peter Zijlstra <peterz@infradead.org> Cc: linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-csky@vger.kernel.org, linux-arch <linux-arch@vger.kernel.org>, Guo Ren <guoren@linux.alibaba.com>, Will Deacon <will@kernel.org>, Ingo Molnar <mingo@redhat.com>, Waiman Long <longman@redhat.com>, Arnd Bergmann <arnd@arndb.de>, Anup Patel <anup@brainfault.org> Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 Date: Mon, 29 Mar 2021 20:01:41 +0800 [thread overview] Message-ID: <CAJF2gTQUe237NY-kh+4_Yk4DTFJmA5_xgNQ5+BMpFZpUDUEYdw@mail.gmail.com> (raw) In-Reply-To: <YGG5c4QGq6q+lKZI@hirez.programming.kicks-ass.net> On Mon, Mar 29, 2021 at 7:26 PM Peter Zijlstra <peterz@infradead.org> wrote: > > On Mon, Mar 29, 2021 at 07:19:29PM +0800, Guo Ren wrote: > > On Mon, Mar 29, 2021 at 3:50 PM Peter Zijlstra <peterz@infradead.org> wrote: > > > > > > On Sat, Mar 27, 2021 at 06:06:38PM +0000, guoren@kernel.org wrote: > > > > From: Guo Ren <guoren@linux.alibaba.com> > > > > > > > > Some architectures don't have sub-word swap atomic instruction, > > > > they only have the full word's one. > > > > > > > > The sub-word swap only improve the performance when: > > > > NR_CPUS < 16K > > > > * 0- 7: locked byte > > > > * 8: pending > > > > * 9-15: not used > > > > * 16-17: tail index > > > > * 18-31: tail cpu (+1) > > > > > > > > The 9-15 bits are wasted to use xchg16 in xchg_tail. > > > > > > > > Please let architecture select xchg16/xchg32 to implement > > > > xchg_tail. > > > > > > So I really don't like this, this pushes complexity into the generic > > > code for something that's really not needed. > > > > > > Lots of RISC already implement sub-word atomics using word ll/sc. > > > Obviously they're not sharing code like they should be :/ See for > > > example arch/mips/kernel/cmpxchg.c. > > I see, we've done two versions of this: > > - Using cmpxchg codes from MIPS by Michael > > - Re-write with assembly codes by Guo > > > > But using the full-word atomic xchg instructions implement xchg16 has > > the semantic risk for atomic operations. > > What? -ENOPARSE u32 a = 0x55aa66bb; u16 *ptr = &a; CPU0 CPU1 ========= ========= xchg16(ptr, new) while(1) WRITE_ONCE(*(ptr + 1), x); When we use lr.w/sc.w implement xchg16, it'll cause CPU0 deadlock. > > > > Also, I really do think doing ticket locks first is a far more sensible > > > step. > > NACK by Anup > > Who's he when he's not sending NAKs ? We've talked before: https://lore.kernel.org/linux-riscv/CAAhSdy1JHLUFwu7RuCaQ+RUWRBks2KsDva7EpRt8--4ZfofSUQ@mail.gmail.com/T/#t -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-03-29 12:02 UTC|newest] Thread overview: 126+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-27 18:06 [PATCH v4 0/4] riscv: Add qspinlock/qrwlock guoren 2021-03-27 18:06 ` guoren 2021-03-27 18:06 ` [PATCH v4 1/4] riscv: cmpxchg.h: Cleanup unused code guoren 2021-03-27 18:06 ` guoren 2021-03-27 18:06 ` [PATCH v4 2/4] riscv: cmpxchg.h: Merge macros guoren 2021-03-27 18:06 ` guoren 2021-03-27 21:25 ` Arnd Bergmann 2021-03-27 21:25 ` Arnd Bergmann 2021-03-28 1:50 ` Guo Ren 2021-03-28 1:50 ` Guo Ren 2021-03-27 18:06 ` [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren 2021-03-27 18:06 ` guoren 2021-03-27 18:43 ` Waiman Long 2021-03-27 18:43 ` Waiman Long 2021-03-28 1:48 ` Guo Ren 2021-03-28 1:48 ` Guo Ren 2021-03-29 7:50 ` Peter Zijlstra 2021-03-29 7:50 ` Peter Zijlstra 2021-03-29 9:41 ` Arnd Bergmann 2021-03-29 9:41 ` Arnd Bergmann 2021-03-29 11:16 ` Peter Zijlstra 2021-03-29 11:16 ` Peter Zijlstra 2021-03-29 11:29 ` Peter Zijlstra 2021-03-29 11:29 ` Peter Zijlstra 2021-03-29 12:52 ` Guo Ren 2021-03-29 12:52 ` Guo Ren 2021-03-29 13:56 ` Arnd Bergmann 2021-03-29 13:56 ` Arnd Bergmann 2021-03-30 2:26 ` Guo Ren 2021-03-30 2:26 ` Guo Ren 2021-03-30 5:51 ` Anup Patel 2021-03-30 5:51 ` Anup Patel 2021-03-30 6:26 ` Guo Ren 2021-03-30 6:26 ` Guo Ren 2021-03-30 7:11 ` Arnd Bergmann 2021-03-30 7:11 ` Arnd Bergmann 2021-03-31 4:18 ` Guo Ren 2021-03-31 4:18 ` Guo Ren 2021-03-31 5:33 ` Paul Campbell 2021-03-31 5:33 ` Paul Campbell 2021-04-05 16:12 ` Guo Ren 2021-04-05 16:12 ` Guo Ren 2021-03-31 6:44 ` Guo Ren 2021-03-31 6:44 ` Guo Ren 2021-03-31 7:12 ` Arnd Bergmann 2021-03-31 7:12 ` Arnd Bergmann 2021-03-29 11:19 ` Guo Ren 2021-03-29 11:19 ` Guo Ren 2021-03-29 11:26 ` Peter Zijlstra 2021-03-29 11:26 ` Peter Zijlstra 2021-03-29 12:01 ` Guo Ren [this message] 2021-03-29 12:01 ` Guo Ren 2021-03-29 12:49 ` Peter Zijlstra 2021-03-29 12:49 ` Peter Zijlstra 2021-03-30 3:13 ` Guo Ren 2021-03-30 3:13 ` Guo Ren 2021-03-30 4:54 ` Anup Patel 2021-03-30 4:54 ` Anup Patel 2021-03-30 6:27 ` Guo Ren 2021-03-30 6:27 ` Guo Ren 2021-03-30 8:31 ` David Laight 2021-03-30 8:31 ` David Laight 2021-03-30 14:09 ` Waiman Long 2021-03-30 14:09 ` Waiman Long 2021-03-31 14:47 ` Guo Ren 2021-03-31 14:47 ` Guo Ren 2021-04-05 16:45 ` Guo Ren 2021-04-05 16:45 ` Guo Ren 2021-03-30 16:08 ` Peter Zijlstra 2021-03-30 16:08 ` Peter Zijlstra 2021-03-30 22:35 ` Stafford Horne 2021-03-30 22:35 ` Stafford Horne 2021-03-31 7:23 ` Arnd Bergmann 2021-03-31 7:23 ` Arnd Bergmann 2021-03-31 12:31 ` Stafford Horne 2021-03-31 12:31 ` Stafford Horne 2021-03-31 15:10 ` Guo Ren 2021-03-31 15:10 ` Guo Ren 2021-04-06 8:51 ` Stafford Horne 2021-04-06 8:51 ` Stafford Horne 2021-04-06 3:50 ` Guo Ren 2021-04-06 3:50 ` Guo Ren 2021-04-06 8:56 ` Stafford Horne 2021-04-06 8:56 ` Stafford Horne 2021-04-07 8:42 ` Arnd Bergmann 2021-04-07 8:42 ` Arnd Bergmann 2021-04-07 11:36 ` Peter Zijlstra 2021-04-07 11:36 ` Peter Zijlstra 2021-04-07 11:57 ` Arnd Bergmann 2021-04-07 11:57 ` Arnd Bergmann 2021-04-07 12:02 ` Peter Zijlstra 2021-04-07 12:02 ` Peter Zijlstra 2021-04-05 16:40 ` Guo Ren 2021-04-05 16:40 ` Guo Ren 2021-03-31 15:22 ` Guo Ren 2021-03-31 15:22 ` Guo Ren 2021-04-06 7:15 ` Peter Zijlstra 2021-04-06 7:15 ` Peter Zijlstra 2021-04-07 9:42 ` Christoph Hellwig 2021-04-07 9:42 ` Christoph Hellwig 2021-04-07 14:29 ` Christoph Müllner 2021-04-07 14:29 ` Christoph Müllner 2021-04-07 14:34 ` Christoph Hellwig 2021-04-07 14:34 ` Christoph Hellwig 2021-04-07 15:51 ` Peter Zijlstra 2021-04-07 15:51 ` Peter Zijlstra 2021-04-07 16:44 ` Peter Zijlstra 2021-04-07 16:44 ` Peter Zijlstra 2021-04-07 15:52 ` Peter Zijlstra 2021-04-07 15:52 ` Peter Zijlstra 2021-04-07 16:54 ` Peter Zijlstra 2021-04-07 16:54 ` Peter Zijlstra 2021-04-07 16:00 ` Peter Zijlstra 2021-04-07 16:00 ` Peter Zijlstra 2021-04-07 19:50 ` Christoph Müllner 2021-04-07 19:50 ` Christoph Müllner 2021-04-06 17:24 ` Boqun Feng 2021-04-06 17:24 ` Boqun Feng 2021-04-07 9:26 ` Peter Zijlstra 2021-04-07 9:26 ` Peter Zijlstra 2021-03-29 12:13 ` Anup Patel 2021-03-29 12:13 ` Anup Patel 2021-03-29 12:54 ` Peter Zijlstra 2021-03-29 12:54 ` Peter Zijlstra 2021-03-27 18:06 ` [PATCH v4 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren 2021-03-27 18:06 ` guoren
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