* [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs
@ 2021-09-24 6:12 Deepak Sharma
2021-09-24 16:48 ` Rafael J. Wysocki
0 siblings, 1 reply; 5+ messages in thread
From: Deepak Sharma @ 2021-09-24 6:12 UTC (permalink / raw)
To: rafael, len.brown, pavel, tglx, mingo, bp
Cc: x86, linux-kernel, linux-pm, Deepak Sharma
All Zen or newer CPU which support C3 shares cache. Its not necessary to
flush the caches in software before entering C3. This will cause drop in
performance for the cores which share some caches. ARB_DIS is not used
with current AMD C state implementation. So set related flags correctly.
Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
---
arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 7de599eba7f0..7945eae5b315 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
*/
flags->bm_control = 0;
}
+ if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) {
+ /*
+ * For all AMD Zen or newer CPUs that support C3, caches
+ * should not be flushed by software while entering C3
+ * type state. Set bm->check to 1 so that kernel doesn't
+ * need to execute cache flush operation.
+ */
+ flags->bm_check = 1;
+ /*
+ * In current AMD C state implementation ARB_DIS is no longer
+ * used. So set bm_control to zero to indicate ARB_DIS is not
+ * required while entering C3 type state.
+ */
+ flags->bm_control = 0;
+ }
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs
2021-09-24 6:12 [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs Deepak Sharma
@ 2021-09-24 16:48 ` Rafael J. Wysocki
2021-09-26 15:12 ` Thomas Gleixner
2021-09-29 9:20 ` Peter Zijlstra
0 siblings, 2 replies; 5+ messages in thread
From: Rafael J. Wysocki @ 2021-09-24 16:48 UTC (permalink / raw)
To: Deepak Sharma
Cc: Rafael J. Wysocki, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, the arch/x86 maintainers,
Linux Kernel Mailing List, Linux PM
On Fri, Sep 24, 2021 at 8:12 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
>
> All Zen or newer CPU which support C3 shares cache. Its not necessary to
> flush the caches in software before entering C3. This will cause drop in
> performance for the cores which share some caches. ARB_DIS is not used
> with current AMD C state implementation. So set related flags correctly.
>
> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
I'm planning to take this one unless the x86 maintainers have concerns, thanks.
> ---
> arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index 7de599eba7f0..7945eae5b315 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
> */
> flags->bm_control = 0;
> }
> + if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) {
> + /*
> + * For all AMD Zen or newer CPUs that support C3, caches
> + * should not be flushed by software while entering C3
> + * type state. Set bm->check to 1 so that kernel doesn't
> + * need to execute cache flush operation.
> + */
> + flags->bm_check = 1;
> + /*
> + * In current AMD C state implementation ARB_DIS is no longer
> + * used. So set bm_control to zero to indicate ARB_DIS is not
> + * required while entering C3 type state.
> + */
> + flags->bm_control = 0;
> + }
> }
> EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs
2021-09-24 16:48 ` Rafael J. Wysocki
@ 2021-09-26 15:12 ` Thomas Gleixner
2021-10-01 18:46 ` Rafael J. Wysocki
2021-09-29 9:20 ` Peter Zijlstra
1 sibling, 1 reply; 5+ messages in thread
From: Thomas Gleixner @ 2021-09-26 15:12 UTC (permalink / raw)
To: Rafael J. Wysocki, Deepak Sharma
Cc: Rafael J. Wysocki, Len Brown, Pavel Machek, Ingo Molnar,
Borislav Petkov, the arch/x86 maintainers,
Linux Kernel Mailing List, Linux PM
On Fri, Sep 24 2021 at 18:48, Rafael J. Wysocki wrote:
> On Fri, Sep 24, 2021 at 8:12 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
>>
>> All Zen or newer CPU which support C3 shares cache. Its not necessary to
>> flush the caches in software before entering C3. This will cause drop in
>> performance for the cores which share some caches. ARB_DIS is not used
>> with current AMD C state implementation. So set related flags correctly.
>>
>> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
>
> I'm planning to take this one unless the x86 maintainers have concerns, thanks.
Acked-by: Thomas Gleixner <tglx@linutronix.de>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs
2021-09-24 16:48 ` Rafael J. Wysocki
2021-09-26 15:12 ` Thomas Gleixner
@ 2021-09-29 9:20 ` Peter Zijlstra
1 sibling, 0 replies; 5+ messages in thread
From: Peter Zijlstra @ 2021-09-29 9:20 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Deepak Sharma, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, the arch/x86 maintainers,
Linux Kernel Mailing List, Linux PM
On Fri, Sep 24, 2021 at 06:48:48PM +0200, Rafael J. Wysocki wrote:
> On Fri, Sep 24, 2021 at 8:12 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
> >
> > All Zen or newer CPU which support C3 shares cache. Its not necessary to
> > flush the caches in software before entering C3. This will cause drop in
> > performance for the cores which share some caches. ARB_DIS is not used
> > with current AMD C state implementation. So set related flags correctly.
> >
> > Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
>
> I'm planning to take this one unless the x86 maintainers have concerns, thanks.
>
> > ---
> > arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> > index 7de599eba7f0..7945eae5b315 100644
> > --- a/arch/x86/kernel/acpi/cstate.c
> > +++ b/arch/x86/kernel/acpi/cstate.c
> > @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
> > */
> > flags->bm_control = 0;
> > }
> > + if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) {
> > + /*
> > + * For all AMD Zen or newer CPUs that support C3, caches
> > + * should not be flushed by software while entering C3
> > + * type state. Set bm->check to 1 so that kernel doesn't
> > + * need to execute cache flush operation.
> > + */
> > + flags->bm_check = 1;
> > + /*
> > + * In current AMD C state implementation ARB_DIS is no longer
> > + * used. So set bm_control to zero to indicate ARB_DIS is not
> > + * required while entering C3 type state.
> > + */
> > + flags->bm_control = 0;
> > + }
My only concern is the blatant code duplication between AMD and ZHAOXIN
here. Other than that, this is obviously correct since the ZHAOXIN thing
is basically rebranded AMD IP.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs
2021-09-26 15:12 ` Thomas Gleixner
@ 2021-10-01 18:46 ` Rafael J. Wysocki
0 siblings, 0 replies; 5+ messages in thread
From: Rafael J. Wysocki @ 2021-10-01 18:46 UTC (permalink / raw)
To: Thomas Gleixner, Deepak Sharma
Cc: Rafael J. Wysocki, Len Brown, Pavel Machek, Ingo Molnar,
Borislav Petkov, the arch/x86 maintainers,
Linux Kernel Mailing List, Linux PM
On Sun, Sep 26, 2021 at 5:13 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Fri, Sep 24 2021 at 18:48, Rafael J. Wysocki wrote:
>
> > On Fri, Sep 24, 2021 at 8:12 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
> >>
> >> All Zen or newer CPU which support C3 shares cache. Its not necessary to
> >> flush the caches in software before entering C3. This will cause drop in
> >> performance for the cores which share some caches. ARB_DIS is not used
> >> with current AMD C state implementation. So set related flags correctly.
> >>
> >> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
> >
> > I'm planning to take this one unless the x86 maintainers have concerns, thanks.
>
> Acked-by: Thomas Gleixner <tglx@linutronix.de>
Thanks!
Applied as 5.16 material, thanks!
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-10-01 18:46 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-24 6:12 [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs Deepak Sharma
2021-09-24 16:48 ` Rafael J. Wysocki
2021-09-26 15:12 ` Thomas Gleixner
2021-10-01 18:46 ` Rafael J. Wysocki
2021-09-29 9:20 ` Peter Zijlstra
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