From: "Clément Péron" <peron.clem@gmail.com> To: Maxime Ripard <maxime@cerno.tech> Cc: Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, devicetree <devicetree@vger.kernel.org>, linux-kernel <linux-kernel@vger.kernel.org>, linux-sunxi <linux-sunxi@googlegroups.com>, Ondrej Jirman <megous@megous.com> Subject: Re: [PATCH v2 3/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Date: Mon, 6 Apr 2020 20:03:34 +0200 [thread overview] Message-ID: <CAJiuCcdTQHGhZ=7Z_Du-zcZ_OWdGO1iEpYOBD4z=eNDYzMA5tg@mail.gmail.com> (raw) In-Reply-To: <20200406081412.ubdogkjknlofynei@gilmour.lan> Hi, On Mon, 6 Apr 2020 at 10:14, Maxime Ripard <maxime@cerno.tech> wrote: > > On Sun, Apr 05, 2020 at 07:35:57PM +0200, Clément Péron wrote: > > From: Ondrej Jirman <megous@megous.com> > > > > Add an Operating Performance Points table for the CPU cores to > > enable Dynamic Voltage & Frequency Scaling on the H6. > > > > Signed-off-by: Ondrej Jirman <megous@megous.com> > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > --- > > .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++ > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 + > > 2 files changed, 125 insertions(+) > > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi > > new file mode 100644 > > index 000000000000..8c1e413c6af9 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi > > @@ -0,0 +1,121 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +// Copyright (C) 2020 Ondrej Jirman <megous@megous.com> > > +// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com> > > + > > +/ { > > + cpu0_opp_table: opp_table0 { > > Node names shouldn't have an underscore, this will trigger a DTC > warning. > > > + compatible = "allwinner,sun50i-h6-operating-points"; > > + nvmem-cells = <&speedbin_efuse>; > > + opp-shared; > > + > > + opp@480000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <480000000>; > > + > > + opp-microvolt-speed0 = <880000>; > > + opp-microvolt-speed1 = <820000>; > > + opp-microvolt-speed2 = <820000>; > > + }; > > And similarly, if you have a unit-address (the part after @), you > should have a matching reg property. You should use a dash instead. > > > + opp@720000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <720000000>; > > + > > + opp-microvolt-speed0 = <880000>; > > + opp-microvolt-speed1 = <820000>; > > + opp-microvolt-speed2 = <820000>; > > + }; > > + > > + opp@816000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <816000000>; > > + > > + opp-microvolt-speed0 = <880000>; > > + opp-microvolt-speed1 = <820000>; > > + opp-microvolt-speed2 = <820000>; > > + }; > > + > > + opp@888000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <888000000>; > > + > > + opp-microvolt-speed0 = <880000>; > > + opp-microvolt-speed1 = <820000>; > > + opp-microvolt-speed2 = <820000>; > > + }; > > + > > + opp@1080000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1080000000>; > > + > > + opp-microvolt-speed0 = <940000>; > > + opp-microvolt-speed1 = <880000>; > > + opp-microvolt-speed2 = <880000>; > > + }; > > + > > + opp@1320000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1320000000>; > > + > > + opp-microvolt-speed0 = <1000000>; > > + opp-microvolt-speed1 = <940000>; > > + opp-microvolt-speed2 = <940000>; > > + }; > > + > > + opp@1488000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1488000000>; > > + > > + opp-microvolt-speed0 = <1060000>; > > + opp-microvolt-speed1 = <1000000>; > > + opp-microvolt-speed2 = <1000000>; > > + }; > > + > > + opp@1608000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1608000000>; > > + > > + opp-microvolt-speed0 = <1090000>; > > + opp-microvolt-speed1 = <1030000>; > > + opp-microvolt-speed2 = <1030000>; > > + }; > > + > > + opp@1704000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1704000000>; > > + > > + opp-microvolt-speed0 = <1120000>; > > + opp-microvolt-speed1 = <1060000>; > > + opp-microvolt-speed2 = <1060000>; > > + }; > > + > > + opp@1800000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1800000000>; > > + > > + opp-microvolt-speed0 = <1160000>; > > + opp-microvolt-speed1 = <1100000>; > > + opp-microvolt-speed2 = <1100000>; > > + }; > > + }; > > +}; > > + > > +&cpu0 { > > + operating-points-v2 = <&cpu0_opp_table>; > > + #cooling-cells = <2>; > > +}; > > + > > +&cpu1 { > > + operating-points-v2 = <&cpu0_opp_table>; > > + #cooling-cells = <2>; > > +}; > > + > > +&cpu2 { > > + operating-points-v2 = <&cpu0_opp_table>; > > + #cooling-cells = <2>; > > +}; > > + > > +&cpu3 { > > + operating-points-v2 = <&cpu0_opp_table>; > > + #cooling-cells = <2>; > > +}; > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > index e0dd0757be0b..6b7af858614a 100644 > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > @@ -253,6 +253,10 @@ > > #address-cells = <1>; > > #size-cells = <1>; > > > > + speedbin_efuse: speed@1c { > > + reg = <0x1c 0x4>; > > + }; > > + > > You should order this by address, so after the THS calibration. Also, > using a less generic node name than "speed" would be great. What about > soc-bin ? Indeed it's too generic. I will keep coherency with i.MX8 and use "cpu_speed_grade" Thanks for the review, Clement > > Maxime
WARNING: multiple messages have this Message-ID (diff)
From: "Clément Péron" <peron.clem@gmail.com> To: Maxime Ripard <maxime@cerno.tech> Cc: Ondrej Jirman <megous@megous.com>, devicetree <devicetree@vger.kernel.org>, Chen-Yu Tsai <wens@csie.org>, linux-kernel <linux-kernel@vger.kernel.org>, linux-sunxi <linux-sunxi@googlegroups.com>, Rob Herring <robh+dt@kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH v2 3/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Date: Mon, 6 Apr 2020 20:03:34 +0200 [thread overview] Message-ID: <CAJiuCcdTQHGhZ=7Z_Du-zcZ_OWdGO1iEpYOBD4z=eNDYzMA5tg@mail.gmail.com> (raw) In-Reply-To: <20200406081412.ubdogkjknlofynei@gilmour.lan> Hi, On Mon, 6 Apr 2020 at 10:14, Maxime Ripard <maxime@cerno.tech> wrote: > > On Sun, Apr 05, 2020 at 07:35:57PM +0200, Clément Péron wrote: > > From: Ondrej Jirman <megous@megous.com> > > > > Add an Operating Performance Points table for the CPU cores to > > enable Dynamic Voltage & Frequency Scaling on the H6. > > > > Signed-off-by: Ondrej Jirman <megous@megous.com> > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > --- > > .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++ > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 + > > 2 files changed, 125 insertions(+) > > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi > > new file mode 100644 > > index 000000000000..8c1e413c6af9 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi > > @@ -0,0 +1,121 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +// Copyright (C) 2020 Ondrej Jirman <megous@megous.com> > > +// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com> > > + > > +/ { > > + cpu0_opp_table: opp_table0 { > > Node names shouldn't have an underscore, this will trigger a DTC > warning. > > > + compatible = "allwinner,sun50i-h6-operating-points"; > > + nvmem-cells = <&speedbin_efuse>; > > + opp-shared; > > + > > + opp@480000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <480000000>; > > + > > + opp-microvolt-speed0 = <880000>; > > + opp-microvolt-speed1 = <820000>; > > + opp-microvolt-speed2 = <820000>; > > + }; > > And similarly, if you have a unit-address (the part after @), you > should have a matching reg property. You should use a dash instead. > > > + opp@720000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <720000000>; > > + > > + opp-microvolt-speed0 = <880000>; > > + opp-microvolt-speed1 = <820000>; > > + opp-microvolt-speed2 = <820000>; > > + }; > > + > > + opp@816000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <816000000>; > > + > > + opp-microvolt-speed0 = <880000>; > > + opp-microvolt-speed1 = <820000>; > > + opp-microvolt-speed2 = <820000>; > > + }; > > + > > + opp@888000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <888000000>; > > + > > + opp-microvolt-speed0 = <880000>; > > + opp-microvolt-speed1 = <820000>; > > + opp-microvolt-speed2 = <820000>; > > + }; > > + > > + opp@1080000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1080000000>; > > + > > + opp-microvolt-speed0 = <940000>; > > + opp-microvolt-speed1 = <880000>; > > + opp-microvolt-speed2 = <880000>; > > + }; > > + > > + opp@1320000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1320000000>; > > + > > + opp-microvolt-speed0 = <1000000>; > > + opp-microvolt-speed1 = <940000>; > > + opp-microvolt-speed2 = <940000>; > > + }; > > + > > + opp@1488000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1488000000>; > > + > > + opp-microvolt-speed0 = <1060000>; > > + opp-microvolt-speed1 = <1000000>; > > + opp-microvolt-speed2 = <1000000>; > > + }; > > + > > + opp@1608000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1608000000>; > > + > > + opp-microvolt-speed0 = <1090000>; > > + opp-microvolt-speed1 = <1030000>; > > + opp-microvolt-speed2 = <1030000>; > > + }; > > + > > + opp@1704000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1704000000>; > > + > > + opp-microvolt-speed0 = <1120000>; > > + opp-microvolt-speed1 = <1060000>; > > + opp-microvolt-speed2 = <1060000>; > > + }; > > + > > + opp@1800000000 { > > + clock-latency-ns = <244144>; /* 8 32k periods */ > > + opp-hz = /bits/ 64 <1800000000>; > > + > > + opp-microvolt-speed0 = <1160000>; > > + opp-microvolt-speed1 = <1100000>; > > + opp-microvolt-speed2 = <1100000>; > > + }; > > + }; > > +}; > > + > > +&cpu0 { > > + operating-points-v2 = <&cpu0_opp_table>; > > + #cooling-cells = <2>; > > +}; > > + > > +&cpu1 { > > + operating-points-v2 = <&cpu0_opp_table>; > > + #cooling-cells = <2>; > > +}; > > + > > +&cpu2 { > > + operating-points-v2 = <&cpu0_opp_table>; > > + #cooling-cells = <2>; > > +}; > > + > > +&cpu3 { > > + operating-points-v2 = <&cpu0_opp_table>; > > + #cooling-cells = <2>; > > +}; > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > index e0dd0757be0b..6b7af858614a 100644 > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > @@ -253,6 +253,10 @@ > > #address-cells = <1>; > > #size-cells = <1>; > > > > + speedbin_efuse: speed@1c { > > + reg = <0x1c 0x4>; > > + }; > > + > > You should order this by address, so after the THS calibration. Also, > using a less generic node name than "speed" would be great. What about > soc-bin ? Indeed it's too generic. I will keep coherency with i.MX8 and use "cpu_speed_grade" Thanks for the review, Clement > > Maxime _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-04-06 18:03 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-05 17:35 [PATCH v2 0/7] Add support for Allwinner H6 DVFS Clément Péron 2020-04-05 17:35 ` Clément Péron 2020-04-05 17:35 ` [PATCH v2 1/7] arm64: dts: allwinner: h6: Add clock to CPU cores Clément Péron 2020-04-05 17:35 ` Clément Péron 2020-04-05 17:35 ` [PATCH v2 2/7] arm64: dts: allwinner: h6: Add thermal trip points/cooling map Clément Péron 2020-04-05 17:35 ` Clément Péron 2020-04-05 17:35 ` [PATCH v2 3/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Clément Péron 2020-04-05 17:35 ` Clément Péron 2020-04-06 8:14 ` Maxime Ripard 2020-04-06 8:14 ` Maxime Ripard 2020-04-06 18:03 ` Clément Péron [this message] 2020-04-06 18:03 ` Clément Péron 2020-04-07 8:47 ` Maxime Ripard 2020-04-07 8:47 ` Maxime Ripard 2020-04-05 17:35 ` [PATCH v2 4/7] arm64: dts: allwinner: h6: Add GPU " Clément Péron 2020-04-05 17:35 ` Clément Péron 2020-04-06 8:16 ` Maxime Ripard 2020-04-06 8:16 ` Maxime Ripard 2020-04-06 8:58 ` Clément Péron 2020-04-06 8:58 ` Clément Péron 2020-04-05 17:35 ` [PATCH v2 5/7] arm64: configs: Enable sun50i cpufreq nvmem Clément Péron 2020-04-05 17:35 ` Clément Péron 2020-04-06 8:16 ` Maxime Ripard 2020-04-06 8:16 ` Maxime Ripard 2020-04-05 17:36 ` [PATCH v2 6/7] arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink GS1 Clément Péron 2020-04-05 17:36 ` Clément Péron 2020-04-05 17:36 ` [PATCH v2 7/7] arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Orange Pi boards Clément Péron 2020-04-05 17:36 ` Clément Péron 2020-04-06 9:10 ` Clément Péron 2020-04-06 9:10 ` Clément Péron 2020-04-06 8:10 ` [PATCH v2 0/7] Add support for Allwinner H6 DVFS Maxime Ripard 2020-04-06 8:10 ` Maxime Ripard 2020-04-06 9:07 ` Clément Péron 2020-04-06 9:07 ` Clément Péron 2020-04-13 13:37 ` Clément Péron 2020-04-13 13:37 ` Clément Péron 2020-04-15 10:28 ` Maxime Ripard 2020-04-15 10:28 ` Maxime Ripard
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