* [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-27 16:21 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-27 16:21 UTC (permalink / raw) To: soc, linux-arm-kernel, devicetree Cc: arnd, olof, robh+dt, krzysztof.kozlowski+dt, andrew, sebastian.hesselbarth, Mauri Sandberg Hello all, I am making an attempt to create a device tree for D-Link DNS-323 devices but I am falling short on a few specific details. I am requesting a general review of the device tree files. I have access to DNS-323 rev A1 only and the B1 and C1 need to be tested separately, so I am reaching out to people who might have them. The questions that I have at the moment are below. - some of resulting IRQs are different from what was requested in device tree - logs say NR_IRQS is different from mach file one - sata_mv fails to initialise with -22 (-EINVAL) - there is no concensus on how to get ascii formatted MAC address from mtd partitions so eth is not fully functional without setting the MAC from userspace - revs B1 and C1 need testing - how to configure RTC to wake system from sleep? What currently works in rev A1 - leds - keys - fan - temperature sensor - shutdown - reboot - mtd partitions - ethernet (mac address must be set manually) I have included relevant parts from boot log to better illustrate what seems to be off target -------------------------------- DT log --------------------------------------- ... NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 ... sata_mv 0000:00:01.0: Gen-IIE 32 slots 4 ports SCSI mode IRQ via INTx sata_mv: probe of 0000:00:01.0 failed with error -22 ... mv64xxx_i2c mv64xxx_i2c.0: can't get pinctrl, bus recovery not supported ... ------------------------------------------------------------------------------- Best regards, Mauri Mauri Sandberg (1): ARM: orion5x: convert D-Link DNS-323 to the Device Tree arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ arch/arm/mach-orion5x/Kconfig | 6 +- arch/arm/mach-orion5x/Makefile | 2 +- arch/arm/mach-orion5x/board-dns323.c | 118 +++ arch/arm/mach-orion5x/board-dt.c | 3 + arch/arm/mach-orion5x/common.h | 6 + arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- 11 files changed, 528 insertions(+), 728 deletions(-) create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts create mode 100644 arch/arm/mach-orion5x/board-dns323.c delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c base-commit: 46cf2c613f4b10eb12f749207b0fd2c1bfae3088 -- 2.25.1 ^ permalink raw reply [flat|nested] 91+ messages in thread
* [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-27 16:21 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-27 16:21 UTC (permalink / raw) To: soc, linux-arm-kernel, devicetree Cc: arnd, olof, robh+dt, krzysztof.kozlowski+dt, andrew, sebastian.hesselbarth, Mauri Sandberg Hello all, I am making an attempt to create a device tree for D-Link DNS-323 devices but I am falling short on a few specific details. I am requesting a general review of the device tree files. I have access to DNS-323 rev A1 only and the B1 and C1 need to be tested separately, so I am reaching out to people who might have them. The questions that I have at the moment are below. - some of resulting IRQs are different from what was requested in device tree - logs say NR_IRQS is different from mach file one - sata_mv fails to initialise with -22 (-EINVAL) - there is no concensus on how to get ascii formatted MAC address from mtd partitions so eth is not fully functional without setting the MAC from userspace - revs B1 and C1 need testing - how to configure RTC to wake system from sleep? What currently works in rev A1 - leds - keys - fan - temperature sensor - shutdown - reboot - mtd partitions - ethernet (mac address must be set manually) I have included relevant parts from boot log to better illustrate what seems to be off target -------------------------------- DT log --------------------------------------- ... NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 ... sata_mv 0000:00:01.0: Gen-IIE 32 slots 4 ports SCSI mode IRQ via INTx sata_mv: probe of 0000:00:01.0 failed with error -22 ... mv64xxx_i2c mv64xxx_i2c.0: can't get pinctrl, bus recovery not supported ... ------------------------------------------------------------------------------- Best regards, Mauri Mauri Sandberg (1): ARM: orion5x: convert D-Link DNS-323 to the Device Tree arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ arch/arm/mach-orion5x/Kconfig | 6 +- arch/arm/mach-orion5x/Makefile | 2 +- arch/arm/mach-orion5x/board-dns323.c | 118 +++ arch/arm/mach-orion5x/board-dt.c | 3 + arch/arm/mach-orion5x/common.h | 6 + arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- 11 files changed, 528 insertions(+), 728 deletions(-) create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts create mode 100644 arch/arm/mach-orion5x/board-dns323.c delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c base-commit: 46cf2c613f4b10eb12f749207b0fd2c1bfae3088 -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-27 16:21 ` Mauri Sandberg @ 2022-04-27 16:21 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-27 16:21 UTC (permalink / raw) To: soc, linux-arm-kernel, devicetree Cc: arnd, olof, robh+dt, krzysztof.kozlowski+dt, andrew, sebastian.hesselbarth, Mauri Sandberg Convert D-Link DNS-323 to use the device tree and remove associated mach file. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ arch/arm/mach-orion5x/Kconfig | 6 +- arch/arm/mach-orion5x/Makefile | 2 +- arch/arm/mach-orion5x/board-dns323.c | 118 +++ arch/arm/mach-orion5x/board-dt.c | 3 + arch/arm/mach-orion5x/common.h | 6 + arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- 11 files changed, 528 insertions(+), 728 deletions(-) create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts create mode 100644 arch/arm/mach-orion5x/board-dns323.c delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..c7c5c0b6c843 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -949,6 +949,9 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ dra71-evm.dtb \ dra76-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += \ + orion5x-dlink-dns323a1.dtb \ + orion5x-dlink-dns323b1.dtb \ + orion5x-dlink-dns323c1.dtb \ orion5x-kuroboxpro.dtb \ orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi new file mode 100644 index 000000000000..2b033d37cbf8 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/ { + model = "D-Link DNS-323"; + compatible = "dlink,dns323", "marvell,orion5x"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>; + + /delete-node/ devbus-cs0; + /delete-node/ devbus-cs1; + /delete-node/ devbus-cs2; + + internal-regs { + /delete-node/ dma-controller@60900; /* xor */ + /delete-node/ ehci@a0000; /* ehci1 */ + /delete-node/ serial@12100; /* uart1 */ + /delete-node/ spi@10600; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_gpio_keys>; + pinctrl-names = "default"; + + key-0 { + label = "Power button"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + key-1 { + label = "Reset button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_gpio_leds>; + pinctrl-names = "default"; + + led-0 { + label = "amber:right"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "amber:left"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "blue:power"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; + + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + timeout-ms = <3000>; + }; +}; + +&devbus_bootcs { + status = "okay"; + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x800000>; + bank-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "MTD1"; + reg = <0x000000 0x010000>; + read-only; + }; + + partition@10000 { + label = "MTD2"; + reg = <0x010000 0x010000>; + read-only; + }; + + partition@20000 { + label = "Linux Kernel"; + reg = <0x020000 0x180000>; + }; + + partition@1a0000 { + label = "File System"; + reg = <0x1a0000 0x630000>; + }; + + uboot: partition@7d0000 { + label = "U-boot"; + reg = <0x7d0000 0x030000>; + read-only; + }; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + + /* fan speed PWM */ + fan@3e { + compatible = "g760a"; + reg = <0x3e>; + }; + + /* temp sensor and thermal watchdog */ + temperature-sensor@48 { + compatible = "gmt,g751"; + reg = <0x48>; + }; + + /* RTC w/ alarm */ + rtc@68 { + compatible = "st,m41t80"; + reg = <0x68>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +ð { + status = "okay"; + pinctrl-0 = <&pmx_ge>; + pinctrl-names = "default"; +}; + +ðport { + phy-handle = <ðphy>; +}; + +&uart0 { + status = "okay"; +}; + +&pinctrl { + pmx_gpio_leds: pmx-gpio-leds { + marvell,pins = "mpp1", "mpp2", "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_misc: pmx-gpio-misc { + /* set marvell,pins in board file */ + marvell,function = "gpio"; + }; + + pmx_power_off: pmx-power-off { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_keys: pmx-gpio-keys { + marvell,pins = "mpp9", "mpp10"; + marvell,function = "gpio"; + }; + + pmx_ge: pmx-ge { + marvell,function = "ge"; + }; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts new file mode 100644 index 000000000000..73e7006ab5a7 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5181.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + compatible = "dlink,dns323a1", "dlink,dns323", "marvell,orion5x-88f5181", + "marvell,orion5x"; + + /delete-node/ sa-sram; /* crypto_sram */ + + soc { + internal-regs { + /delete-node/ crypto@90000; + /delete-node/ sata@80000; + }; + }; +}; + +&gpio0 { + pinctrl-0 = <&pmx_gpio_misc>; + pinctrl-names = "default"; + + /* The DNS323 rev A1 power LED requires GPIO 4 to be low. */ + pin_gpio0_4 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-high; + line-name = "Power led enable"; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_pci_pins>; + pinctrl-names = "default"; + + pmx_pci_pins: pmx-pci-pins { + marvell,pins = "mpp0"; + marvell,function = "pcie"; + }; +}; + +&pmx_gpio_misc { + marvell,pins = "mpp4"; +}; + +&pmx_ge { + marvell,pins = "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts new file mode 100644 index 000000000000..31251f64c573 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5182.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + compatible = "dlink,dns323b1", "dlink,dns323", "marvell,orion5x-88f5182", + "marvell,orion5x"; +}; + +&gpio0 { + pinctrl-0 = <&pmx_gpio_misc>; + pinctrl-names = "default"; + + /* The rev B1 has a flag to indicate the system is up. + * Without this flag set, power LED will flash and cannot be + * controlled via gpio-leds. + */ + pin_gpio0_3 { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-high; + line-name = "System up"; + }; +}; + +&pmx_gpio_misc { + marvell,pins = "mpp3"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts new file mode 100644 index 000000000000..c36af513ecd7 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5182.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + compatible = "dlink,dns323c1", "dlink,dns323", "marvell,orion5x-88f5182", + "marvell,orion5x"; + + fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_gpio_fan>; + pinctrl-names = "default"; + + gpios = <&gpio0 19 GPIO_ACTIVE_LOW + &gpio0 18 GPIO_ACTIVE_LOW>; + + gpio-fan,speed-map = <0 0 + 1000 1 + 2000 2>; + alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + /delete-node/ key-1; + + key-0 { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + led-0 { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + led-1 { + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + led-2 { + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; + +}; + +&i2c { + /delete-node/ fan@3e; +}; + +&pinctrl { + /delete-node/ pmx-gpio-misc; + + pmx_gpio_fan: pmx-gpio-fan { + marvell,pins = "mpp10", "mpp18", "mpp19"; + marvell,function = "gpio"; + }; +}; + +&pmx_gpio_leds { + marvell,pins = "mpp8", "mpp9", "mpp17"; +}; + +&pmx_power_off { + marvell,pins = "mpp2"; +}; + +&pmx_gpio_keys { + marvell,pins = "mpp1"; +}; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index c77f3b4e287b..65cd5307a460 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -55,9 +55,9 @@ config MACH_KUROBOX_PRO Say 'Y' here if you want your kernel to support the KuroBox Pro platform. -config MACH_DNS323 - bool "D-Link DNS-323" - select I2C_BOARDINFO if I2C +config MACH_DNS323_DT + bool "D-Link DNS-323 (Flattened Device Tree)" + select ARCH_ORION5X_DT help Say 'Y' here if you want your kernel to support the D-Link DNS-323 platform. diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 1a585a62d5e6..b8c0671fbd1c 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -8,7 +8,6 @@ obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_LINKSTATION_LS_HGL) += ls_hgl-setup.o -obj-$(CONFIG_MACH_DNS323) += dns323-setup.o obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o @@ -22,5 +21,6 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o +obj-$(CONFIG_MACH_DNS323_DT) += board-dns323.o obj-$(CONFIG_MACH_MSS2_DT) += board-mss2.o obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o diff --git a/arch/arm/mach-orion5x/board-dns323.c b/arch/arm/mach-orion5x/board-dns323.c new file mode 100644 index 000000000000..705ddb7b691a --- /dev/null +++ b/arch/arm/mach-orion5x/board-dns323.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + * Flattened Device Tree board initialization + * + * This is adapted from existing mach file and most of the source code is + * originally written by: + * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> + * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org> + */ + +#include <linux/of.h> +#include <linux/phy.h> +#include <linux/marvell_phy.h> +#include <asm/mach/pci.h> +#include "bridge-regs.h" +#include "common.h" + +/* Rev A1 and B1 */ +#define DNS323_GPIO_LED_RIGHT_AMBER 1 +#define DNS323_GPIO_LED_LEFT_AMBER 2 +#define DNS323_GPIO_SYSTEM_UP 3 +#define DNS323_GPIO_LED_POWER1 4 +#define DNS323_GPIO_LED_POWER2 5 +#define DNS323_GPIO_OVERTEMP 6 +#define DNS323_GPIO_RTC 7 +#define DNS323_GPIO_POWER_OFF 8 +#define DNS323_GPIO_KEY_POWER 9 +#define DNS323_GPIO_KEY_RESET 10 + +/* Rev C1 */ +#define DNS323C_GPIO_KEY_POWER 1 +#define DNS323C_GPIO_POWER_OFF 2 +#define DNS323C_GPIO_LED_RIGHT_AMBER 8 +#define DNS323C_GPIO_LED_LEFT_AMBER 9 +#define DNS323C_GPIO_LED_POWER 17 +#define DNS323C_GPIO_FAN_BIT1 18 +#define DNS323C_GPIO_FAN_BIT0 19 + +/* Exposed to userspace, do not change */ +enum { + DNS323_REV_A1, /* 0 */ + DNS323_REV_B1, /* 1 */ + DNS323_REV_C1, /* 2 */ +}; + +/**************************************************************************** + * PCI setup + */ + +static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + return -1; +} + +static struct hw_pci dns323_pci __initdata = { + .nr_controllers = 2, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = dns323_pci_map_irq, +}; + +static int __init dns323_pci_init(void) +{ + /* Rev B1 and C1 doesn't really use its PCI bus, and + * initialising PCI gets in the way of initialising the SATA + * controller. + */ + if (of_machine_is_compatible("dlink,dns323a1")) + pci_common_init(&dns323_pci); + + return 0; +} +subsys_initcall(dns323_pci_init); + +/**************************************************************************** + * Fix-ups + */ + +static int dns323c_phy_fixup(struct phy_device *phy) +{ + phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS; + + return 0; +} + +void __init dns323_init(void) +{ + if (of_machine_is_compatible("dlink,dns323a1")) { + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ + } else if (of_machine_is_compatible("dlink,dns323c1") && + IS_BUILTIN(CONFIG_PHYLIB)) { + /* Register fixup for the PHY LEDs */ + phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118, + MARVELL_PHY_ID_MASK, + dns323c_phy_fixup); + + /* Now, -this- should theorically be done by the sata_mv driver + * once I figure out what's going on there. Maybe the behaviour + * of the LEDs should be somewhat passed via the platform_data. + * for now, just whack the register and make the LEDs happy + * + * Note: AFAIK, rev B1 needs the same treatement but I'll let + * somebody else test it. + */ + writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); + } +} diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 3d36f1d95196..279194483fcf 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -60,6 +60,9 @@ static void __init orion5x_dt_init(void) cpu_idle_poll_ctrl(true); } + if (of_machine_is_compatible("dlink,dns323")) + dns323_init(); + if (of_machine_is_compatible("maxtor,shared-storage-2")) mss2_init(); diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index eb96009e21c4..ac92b67bf9ec 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -75,6 +75,12 @@ extern void mss2_init(void); static inline void mss2_init(void) {} #endif +#ifdef CONFIG_MACH_DNS323_DT +extern void dns323_init(void); +#else +static inline void dns323_init(void) {} +#endif + /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c deleted file mode 100644 index 87cb47220e82..000000000000 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ /dev/null @@ -1,724 +0,0 @@ -/* - * arch/arm/mach-orion5x/dns323-setup.c - * - * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> - * - * Support for HW Rev C1: - * - * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/mtd/physmap.h> -#include <linux/mv643xx_eth.h> -#include <linux/leds.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/ata_platform.h> -#include <linux/phy.h> -#include <linux/marvell_phy.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> -#include <asm/system_info.h> -#include <plat/orion-gpio.h> -#include "orion5x.h" -#include "common.h" -#include "mpp.h" - -/* Rev A1 and B1 */ -#define DNS323_GPIO_LED_RIGHT_AMBER 1 -#define DNS323_GPIO_LED_LEFT_AMBER 2 -#define DNS323_GPIO_SYSTEM_UP 3 -#define DNS323_GPIO_LED_POWER1 4 -#define DNS323_GPIO_LED_POWER2 5 -#define DNS323_GPIO_OVERTEMP 6 -#define DNS323_GPIO_RTC 7 -#define DNS323_GPIO_POWER_OFF 8 -#define DNS323_GPIO_KEY_POWER 9 -#define DNS323_GPIO_KEY_RESET 10 - -/* Rev C1 */ -#define DNS323C_GPIO_KEY_POWER 1 -#define DNS323C_GPIO_POWER_OFF 2 -#define DNS323C_GPIO_LED_RIGHT_AMBER 8 -#define DNS323C_GPIO_LED_LEFT_AMBER 9 -#define DNS323C_GPIO_LED_POWER 17 -#define DNS323C_GPIO_FAN_BIT1 18 -#define DNS323C_GPIO_FAN_BIT0 19 - -/* Exposed to userspace, do not change */ -enum { - DNS323_REV_A1, /* 0 */ - DNS323_REV_B1, /* 1 */ - DNS323_REV_C1, /* 2 */ -}; - - -/**************************************************************************** - * PCI setup - */ - -static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - return -1; -} - -static struct hw_pci dns323_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = dns323_pci_map_irq, -}; - -static int __init dns323_pci_init(void) -{ - /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI - * gets in the way of initialising the SATA controller. - */ - if (machine_is_dns323() && system_rev == DNS323_REV_A1) - pci_common_init(&dns323_pci); - - return 0; -} - -subsys_initcall(dns323_pci_init); - -/**************************************************************************** - * 8MiB NOR flash (Spansion S29GL064M90TFIR4) - * - * Layout as used by D-Link: - * 0x00000000-0x00010000 : "MTD1" - * 0x00010000-0x00020000 : "MTD2" - * 0x00020000-0x001a0000 : "Linux Kernel" - * 0x001a0000-0x007d0000 : "File System" - * 0x007d0000-0x00800000 : "u-boot" - */ - -#define DNS323_NOR_BOOT_BASE 0xf4000000 -#define DNS323_NOR_BOOT_SIZE SZ_8M - -static struct mtd_partition dns323_partitions[] = { - { - .name = "MTD1", - .size = 0x00010000, - .offset = 0, - }, { - .name = "MTD2", - .size = 0x00010000, - .offset = 0x00010000, - }, { - .name = "Linux Kernel", - .size = 0x00180000, - .offset = 0x00020000, - }, { - .name = "File System", - .size = 0x00630000, - .offset = 0x001A0000, - }, { - .name = "u-boot", - .size = 0x00030000, - .offset = 0x007d0000, - }, -}; - -static struct physmap_flash_data dns323_nor_flash_data = { - .width = 1, - .parts = dns323_partitions, - .nr_parts = ARRAY_SIZE(dns323_partitions) -}; - -static struct resource dns323_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = DNS323_NOR_BOOT_BASE, - .end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device dns323_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &dns323_nor_flash_data, - }, - .resource = &dns323_nor_flash_resource, - .num_resources = 1, -}; - -/**************************************************************************** - * Ethernet - */ - -static struct mv643xx_eth_platform_data dns323_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these - * functions be kept somewhere? - */ -static int __init dns323_parse_hex_nibble(char n) -{ - if (n >= '0' && n <= '9') - return n - '0'; - - if (n >= 'A' && n <= 'F') - return n - 'A' + 10; - - if (n >= 'a' && n <= 'f') - return n - 'a' + 10; - - return -1; -} - -static int __init dns323_parse_hex_byte(const char *b) -{ - int hi; - int lo; - - hi = dns323_parse_hex_nibble(b[0]); - lo = dns323_parse_hex_nibble(b[1]); - - if (hi < 0 || lo < 0) - return -1; - - return (hi << 4) | lo; -} - -static int __init dns323_read_mac_addr(void) -{ - u_int8_t addr[6]; - int i; - char *mac_page; - - /* MAC address is stored as a regular ol' string in /dev/mtdblock4 - * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80). - */ - mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024); - if (!mac_page) - return -ENOMEM; - - /* Sanity check the string we're looking at */ - for (i = 0; i < 5; i++) { - if (*(mac_page + (i * 3) + 2) != ':') { - goto error_fail; - } - } - - for (i = 0; i < 6; i++) { - int byte; - - byte = dns323_parse_hex_byte(mac_page + (i * 3)); - if (byte < 0) { - goto error_fail; - } - - addr[i] = byte; - } - - iounmap(mac_page); - printk("DNS-323: Found ethernet MAC address: %pM\n", addr); - - memcpy(dns323_eth_data.mac_addr, addr, 6); - - return 0; - -error_fail: - iounmap(mac_page); - return -EINVAL; -} - -/**************************************************************************** - * GPIO LEDs (simple - doesn't use hardware blinking support) - */ - -static struct gpio_led dns323ab_leds[] = { - { - .name = "power:blue", - .gpio = DNS323_GPIO_LED_POWER2, - .default_trigger = "default-on", - }, { - .name = "right:amber", - .gpio = DNS323_GPIO_LED_RIGHT_AMBER, - .active_low = 1, - }, { - .name = "left:amber", - .gpio = DNS323_GPIO_LED_LEFT_AMBER, - .active_low = 1, - }, -}; - - -static struct gpio_led dns323c_leds[] = { - { - .name = "power:blue", - .gpio = DNS323C_GPIO_LED_POWER, - .default_trigger = "timer", - .active_low = 1, - }, { - .name = "right:amber", - .gpio = DNS323C_GPIO_LED_RIGHT_AMBER, - .active_low = 1, - }, { - .name = "left:amber", - .gpio = DNS323C_GPIO_LED_LEFT_AMBER, - .active_low = 1, - }, -}; - - -static struct gpio_led_platform_data dns323ab_led_data = { - .num_leds = ARRAY_SIZE(dns323ab_leds), - .leds = dns323ab_leds, - .gpio_blink_set = orion_gpio_led_blink_set, -}; - -static struct gpio_led_platform_data dns323c_led_data = { - .num_leds = ARRAY_SIZE(dns323c_leds), - .leds = dns323c_leds, - .gpio_blink_set = orion_gpio_led_blink_set, -}; - -static struct platform_device dns323_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &dns323ab_led_data, - }, -}; - -/**************************************************************************** - * GPIO Attached Keys - */ - -static struct gpio_keys_button dns323ab_buttons[] = { - { - .code = KEY_RESTART, - .gpio = DNS323_GPIO_KEY_RESET, - .desc = "Reset Button", - .active_low = 1, - }, { - .code = KEY_POWER, - .gpio = DNS323_GPIO_KEY_POWER, - .desc = "Power Button", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data dns323ab_button_data = { - .buttons = dns323ab_buttons, - .nbuttons = ARRAY_SIZE(dns323ab_buttons), -}; - -static struct gpio_keys_button dns323c_buttons[] = { - { - .code = KEY_POWER, - .gpio = DNS323C_GPIO_KEY_POWER, - .desc = "Power Button", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data dns323c_button_data = { - .buttons = dns323c_buttons, - .nbuttons = ARRAY_SIZE(dns323c_buttons), -}; - -static struct platform_device dns323_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &dns323ab_button_data, - }, -}; - -/***************************************************************************** - * SATA - */ -static struct mv_sata_platform_data dns323_sata_data = { - .n_ports = 2, -}; - -/**************************************************************************** - * General Setup - */ -static unsigned int dns323a_mpp_modes[] __initdata = { - MPP0_PCIE_RST_OUTn, - MPP1_GPIO, /* right amber LED (sata ch0) */ - MPP2_GPIO, /* left amber LED (sata ch1) */ - MPP3_UNUSED, - MPP4_GPIO, /* power button LED */ - MPP5_GPIO, /* power button LED */ - MPP6_GPIO, /* GMT G751-2f overtemp */ - MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */ - MPP8_GPIO, /* triggers power off */ - MPP9_GPIO, /* power button switch */ - MPP10_GPIO, /* reset button switch */ - MPP11_UNUSED, - MPP12_UNUSED, - MPP13_UNUSED, - MPP14_UNUSED, - MPP15_UNUSED, - MPP16_UNUSED, - MPP17_UNUSED, - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static unsigned int dns323b_mpp_modes[] __initdata = { - MPP0_UNUSED, - MPP1_GPIO, /* right amber LED (sata ch0) */ - MPP2_GPIO, /* left amber LED (sata ch1) */ - MPP3_GPIO, /* system up flag */ - MPP4_GPIO, /* power button LED */ - MPP5_GPIO, /* power button LED */ - MPP6_GPIO, /* GMT G751-2f overtemp */ - MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */ - MPP8_GPIO, /* triggers power off */ - MPP9_GPIO, /* power button switch */ - MPP10_GPIO, /* reset button switch */ - MPP11_UNUSED, - MPP12_SATA_LED, - MPP13_SATA_LED, - MPP14_SATA_LED, - MPP15_SATA_LED, - MPP16_UNUSED, - MPP17_UNUSED, - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static unsigned int dns323c_mpp_modes[] __initdata = { - MPP0_GPIO, /* ? input */ - MPP1_GPIO, /* input power switch (0 = pressed) */ - MPP2_GPIO, /* output power off */ - MPP3_UNUSED, /* ? output */ - MPP4_UNUSED, /* ? output */ - MPP5_UNUSED, /* ? output */ - MPP6_UNUSED, /* ? output */ - MPP7_UNUSED, /* ? output */ - MPP8_GPIO, /* i/o right amber LED */ - MPP9_GPIO, /* i/o left amber LED */ - MPP10_GPIO, /* input */ - MPP11_UNUSED, - MPP12_SATA_LED, - MPP13_SATA_LED, - MPP14_SATA_LED, - MPP15_SATA_LED, - MPP16_UNUSED, - MPP17_GPIO, /* power button LED */ - MPP18_GPIO, /* fan speed bit 0 */ - MPP19_GPIO, /* fan speed bit 1 */ - 0, -}; - -/* Rev C1 Fan speed notes: - * - * The fan is controlled by 2 GPIOs on this board. The settings - * of the bits is as follow: - * - * GPIO 18 GPIO 19 Fan - * - * 0 0 stopped - * 0 1 low speed - * 1 0 high speed - * 1 1 don't do that (*) - * - * (*) I think the two bits control two feed-in resistors into a fixed - * PWN circuit, setting both bits will basically go a 'bit' faster - * than high speed, but d-link doesn't do it and you may get out of - * HW spec so don't do it. - */ - -/* - * On the DNS-323 A1 and B1 the following devices are attached via I2C: - * - * i2c addr | chip | description - * 0x3e | GMT G760Af | fan speed PWM controller - * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) - * 0x68 | ST M41T80 | RTC w/ alarm - */ -static struct i2c_board_info __initdata dns323ab_i2c_devices[] = { - { - I2C_BOARD_INFO("g760a", 0x3e), - }, { - I2C_BOARD_INFO("lm75", 0x48), - }, { - I2C_BOARD_INFO("m41t80", 0x68), - }, -}; - -/* - * On the DNS-323 C1 the following devices are attached via I2C: - * - * i2c addr | chip | description - * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) - * 0x68 | ST M41T80 | RTC w/ alarm - */ -static struct i2c_board_info __initdata dns323c_i2c_devices[] = { - { - I2C_BOARD_INFO("lm75", 0x48), - }, { - I2C_BOARD_INFO("m41t80", 0x68), - }, -}; - -/* DNS-323 rev. A specific power off method */ -static void dns323a_power_off(void) -{ - pr_info("DNS-323: Triggering power-off...\n"); - gpio_set_value(DNS323_GPIO_POWER_OFF, 1); -} - -/* DNS-323 rev B specific power off method */ -static void dns323b_power_off(void) -{ - pr_info("DNS-323: Triggering power-off...\n"); - /* Pin has to be changed to 1 and back to 0 to do actual power off. */ - gpio_set_value(DNS323_GPIO_POWER_OFF, 1); - mdelay(100); - gpio_set_value(DNS323_GPIO_POWER_OFF, 0); -} - -/* DNS-323 rev. C specific power off method */ -static void dns323c_power_off(void) -{ - pr_info("DNS-323: Triggering power-off...\n"); - gpio_set_value(DNS323C_GPIO_POWER_OFF, 1); -} - -static int dns323c_phy_fixup(struct phy_device *phy) -{ - phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS; - - return 0; -} - -static int __init dns323_identify_rev(void) -{ - u32 dev, rev, i, reg; - - pr_debug("DNS-323: Identifying board ... \n"); - - /* Rev A1 has a 5181 */ - orion5x_pcie_id(&dev, &rev); - if (dev == MV88F5181_DEV_ID) { - pr_debug("DNS-323: 5181 found, board is A1\n"); - return DNS323_REV_A1; - } - pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n"); - - /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is - * a bit gross but we want to do that without links into the eth - * driver so let's poke at it directly. We default to rev B1 in - * case the accesses fail - */ - -#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004) -#define SMI_BUSY 0x10000000 -#define SMI_READ_VALID 0x08000000 -#define SMI_OPCODE_READ 0x04000000 -#define SMI_OPCODE_WRITE 0x00000000 - - for (i = 0; i < 1000; i++) { - reg = readl(ETH_SMI_REG); - if (!(reg & SMI_BUSY)) - break; - } - if (i >= 1000) { - pr_warn("DNS-323: Timeout accessing PHY, assuming rev B1\n"); - return DNS323_REV_B1; - } - writel((3 << 21) /* phy ID reg */ | - (8 << 16) /* phy addr */ | - SMI_OPCODE_READ, ETH_SMI_REG); - for (i = 0; i < 1000; i++) { - reg = readl(ETH_SMI_REG); - if (reg & SMI_READ_VALID) - break; - } - if (i >= 1000) { - pr_warn("DNS-323: Timeout reading PHY, assuming rev B1\n"); - return DNS323_REV_B1; - } - pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff); - - /* Note: the Marvell tools mask the ID with 0x3f0 before comparison - * but I don't see that making a difference here, at least with - * any known Marvell PHY ID - */ - switch(reg & 0xfff0) { - case 0x0cc0: /* MV88E1111 */ - return DNS323_REV_B1; - case 0x0e10: /* MV88E1118 */ - return DNS323_REV_C1; - default: - pr_warn("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n", - reg & 0xffff); - } - return DNS323_REV_B1; -} - -static void __init dns323_init(void) -{ - /* Setup basic Orion functions. Need to be called early. */ - orion5x_init(); - - /* Identify revision */ - system_rev = dns323_identify_rev(); - pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev); - - /* Just to be tricky, the 5182 has a completely different - * set of MPP modes to the 5181. - */ - switch(system_rev) { - case DNS323_REV_A1: - orion5x_mpp_conf(dns323a_mpp_modes); - writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ - break; - case DNS323_REV_B1: - orion5x_mpp_conf(dns323b_mpp_modes); - break; - case DNS323_REV_C1: - orion5x_mpp_conf(dns323c_mpp_modes); - break; - } - - /* setup flash mapping - * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 - */ - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - DNS323_NOR_BOOT_BASE, - DNS323_NOR_BOOT_SIZE); - platform_device_register(&dns323_nor_flash); - - /* Sort out LEDs, Buttons and i2c devices */ - switch(system_rev) { - case DNS323_REV_A1: - /* The 5181 power LED is active low and requires - * DNS323_GPIO_LED_POWER1 to also be low. - */ - dns323ab_leds[0].active_low = 1; - gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); - gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); - fallthrough; - case DNS323_REV_B1: - i2c_register_board_info(0, dns323ab_i2c_devices, - ARRAY_SIZE(dns323ab_i2c_devices)); - break; - case DNS323_REV_C1: - /* Hookup LEDs & Buttons */ - dns323_gpio_leds.dev.platform_data = &dns323c_led_data; - dns323_button_device.dev.platform_data = &dns323c_button_data; - - /* Hookup i2c devices and fan driver */ - i2c_register_board_info(0, dns323c_i2c_devices, - ARRAY_SIZE(dns323c_i2c_devices)); - platform_device_register_simple("dns323c-fan", 0, NULL, 0); - - /* Register fixup for the PHY LEDs */ - if (!IS_BUILTIN(CONFIG_PHYLIB)) - break; - phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118, - MARVELL_PHY_ID_MASK, - dns323c_phy_fixup); - } - - platform_device_register(&dns323_gpio_leds); - platform_device_register(&dns323_button_device); - - /* - * Configure peripherals. - */ - if (dns323_read_mac_addr() < 0) - printk("DNS-323: Failed to read MAC address\n"); - orion5x_ehci0_init(); - orion5x_eth_init(&dns323_eth_data); - orion5x_i2c_init(); - orion5x_uart0_init(); - - /* Remaining GPIOs */ - switch(system_rev) { - case DNS323_REV_A1: - /* Poweroff GPIO */ - if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || - gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) - pr_err("DNS-323: failed to setup power-off GPIO\n"); - pm_power_off = dns323a_power_off; - break; - case DNS323_REV_B1: - /* 5182 built-in SATA init */ - orion5x_sata_init(&dns323_sata_data); - - /* The DNS323 rev B1 has flag to indicate the system is up. - * Without this flag set, power LED will flash and cannot be - * controlled via leds-gpio. - */ - if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0) - gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1); - - /* Poweroff GPIO */ - if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || - gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) - pr_err("DNS-323: failed to setup power-off GPIO\n"); - pm_power_off = dns323b_power_off; - break; - case DNS323_REV_C1: - /* 5182 built-in SATA init */ - orion5x_sata_init(&dns323_sata_data); - - /* Poweroff GPIO */ - if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 || - gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0) - pr_err("DNS-323: failed to setup power-off GPIO\n"); - pm_power_off = dns323c_power_off; - - /* Now, -this- should theorically be done by the sata_mv driver - * once I figure out what's going on there. Maybe the behaviour - * of the LEDs should be somewhat passed via the platform_data. - * for now, just whack the register and make the LEDs happy - * - * Note: AFAIK, rev B1 needs the same treatement but I'll let - * somebody else test it. - */ - writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); - break; - } -} - -/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ -MACHINE_START(DNS323, "D-Link DNS-323") - /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = dns323_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END -- 2.25.1 ^ permalink raw reply related [flat|nested] 91+ messages in thread
* [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-27 16:21 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-27 16:21 UTC (permalink / raw) To: soc, linux-arm-kernel, devicetree Cc: arnd, olof, robh+dt, krzysztof.kozlowski+dt, andrew, sebastian.hesselbarth, Mauri Sandberg Convert D-Link DNS-323 to use the device tree and remove associated mach file. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ arch/arm/mach-orion5x/Kconfig | 6 +- arch/arm/mach-orion5x/Makefile | 2 +- arch/arm/mach-orion5x/board-dns323.c | 118 +++ arch/arm/mach-orion5x/board-dt.c | 3 + arch/arm/mach-orion5x/common.h | 6 + arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- 11 files changed, 528 insertions(+), 728 deletions(-) create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts create mode 100644 arch/arm/mach-orion5x/board-dns323.c delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..c7c5c0b6c843 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -949,6 +949,9 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ dra71-evm.dtb \ dra76-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += \ + orion5x-dlink-dns323a1.dtb \ + orion5x-dlink-dns323b1.dtb \ + orion5x-dlink-dns323c1.dtb \ orion5x-kuroboxpro.dtb \ orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi new file mode 100644 index 000000000000..2b033d37cbf8 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/ { + model = "D-Link DNS-323"; + compatible = "dlink,dns323", "marvell,orion5x"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>; + + /delete-node/ devbus-cs0; + /delete-node/ devbus-cs1; + /delete-node/ devbus-cs2; + + internal-regs { + /delete-node/ dma-controller@60900; /* xor */ + /delete-node/ ehci@a0000; /* ehci1 */ + /delete-node/ serial@12100; /* uart1 */ + /delete-node/ spi@10600; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_gpio_keys>; + pinctrl-names = "default"; + + key-0 { + label = "Power button"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + key-1 { + label = "Reset button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_gpio_leds>; + pinctrl-names = "default"; + + led-0 { + label = "amber:right"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "amber:left"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "blue:power"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; + + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + timeout-ms = <3000>; + }; +}; + +&devbus_bootcs { + status = "okay"; + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x800000>; + bank-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "MTD1"; + reg = <0x000000 0x010000>; + read-only; + }; + + partition@10000 { + label = "MTD2"; + reg = <0x010000 0x010000>; + read-only; + }; + + partition@20000 { + label = "Linux Kernel"; + reg = <0x020000 0x180000>; + }; + + partition@1a0000 { + label = "File System"; + reg = <0x1a0000 0x630000>; + }; + + uboot: partition@7d0000 { + label = "U-boot"; + reg = <0x7d0000 0x030000>; + read-only; + }; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + + /* fan speed PWM */ + fan@3e { + compatible = "g760a"; + reg = <0x3e>; + }; + + /* temp sensor and thermal watchdog */ + temperature-sensor@48 { + compatible = "gmt,g751"; + reg = <0x48>; + }; + + /* RTC w/ alarm */ + rtc@68 { + compatible = "st,m41t80"; + reg = <0x68>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +ð { + status = "okay"; + pinctrl-0 = <&pmx_ge>; + pinctrl-names = "default"; +}; + +ðport { + phy-handle = <ðphy>; +}; + +&uart0 { + status = "okay"; +}; + +&pinctrl { + pmx_gpio_leds: pmx-gpio-leds { + marvell,pins = "mpp1", "mpp2", "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_misc: pmx-gpio-misc { + /* set marvell,pins in board file */ + marvell,function = "gpio"; + }; + + pmx_power_off: pmx-power-off { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_keys: pmx-gpio-keys { + marvell,pins = "mpp9", "mpp10"; + marvell,function = "gpio"; + }; + + pmx_ge: pmx-ge { + marvell,function = "ge"; + }; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts new file mode 100644 index 000000000000..73e7006ab5a7 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5181.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + compatible = "dlink,dns323a1", "dlink,dns323", "marvell,orion5x-88f5181", + "marvell,orion5x"; + + /delete-node/ sa-sram; /* crypto_sram */ + + soc { + internal-regs { + /delete-node/ crypto@90000; + /delete-node/ sata@80000; + }; + }; +}; + +&gpio0 { + pinctrl-0 = <&pmx_gpio_misc>; + pinctrl-names = "default"; + + /* The DNS323 rev A1 power LED requires GPIO 4 to be low. */ + pin_gpio0_4 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-high; + line-name = "Power led enable"; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_pci_pins>; + pinctrl-names = "default"; + + pmx_pci_pins: pmx-pci-pins { + marvell,pins = "mpp0"; + marvell,function = "pcie"; + }; +}; + +&pmx_gpio_misc { + marvell,pins = "mpp4"; +}; + +&pmx_ge { + marvell,pins = "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts new file mode 100644 index 000000000000..31251f64c573 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5182.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + compatible = "dlink,dns323b1", "dlink,dns323", "marvell,orion5x-88f5182", + "marvell,orion5x"; +}; + +&gpio0 { + pinctrl-0 = <&pmx_gpio_misc>; + pinctrl-names = "default"; + + /* The rev B1 has a flag to indicate the system is up. + * Without this flag set, power LED will flash and cannot be + * controlled via gpio-leds. + */ + pin_gpio0_3 { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-high; + line-name = "System up"; + }; +}; + +&pmx_gpio_misc { + marvell,pins = "mpp3"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts new file mode 100644 index 000000000000..c36af513ecd7 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5182.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + compatible = "dlink,dns323c1", "dlink,dns323", "marvell,orion5x-88f5182", + "marvell,orion5x"; + + fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_gpio_fan>; + pinctrl-names = "default"; + + gpios = <&gpio0 19 GPIO_ACTIVE_LOW + &gpio0 18 GPIO_ACTIVE_LOW>; + + gpio-fan,speed-map = <0 0 + 1000 1 + 2000 2>; + alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + /delete-node/ key-1; + + key-0 { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + led-0 { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + led-1 { + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + led-2 { + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; + +}; + +&i2c { + /delete-node/ fan@3e; +}; + +&pinctrl { + /delete-node/ pmx-gpio-misc; + + pmx_gpio_fan: pmx-gpio-fan { + marvell,pins = "mpp10", "mpp18", "mpp19"; + marvell,function = "gpio"; + }; +}; + +&pmx_gpio_leds { + marvell,pins = "mpp8", "mpp9", "mpp17"; +}; + +&pmx_power_off { + marvell,pins = "mpp2"; +}; + +&pmx_gpio_keys { + marvell,pins = "mpp1"; +}; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index c77f3b4e287b..65cd5307a460 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -55,9 +55,9 @@ config MACH_KUROBOX_PRO Say 'Y' here if you want your kernel to support the KuroBox Pro platform. -config MACH_DNS323 - bool "D-Link DNS-323" - select I2C_BOARDINFO if I2C +config MACH_DNS323_DT + bool "D-Link DNS-323 (Flattened Device Tree)" + select ARCH_ORION5X_DT help Say 'Y' here if you want your kernel to support the D-Link DNS-323 platform. diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 1a585a62d5e6..b8c0671fbd1c 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -8,7 +8,6 @@ obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_LINKSTATION_LS_HGL) += ls_hgl-setup.o -obj-$(CONFIG_MACH_DNS323) += dns323-setup.o obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o @@ -22,5 +21,6 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o +obj-$(CONFIG_MACH_DNS323_DT) += board-dns323.o obj-$(CONFIG_MACH_MSS2_DT) += board-mss2.o obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o diff --git a/arch/arm/mach-orion5x/board-dns323.c b/arch/arm/mach-orion5x/board-dns323.c new file mode 100644 index 000000000000..705ddb7b691a --- /dev/null +++ b/arch/arm/mach-orion5x/board-dns323.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + * Flattened Device Tree board initialization + * + * This is adapted from existing mach file and most of the source code is + * originally written by: + * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> + * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org> + */ + +#include <linux/of.h> +#include <linux/phy.h> +#include <linux/marvell_phy.h> +#include <asm/mach/pci.h> +#include "bridge-regs.h" +#include "common.h" + +/* Rev A1 and B1 */ +#define DNS323_GPIO_LED_RIGHT_AMBER 1 +#define DNS323_GPIO_LED_LEFT_AMBER 2 +#define DNS323_GPIO_SYSTEM_UP 3 +#define DNS323_GPIO_LED_POWER1 4 +#define DNS323_GPIO_LED_POWER2 5 +#define DNS323_GPIO_OVERTEMP 6 +#define DNS323_GPIO_RTC 7 +#define DNS323_GPIO_POWER_OFF 8 +#define DNS323_GPIO_KEY_POWER 9 +#define DNS323_GPIO_KEY_RESET 10 + +/* Rev C1 */ +#define DNS323C_GPIO_KEY_POWER 1 +#define DNS323C_GPIO_POWER_OFF 2 +#define DNS323C_GPIO_LED_RIGHT_AMBER 8 +#define DNS323C_GPIO_LED_LEFT_AMBER 9 +#define DNS323C_GPIO_LED_POWER 17 +#define DNS323C_GPIO_FAN_BIT1 18 +#define DNS323C_GPIO_FAN_BIT0 19 + +/* Exposed to userspace, do not change */ +enum { + DNS323_REV_A1, /* 0 */ + DNS323_REV_B1, /* 1 */ + DNS323_REV_C1, /* 2 */ +}; + +/**************************************************************************** + * PCI setup + */ + +static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + return -1; +} + +static struct hw_pci dns323_pci __initdata = { + .nr_controllers = 2, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = dns323_pci_map_irq, +}; + +static int __init dns323_pci_init(void) +{ + /* Rev B1 and C1 doesn't really use its PCI bus, and + * initialising PCI gets in the way of initialising the SATA + * controller. + */ + if (of_machine_is_compatible("dlink,dns323a1")) + pci_common_init(&dns323_pci); + + return 0; +} +subsys_initcall(dns323_pci_init); + +/**************************************************************************** + * Fix-ups + */ + +static int dns323c_phy_fixup(struct phy_device *phy) +{ + phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS; + + return 0; +} + +void __init dns323_init(void) +{ + if (of_machine_is_compatible("dlink,dns323a1")) { + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ + } else if (of_machine_is_compatible("dlink,dns323c1") && + IS_BUILTIN(CONFIG_PHYLIB)) { + /* Register fixup for the PHY LEDs */ + phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118, + MARVELL_PHY_ID_MASK, + dns323c_phy_fixup); + + /* Now, -this- should theorically be done by the sata_mv driver + * once I figure out what's going on there. Maybe the behaviour + * of the LEDs should be somewhat passed via the platform_data. + * for now, just whack the register and make the LEDs happy + * + * Note: AFAIK, rev B1 needs the same treatement but I'll let + * somebody else test it. + */ + writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); + } +} diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 3d36f1d95196..279194483fcf 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -60,6 +60,9 @@ static void __init orion5x_dt_init(void) cpu_idle_poll_ctrl(true); } + if (of_machine_is_compatible("dlink,dns323")) + dns323_init(); + if (of_machine_is_compatible("maxtor,shared-storage-2")) mss2_init(); diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index eb96009e21c4..ac92b67bf9ec 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -75,6 +75,12 @@ extern void mss2_init(void); static inline void mss2_init(void) {} #endif +#ifdef CONFIG_MACH_DNS323_DT +extern void dns323_init(void); +#else +static inline void dns323_init(void) {} +#endif + /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c deleted file mode 100644 index 87cb47220e82..000000000000 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ /dev/null @@ -1,724 +0,0 @@ -/* - * arch/arm/mach-orion5x/dns323-setup.c - * - * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> - * - * Support for HW Rev C1: - * - * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/mtd/physmap.h> -#include <linux/mv643xx_eth.h> -#include <linux/leds.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/ata_platform.h> -#include <linux/phy.h> -#include <linux/marvell_phy.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> -#include <asm/system_info.h> -#include <plat/orion-gpio.h> -#include "orion5x.h" -#include "common.h" -#include "mpp.h" - -/* Rev A1 and B1 */ -#define DNS323_GPIO_LED_RIGHT_AMBER 1 -#define DNS323_GPIO_LED_LEFT_AMBER 2 -#define DNS323_GPIO_SYSTEM_UP 3 -#define DNS323_GPIO_LED_POWER1 4 -#define DNS323_GPIO_LED_POWER2 5 -#define DNS323_GPIO_OVERTEMP 6 -#define DNS323_GPIO_RTC 7 -#define DNS323_GPIO_POWER_OFF 8 -#define DNS323_GPIO_KEY_POWER 9 -#define DNS323_GPIO_KEY_RESET 10 - -/* Rev C1 */ -#define DNS323C_GPIO_KEY_POWER 1 -#define DNS323C_GPIO_POWER_OFF 2 -#define DNS323C_GPIO_LED_RIGHT_AMBER 8 -#define DNS323C_GPIO_LED_LEFT_AMBER 9 -#define DNS323C_GPIO_LED_POWER 17 -#define DNS323C_GPIO_FAN_BIT1 18 -#define DNS323C_GPIO_FAN_BIT0 19 - -/* Exposed to userspace, do not change */ -enum { - DNS323_REV_A1, /* 0 */ - DNS323_REV_B1, /* 1 */ - DNS323_REV_C1, /* 2 */ -}; - - -/**************************************************************************** - * PCI setup - */ - -static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - return -1; -} - -static struct hw_pci dns323_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = dns323_pci_map_irq, -}; - -static int __init dns323_pci_init(void) -{ - /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI - * gets in the way of initialising the SATA controller. - */ - if (machine_is_dns323() && system_rev == DNS323_REV_A1) - pci_common_init(&dns323_pci); - - return 0; -} - -subsys_initcall(dns323_pci_init); - -/**************************************************************************** - * 8MiB NOR flash (Spansion S29GL064M90TFIR4) - * - * Layout as used by D-Link: - * 0x00000000-0x00010000 : "MTD1" - * 0x00010000-0x00020000 : "MTD2" - * 0x00020000-0x001a0000 : "Linux Kernel" - * 0x001a0000-0x007d0000 : "File System" - * 0x007d0000-0x00800000 : "u-boot" - */ - -#define DNS323_NOR_BOOT_BASE 0xf4000000 -#define DNS323_NOR_BOOT_SIZE SZ_8M - -static struct mtd_partition dns323_partitions[] = { - { - .name = "MTD1", - .size = 0x00010000, - .offset = 0, - }, { - .name = "MTD2", - .size = 0x00010000, - .offset = 0x00010000, - }, { - .name = "Linux Kernel", - .size = 0x00180000, - .offset = 0x00020000, - }, { - .name = "File System", - .size = 0x00630000, - .offset = 0x001A0000, - }, { - .name = "u-boot", - .size = 0x00030000, - .offset = 0x007d0000, - }, -}; - -static struct physmap_flash_data dns323_nor_flash_data = { - .width = 1, - .parts = dns323_partitions, - .nr_parts = ARRAY_SIZE(dns323_partitions) -}; - -static struct resource dns323_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = DNS323_NOR_BOOT_BASE, - .end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device dns323_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &dns323_nor_flash_data, - }, - .resource = &dns323_nor_flash_resource, - .num_resources = 1, -}; - -/**************************************************************************** - * Ethernet - */ - -static struct mv643xx_eth_platform_data dns323_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these - * functions be kept somewhere? - */ -static int __init dns323_parse_hex_nibble(char n) -{ - if (n >= '0' && n <= '9') - return n - '0'; - - if (n >= 'A' && n <= 'F') - return n - 'A' + 10; - - if (n >= 'a' && n <= 'f') - return n - 'a' + 10; - - return -1; -} - -static int __init dns323_parse_hex_byte(const char *b) -{ - int hi; - int lo; - - hi = dns323_parse_hex_nibble(b[0]); - lo = dns323_parse_hex_nibble(b[1]); - - if (hi < 0 || lo < 0) - return -1; - - return (hi << 4) | lo; -} - -static int __init dns323_read_mac_addr(void) -{ - u_int8_t addr[6]; - int i; - char *mac_page; - - /* MAC address is stored as a regular ol' string in /dev/mtdblock4 - * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80). - */ - mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024); - if (!mac_page) - return -ENOMEM; - - /* Sanity check the string we're looking at */ - for (i = 0; i < 5; i++) { - if (*(mac_page + (i * 3) + 2) != ':') { - goto error_fail; - } - } - - for (i = 0; i < 6; i++) { - int byte; - - byte = dns323_parse_hex_byte(mac_page + (i * 3)); - if (byte < 0) { - goto error_fail; - } - - addr[i] = byte; - } - - iounmap(mac_page); - printk("DNS-323: Found ethernet MAC address: %pM\n", addr); - - memcpy(dns323_eth_data.mac_addr, addr, 6); - - return 0; - -error_fail: - iounmap(mac_page); - return -EINVAL; -} - -/**************************************************************************** - * GPIO LEDs (simple - doesn't use hardware blinking support) - */ - -static struct gpio_led dns323ab_leds[] = { - { - .name = "power:blue", - .gpio = DNS323_GPIO_LED_POWER2, - .default_trigger = "default-on", - }, { - .name = "right:amber", - .gpio = DNS323_GPIO_LED_RIGHT_AMBER, - .active_low = 1, - }, { - .name = "left:amber", - .gpio = DNS323_GPIO_LED_LEFT_AMBER, - .active_low = 1, - }, -}; - - -static struct gpio_led dns323c_leds[] = { - { - .name = "power:blue", - .gpio = DNS323C_GPIO_LED_POWER, - .default_trigger = "timer", - .active_low = 1, - }, { - .name = "right:amber", - .gpio = DNS323C_GPIO_LED_RIGHT_AMBER, - .active_low = 1, - }, { - .name = "left:amber", - .gpio = DNS323C_GPIO_LED_LEFT_AMBER, - .active_low = 1, - }, -}; - - -static struct gpio_led_platform_data dns323ab_led_data = { - .num_leds = ARRAY_SIZE(dns323ab_leds), - .leds = dns323ab_leds, - .gpio_blink_set = orion_gpio_led_blink_set, -}; - -static struct gpio_led_platform_data dns323c_led_data = { - .num_leds = ARRAY_SIZE(dns323c_leds), - .leds = dns323c_leds, - .gpio_blink_set = orion_gpio_led_blink_set, -}; - -static struct platform_device dns323_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &dns323ab_led_data, - }, -}; - -/**************************************************************************** - * GPIO Attached Keys - */ - -static struct gpio_keys_button dns323ab_buttons[] = { - { - .code = KEY_RESTART, - .gpio = DNS323_GPIO_KEY_RESET, - .desc = "Reset Button", - .active_low = 1, - }, { - .code = KEY_POWER, - .gpio = DNS323_GPIO_KEY_POWER, - .desc = "Power Button", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data dns323ab_button_data = { - .buttons = dns323ab_buttons, - .nbuttons = ARRAY_SIZE(dns323ab_buttons), -}; - -static struct gpio_keys_button dns323c_buttons[] = { - { - .code = KEY_POWER, - .gpio = DNS323C_GPIO_KEY_POWER, - .desc = "Power Button", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data dns323c_button_data = { - .buttons = dns323c_buttons, - .nbuttons = ARRAY_SIZE(dns323c_buttons), -}; - -static struct platform_device dns323_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &dns323ab_button_data, - }, -}; - -/***************************************************************************** - * SATA - */ -static struct mv_sata_platform_data dns323_sata_data = { - .n_ports = 2, -}; - -/**************************************************************************** - * General Setup - */ -static unsigned int dns323a_mpp_modes[] __initdata = { - MPP0_PCIE_RST_OUTn, - MPP1_GPIO, /* right amber LED (sata ch0) */ - MPP2_GPIO, /* left amber LED (sata ch1) */ - MPP3_UNUSED, - MPP4_GPIO, /* power button LED */ - MPP5_GPIO, /* power button LED */ - MPP6_GPIO, /* GMT G751-2f overtemp */ - MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */ - MPP8_GPIO, /* triggers power off */ - MPP9_GPIO, /* power button switch */ - MPP10_GPIO, /* reset button switch */ - MPP11_UNUSED, - MPP12_UNUSED, - MPP13_UNUSED, - MPP14_UNUSED, - MPP15_UNUSED, - MPP16_UNUSED, - MPP17_UNUSED, - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static unsigned int dns323b_mpp_modes[] __initdata = { - MPP0_UNUSED, - MPP1_GPIO, /* right amber LED (sata ch0) */ - MPP2_GPIO, /* left amber LED (sata ch1) */ - MPP3_GPIO, /* system up flag */ - MPP4_GPIO, /* power button LED */ - MPP5_GPIO, /* power button LED */ - MPP6_GPIO, /* GMT G751-2f overtemp */ - MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */ - MPP8_GPIO, /* triggers power off */ - MPP9_GPIO, /* power button switch */ - MPP10_GPIO, /* reset button switch */ - MPP11_UNUSED, - MPP12_SATA_LED, - MPP13_SATA_LED, - MPP14_SATA_LED, - MPP15_SATA_LED, - MPP16_UNUSED, - MPP17_UNUSED, - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static unsigned int dns323c_mpp_modes[] __initdata = { - MPP0_GPIO, /* ? input */ - MPP1_GPIO, /* input power switch (0 = pressed) */ - MPP2_GPIO, /* output power off */ - MPP3_UNUSED, /* ? output */ - MPP4_UNUSED, /* ? output */ - MPP5_UNUSED, /* ? output */ - MPP6_UNUSED, /* ? output */ - MPP7_UNUSED, /* ? output */ - MPP8_GPIO, /* i/o right amber LED */ - MPP9_GPIO, /* i/o left amber LED */ - MPP10_GPIO, /* input */ - MPP11_UNUSED, - MPP12_SATA_LED, - MPP13_SATA_LED, - MPP14_SATA_LED, - MPP15_SATA_LED, - MPP16_UNUSED, - MPP17_GPIO, /* power button LED */ - MPP18_GPIO, /* fan speed bit 0 */ - MPP19_GPIO, /* fan speed bit 1 */ - 0, -}; - -/* Rev C1 Fan speed notes: - * - * The fan is controlled by 2 GPIOs on this board. The settings - * of the bits is as follow: - * - * GPIO 18 GPIO 19 Fan - * - * 0 0 stopped - * 0 1 low speed - * 1 0 high speed - * 1 1 don't do that (*) - * - * (*) I think the two bits control two feed-in resistors into a fixed - * PWN circuit, setting both bits will basically go a 'bit' faster - * than high speed, but d-link doesn't do it and you may get out of - * HW spec so don't do it. - */ - -/* - * On the DNS-323 A1 and B1 the following devices are attached via I2C: - * - * i2c addr | chip | description - * 0x3e | GMT G760Af | fan speed PWM controller - * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) - * 0x68 | ST M41T80 | RTC w/ alarm - */ -static struct i2c_board_info __initdata dns323ab_i2c_devices[] = { - { - I2C_BOARD_INFO("g760a", 0x3e), - }, { - I2C_BOARD_INFO("lm75", 0x48), - }, { - I2C_BOARD_INFO("m41t80", 0x68), - }, -}; - -/* - * On the DNS-323 C1 the following devices are attached via I2C: - * - * i2c addr | chip | description - * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) - * 0x68 | ST M41T80 | RTC w/ alarm - */ -static struct i2c_board_info __initdata dns323c_i2c_devices[] = { - { - I2C_BOARD_INFO("lm75", 0x48), - }, { - I2C_BOARD_INFO("m41t80", 0x68), - }, -}; - -/* DNS-323 rev. A specific power off method */ -static void dns323a_power_off(void) -{ - pr_info("DNS-323: Triggering power-off...\n"); - gpio_set_value(DNS323_GPIO_POWER_OFF, 1); -} - -/* DNS-323 rev B specific power off method */ -static void dns323b_power_off(void) -{ - pr_info("DNS-323: Triggering power-off...\n"); - /* Pin has to be changed to 1 and back to 0 to do actual power off. */ - gpio_set_value(DNS323_GPIO_POWER_OFF, 1); - mdelay(100); - gpio_set_value(DNS323_GPIO_POWER_OFF, 0); -} - -/* DNS-323 rev. C specific power off method */ -static void dns323c_power_off(void) -{ - pr_info("DNS-323: Triggering power-off...\n"); - gpio_set_value(DNS323C_GPIO_POWER_OFF, 1); -} - -static int dns323c_phy_fixup(struct phy_device *phy) -{ - phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS; - - return 0; -} - -static int __init dns323_identify_rev(void) -{ - u32 dev, rev, i, reg; - - pr_debug("DNS-323: Identifying board ... \n"); - - /* Rev A1 has a 5181 */ - orion5x_pcie_id(&dev, &rev); - if (dev == MV88F5181_DEV_ID) { - pr_debug("DNS-323: 5181 found, board is A1\n"); - return DNS323_REV_A1; - } - pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n"); - - /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is - * a bit gross but we want to do that without links into the eth - * driver so let's poke at it directly. We default to rev B1 in - * case the accesses fail - */ - -#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004) -#define SMI_BUSY 0x10000000 -#define SMI_READ_VALID 0x08000000 -#define SMI_OPCODE_READ 0x04000000 -#define SMI_OPCODE_WRITE 0x00000000 - - for (i = 0; i < 1000; i++) { - reg = readl(ETH_SMI_REG); - if (!(reg & SMI_BUSY)) - break; - } - if (i >= 1000) { - pr_warn("DNS-323: Timeout accessing PHY, assuming rev B1\n"); - return DNS323_REV_B1; - } - writel((3 << 21) /* phy ID reg */ | - (8 << 16) /* phy addr */ | - SMI_OPCODE_READ, ETH_SMI_REG); - for (i = 0; i < 1000; i++) { - reg = readl(ETH_SMI_REG); - if (reg & SMI_READ_VALID) - break; - } - if (i >= 1000) { - pr_warn("DNS-323: Timeout reading PHY, assuming rev B1\n"); - return DNS323_REV_B1; - } - pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff); - - /* Note: the Marvell tools mask the ID with 0x3f0 before comparison - * but I don't see that making a difference here, at least with - * any known Marvell PHY ID - */ - switch(reg & 0xfff0) { - case 0x0cc0: /* MV88E1111 */ - return DNS323_REV_B1; - case 0x0e10: /* MV88E1118 */ - return DNS323_REV_C1; - default: - pr_warn("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n", - reg & 0xffff); - } - return DNS323_REV_B1; -} - -static void __init dns323_init(void) -{ - /* Setup basic Orion functions. Need to be called early. */ - orion5x_init(); - - /* Identify revision */ - system_rev = dns323_identify_rev(); - pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev); - - /* Just to be tricky, the 5182 has a completely different - * set of MPP modes to the 5181. - */ - switch(system_rev) { - case DNS323_REV_A1: - orion5x_mpp_conf(dns323a_mpp_modes); - writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ - break; - case DNS323_REV_B1: - orion5x_mpp_conf(dns323b_mpp_modes); - break; - case DNS323_REV_C1: - orion5x_mpp_conf(dns323c_mpp_modes); - break; - } - - /* setup flash mapping - * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 - */ - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - DNS323_NOR_BOOT_BASE, - DNS323_NOR_BOOT_SIZE); - platform_device_register(&dns323_nor_flash); - - /* Sort out LEDs, Buttons and i2c devices */ - switch(system_rev) { - case DNS323_REV_A1: - /* The 5181 power LED is active low and requires - * DNS323_GPIO_LED_POWER1 to also be low. - */ - dns323ab_leds[0].active_low = 1; - gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); - gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); - fallthrough; - case DNS323_REV_B1: - i2c_register_board_info(0, dns323ab_i2c_devices, - ARRAY_SIZE(dns323ab_i2c_devices)); - break; - case DNS323_REV_C1: - /* Hookup LEDs & Buttons */ - dns323_gpio_leds.dev.platform_data = &dns323c_led_data; - dns323_button_device.dev.platform_data = &dns323c_button_data; - - /* Hookup i2c devices and fan driver */ - i2c_register_board_info(0, dns323c_i2c_devices, - ARRAY_SIZE(dns323c_i2c_devices)); - platform_device_register_simple("dns323c-fan", 0, NULL, 0); - - /* Register fixup for the PHY LEDs */ - if (!IS_BUILTIN(CONFIG_PHYLIB)) - break; - phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118, - MARVELL_PHY_ID_MASK, - dns323c_phy_fixup); - } - - platform_device_register(&dns323_gpio_leds); - platform_device_register(&dns323_button_device); - - /* - * Configure peripherals. - */ - if (dns323_read_mac_addr() < 0) - printk("DNS-323: Failed to read MAC address\n"); - orion5x_ehci0_init(); - orion5x_eth_init(&dns323_eth_data); - orion5x_i2c_init(); - orion5x_uart0_init(); - - /* Remaining GPIOs */ - switch(system_rev) { - case DNS323_REV_A1: - /* Poweroff GPIO */ - if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || - gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) - pr_err("DNS-323: failed to setup power-off GPIO\n"); - pm_power_off = dns323a_power_off; - break; - case DNS323_REV_B1: - /* 5182 built-in SATA init */ - orion5x_sata_init(&dns323_sata_data); - - /* The DNS323 rev B1 has flag to indicate the system is up. - * Without this flag set, power LED will flash and cannot be - * controlled via leds-gpio. - */ - if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0) - gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1); - - /* Poweroff GPIO */ - if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || - gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) - pr_err("DNS-323: failed to setup power-off GPIO\n"); - pm_power_off = dns323b_power_off; - break; - case DNS323_REV_C1: - /* 5182 built-in SATA init */ - orion5x_sata_init(&dns323_sata_data); - - /* Poweroff GPIO */ - if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 || - gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0) - pr_err("DNS-323: failed to setup power-off GPIO\n"); - pm_power_off = dns323c_power_off; - - /* Now, -this- should theorically be done by the sata_mv driver - * once I figure out what's going on there. Maybe the behaviour - * of the LEDs should be somewhat passed via the platform_data. - * for now, just whack the register and make the LEDs happy - * - * Note: AFAIK, rev B1 needs the same treatement but I'll let - * somebody else test it. - */ - writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); - break; - } -} - -/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ -MACHINE_START(DNS323, "D-Link DNS-323") - /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = dns323_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-27 16:21 ` Mauri Sandberg @ 2022-04-27 18:12 ` Arnd Bergmann -1 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-04-27 18:12 UTC (permalink / raw) To: Mauri Sandberg Cc: SoC Team, Linux ARM, DTML, Arnd Bergmann, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > Convert D-Link DNS-323 to use the device tree and remove associated > mach file. > > Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> > --- > arch/arm/boot/dts/Makefile | 3 + > arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ > arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ > arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + > arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ > arch/arm/mach-orion5x/Kconfig | 6 +- > arch/arm/mach-orion5x/Makefile | 2 +- > arch/arm/mach-orion5x/board-dns323.c | 118 +++ > arch/arm/mach-orion5x/board-dt.c | 3 + > arch/arm/mach-orion5x/common.h | 6 + > arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- > 11 files changed, 528 insertions(+), 728 deletions(-) > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts > create mode 100644 arch/arm/mach-orion5x/board-dns323.c > delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c Having the combined patch is generally fine for review, but for actually merging it, I would prefer splitting the new DT from the code removal, as I send these through different trees to Linus. Arnd ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-27 18:12 ` Arnd Bergmann 0 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-04-27 18:12 UTC (permalink / raw) To: Mauri Sandberg Cc: SoC Team, Linux ARM, DTML, Arnd Bergmann, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > Convert D-Link DNS-323 to use the device tree and remove associated > mach file. > > Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> > --- > arch/arm/boot/dts/Makefile | 3 + > arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ > arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ > arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + > arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ > arch/arm/mach-orion5x/Kconfig | 6 +- > arch/arm/mach-orion5x/Makefile | 2 +- > arch/arm/mach-orion5x/board-dns323.c | 118 +++ > arch/arm/mach-orion5x/board-dt.c | 3 + > arch/arm/mach-orion5x/common.h | 6 + > arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- > 11 files changed, 528 insertions(+), 728 deletions(-) > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts > create mode 100644 arch/arm/mach-orion5x/board-dns323.c > delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c Having the combined patch is generally fine for review, but for actually merging it, I would prefer splitting the new DT from the code removal, as I send these through different trees to Linus. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-27 18:12 ` Arnd Bergmann @ 2022-04-28 20:06 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-28 20:06 UTC (permalink / raw) To: Arnd Bergmann Cc: SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, maukka On 27.4.2022 21.12, Arnd Bergmann wrote: > On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >> >> Convert D-Link DNS-323 to use the device tree and remove associated >> mach file. >> >> Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> >> --- >> arch/arm/boot/dts/Makefile | 3 + >> arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ >> arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ >> arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + >> arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ >> arch/arm/mach-orion5x/Kconfig | 6 +- >> arch/arm/mach-orion5x/Makefile | 2 +- >> arch/arm/mach-orion5x/board-dns323.c | 118 +++ >> arch/arm/mach-orion5x/board-dt.c | 3 + >> arch/arm/mach-orion5x/common.h | 6 + >> arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- >> 11 files changed, 528 insertions(+), 728 deletions(-) >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts >> create mode 100644 arch/arm/mach-orion5x/board-dns323.c >> delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c > > Having the combined patch is generally fine for review, but for actually > merging it, I would prefer splitting the new DT from the code removal, > as I send these through different trees to Linus. You know, I had them initially in separate patches but then I looked at the existing commit history and at least a few ones were in a single commit so I merged them. :) Will split this in two in the next iteration. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 20:06 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-28 20:06 UTC (permalink / raw) To: Arnd Bergmann Cc: SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, maukka On 27.4.2022 21.12, Arnd Bergmann wrote: > On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >> >> Convert D-Link DNS-323 to use the device tree and remove associated >> mach file. >> >> Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> >> --- >> arch/arm/boot/dts/Makefile | 3 + >> arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ >> arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ >> arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + >> arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ >> arch/arm/mach-orion5x/Kconfig | 6 +- >> arch/arm/mach-orion5x/Makefile | 2 +- >> arch/arm/mach-orion5x/board-dns323.c | 118 +++ >> arch/arm/mach-orion5x/board-dt.c | 3 + >> arch/arm/mach-orion5x/common.h | 6 + >> arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- >> 11 files changed, 528 insertions(+), 728 deletions(-) >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts >> create mode 100644 arch/arm/mach-orion5x/board-dns323.c >> delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c > > Having the combined patch is generally fine for review, but for actually > merging it, I would prefer splitting the new DT from the code removal, > as I send these through different trees to Linus. You know, I had them initially in separate patches but then I looked at the existing commit history and at least a few ones were in a single commit so I merged them. :) Will split this in two in the next iteration. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-28 20:06 ` Mauri Sandberg @ 2022-04-28 20:47 ` Arnd Bergmann -1 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-04-28 20:47 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On Thu, Apr 28, 2022 at 10:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > You know, I had them initially in separate patches but then I looked at > the existing commit history and at least a few ones were in a single > commit so I merged them. :) Just for context, we sometimes do a mass-conversion in a separate branch when there are a lot of changes that touch both DT and source files. If you only do a single board, I would not make that a separate top-level pull request, so it has to fit into the regular branches. Arnd ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 20:47 ` Arnd Bergmann 0 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-04-28 20:47 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On Thu, Apr 28, 2022 at 10:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > You know, I had them initially in separate patches but then I looked at > the existing commit history and at least a few ones were in a single > commit so I merged them. :) Just for context, we sometimes do a mass-conversion in a separate branch when there are a lot of changes that touch both DT and source files. If you only do a single board, I would not make that a separate top-level pull request, so it has to fit into the regular branches. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-27 16:21 ` Mauri Sandberg @ 2022-04-28 7:13 ` Krzysztof Kozlowski -1 siblings, 0 replies; 91+ messages in thread From: Krzysztof Kozlowski @ 2022-04-28 7:13 UTC (permalink / raw) To: Mauri Sandberg, soc, linux-arm-kernel, devicetree Cc: arnd, olof, robh+dt, krzysztof.kozlowski+dt, andrew, sebastian.hesselbarth On 27/04/2022 18:21, Mauri Sandberg wrote: > Convert D-Link DNS-323 to use the device tree and remove associated > mach file. > Thank you for your patch. There is something to discuss/improve. > Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> > --- > arch/arm/boot/dts/Makefile | 3 + > arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ > arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ > arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + > arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ > arch/arm/mach-orion5x/Kconfig | 6 +- > arch/arm/mach-orion5x/Makefile | 2 +- > arch/arm/mach-orion5x/board-dns323.c | 118 +++ > arch/arm/mach-orion5x/board-dt.c | 3 + > arch/arm/mach-orion5x/common.h | 6 + > arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- > 11 files changed, 528 insertions(+), 728 deletions(-) > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts > create mode 100644 arch/arm/mach-orion5x/board-dns323.c > delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c DTS goes separately. > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 7c16f8a2b738..c7c5c0b6c843 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -949,6 +949,9 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ > dra71-evm.dtb \ > dra76-evm.dtb > dtb-$(CONFIG_ARCH_ORION5X) += \ > + orion5x-dlink-dns323a1.dtb \ > + orion5x-dlink-dns323b1.dtb \ > + orion5x-dlink-dns323c1.dtb \ > orion5x-kuroboxpro.dtb \ > orion5x-lacie-d2-network.dtb \ > orion5x-lacie-ethernet-disk-mini-v2.dtb \ > diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi > new file mode 100644 > index 000000000000..2b033d37cbf8 > --- /dev/null > +++ b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi > @@ -0,0 +1,217 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> > + * > + */ > + > +/ { > + model = "D-Link DNS-323"; > + compatible = "dlink,dns323", "marvell,orion5x"; > You need to also document the compatibles in bindings file for boards. It would be nice to convert Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt to DT Schema (see armada-7k-8k.yaml for example), but it is not a requirement. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 7:13 ` Krzysztof Kozlowski 0 siblings, 0 replies; 91+ messages in thread From: Krzysztof Kozlowski @ 2022-04-28 7:13 UTC (permalink / raw) To: Mauri Sandberg, soc, linux-arm-kernel, devicetree Cc: arnd, olof, robh+dt, krzysztof.kozlowski+dt, andrew, sebastian.hesselbarth On 27/04/2022 18:21, Mauri Sandberg wrote: > Convert D-Link DNS-323 to use the device tree and remove associated > mach file. > Thank you for your patch. There is something to discuss/improve. > Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> > --- > arch/arm/boot/dts/Makefile | 3 + > arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ > arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ > arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + > arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ > arch/arm/mach-orion5x/Kconfig | 6 +- > arch/arm/mach-orion5x/Makefile | 2 +- > arch/arm/mach-orion5x/board-dns323.c | 118 +++ > arch/arm/mach-orion5x/board-dt.c | 3 + > arch/arm/mach-orion5x/common.h | 6 + > arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- > 11 files changed, 528 insertions(+), 728 deletions(-) > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts > create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts > create mode 100644 arch/arm/mach-orion5x/board-dns323.c > delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c DTS goes separately. > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 7c16f8a2b738..c7c5c0b6c843 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -949,6 +949,9 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ > dra71-evm.dtb \ > dra76-evm.dtb > dtb-$(CONFIG_ARCH_ORION5X) += \ > + orion5x-dlink-dns323a1.dtb \ > + orion5x-dlink-dns323b1.dtb \ > + orion5x-dlink-dns323c1.dtb \ > orion5x-kuroboxpro.dtb \ > orion5x-lacie-d2-network.dtb \ > orion5x-lacie-ethernet-disk-mini-v2.dtb \ > diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi > new file mode 100644 > index 000000000000..2b033d37cbf8 > --- /dev/null > +++ b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi > @@ -0,0 +1,217 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> > + * > + */ > + > +/ { > + model = "D-Link DNS-323"; > + compatible = "dlink,dns323", "marvell,orion5x"; > You need to also document the compatibles in bindings file for boards. It would be nice to convert Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt to DT Schema (see armada-7k-8k.yaml for example), but it is not a requirement. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-28 7:13 ` Krzysztof Kozlowski @ 2022-04-28 20:09 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-28 20:09 UTC (permalink / raw) To: Krzysztof Kozlowski, soc, linux-arm-kernel, devicetree Cc: arnd, olof, robh+dt, krzysztof.kozlowski+dt, andrew, sebastian.hesselbarth, maukka Hello Krzysztof and thanks for your feedback On 28.4.2022 10.13, Krzysztof Kozlowski wrote: > On 27/04/2022 18:21, Mauri Sandberg wrote: >> Convert D-Link DNS-323 to use the device tree and remove associated >> mach file. >> > > Thank you for your patch. There is something to discuss/improve. > >> Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> >> --- >> arch/arm/boot/dts/Makefile | 3 + >> arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ >> arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ >> arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + >> arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ >> arch/arm/mach-orion5x/Kconfig | 6 +- >> arch/arm/mach-orion5x/Makefile | 2 +- >> arch/arm/mach-orion5x/board-dns323.c | 118 +++ >> arch/arm/mach-orion5x/board-dt.c | 3 + >> arch/arm/mach-orion5x/common.h | 6 + >> arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- >> 11 files changed, 528 insertions(+), 728 deletions(-) >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts >> create mode 100644 arch/arm/mach-orion5x/board-dns323.c >> delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c > > DTS goes separately. Duly noted. :) > >> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index 7c16f8a2b738..c7c5c0b6c843 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -949,6 +949,9 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ >> dra71-evm.dtb \ >> dra76-evm.dtb >> dtb-$(CONFIG_ARCH_ORION5X) += \ >> + orion5x-dlink-dns323a1.dtb \ >> + orion5x-dlink-dns323b1.dtb \ >> + orion5x-dlink-dns323c1.dtb \ >> orion5x-kuroboxpro.dtb \ >> orion5x-lacie-d2-network.dtb \ >> orion5x-lacie-ethernet-disk-mini-v2.dtb \ >> diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi >> new file mode 100644 >> index 000000000000..2b033d37cbf8 >> --- /dev/null >> +++ b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi >> @@ -0,0 +1,217 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> >> + * >> + */ >> + >> +/ { >> + model = "D-Link DNS-323"; >> + compatible = "dlink,dns323", "marvell,orion5x"; >> > > You need to also document the compatibles in bindings file for boards. > It would be nice to convert > Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt to DT > Schema (see armada-7k-8k.yaml for example), but it is not a requirement. Ah, I hadn't even noticed them before. Will look into this. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 1/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 20:09 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-28 20:09 UTC (permalink / raw) To: Krzysztof Kozlowski, soc, linux-arm-kernel, devicetree Cc: arnd, olof, robh+dt, krzysztof.kozlowski+dt, andrew, sebastian.hesselbarth, maukka Hello Krzysztof and thanks for your feedback On 28.4.2022 10.13, Krzysztof Kozlowski wrote: > On 27/04/2022 18:21, Mauri Sandberg wrote: >> Convert D-Link DNS-323 to use the device tree and remove associated >> mach file. >> > > Thank you for your patch. There is something to discuss/improve. > >> Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> >> --- >> arch/arm/boot/dts/Makefile | 3 + >> arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 217 ++++++ >> arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 59 ++ >> arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 38 + >> arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 80 ++ >> arch/arm/mach-orion5x/Kconfig | 6 +- >> arch/arm/mach-orion5x/Makefile | 2 +- >> arch/arm/mach-orion5x/board-dns323.c | 118 +++ >> arch/arm/mach-orion5x/board-dt.c | 3 + >> arch/arm/mach-orion5x/common.h | 6 + >> arch/arm/mach-orion5x/dns323-setup.c | 724 ------------------- >> 11 files changed, 528 insertions(+), 728 deletions(-) >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts >> create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts >> create mode 100644 arch/arm/mach-orion5x/board-dns323.c >> delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c > > DTS goes separately. Duly noted. :) > >> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index 7c16f8a2b738..c7c5c0b6c843 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -949,6 +949,9 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ >> dra71-evm.dtb \ >> dra76-evm.dtb >> dtb-$(CONFIG_ARCH_ORION5X) += \ >> + orion5x-dlink-dns323a1.dtb \ >> + orion5x-dlink-dns323b1.dtb \ >> + orion5x-dlink-dns323c1.dtb \ >> orion5x-kuroboxpro.dtb \ >> orion5x-lacie-d2-network.dtb \ >> orion5x-lacie-ethernet-disk-mini-v2.dtb \ >> diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi >> new file mode 100644 >> index 000000000000..2b033d37cbf8 >> --- /dev/null >> +++ b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi >> @@ -0,0 +1,217 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> >> + * >> + */ >> + >> +/ { >> + model = "D-Link DNS-323"; >> + compatible = "dlink,dns323", "marvell,orion5x"; >> > > You need to also document the compatibles in bindings file for boards. > It would be nice to convert > Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt to DT > Schema (see armada-7k-8k.yaml for example), but it is not a requirement. Ah, I hadn't even noticed them before. Will look into this. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-27 16:21 ` Mauri Sandberg @ 2022-04-27 18:10 ` Arnd Bergmann -1 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-04-27 18:10 UTC (permalink / raw) To: Mauri Sandberg Cc: SoC Team, Linux ARM, DTML, Arnd Bergmann, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > Hello all, > > I am making an attempt to create a device tree for D-Link DNS-323 devices > but I am falling short on a few specific details. I am requesting a > general review of the device tree files. I have access to DNS-323 rev A1 > only and the B1 and C1 need to be tested separately, so I am reaching out > to people who might have them. Hi Mauri, It's really nice to see some progress on this! I don't have the hardware, but I'll try to answer some of your questions anyway. > The questions that I have at the moment are below. > > - some of resulting IRQs are different from what was requested in device tree > - logs say NR_IRQS is different from mach file one This is all normal: with a board file, all on-board IRQs are statically assigned to fixed numbers. With DT based boot, IRQ controllers usually define their own IRQ domains, which get a number space assigned according to probe order, and above the preallocated IRQ numbers. > - sata_mv fails to initialise with -22 (-EINVAL) No idea, I'd try inserting a printk in every code path that can return -EINVAL from there > - there is no concensus on how to get ascii formatted MAC address from mtd > partitions so eth is not fully functional without setting the MAC from > userspace Ideally this is handled by the boot loader, but that requires being able to update it. If you cannot, this could perhaps be done using something like https://github.com/zonque/pxa-impedance-matcher Arnd ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-27 18:10 ` Arnd Bergmann 0 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-04-27 18:10 UTC (permalink / raw) To: Mauri Sandberg Cc: SoC Team, Linux ARM, DTML, Arnd Bergmann, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > Hello all, > > I am making an attempt to create a device tree for D-Link DNS-323 devices > but I am falling short on a few specific details. I am requesting a > general review of the device tree files. I have access to DNS-323 rev A1 > only and the B1 and C1 need to be tested separately, so I am reaching out > to people who might have them. Hi Mauri, It's really nice to see some progress on this! I don't have the hardware, but I'll try to answer some of your questions anyway. > The questions that I have at the moment are below. > > - some of resulting IRQs are different from what was requested in device tree > - logs say NR_IRQS is different from mach file one This is all normal: with a board file, all on-board IRQs are statically assigned to fixed numbers. With DT based boot, IRQ controllers usually define their own IRQ domains, which get a number space assigned according to probe order, and above the preallocated IRQ numbers. > - sata_mv fails to initialise with -22 (-EINVAL) No idea, I'd try inserting a printk in every code path that can return -EINVAL from there > - there is no concensus on how to get ascii formatted MAC address from mtd > partitions so eth is not fully functional without setting the MAC from > userspace Ideally this is handled by the boot loader, but that requires being able to update it. If you cannot, this could perhaps be done using something like https://github.com/zonque/pxa-impedance-matcher Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-27 18:10 ` Arnd Bergmann @ 2022-04-28 0:18 ` Andrew Lunn -1 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-04-28 0:18 UTC (permalink / raw) To: Arnd Bergmann Cc: Mauri Sandberg, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Sebastian Hesselbarth > > - there is no concensus on how to get ascii formatted MAC address from mtd > > partitions so eth is not fully functional without setting the MAC from > > userspace > > Ideally this is handled by the boot loader, but that requires being > able to update > it. The mv643xx Ethernet driver is happy if it finds the MAC address already in the hardware. The vendor uboot often does this. Does tftp boot work in uboot? That would indicate it has access to the MAC address. Andrew ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 0:18 ` Andrew Lunn 0 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-04-28 0:18 UTC (permalink / raw) To: Arnd Bergmann Cc: Mauri Sandberg, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Sebastian Hesselbarth > > - there is no concensus on how to get ascii formatted MAC address from mtd > > partitions so eth is not fully functional without setting the MAC from > > userspace > > Ideally this is handled by the boot loader, but that requires being > able to update > it. The mv643xx Ethernet driver is happy if it finds the MAC address already in the hardware. The vendor uboot often does this. Does tftp boot work in uboot? That would indicate it has access to the MAC address. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-28 0:18 ` Andrew Lunn @ 2022-04-28 20:25 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-28 20:25 UTC (permalink / raw) To: Andrew Lunn, Arnd Bergmann Cc: maukka, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Sebastian Hesselbarth Hello Andrew! On 28.4.2022 3.18, Andrew Lunn wrote: >>> - there is no concensus on how to get ascii formatted MAC address from mtd >>> partitions so eth is not fully functional without setting the MAC from >>> userspace >> >> Ideally this is handled by the boot loader, but that requires being >> able to update >> it. > > The mv643xx Ethernet driver is happy if it finds the MAC address > already in the hardware. The vendor uboot often does this. Does tftp > boot work in uboot? That would indicate it has access to the MAC > address. The u-boot is really limited and I am transferring new images over kermit. Tftp is not enabled. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 20:25 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-28 20:25 UTC (permalink / raw) To: Andrew Lunn, Arnd Bergmann Cc: maukka, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Sebastian Hesselbarth Hello Andrew! On 28.4.2022 3.18, Andrew Lunn wrote: >>> - there is no concensus on how to get ascii formatted MAC address from mtd >>> partitions so eth is not fully functional without setting the MAC from >>> userspace >> >> Ideally this is handled by the boot loader, but that requires being >> able to update >> it. > > The mv643xx Ethernet driver is happy if it finds the MAC address > already in the hardware. The vendor uboot often does this. Does tftp > boot work in uboot? That would indicate it has access to the MAC > address. The u-boot is really limited and I am transferring new images over kermit. Tftp is not enabled. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-28 20:25 ` Mauri Sandberg @ 2022-04-28 23:26 ` Andrew Lunn -1 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-04-28 23:26 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Sebastian Hesselbarth On Thu, Apr 28, 2022 at 11:25:00PM +0300, Mauri Sandberg wrote: > Hello Andrew! > > On 28.4.2022 3.18, Andrew Lunn wrote: > > > > - there is no concensus on how to get ascii formatted MAC address from mtd > > > > partitions so eth is not fully functional without setting the MAC from > > > > userspace > > > > > > Ideally this is handled by the boot loader, but that requires being > > > able to update > > > it. > > > > The mv643xx Ethernet driver is happy if it finds the MAC address > > already in the hardware. The vendor uboot often does this. Does tftp > > boot work in uboot? That would indicate it has access to the MAC > > address. > > The u-boot is really limited and I am transferring new images over kermit. Ouch! If you can, try kexec. You can use wget or similar to grab the kernel from you host machine, and then something like: kexec --append 'rootwait ro earlyprintk console=ttyS0,115200n8' bzImage wget will be much faster then kernel. Andrew ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 23:26 ` Andrew Lunn 0 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-04-28 23:26 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Sebastian Hesselbarth On Thu, Apr 28, 2022 at 11:25:00PM +0300, Mauri Sandberg wrote: > Hello Andrew! > > On 28.4.2022 3.18, Andrew Lunn wrote: > > > > - there is no concensus on how to get ascii formatted MAC address from mtd > > > > partitions so eth is not fully functional without setting the MAC from > > > > userspace > > > > > > Ideally this is handled by the boot loader, but that requires being > > > able to update > > > it. > > > > The mv643xx Ethernet driver is happy if it finds the MAC address > > already in the hardware. The vendor uboot often does this. Does tftp > > boot work in uboot? That would indicate it has access to the MAC > > address. > > The u-boot is really limited and I am transferring new images over kermit. Ouch! If you can, try kexec. You can use wget or similar to grab the kernel from you host machine, and then something like: kexec --append 'rootwait ro earlyprintk console=ttyS0,115200n8' bzImage wget will be much faster then kernel. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-28 23:26 ` Andrew Lunn @ 2022-05-03 8:20 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-03 8:20 UTC (permalink / raw) To: Andrew Lunn Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Sebastian Hesselbarth On 29.04.22 02:26, Andrew Lunn wrote: > On Thu, Apr 28, 2022 at 11:25:00PM +0300, Mauri Sandberg wrote: >> Hello Andrew! >> >> On 28.4.2022 3.18, Andrew Lunn wrote: >>>>> - there is no concensus on how to get ascii formatted MAC address from mtd >>>>> partitions so eth is not fully functional without setting the MAC from >>>>> userspace >>>> Ideally this is handled by the boot loader, but that requires being >>>> able to update >>>> it. >>> The mv643xx Ethernet driver is happy if it finds the MAC address >>> already in the hardware. The vendor uboot often does this. Does tftp >>> boot work in uboot? That would indicate it has access to the MAC >>> address. >> The u-boot is really limited and I am transferring new images over kermit. > Ouch! > > If you can, try kexec. You can use wget or similar to grab the kernel > from you host machine, and then something like: > > kexec --append 'rootwait ro earlyprintk console=ttyS0,115200n8' bzImage > > wget will be much faster then kernel. > Nice, this looks promising. Thanks for the tip. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-03 8:20 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-03 8:20 UTC (permalink / raw) To: Andrew Lunn Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Sebastian Hesselbarth On 29.04.22 02:26, Andrew Lunn wrote: > On Thu, Apr 28, 2022 at 11:25:00PM +0300, Mauri Sandberg wrote: >> Hello Andrew! >> >> On 28.4.2022 3.18, Andrew Lunn wrote: >>>>> - there is no concensus on how to get ascii formatted MAC address from mtd >>>>> partitions so eth is not fully functional without setting the MAC from >>>>> userspace >>>> Ideally this is handled by the boot loader, but that requires being >>>> able to update >>>> it. >>> The mv643xx Ethernet driver is happy if it finds the MAC address >>> already in the hardware. The vendor uboot often does this. Does tftp >>> boot work in uboot? That would indicate it has access to the MAC >>> address. >> The u-boot is really limited and I am transferring new images over kermit. > Ouch! > > If you can, try kexec. You can use wget or similar to grab the kernel > from you host machine, and then something like: > > kexec --append 'rootwait ro earlyprintk console=ttyS0,115200n8' bzImage > > wget will be much faster then kernel. > Nice, this looks promising. Thanks for the tip. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-27 18:10 ` Arnd Bergmann @ 2022-04-28 20:01 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-28 20:01 UTC (permalink / raw) To: Arnd Bergmann Cc: SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, maukka Hi Arnd and thanks for your quick reply. On 27.4.2022 21.10, Arnd Bergmann wrote: > On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >> >> Hello all, >> >> I am making an attempt to create a device tree for D-Link DNS-323 devices >> but I am falling short on a few specific details. I am requesting a >> general review of the device tree files. I have access to DNS-323 rev A1 >> only and the B1 and C1 need to be tested separately, so I am reaching out >> to people who might have them. > > Hi Mauri, > > It's really nice to see some progress on this! I don't have the hardware, > but I'll try to answer some of your questions anyway. > >> The questions that I have at the moment are below. >> >> - some of resulting IRQs are different from what was requested in device tree >> - logs say NR_IRQS is different from mach file one > Ok thanks, I won't worry about it anymore. > This is all normal: with a board file, all on-board IRQs are statically > assigned to fixed numbers. With DT based boot, IRQ controllers > usually define their own IRQ domains, which get a number space assigned > according to probe order, and above the preallocated IRQ numbers. > >> - sata_mv fails to initialise with -22 (-EINVAL) > > No idea, I'd try inserting a printk in every code path that can return -EINVAL > from there > I had something like that but I didn't get any wiser immediately. Then I suspected it's something to do with initialisation of the PCIe bus and that clashing with sata_mv initialisation and thought it's better to ask. The PCIe initialisation uses hardwired irq and maybe that was getting in the way. Is there a way to describe the PCIe bus in the device tree? The initalisation of that bus is done for rev A1 only. >> - there is no concensus on how to get ascii formatted MAC address from mtd >> partitions so eth is not fully functional without setting the MAC from >> userspace > > Ideally this is handled by the boot loader, but that requires being > able to update > it. If you cannot, this could perhaps be done using something like > https://github.com/zonque/pxa-impedance-matcher I had a look at the pxa-impedance-matcher but I am not sure how to use it. Should it be flashed on the device and then it would the boot the rest of the system? Maybe I'll have to add some dns323 specifics there too first. On the dns323 there are these mtd partitions MTD1 and MTD2, which I am not really sure what they are for. Maybe those could accommodate a 3rd stage loader. But I'll consider it as my last resort as they put it in their documentation too. In linux-mtd there's been a few attempts to find a solution and I am hoping one will be found eventually. Adding support in the u-boot was stalled back in the days for some reason and I am not sure I will be much wiser than the previous people that were at it. But I have jtag programmer that should be suitable. -- Mauri ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 20:01 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-04-28 20:01 UTC (permalink / raw) To: Arnd Bergmann Cc: SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, maukka Hi Arnd and thanks for your quick reply. On 27.4.2022 21.10, Arnd Bergmann wrote: > On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >> >> Hello all, >> >> I am making an attempt to create a device tree for D-Link DNS-323 devices >> but I am falling short on a few specific details. I am requesting a >> general review of the device tree files. I have access to DNS-323 rev A1 >> only and the B1 and C1 need to be tested separately, so I am reaching out >> to people who might have them. > > Hi Mauri, > > It's really nice to see some progress on this! I don't have the hardware, > but I'll try to answer some of your questions anyway. > >> The questions that I have at the moment are below. >> >> - some of resulting IRQs are different from what was requested in device tree >> - logs say NR_IRQS is different from mach file one > Ok thanks, I won't worry about it anymore. > This is all normal: with a board file, all on-board IRQs are statically > assigned to fixed numbers. With DT based boot, IRQ controllers > usually define their own IRQ domains, which get a number space assigned > according to probe order, and above the preallocated IRQ numbers. > >> - sata_mv fails to initialise with -22 (-EINVAL) > > No idea, I'd try inserting a printk in every code path that can return -EINVAL > from there > I had something like that but I didn't get any wiser immediately. Then I suspected it's something to do with initialisation of the PCIe bus and that clashing with sata_mv initialisation and thought it's better to ask. The PCIe initialisation uses hardwired irq and maybe that was getting in the way. Is there a way to describe the PCIe bus in the device tree? The initalisation of that bus is done for rev A1 only. >> - there is no concensus on how to get ascii formatted MAC address from mtd >> partitions so eth is not fully functional without setting the MAC from >> userspace > > Ideally this is handled by the boot loader, but that requires being > able to update > it. If you cannot, this could perhaps be done using something like > https://github.com/zonque/pxa-impedance-matcher I had a look at the pxa-impedance-matcher but I am not sure how to use it. Should it be flashed on the device and then it would the boot the rest of the system? Maybe I'll have to add some dns323 specifics there too first. On the dns323 there are these mtd partitions MTD1 and MTD2, which I am not really sure what they are for. Maybe those could accommodate a 3rd stage loader. But I'll consider it as my last resort as they put it in their documentation too. In linux-mtd there's been a few attempts to find a solution and I am hoping one will be found eventually. Adding support in the u-boot was stalled back in the days for some reason and I am not sure I will be much wiser than the previous people that were at it. But I have jtag programmer that should be suitable. -- Mauri _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-28 20:01 ` Mauri Sandberg @ 2022-04-28 20:56 ` Arnd Bergmann -1 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-04-28 20:56 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > On 27.4.2022 21.10, Arnd Bergmann wrote: > > On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > This is all normal: with a board file, all on-board IRQs are statically > > assigned to fixed numbers. With DT based boot, IRQ controllers > > usually define their own IRQ domains, which get a number space assigned > > according to probe order, and above the preallocated IRQ numbers. > > > >> - sata_mv fails to initialise with -22 (-EINVAL) > > > > No idea, I'd try inserting a printk in every code path that can return -EINVAL > > from there > > > I had something like that but I didn't get any wiser immediately. Then I > suspected it's something to do with initialisation of the PCIe bus and > that clashing with sata_mv initialisation and thought it's better to > ask. The PCIe initialisation uses hardwired irq and maybe that was > getting in the way. Is there a way to describe the PCIe bus in the > device tree? The initalisation of that bus is done for rev A1 only. I'm not too familiar with the platform, but my interpretation is that the DT support here is incomplete: The DT based PCI probe using drivers/pci/controller/pci-mvebu.c is not hooked up in orion5x.dtsi, and the traditional pci code does not work with DT. I see that orion5x has two separate blocks -- a PCIe host that is similar to the kirkwood one, and a legacy PCI host that needs a completely separate driver. Which of the two do you actually need here? > >> - there is no concensus on how to get ascii formatted MAC address from mtd > >> partitions so eth is not fully functional without setting the MAC from > >> userspace > > > > Ideally this is handled by the boot loader, but that requires being > > able to update > > it. If you cannot, this could perhaps be done using something like > > https://github.com/zonque/pxa-impedance-matcher > > I had a look at the pxa-impedance-matcher but I am not sure how to use > it. Should it be flashed on the device and then it would the boot the > rest of the system? Maybe I'll have to add some dns323 specifics there > too first. On the dns323 there are these mtd partitions MTD1 and MTD2, > which I am not really sure what they are for. Maybe those could > accommodate a 3rd stage loader. But I'll consider it as my last resort > as they put it in their documentation too. In linux-mtd there's been a > few attempts to find a solution and I am hoping one will be found > eventually. > > Adding support in the u-boot was stalled back in the days for some > reason and I am not sure I will be much wiser than the previous people > that were at it. But I have jtag programmer that should be suitable. I think the idea of the impedance-matcher is that you can combine it with a DT-enabled kernel image into a file that looks to the existing boot loader like an old kernel and then provides both a way for code to run before booting the kernel, and for adding in the DT. Arnd ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 20:56 ` Arnd Bergmann 0 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-04-28 20:56 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > On 27.4.2022 21.10, Arnd Bergmann wrote: > > On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > This is all normal: with a board file, all on-board IRQs are statically > > assigned to fixed numbers. With DT based boot, IRQ controllers > > usually define their own IRQ domains, which get a number space assigned > > according to probe order, and above the preallocated IRQ numbers. > > > >> - sata_mv fails to initialise with -22 (-EINVAL) > > > > No idea, I'd try inserting a printk in every code path that can return -EINVAL > > from there > > > I had something like that but I didn't get any wiser immediately. Then I > suspected it's something to do with initialisation of the PCIe bus and > that clashing with sata_mv initialisation and thought it's better to > ask. The PCIe initialisation uses hardwired irq and maybe that was > getting in the way. Is there a way to describe the PCIe bus in the > device tree? The initalisation of that bus is done for rev A1 only. I'm not too familiar with the platform, but my interpretation is that the DT support here is incomplete: The DT based PCI probe using drivers/pci/controller/pci-mvebu.c is not hooked up in orion5x.dtsi, and the traditional pci code does not work with DT. I see that orion5x has two separate blocks -- a PCIe host that is similar to the kirkwood one, and a legacy PCI host that needs a completely separate driver. Which of the two do you actually need here? > >> - there is no concensus on how to get ascii formatted MAC address from mtd > >> partitions so eth is not fully functional without setting the MAC from > >> userspace > > > > Ideally this is handled by the boot loader, but that requires being > > able to update > > it. If you cannot, this could perhaps be done using something like > > https://github.com/zonque/pxa-impedance-matcher > > I had a look at the pxa-impedance-matcher but I am not sure how to use > it. Should it be flashed on the device and then it would the boot the > rest of the system? Maybe I'll have to add some dns323 specifics there > too first. On the dns323 there are these mtd partitions MTD1 and MTD2, > which I am not really sure what they are for. Maybe those could > accommodate a 3rd stage loader. But I'll consider it as my last resort > as they put it in their documentation too. In linux-mtd there's been a > few attempts to find a solution and I am hoping one will be found > eventually. > > Adding support in the u-boot was stalled back in the days for some > reason and I am not sure I will be much wiser than the previous people > that were at it. But I have jtag programmer that should be suitable. I think the idea of the impedance-matcher is that you can combine it with a DT-enabled kernel image into a file that looks to the existing boot loader like an old kernel and then provides both a way for code to run before booting the kernel, and for adding in the DT. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-28 20:56 ` Arnd Bergmann @ 2022-05-08 14:06 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-08 14:06 UTC (permalink / raw) To: Arnd Bergmann Cc: maukka, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On 28.4.2022 23.56, Arnd Bergmann wrote: > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >> On 27.4.2022 21.10, Arnd Bergmann wrote: >>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>> - sata_mv fails to initialise with -22 (-EINVAL) >>> >>> No idea, I'd try inserting a printk in every code path that can return -EINVAL >>> from there >>> With debugging the reason for -EINVAL remains a bit mystery. - sata_mv calls ata_host_activate() [1] - later on, in request_threaded_irq(), there are sanity checks [2] - that fail with irq_settings_can_request() returning 0 [3] I cannot really put my finger on why the irq cannot be requested in DT approach. >> Is there a way to describe the PCIe bus in the >> device tree? The initalisation of that bus is done for rev A1 only. > > I'm not too familiar with the platform, but my interpretation is that the > DT support here is incomplete: > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > is not hooked up in orion5x.dtsi, and the traditional pci code does > not work with DT. Can the existing pci code still be used to init the PCI bus and describe the rest in the DT or is it a futile attempt? > I see that orion5x has two separate blocks -- a PCIe host that is > similar to the kirkwood one, and a legacy PCI host that needs > a completely separate driver. > > Which of the two do you actually need here? > I really cannot say which one is it. How can I tell? The functions given in struct hw_pci find their way to drivers/pci/probe.c eventually and use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or kirkwood explicitly at least. Here's the output from lspci if the ids reveal anything. # lspci -v -k 00:00.0 Class 0580: 11ab:5181 01:00.0 Class 0580: 11ab:5181 00:01.0 Class 0100: 11ab:7042 sata_mv -- Mauri [1] https://elixir.bootlin.com/linux/v5.17/source/drivers/ata/sata_mv.c#L4434 [2] https://elixir.bootlin.com/linux/v5.17/source/kernel/irq/manage.c#L2146 [3] https://elixir.bootlin.com/linux/v5.17/source/kernel/irq/settings.h#L100 ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-08 14:06 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-08 14:06 UTC (permalink / raw) To: Arnd Bergmann Cc: maukka, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth On 28.4.2022 23.56, Arnd Bergmann wrote: > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >> On 27.4.2022 21.10, Arnd Bergmann wrote: >>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>> - sata_mv fails to initialise with -22 (-EINVAL) >>> >>> No idea, I'd try inserting a printk in every code path that can return -EINVAL >>> from there >>> With debugging the reason for -EINVAL remains a bit mystery. - sata_mv calls ata_host_activate() [1] - later on, in request_threaded_irq(), there are sanity checks [2] - that fail with irq_settings_can_request() returning 0 [3] I cannot really put my finger on why the irq cannot be requested in DT approach. >> Is there a way to describe the PCIe bus in the >> device tree? The initalisation of that bus is done for rev A1 only. > > I'm not too familiar with the platform, but my interpretation is that the > DT support here is incomplete: > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > is not hooked up in orion5x.dtsi, and the traditional pci code does > not work with DT. Can the existing pci code still be used to init the PCI bus and describe the rest in the DT or is it a futile attempt? > I see that orion5x has two separate blocks -- a PCIe host that is > similar to the kirkwood one, and a legacy PCI host that needs > a completely separate driver. > > Which of the two do you actually need here? > I really cannot say which one is it. How can I tell? The functions given in struct hw_pci find their way to drivers/pci/probe.c eventually and use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or kirkwood explicitly at least. Here's the output from lspci if the ids reveal anything. # lspci -v -k 00:00.0 Class 0580: 11ab:5181 01:00.0 Class 0580: 11ab:5181 00:01.0 Class 0100: 11ab:7042 sata_mv -- Mauri [1] https://elixir.bootlin.com/linux/v5.17/source/drivers/ata/sata_mv.c#L4434 [2] https://elixir.bootlin.com/linux/v5.17/source/kernel/irq/manage.c#L2146 [3] https://elixir.bootlin.com/linux/v5.17/source/kernel/irq/settings.h#L100 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-05-08 14:06 ` Mauri Sandberg @ 2022-05-08 15:02 ` Arnd Bergmann -1 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-05-08 15:02 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni, Pali Rohár On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > On 28.4.2022 23.56, Arnd Bergmann wrote: > > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >> On 27.4.2022 21.10, Arnd Bergmann wrote: > >>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >>>> - sata_mv fails to initialise with -22 (-EINVAL) > >>> > >>> No idea, I'd try inserting a printk in every code path that can return -EINVAL > >>> from there > >>> > > With debugging the reason for -EINVAL remains a bit mystery. > - sata_mv calls ata_host_activate() [1] > - later on, in request_threaded_irq(), there are sanity checks [2] > - that fail with irq_settings_can_request() returning 0 [3] > > I cannot really put my finger on why the irq cannot be requested in DT > approach. Are you sure the marvell,orion-intc driver is successfully probed at this point? If not, the interrupt won't be there. I see that the "sata_mv" driver can be used either as a platform driver for the orion5x on-chip controller, or as a PCI driver for an add-on chip connected to the external bus. It sounds like your system has both. Do you know which one fails? The PCI driver cannot work unless the PCI host works correctly, and that in turn requires a correct devicetree description for it. > >> Is there a way to describe the PCIe bus in the > >> device tree? The initalisation of that bus is done for rev A1 only. > > > > I'm not too familiar with the platform, but my interpretation is that the > > DT support here is incomplete: > > > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > > is not hooked up in orion5x.dtsi, and the traditional pci code does > > not work with DT. > > Can the existing pci code still be used to init the PCI bus and describe > the rest in the DT or is it a futile attempt? > > > I see that orion5x has two separate blocks -- a PCIe host that is > > similar to the kirkwood one, and a legacy PCI host that needs > > a completely separate driver. > > > > Which of the two do you actually need here? > > > > I really cannot say which one is it. How can I tell? The functions given > in struct hw_pci find their way to drivers/pci/probe.c eventually and > use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > kirkwood explicitly at least. > > Here's the output from lspci if the ids reveal anything. > > # lspci -v -k > 00:00.0 Class 0580: 11ab:5181 > 01:00.0 Class 0580: 11ab:5181 > 00:01.0 Class 0100: 11ab:7042 sata_mv The first two seem to be the host bridges, but unfortunately they seem both have the same device ID, despite being very different devices. The first one (00:00.0) should be the PCIe driver, the second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 device is a PCIe device, and it's on the bus (00) of the first host bridge. I think this should work with drivers/pci/controller/pci-mvebu.c if you add the bits for probing. Thomas Petazzoni originally wrote the new driver, and I think he was planning at one point to use it for orion5x. I don't know if there were any major problems preventing this at the time, or if it just needs to get hooked up in the dtsi file. Arnd ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-08 15:02 ` Arnd Bergmann 0 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-05-08 15:02 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni, Pali Rohár On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > On 28.4.2022 23.56, Arnd Bergmann wrote: > > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >> On 27.4.2022 21.10, Arnd Bergmann wrote: > >>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >>>> - sata_mv fails to initialise with -22 (-EINVAL) > >>> > >>> No idea, I'd try inserting a printk in every code path that can return -EINVAL > >>> from there > >>> > > With debugging the reason for -EINVAL remains a bit mystery. > - sata_mv calls ata_host_activate() [1] > - later on, in request_threaded_irq(), there are sanity checks [2] > - that fail with irq_settings_can_request() returning 0 [3] > > I cannot really put my finger on why the irq cannot be requested in DT > approach. Are you sure the marvell,orion-intc driver is successfully probed at this point? If not, the interrupt won't be there. I see that the "sata_mv" driver can be used either as a platform driver for the orion5x on-chip controller, or as a PCI driver for an add-on chip connected to the external bus. It sounds like your system has both. Do you know which one fails? The PCI driver cannot work unless the PCI host works correctly, and that in turn requires a correct devicetree description for it. > >> Is there a way to describe the PCIe bus in the > >> device tree? The initalisation of that bus is done for rev A1 only. > > > > I'm not too familiar with the platform, but my interpretation is that the > > DT support here is incomplete: > > > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > > is not hooked up in orion5x.dtsi, and the traditional pci code does > > not work with DT. > > Can the existing pci code still be used to init the PCI bus and describe > the rest in the DT or is it a futile attempt? > > > I see that orion5x has two separate blocks -- a PCIe host that is > > similar to the kirkwood one, and a legacy PCI host that needs > > a completely separate driver. > > > > Which of the two do you actually need here? > > > > I really cannot say which one is it. How can I tell? The functions given > in struct hw_pci find their way to drivers/pci/probe.c eventually and > use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > kirkwood explicitly at least. > > Here's the output from lspci if the ids reveal anything. > > # lspci -v -k > 00:00.0 Class 0580: 11ab:5181 > 01:00.0 Class 0580: 11ab:5181 > 00:01.0 Class 0100: 11ab:7042 sata_mv The first two seem to be the host bridges, but unfortunately they seem both have the same device ID, despite being very different devices. The first one (00:00.0) should be the PCIe driver, the second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 device is a PCIe device, and it's on the bus (00) of the first host bridge. I think this should work with drivers/pci/controller/pci-mvebu.c if you add the bits for probing. Thomas Petazzoni originally wrote the new driver, and I think he was planning at one point to use it for orion5x. I don't know if there were any major problems preventing this at the time, or if it just needs to get hooked up in the dtsi file. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-05-08 15:02 ` Arnd Bergmann @ 2022-05-08 15:22 ` Pali Rohár -1 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-05-08 15:22 UTC (permalink / raw) To: Arnd Bergmann Cc: Mauri Sandberg, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > On 28.4.2022 23.56, Arnd Bergmann wrote: > > > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > >> On 27.4.2022 21.10, Arnd Bergmann wrote: > > >>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > >>>> - sata_mv fails to initialise with -22 (-EINVAL) > > >>> > > >>> No idea, I'd try inserting a printk in every code path that can return -EINVAL > > >>> from there > > >>> > > > > With debugging the reason for -EINVAL remains a bit mystery. > > - sata_mv calls ata_host_activate() [1] > > - later on, in request_threaded_irq(), there are sanity checks [2] > > - that fail with irq_settings_can_request() returning 0 [3] > > > > I cannot really put my finger on why the irq cannot be requested in DT > > approach. > > Are you sure the marvell,orion-intc driver is successfully probed > at this point? If not, the interrupt won't be there. > > I see that the "sata_mv" driver can be used either as a platform > driver for the orion5x on-chip controller, or as a PCI driver for > an add-on chip connected to the external bus. It sounds like > your system has both. Do you know which one fails? > > The PCI driver cannot work unless the PCI host works correctly, > and that in turn requires a correct devicetree description for it. > > > >> Is there a way to describe the PCIe bus in the > > >> device tree? The initalisation of that bus is done for rev A1 only. > > > > > > I'm not too familiar with the platform, but my interpretation is that the > > > DT support here is incomplete: > > > > > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > > > is not hooked up in orion5x.dtsi, and the traditional pci code does > > > not work with DT. > > > > Can the existing pci code still be used to init the PCI bus and describe > > the rest in the DT or is it a futile attempt? Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and PCIe buses. This is not device tree driver. > > > I see that orion5x has two separate blocks -- a PCIe host that is > > > similar to the kirkwood one, and a legacy PCI host that needs > > > a completely separate driver. > > > > > > Which of the two do you actually need here? > > > > > > > I really cannot say which one is it. How can I tell? The functions given > > in struct hw_pci find their way to drivers/pci/probe.c eventually and > > use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > > kirkwood explicitly at least. > > > > Here's the output from lspci if the ids reveal anything. > > > > # lspci -v -k > > 00:00.0 Class 0580: 11ab:5181 > > 01:00.0 Class 0580: 11ab:5181 > > 00:01.0 Class 0100: 11ab:7042 sata_mv > > The first two seem to be the host bridges, but unfortunately they > seem both have the same device ID, despite being very different > devices. The first one (00:00.0) should be the PCIe driver, the > second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 > device is a PCIe device, and it's on the bus (00) of the first host > bridge. I think this should work with drivers/pci/controller/pci-mvebu.c > if you add the bits for probing. Last time when I looked on Orion PCIe controller registers, I though that they are same as in Kirkwood PCIe controller registers. And Kirkwood is already supported by pci-mvebu.c driver. About PCI host bridge, I do not know. Beware that PCI Class Id and all PCI registers which are different for Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit Marvell SoCs. Those registers on Marvell SoCs have different meaning as what is defined in PCI and PCIe specs. So it means that lspci _may_ display bogus information about PCIe Root Port. pci-mvebu.c uses Root Port emulator which fills correct data to make kernel and lspci happy. If you are going to extend pci-mvebu.c to support also Orion PCIe controller, I could try to help with it. But I do not have any Orion hardware, so just basic help... Links to Orion documentations, including PCIe errata is available in kernel documentation. So this could help to understand some details: https://www.kernel.org/doc/html/latest/arm/marvell.html Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' outputs from Orion? > Thomas Petazzoni originally wrote the new driver, and I think he was > planning at one point to use it for orion5x. I don't know if there were > any major problems preventing this at the time, or if it just needs to > get hooked up in the dtsi file. > > Arnd ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-08 15:22 ` Pali Rohár 0 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-05-08 15:22 UTC (permalink / raw) To: Arnd Bergmann Cc: Mauri Sandberg, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > On 28.4.2022 23.56, Arnd Bergmann wrote: > > > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > >> On 27.4.2022 21.10, Arnd Bergmann wrote: > > >>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > >>>> - sata_mv fails to initialise with -22 (-EINVAL) > > >>> > > >>> No idea, I'd try inserting a printk in every code path that can return -EINVAL > > >>> from there > > >>> > > > > With debugging the reason for -EINVAL remains a bit mystery. > > - sata_mv calls ata_host_activate() [1] > > - later on, in request_threaded_irq(), there are sanity checks [2] > > - that fail with irq_settings_can_request() returning 0 [3] > > > > I cannot really put my finger on why the irq cannot be requested in DT > > approach. > > Are you sure the marvell,orion-intc driver is successfully probed > at this point? If not, the interrupt won't be there. > > I see that the "sata_mv" driver can be used either as a platform > driver for the orion5x on-chip controller, or as a PCI driver for > an add-on chip connected to the external bus. It sounds like > your system has both. Do you know which one fails? > > The PCI driver cannot work unless the PCI host works correctly, > and that in turn requires a correct devicetree description for it. > > > >> Is there a way to describe the PCIe bus in the > > >> device tree? The initalisation of that bus is done for rev A1 only. > > > > > > I'm not too familiar with the platform, but my interpretation is that the > > > DT support here is incomplete: > > > > > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > > > is not hooked up in orion5x.dtsi, and the traditional pci code does > > > not work with DT. > > > > Can the existing pci code still be used to init the PCI bus and describe > > the rest in the DT or is it a futile attempt? Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and PCIe buses. This is not device tree driver. > > > I see that orion5x has two separate blocks -- a PCIe host that is > > > similar to the kirkwood one, and a legacy PCI host that needs > > > a completely separate driver. > > > > > > Which of the two do you actually need here? > > > > > > > I really cannot say which one is it. How can I tell? The functions given > > in struct hw_pci find their way to drivers/pci/probe.c eventually and > > use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > > kirkwood explicitly at least. > > > > Here's the output from lspci if the ids reveal anything. > > > > # lspci -v -k > > 00:00.0 Class 0580: 11ab:5181 > > 01:00.0 Class 0580: 11ab:5181 > > 00:01.0 Class 0100: 11ab:7042 sata_mv > > The first two seem to be the host bridges, but unfortunately they > seem both have the same device ID, despite being very different > devices. The first one (00:00.0) should be the PCIe driver, the > second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 > device is a PCIe device, and it's on the bus (00) of the first host > bridge. I think this should work with drivers/pci/controller/pci-mvebu.c > if you add the bits for probing. Last time when I looked on Orion PCIe controller registers, I though that they are same as in Kirkwood PCIe controller registers. And Kirkwood is already supported by pci-mvebu.c driver. About PCI host bridge, I do not know. Beware that PCI Class Id and all PCI registers which are different for Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit Marvell SoCs. Those registers on Marvell SoCs have different meaning as what is defined in PCI and PCIe specs. So it means that lspci _may_ display bogus information about PCIe Root Port. pci-mvebu.c uses Root Port emulator which fills correct data to make kernel and lspci happy. If you are going to extend pci-mvebu.c to support also Orion PCIe controller, I could try to help with it. But I do not have any Orion hardware, so just basic help... Links to Orion documentations, including PCIe errata is available in kernel documentation. So this could help to understand some details: https://www.kernel.org/doc/html/latest/arm/marvell.html Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' outputs from Orion? > Thomas Petazzoni originally wrote the new driver, and I think he was > planning at one point to use it for orion5x. I don't know if there were > any major problems preventing this at the time, or if it just needs to > get hooked up in the dtsi file. > > Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-05-08 15:22 ` Pali Rohár @ 2022-05-08 15:41 ` Pali Rohár -1 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-05-08 15:41 UTC (permalink / raw) To: Arnd Bergmann Cc: Mauri Sandberg, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Sunday 08 May 2022 17:22:37 Pali Rohár wrote: > On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > > On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > On 28.4.2022 23.56, Arnd Bergmann wrote: > > > > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > >> On 27.4.2022 21.10, Arnd Bergmann wrote: > > > >>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > >>>> - sata_mv fails to initialise with -22 (-EINVAL) > > > >>> > > > >>> No idea, I'd try inserting a printk in every code path that can return -EINVAL > > > >>> from there > > > >>> > > > > > > With debugging the reason for -EINVAL remains a bit mystery. > > > - sata_mv calls ata_host_activate() [1] > > > - later on, in request_threaded_irq(), there are sanity checks [2] > > > - that fail with irq_settings_can_request() returning 0 [3] > > > > > > I cannot really put my finger on why the irq cannot be requested in DT > > > approach. > > > > Are you sure the marvell,orion-intc driver is successfully probed > > at this point? If not, the interrupt won't be there. > > > > I see that the "sata_mv" driver can be used either as a platform > > driver for the orion5x on-chip controller, or as a PCI driver for > > an add-on chip connected to the external bus. It sounds like > > your system has both. Do you know which one fails? > > > > The PCI driver cannot work unless the PCI host works correctly, > > and that in turn requires a correct devicetree description for it. > > > > > >> Is there a way to describe the PCIe bus in the > > > >> device tree? The initalisation of that bus is done for rev A1 only. > > > > > > > > I'm not too familiar with the platform, but my interpretation is that the > > > > DT support here is incomplete: > > > > > > > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > > > > is not hooked up in orion5x.dtsi, and the traditional pci code does > > > > not work with DT. > > > > > > Can the existing pci code still be used to init the PCI bus and describe > > > the rest in the DT or is it a futile attempt? > > Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > PCIe buses. This is not device tree driver. Correction, Orion PCIe driver is arch/arm/plat-orion/pcie.c and it calls common functions from mach-orion5x/pci.c driver. > > > > I see that orion5x has two separate blocks -- a PCIe host that is > > > > similar to the kirkwood one, and a legacy PCI host that needs > > > > a completely separate driver. > > > > > > > > Which of the two do you actually need here? > > > > > > > > > > I really cannot say which one is it. How can I tell? The functions given > > > in struct hw_pci find their way to drivers/pci/probe.c eventually and > > > use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > > > kirkwood explicitly at least. > > > > > > Here's the output from lspci if the ids reveal anything. > > > > > > # lspci -v -k > > > 00:00.0 Class 0580: 11ab:5181 > > > 01:00.0 Class 0580: 11ab:5181 > > > 00:01.0 Class 0100: 11ab:7042 sata_mv > > > > The first two seem to be the host bridges, but unfortunately they > > seem both have the same device ID, despite being very different > > devices. The first one (00:00.0) should be the PCIe driver, the > > second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 > > device is a PCIe device, and it's on the bus (00) of the first host > > bridge. I think this should work with drivers/pci/controller/pci-mvebu.c > > if you add the bits for probing. > > Last time when I looked on Orion PCIe controller registers, I though > that they are same as in Kirkwood PCIe controller registers. And > Kirkwood is already supported by pci-mvebu.c driver. > > About PCI host bridge, I do not know. > > Beware that PCI Class Id and all PCI registers which are different for > Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit > Marvell SoCs. Those registers on Marvell SoCs have different meaning as > what is defined in PCI and PCIe specs. So it means that lspci _may_ > display bogus information about PCIe Root Port. pci-mvebu.c uses Root > Port emulator which fills correct data to make kernel and lspci happy. > > If you are going to extend pci-mvebu.c to support also Orion PCIe > controller, I could try to help with it. But I do not have any Orion > hardware, so just basic help... > > Links to Orion documentations, including PCIe errata is available in > kernel documentation. So this could help to understand some details: > https://www.kernel.org/doc/html/latest/arm/marvell.html > > Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' > outputs from Orion? > > > Thomas Petazzoni originally wrote the new driver, and I think he was > > planning at one point to use it for orion5x. I don't know if there were > > any major problems preventing this at the time, or if it just needs to > > get hooked up in the dtsi file. > > > > Arnd There is Orion-specific errata that config space via CF8/CFC registers is broken. Workaround documented in errata documented (linked from above documentation) does not work when DMA is used and instead other undocumented workaround is needed (implemented in arch/arm) which maps config space to memory (and therefore avoids usage of broken CF8/CFC memory mapped registers). ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-08 15:41 ` Pali Rohár 0 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-05-08 15:41 UTC (permalink / raw) To: Arnd Bergmann Cc: Mauri Sandberg, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Sunday 08 May 2022 17:22:37 Pali Rohár wrote: > On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > > On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > On 28.4.2022 23.56, Arnd Bergmann wrote: > > > > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > >> On 27.4.2022 21.10, Arnd Bergmann wrote: > > > >>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > >>>> - sata_mv fails to initialise with -22 (-EINVAL) > > > >>> > > > >>> No idea, I'd try inserting a printk in every code path that can return -EINVAL > > > >>> from there > > > >>> > > > > > > With debugging the reason for -EINVAL remains a bit mystery. > > > - sata_mv calls ata_host_activate() [1] > > > - later on, in request_threaded_irq(), there are sanity checks [2] > > > - that fail with irq_settings_can_request() returning 0 [3] > > > > > > I cannot really put my finger on why the irq cannot be requested in DT > > > approach. > > > > Are you sure the marvell,orion-intc driver is successfully probed > > at this point? If not, the interrupt won't be there. > > > > I see that the "sata_mv" driver can be used either as a platform > > driver for the orion5x on-chip controller, or as a PCI driver for > > an add-on chip connected to the external bus. It sounds like > > your system has both. Do you know which one fails? > > > > The PCI driver cannot work unless the PCI host works correctly, > > and that in turn requires a correct devicetree description for it. > > > > > >> Is there a way to describe the PCIe bus in the > > > >> device tree? The initalisation of that bus is done for rev A1 only. > > > > > > > > I'm not too familiar with the platform, but my interpretation is that the > > > > DT support here is incomplete: > > > > > > > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > > > > is not hooked up in orion5x.dtsi, and the traditional pci code does > > > > not work with DT. > > > > > > Can the existing pci code still be used to init the PCI bus and describe > > > the rest in the DT or is it a futile attempt? > > Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > PCIe buses. This is not device tree driver. Correction, Orion PCIe driver is arch/arm/plat-orion/pcie.c and it calls common functions from mach-orion5x/pci.c driver. > > > > I see that orion5x has two separate blocks -- a PCIe host that is > > > > similar to the kirkwood one, and a legacy PCI host that needs > > > > a completely separate driver. > > > > > > > > Which of the two do you actually need here? > > > > > > > > > > I really cannot say which one is it. How can I tell? The functions given > > > in struct hw_pci find their way to drivers/pci/probe.c eventually and > > > use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > > > kirkwood explicitly at least. > > > > > > Here's the output from lspci if the ids reveal anything. > > > > > > # lspci -v -k > > > 00:00.0 Class 0580: 11ab:5181 > > > 01:00.0 Class 0580: 11ab:5181 > > > 00:01.0 Class 0100: 11ab:7042 sata_mv > > > > The first two seem to be the host bridges, but unfortunately they > > seem both have the same device ID, despite being very different > > devices. The first one (00:00.0) should be the PCIe driver, the > > second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 > > device is a PCIe device, and it's on the bus (00) of the first host > > bridge. I think this should work with drivers/pci/controller/pci-mvebu.c > > if you add the bits for probing. > > Last time when I looked on Orion PCIe controller registers, I though > that they are same as in Kirkwood PCIe controller registers. And > Kirkwood is already supported by pci-mvebu.c driver. > > About PCI host bridge, I do not know. > > Beware that PCI Class Id and all PCI registers which are different for > Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit > Marvell SoCs. Those registers on Marvell SoCs have different meaning as > what is defined in PCI and PCIe specs. So it means that lspci _may_ > display bogus information about PCIe Root Port. pci-mvebu.c uses Root > Port emulator which fills correct data to make kernel and lspci happy. > > If you are going to extend pci-mvebu.c to support also Orion PCIe > controller, I could try to help with it. But I do not have any Orion > hardware, so just basic help... > > Links to Orion documentations, including PCIe errata is available in > kernel documentation. So this could help to understand some details: > https://www.kernel.org/doc/html/latest/arm/marvell.html > > Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' > outputs from Orion? > > > Thomas Petazzoni originally wrote the new driver, and I think he was > > planning at one point to use it for orion5x. I don't know if there were > > any major problems preventing this at the time, or if it just needs to > > get hooked up in the dtsi file. > > > > Arnd There is Orion-specific errata that config space via CF8/CFC registers is broken. Workaround documented in errata documented (linked from above documentation) does not work when DMA is used and instead other undocumented workaround is needed (implemented in arch/arm) which maps config space to memory (and therefore avoids usage of broken CF8/CFC memory mapped registers). _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-05-08 15:41 ` Pali Rohár @ 2022-05-09 7:21 ` Arnd Bergmann -1 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-05-09 7:21 UTC (permalink / raw) To: Pali Rohár Cc: Arnd Bergmann, Mauri Sandberg, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Sun, May 8, 2022 at 5:41 PM Pali Rohár <pali@kernel.org> wrote: > On Sunday 08 May 2022 17:22:37 Pali Rohár wrote: > > On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > > > > > > > > Can the existing pci code still be used to init the PCI bus and describe > > > > the rest in the DT or is it a futile attempt? > > > > Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > > PCIe buses. This is not device tree driver. > > Correction, Orion PCIe driver is arch/arm/plat-orion/pcie.c and it calls > common functions from mach-orion5x/pci.c driver. FWIW, I have an older patch series that turns the plat-orion/pcie.c and mach-orion5x/pci.c into standalone host bridge drivers that no longer use the arm/kernel/bios32.c helpers. If anyone wants to work on DT support for the legacy-pci side (not for this machine but maybe another orion5x one), I can try to rebase those patches to make it easier to add the missing DT support. Arnd ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-09 7:21 ` Arnd Bergmann 0 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-05-09 7:21 UTC (permalink / raw) To: Pali Rohár Cc: Arnd Bergmann, Mauri Sandberg, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Sun, May 8, 2022 at 5:41 PM Pali Rohár <pali@kernel.org> wrote: > On Sunday 08 May 2022 17:22:37 Pali Rohár wrote: > > On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > > > > > > > > Can the existing pci code still be used to init the PCI bus and describe > > > > the rest in the DT or is it a futile attempt? > > > > Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > > PCIe buses. This is not device tree driver. > > Correction, Orion PCIe driver is arch/arm/plat-orion/pcie.c and it calls > common functions from mach-orion5x/pci.c driver. FWIW, I have an older patch series that turns the plat-orion/pcie.c and mach-orion5x/pci.c into standalone host bridge drivers that no longer use the arm/kernel/bios32.c helpers. If anyone wants to work on DT support for the legacy-pci side (not for this machine but maybe another orion5x one), I can try to rebase those patches to make it easier to add the missing DT support. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-05-08 15:41 ` Pali Rohár @ 2022-05-09 10:48 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-09 10:48 UTC (permalink / raw) To: Pali Rohár, Arnd Bergmann Cc: maukka, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On 8.5.2022 18.41, Pali Rohár wrote: > On Sunday 08 May 2022 17:22:37 Pali Rohár wrote: >> On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: >>> On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>> On 28.4.2022 23.56, Arnd Bergmann wrote: >>>>> On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>> On 27.4.2022 21.10, Arnd Bergmann wrote: >>>>>>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>>>> - sata_mv fails to initialise with -22 (-EINVAL) >>>>>>> >>>>>>> No idea, I'd try inserting a printk in every code path that can return -EINVAL >>>>>>> from there >>>>>>> >>>> >>>> With debugging the reason for -EINVAL remains a bit mystery. >>>> - sata_mv calls ata_host_activate() [1] >>>> - later on, in request_threaded_irq(), there are sanity checks [2] >>>> - that fail with irq_settings_can_request() returning 0 [3] >>>> >>>> I cannot really put my finger on why the irq cannot be requested in DT >>>> approach. >>> >>> Are you sure the marvell,orion-intc driver is successfully probed >>> at this point? If not, the interrupt won't be there. >>> >>> I see that the "sata_mv" driver can be used either as a platform >>> driver for the orion5x on-chip controller, or as a PCI driver for >>> an add-on chip connected to the external bus. It sounds like >>> your system has both. Do you know which one fails? >>> >>> The PCI driver cannot work unless the PCI host works correctly, >>> and that in turn requires a correct devicetree description for it. >>> >>>>>> Is there a way to describe the PCIe bus in the >>>>>> device tree? The initalisation of that bus is done for rev A1 only. >>>>> >>>>> I'm not too familiar with the platform, but my interpretation is that the >>>>> DT support here is incomplete: >>>>> >>>>> The DT based PCI probe using drivers/pci/controller/pci-mvebu.c >>>>> is not hooked up in orion5x.dtsi, and the traditional pci code does >>>>> not work with DT. >>>> >>>> Can the existing pci code still be used to init the PCI bus and describe >>>> the rest in the DT or is it a futile attempt? >> >> Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and >> PCIe buses. This is not device tree driver. > > Correction, Orion PCIe driver is arch/arm/plat-orion/pcie.c and it calls > common functions from mach-orion5x/pci.c driver. > >>>>> I see that orion5x has two separate blocks -- a PCIe host that is >>>>> similar to the kirkwood one, and a legacy PCI host that needs >>>>> a completely separate driver. >>>>> >>>>> Which of the two do you actually need here? >>>>> >>>> >>>> I really cannot say which one is it. How can I tell? The functions given >>>> in struct hw_pci find their way to drivers/pci/probe.c eventually and >>>> use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or >>>> kirkwood explicitly at least. >>>> >>>> Here's the output from lspci if the ids reveal anything. >>>> >>>> # lspci -v -k >>>> 00:00.0 Class 0580: 11ab:5181 >>>> 01:00.0 Class 0580: 11ab:5181 >>>> 00:01.0 Class 0100: 11ab:7042 sata_mv >>> >>> The first two seem to be the host bridges, but unfortunately they >>> seem both have the same device ID, despite being very different >>> devices. The first one (00:00.0) should be the PCIe driver, the >>> second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 >>> device is a PCIe device, and it's on the bus (00) of the first host >>> bridge. I think this should work with drivers/pci/controller/pci-mvebu.c >>> if you add the bits for probing. >> >> Last time when I looked on Orion PCIe controller registers, I though >> that they are same as in Kirkwood PCIe controller registers. And >> Kirkwood is already supported by pci-mvebu.c driver. >> >> About PCI host bridge, I do not know. >> >> Beware that PCI Class Id and all PCI registers which are different for >> Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit >> Marvell SoCs. Those registers on Marvell SoCs have different meaning as >> what is defined in PCI and PCIe specs. So it means that lspci _may_ >> display bogus information about PCIe Root Port. pci-mvebu.c uses Root >> Port emulator which fills correct data to make kernel and lspci happy. >> >> If you are going to extend pci-mvebu.c to support also Orion PCIe >> controller, I could try to help with it. But I do not have any Orion >> hardware, so just basic help... >> >> Links to Orion documentations, including PCIe errata is available in >> kernel documentation. So this could help to understand some details: >> https://www.kernel.org/doc/html/latest/arm/marvell.html >> >> Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' >> outputs from Orion? >> >>> Thomas Petazzoni originally wrote the new driver, and I think he was >>> planning at one point to use it for orion5x. I don't know if there were >>> any major problems preventing this at the time, or if it just needs to >>> get hooked up in the dtsi file. >>> >>> Arnd > > There is Orion-specific errata that config space via CF8/CFC registers > is broken. Workaround documented in errata documented (linked from above > documentation) does not work when DMA is used and instead other > undocumented workaround is needed (implemented in arch/arm) which maps > config space to memory (and therefore avoids usage of broken CF8/CFC > memory mapped registers). So basically I should look at arch/arm/plat-orion/pcie.c for the configuration part, add new compatible to pci-mvebu.c for orion5x and alter the probing function accoringly for the same. Did I get it correctly? If so, sounds simple when said out lout but I might need some more pointers to get started. Like with configuration people generally mean setting BARs and WINs? Or is there more to it? :) If you could lay out the basic steps that are needed I would really appreciate it. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-09 10:48 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-09 10:48 UTC (permalink / raw) To: Pali Rohár, Arnd Bergmann Cc: maukka, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On 8.5.2022 18.41, Pali Rohár wrote: > On Sunday 08 May 2022 17:22:37 Pali Rohár wrote: >> On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: >>> On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>> On 28.4.2022 23.56, Arnd Bergmann wrote: >>>>> On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>> On 27.4.2022 21.10, Arnd Bergmann wrote: >>>>>>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>>>> - sata_mv fails to initialise with -22 (-EINVAL) >>>>>>> >>>>>>> No idea, I'd try inserting a printk in every code path that can return -EINVAL >>>>>>> from there >>>>>>> >>>> >>>> With debugging the reason for -EINVAL remains a bit mystery. >>>> - sata_mv calls ata_host_activate() [1] >>>> - later on, in request_threaded_irq(), there are sanity checks [2] >>>> - that fail with irq_settings_can_request() returning 0 [3] >>>> >>>> I cannot really put my finger on why the irq cannot be requested in DT >>>> approach. >>> >>> Are you sure the marvell,orion-intc driver is successfully probed >>> at this point? If not, the interrupt won't be there. >>> >>> I see that the "sata_mv" driver can be used either as a platform >>> driver for the orion5x on-chip controller, or as a PCI driver for >>> an add-on chip connected to the external bus. It sounds like >>> your system has both. Do you know which one fails? >>> >>> The PCI driver cannot work unless the PCI host works correctly, >>> and that in turn requires a correct devicetree description for it. >>> >>>>>> Is there a way to describe the PCIe bus in the >>>>>> device tree? The initalisation of that bus is done for rev A1 only. >>>>> >>>>> I'm not too familiar with the platform, but my interpretation is that the >>>>> DT support here is incomplete: >>>>> >>>>> The DT based PCI probe using drivers/pci/controller/pci-mvebu.c >>>>> is not hooked up in orion5x.dtsi, and the traditional pci code does >>>>> not work with DT. >>>> >>>> Can the existing pci code still be used to init the PCI bus and describe >>>> the rest in the DT or is it a futile attempt? >> >> Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and >> PCIe buses. This is not device tree driver. > > Correction, Orion PCIe driver is arch/arm/plat-orion/pcie.c and it calls > common functions from mach-orion5x/pci.c driver. > >>>>> I see that orion5x has two separate blocks -- a PCIe host that is >>>>> similar to the kirkwood one, and a legacy PCI host that needs >>>>> a completely separate driver. >>>>> >>>>> Which of the two do you actually need here? >>>>> >>>> >>>> I really cannot say which one is it. How can I tell? The functions given >>>> in struct hw_pci find their way to drivers/pci/probe.c eventually and >>>> use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or >>>> kirkwood explicitly at least. >>>> >>>> Here's the output from lspci if the ids reveal anything. >>>> >>>> # lspci -v -k >>>> 00:00.0 Class 0580: 11ab:5181 >>>> 01:00.0 Class 0580: 11ab:5181 >>>> 00:01.0 Class 0100: 11ab:7042 sata_mv >>> >>> The first two seem to be the host bridges, but unfortunately they >>> seem both have the same device ID, despite being very different >>> devices. The first one (00:00.0) should be the PCIe driver, the >>> second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 >>> device is a PCIe device, and it's on the bus (00) of the first host >>> bridge. I think this should work with drivers/pci/controller/pci-mvebu.c >>> if you add the bits for probing. >> >> Last time when I looked on Orion PCIe controller registers, I though >> that they are same as in Kirkwood PCIe controller registers. And >> Kirkwood is already supported by pci-mvebu.c driver. >> >> About PCI host bridge, I do not know. >> >> Beware that PCI Class Id and all PCI registers which are different for >> Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit >> Marvell SoCs. Those registers on Marvell SoCs have different meaning as >> what is defined in PCI and PCIe specs. So it means that lspci _may_ >> display bogus information about PCIe Root Port. pci-mvebu.c uses Root >> Port emulator which fills correct data to make kernel and lspci happy. >> >> If you are going to extend pci-mvebu.c to support also Orion PCIe >> controller, I could try to help with it. But I do not have any Orion >> hardware, so just basic help... >> >> Links to Orion documentations, including PCIe errata is available in >> kernel documentation. So this could help to understand some details: >> https://www.kernel.org/doc/html/latest/arm/marvell.html >> >> Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' >> outputs from Orion? >> >>> Thomas Petazzoni originally wrote the new driver, and I think he was >>> planning at one point to use it for orion5x. I don't know if there were >>> any major problems preventing this at the time, or if it just needs to >>> get hooked up in the dtsi file. >>> >>> Arnd > > There is Orion-specific errata that config space via CF8/CFC registers > is broken. Workaround documented in errata documented (linked from above > documentation) does not work when DMA is used and instead other > undocumented workaround is needed (implemented in arch/arm) which maps > config space to memory (and therefore avoids usage of broken CF8/CFC > memory mapped registers). So basically I should look at arch/arm/plat-orion/pcie.c for the configuration part, add new compatible to pci-mvebu.c for orion5x and alter the probing function accoringly for the same. Did I get it correctly? If so, sounds simple when said out lout but I might need some more pointers to get started. Like with configuration people generally mean setting BARs and WINs? Or is there more to it? :) If you could lay out the basic steps that are needed I would really appreciate it. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-05-09 10:48 ` Mauri Sandberg @ 2022-05-09 11:03 ` Pali Rohár -1 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-05-09 11:03 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Monday 09 May 2022 13:48:53 Mauri Sandberg wrote: > On 8.5.2022 18.41, Pali Rohár wrote: > > On Sunday 08 May 2022 17:22:37 Pali Rohár wrote: > >> On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > >>> On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >>>> On 28.4.2022 23.56, Arnd Bergmann wrote: > >>>>> On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >>>>>> On 27.4.2022 21.10, Arnd Bergmann wrote: > >>>>>>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >>>>>>>> - sata_mv fails to initialise with -22 (-EINVAL) > >>>>>>> > >>>>>>> No idea, I'd try inserting a printk in every code path that can return -EINVAL > >>>>>>> from there > >>>>>>> > >>>> > >>>> With debugging the reason for -EINVAL remains a bit mystery. > >>>> - sata_mv calls ata_host_activate() [1] > >>>> - later on, in request_threaded_irq(), there are sanity checks [2] > >>>> - that fail with irq_settings_can_request() returning 0 [3] > >>>> > >>>> I cannot really put my finger on why the irq cannot be requested in DT > >>>> approach. > >>> > >>> Are you sure the marvell,orion-intc driver is successfully probed > >>> at this point? If not, the interrupt won't be there. > >>> > >>> I see that the "sata_mv" driver can be used either as a platform > >>> driver for the orion5x on-chip controller, or as a PCI driver for > >>> an add-on chip connected to the external bus. It sounds like > >>> your system has both. Do you know which one fails? > >>> > >>> The PCI driver cannot work unless the PCI host works correctly, > >>> and that in turn requires a correct devicetree description for it. > >>> > >>>>>> Is there a way to describe the PCIe bus in the > >>>>>> device tree? The initalisation of that bus is done for rev A1 only. > >>>>> > >>>>> I'm not too familiar with the platform, but my interpretation is that the > >>>>> DT support here is incomplete: > >>>>> > >>>>> The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > >>>>> is not hooked up in orion5x.dtsi, and the traditional pci code does > >>>>> not work with DT. > >>>> > >>>> Can the existing pci code still be used to init the PCI bus and describe > >>>> the rest in the DT or is it a futile attempt? > >> > >> Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > >> PCIe buses. This is not device tree driver. > > > > Correction, Orion PCIe driver is arch/arm/plat-orion/pcie.c and it calls > > common functions from mach-orion5x/pci.c driver. > > > >>>>> I see that orion5x has two separate blocks -- a PCIe host that is > >>>>> similar to the kirkwood one, and a legacy PCI host that needs > >>>>> a completely separate driver. > >>>>> > >>>>> Which of the two do you actually need here? > >>>>> > >>>> > >>>> I really cannot say which one is it. How can I tell? The functions given > >>>> in struct hw_pci find their way to drivers/pci/probe.c eventually and > >>>> use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > >>>> kirkwood explicitly at least. > >>>> > >>>> Here's the output from lspci if the ids reveal anything. > >>>> > >>>> # lspci -v -k > >>>> 00:00.0 Class 0580: 11ab:5181 > >>>> 01:00.0 Class 0580: 11ab:5181 > >>>> 00:01.0 Class 0100: 11ab:7042 sata_mv > >>> > >>> The first two seem to be the host bridges, but unfortunately they > >>> seem both have the same device ID, despite being very different > >>> devices. The first one (00:00.0) should be the PCIe driver, the > >>> second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 > >>> device is a PCIe device, and it's on the bus (00) of the first host > >>> bridge. I think this should work with drivers/pci/controller/pci-mvebu.c > >>> if you add the bits for probing. > >> > >> Last time when I looked on Orion PCIe controller registers, I though > >> that they are same as in Kirkwood PCIe controller registers. And > >> Kirkwood is already supported by pci-mvebu.c driver. > >> > >> About PCI host bridge, I do not know. > >> > >> Beware that PCI Class Id and all PCI registers which are different for > >> Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit > >> Marvell SoCs. Those registers on Marvell SoCs have different meaning as > >> what is defined in PCI and PCIe specs. So it means that lspci _may_ > >> display bogus information about PCIe Root Port. pci-mvebu.c uses Root > >> Port emulator which fills correct data to make kernel and lspci happy. > >> > >> If you are going to extend pci-mvebu.c to support also Orion PCIe > >> controller, I could try to help with it. But I do not have any Orion > >> hardware, so just basic help... > >> > >> Links to Orion documentations, including PCIe errata is available in > >> kernel documentation. So this could help to understand some details: > >> https://www.kernel.org/doc/html/latest/arm/marvell.html > >> > >> Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' > >> outputs from Orion? > >> > >>> Thomas Petazzoni originally wrote the new driver, and I think he was > >>> planning at one point to use it for orion5x. I don't know if there were > >>> any major problems preventing this at the time, or if it just needs to > >>> get hooked up in the dtsi file. > >>> > >>> Arnd > > > > There is Orion-specific errata that config space via CF8/CFC registers > > is broken. Workaround documented in errata documented (linked from above > > documentation) does not work when DMA is used and instead other > > undocumented workaround is needed (implemented in arch/arm) which maps > > config space to memory (and therefore avoids usage of broken CF8/CFC > > memory mapped registers). > > So basically I should look at arch/arm/plat-orion/pcie.c for the > configuration part, add new compatible to pci-mvebu.c for orion5x > and alter the probing function accoringly for the same. Did I get > it correctly? You would need to replace mvebu_pcie_child_rd_conf() and mvebu_pcie_child_wr_conf() implementation in pci-mvebu.c with the correct orion implementation. Orion implementation is in function pcie_rd_conf_wa() or pcie_rd_conf() (file arch/arm/mach-orion5x/pci.c) based on the fact if workaround has to be applied or not. Same for *wr* functions. Workaround uses wa_base address, which needs to be mapped via mbus driver. This is something new which is not supported by pci-mvebu.c. And wa_base address should be correctly specified in ranges= property of type "configuration space" (ss = 00). See: https://elinux.org/Device_Tree_Usage#PCI_Address_Translation > If so, sounds simple when said out lout but I might need some more > pointers to get started. Like with configuration people generally > mean setting BARs and WINs? Or is there more to it? :) If you > could lay out the basic steps that are needed I would really > appreciate it. BARs and WINs are configured by pci-mvebu.c. You just have specify correct ids in DTS. See usage of MBUS_ID() macro and Port X IO/MEM comments e.g. in arch/arm/boot/dts/armada-385.dtsi file. Also it is required to set pcie-mem-aperture and pcie-io-aperture properties, see e.g. in arch/arm/boot/dts/armada-38x.dtsi file. I'm not sure if this is clear for you. If not, please ask additional questions :-) ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-09 11:03 ` Pali Rohár 0 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-05-09 11:03 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Monday 09 May 2022 13:48:53 Mauri Sandberg wrote: > On 8.5.2022 18.41, Pali Rohár wrote: > > On Sunday 08 May 2022 17:22:37 Pali Rohár wrote: > >> On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > >>> On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >>>> On 28.4.2022 23.56, Arnd Bergmann wrote: > >>>>> On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >>>>>> On 27.4.2022 21.10, Arnd Bergmann wrote: > >>>>>>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > >>>>>>>> - sata_mv fails to initialise with -22 (-EINVAL) > >>>>>>> > >>>>>>> No idea, I'd try inserting a printk in every code path that can return -EINVAL > >>>>>>> from there > >>>>>>> > >>>> > >>>> With debugging the reason for -EINVAL remains a bit mystery. > >>>> - sata_mv calls ata_host_activate() [1] > >>>> - later on, in request_threaded_irq(), there are sanity checks [2] > >>>> - that fail with irq_settings_can_request() returning 0 [3] > >>>> > >>>> I cannot really put my finger on why the irq cannot be requested in DT > >>>> approach. > >>> > >>> Are you sure the marvell,orion-intc driver is successfully probed > >>> at this point? If not, the interrupt won't be there. > >>> > >>> I see that the "sata_mv" driver can be used either as a platform > >>> driver for the orion5x on-chip controller, or as a PCI driver for > >>> an add-on chip connected to the external bus. It sounds like > >>> your system has both. Do you know which one fails? > >>> > >>> The PCI driver cannot work unless the PCI host works correctly, > >>> and that in turn requires a correct devicetree description for it. > >>> > >>>>>> Is there a way to describe the PCIe bus in the > >>>>>> device tree? The initalisation of that bus is done for rev A1 only. > >>>>> > >>>>> I'm not too familiar with the platform, but my interpretation is that the > >>>>> DT support here is incomplete: > >>>>> > >>>>> The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > >>>>> is not hooked up in orion5x.dtsi, and the traditional pci code does > >>>>> not work with DT. > >>>> > >>>> Can the existing pci code still be used to init the PCI bus and describe > >>>> the rest in the DT or is it a futile attempt? > >> > >> Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > >> PCIe buses. This is not device tree driver. > > > > Correction, Orion PCIe driver is arch/arm/plat-orion/pcie.c and it calls > > common functions from mach-orion5x/pci.c driver. > > > >>>>> I see that orion5x has two separate blocks -- a PCIe host that is > >>>>> similar to the kirkwood one, and a legacy PCI host that needs > >>>>> a completely separate driver. > >>>>> > >>>>> Which of the two do you actually need here? > >>>>> > >>>> > >>>> I really cannot say which one is it. How can I tell? The functions given > >>>> in struct hw_pci find their way to drivers/pci/probe.c eventually and > >>>> use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > >>>> kirkwood explicitly at least. > >>>> > >>>> Here's the output from lspci if the ids reveal anything. > >>>> > >>>> # lspci -v -k > >>>> 00:00.0 Class 0580: 11ab:5181 > >>>> 01:00.0 Class 0580: 11ab:5181 > >>>> 00:01.0 Class 0100: 11ab:7042 sata_mv > >>> > >>> The first two seem to be the host bridges, but unfortunately they > >>> seem both have the same device ID, despite being very different > >>> devices. The first one (00:00.0) should be the PCIe driver, the > >>> second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 > >>> device is a PCIe device, and it's on the bus (00) of the first host > >>> bridge. I think this should work with drivers/pci/controller/pci-mvebu.c > >>> if you add the bits for probing. > >> > >> Last time when I looked on Orion PCIe controller registers, I though > >> that they are same as in Kirkwood PCIe controller registers. And > >> Kirkwood is already supported by pci-mvebu.c driver. > >> > >> About PCI host bridge, I do not know. > >> > >> Beware that PCI Class Id and all PCI registers which are different for > >> Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit > >> Marvell SoCs. Those registers on Marvell SoCs have different meaning as > >> what is defined in PCI and PCIe specs. So it means that lspci _may_ > >> display bogus information about PCIe Root Port. pci-mvebu.c uses Root > >> Port emulator which fills correct data to make kernel and lspci happy. > >> > >> If you are going to extend pci-mvebu.c to support also Orion PCIe > >> controller, I could try to help with it. But I do not have any Orion > >> hardware, so just basic help... > >> > >> Links to Orion documentations, including PCIe errata is available in > >> kernel documentation. So this could help to understand some details: > >> https://www.kernel.org/doc/html/latest/arm/marvell.html > >> > >> Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' > >> outputs from Orion? > >> > >>> Thomas Petazzoni originally wrote the new driver, and I think he was > >>> planning at one point to use it for orion5x. I don't know if there were > >>> any major problems preventing this at the time, or if it just needs to > >>> get hooked up in the dtsi file. > >>> > >>> Arnd > > > > There is Orion-specific errata that config space via CF8/CFC registers > > is broken. Workaround documented in errata documented (linked from above > > documentation) does not work when DMA is used and instead other > > undocumented workaround is needed (implemented in arch/arm) which maps > > config space to memory (and therefore avoids usage of broken CF8/CFC > > memory mapped registers). > > So basically I should look at arch/arm/plat-orion/pcie.c for the > configuration part, add new compatible to pci-mvebu.c for orion5x > and alter the probing function accoringly for the same. Did I get > it correctly? You would need to replace mvebu_pcie_child_rd_conf() and mvebu_pcie_child_wr_conf() implementation in pci-mvebu.c with the correct orion implementation. Orion implementation is in function pcie_rd_conf_wa() or pcie_rd_conf() (file arch/arm/mach-orion5x/pci.c) based on the fact if workaround has to be applied or not. Same for *wr* functions. Workaround uses wa_base address, which needs to be mapped via mbus driver. This is something new which is not supported by pci-mvebu.c. And wa_base address should be correctly specified in ranges= property of type "configuration space" (ss = 00). See: https://elinux.org/Device_Tree_Usage#PCI_Address_Translation > If so, sounds simple when said out lout but I might need some more > pointers to get started. Like with configuration people generally > mean setting BARs and WINs? Or is there more to it? :) If you > could lay out the basic steps that are needed I would really > appreciate it. BARs and WINs are configured by pci-mvebu.c. You just have specify correct ids in DTS. See usage of MBUS_ID() macro and Port X IO/MEM comments e.g. in arch/arm/boot/dts/armada-385.dtsi file. Also it is required to set pcie-mem-aperture and pcie-io-aperture properties, see e.g. in arch/arm/boot/dts/armada-38x.dtsi file. I'm not sure if this is clear for you. If not, please ask additional questions :-) _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-05-08 15:22 ` Pali Rohár @ 2022-05-08 19:34 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-08 19:34 UTC (permalink / raw) To: Pali Rohár, Arnd Bergmann Cc: SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On 08.05.22 18:22, Pali Rohár wrote: > On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: >> On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>> On 28.4.2022 23.56, Arnd Bergmann wrote: >>>> On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>> On 27.4.2022 21.10, Arnd Bergmann wrote: >>>>>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>>> - sata_mv fails to initialise with -22 (-EINVAL) >>>>>> >>>>>> No idea, I'd try inserting a printk in every code path that can return -EINVAL >>>>>> from there >>>>>> >>> >>> With debugging the reason for -EINVAL remains a bit mystery. >>> - sata_mv calls ata_host_activate() [1] >>> - later on, in request_threaded_irq(), there are sanity checks [2] >>> - that fail with irq_settings_can_request() returning 0 [3] >>> >>> I cannot really put my finger on why the irq cannot be requested in DT >>> approach. >> >> Are you sure the marvell,orion-intc driver is successfully probed >> at this point? If not, the interrupt won't be there. I made the pci setup to be the very last thing in the boot and results are still the same. There are other devices that do get their interrupts from intc. >> >> I see that the "sata_mv" driver can be used either as a platform >> driver for the orion5x on-chip controller, or as a PCI driver for >> an add-on chip connected to the external bus. It sounds like >> your system has both. Do you know which one fails? >> >> The PCI driver cannot work unless the PCI host works correctly, >> and that in turn requires a correct devicetree description for it. >> >>>>> Is there a way to describe the PCIe bus in the >>>>> device tree? The initalisation of that bus is done for rev A1 only. >>>> >>>> I'm not too familiar with the platform, but my interpretation is that the >>>> DT support here is incomplete: >>>> >>>> The DT based PCI probe using drivers/pci/controller/pci-mvebu.c >>>> is not hooked up in orion5x.dtsi, and the traditional pci code does >>>> not work with DT. >>> >>> Can the existing pci code still be used to init the PCI bus and describe >>> the rest in the DT or is it a futile attempt? > > Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > PCIe buses. This is not device tree driver. > >>>> I see that orion5x has two separate blocks -- a PCIe host that is >>>> similar to the kirkwood one, and a legacy PCI host that needs >>>> a completely separate driver. >>>> >>>> Which of the two do you actually need here? >>>> >>> >>> I really cannot say which one is it. How can I tell? The functions given >>> in struct hw_pci find their way to drivers/pci/probe.c eventually and >>> use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or >>> kirkwood explicitly at least. >>> >>> Here's the output from lspci if the ids reveal anything. >>> >>> # lspci -v -k >>> 00:00.0 Class 0580: 11ab:5181 >>> 01:00.0 Class 0580: 11ab:5181 >>> 00:01.0 Class 0100: 11ab:7042 sata_mv >> >> The first two seem to be the host bridges, but unfortunately they >> seem both have the same device ID, despite being very different >> devices. The first one (00:00.0) should be the PCIe driver, the >> second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 >> device is a PCIe device, and it's on the bus (00) of the first host >> bridge. I think this should work with drivers/pci/controller/pci-mvebu.c >> if you add the bits for probing. > > Last time when I looked on Orion PCIe controller registers, I though > that they are same as in Kirkwood PCIe controller registers. And > Kirkwood is already supported by pci-mvebu.c driver. > I seemed that way to me too on the first glance. And it looks like there are no devices using the PCI driver. I knocked off that part altogether and the boot log looks pretty much the same it was. Perhaps I can do with describing the PCIe bus only. > About PCI host bridge, I do not know. > > Beware that PCI Class Id and all PCI registers which are different for > Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit > Marvell SoCs. Those registers on Marvell SoCs have different meaning as > what is defined in PCI and PCIe specs. So it means that lspci _may_ > display bogus information about PCIe Root Port. pci-mvebu.c uses Root > Port emulator which fills correct data to make kernel and lspci happy. > > If you are going to extend pci-mvebu.c to support also Orion PCIe > controller, I could try to help with it. But I do not have any Orion > hardware, so just basic help... I could make an attempt at this. Should I try to look at an existing kirkwood based device first, say kirkwood-6281.dtsi? I didn't see anything SoC-specific in pci-mvebu.c. All different compatibles seem to share the same functionality. > > Links to Orion documentations, including PCIe errata is available in > kernel documentation. So this could help to understand some details: > https://www.kernel.org/doc/html/latest/arm/marvell.html > > Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' > outputs from Orion? # lspci -nn -vv 0000:00:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] (rev 03) Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 0 Region 0: Memory at <ignored> (64-bit, prefetchable) Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE- DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s <256ns ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s (ok), Width x1 (ok) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- RootCap: CRSVisible- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- 0000:00:01.0 SCSI storage controller [0100]: Marvell Technology Group Ltd. 88SX7042 PCI-e 4-port SATA-II [11ab:7042] (rev 02) Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 12 Region 0: Memory at e0000000 (64-bit, non-prefetchable) [size=1M] Region 2: I/O ports at 1000 [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) Legacy Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <256ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Exit Latency L0s <256ns ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s (ok), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Kernel driver in use: sata_mv 0001:01:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] (rev 03) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B+ DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 0 BIST result: 00 Region 0: Memory at <unassigned> (64-bit, prefetchable) Region 2: Memory at <ignored> (64-bit, prefetchable) Region 4: Memory at <ignored> (64-bit, non-prefetchable) Expansion ROM at <ignored> [disabled] Capabilities: [40] Power Management version 2 Flags: PMEClk+ DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ Capabilities: [48] Vital Product Data Not readable Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] PCI-X non-bridge device Command: DPERE- ERO- RBC=512 OST=4 Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- DC=bridge DMMRBC=512 DMOST=4 DMCRS=8 RSCEM- 266MHz- 533MHz- Capabilities: [68] CompactPCI hot-swap <?> # lspci -nn -t -v -+-[0001:01]---00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] \-[0000:00]-+-00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] \-01.0 Marvell Technology Group Ltd. 88SX7042 PCI-e 4-port SATA-II [11ab:7042] > >> Thomas Petazzoni originally wrote the new driver, and I think he was >> planning at one point to use it for orion5x. I don't know if there were >> any major problems preventing this at the time, or if it just needs to >> get hooked up in the dtsi file. >> >> Arnd -- Mauri ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-08 19:34 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-08 19:34 UTC (permalink / raw) To: Pali Rohár, Arnd Bergmann Cc: SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On 08.05.22 18:22, Pali Rohár wrote: > On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: >> On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>> On 28.4.2022 23.56, Arnd Bergmann wrote: >>>> On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>> On 27.4.2022 21.10, Arnd Bergmann wrote: >>>>>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>>> - sata_mv fails to initialise with -22 (-EINVAL) >>>>>> >>>>>> No idea, I'd try inserting a printk in every code path that can return -EINVAL >>>>>> from there >>>>>> >>> >>> With debugging the reason for -EINVAL remains a bit mystery. >>> - sata_mv calls ata_host_activate() [1] >>> - later on, in request_threaded_irq(), there are sanity checks [2] >>> - that fail with irq_settings_can_request() returning 0 [3] >>> >>> I cannot really put my finger on why the irq cannot be requested in DT >>> approach. >> >> Are you sure the marvell,orion-intc driver is successfully probed >> at this point? If not, the interrupt won't be there. I made the pci setup to be the very last thing in the boot and results are still the same. There are other devices that do get their interrupts from intc. >> >> I see that the "sata_mv" driver can be used either as a platform >> driver for the orion5x on-chip controller, or as a PCI driver for >> an add-on chip connected to the external bus. It sounds like >> your system has both. Do you know which one fails? >> >> The PCI driver cannot work unless the PCI host works correctly, >> and that in turn requires a correct devicetree description for it. >> >>>>> Is there a way to describe the PCIe bus in the >>>>> device tree? The initalisation of that bus is done for rev A1 only. >>>> >>>> I'm not too familiar with the platform, but my interpretation is that the >>>> DT support here is incomplete: >>>> >>>> The DT based PCI probe using drivers/pci/controller/pci-mvebu.c >>>> is not hooked up in orion5x.dtsi, and the traditional pci code does >>>> not work with DT. >>> >>> Can the existing pci code still be used to init the PCI bus and describe >>> the rest in the DT or is it a futile attempt? > > Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > PCIe buses. This is not device tree driver. > >>>> I see that orion5x has two separate blocks -- a PCIe host that is >>>> similar to the kirkwood one, and a legacy PCI host that needs >>>> a completely separate driver. >>>> >>>> Which of the two do you actually need here? >>>> >>> >>> I really cannot say which one is it. How can I tell? The functions given >>> in struct hw_pci find their way to drivers/pci/probe.c eventually and >>> use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or >>> kirkwood explicitly at least. >>> >>> Here's the output from lspci if the ids reveal anything. >>> >>> # lspci -v -k >>> 00:00.0 Class 0580: 11ab:5181 >>> 01:00.0 Class 0580: 11ab:5181 >>> 00:01.0 Class 0100: 11ab:7042 sata_mv >> >> The first two seem to be the host bridges, but unfortunately they >> seem both have the same device ID, despite being very different >> devices. The first one (00:00.0) should be the PCIe driver, the >> second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 >> device is a PCIe device, and it's on the bus (00) of the first host >> bridge. I think this should work with drivers/pci/controller/pci-mvebu.c >> if you add the bits for probing. > > Last time when I looked on Orion PCIe controller registers, I though > that they are same as in Kirkwood PCIe controller registers. And > Kirkwood is already supported by pci-mvebu.c driver. > I seemed that way to me too on the first glance. And it looks like there are no devices using the PCI driver. I knocked off that part altogether and the boot log looks pretty much the same it was. Perhaps I can do with describing the PCIe bus only. > About PCI host bridge, I do not know. > > Beware that PCI Class Id and all PCI registers which are different for > Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit > Marvell SoCs. Those registers on Marvell SoCs have different meaning as > what is defined in PCI and PCIe specs. So it means that lspci _may_ > display bogus information about PCIe Root Port. pci-mvebu.c uses Root > Port emulator which fills correct data to make kernel and lspci happy. > > If you are going to extend pci-mvebu.c to support also Orion PCIe > controller, I could try to help with it. But I do not have any Orion > hardware, so just basic help... I could make an attempt at this. Should I try to look at an existing kirkwood based device first, say kirkwood-6281.dtsi? I didn't see anything SoC-specific in pci-mvebu.c. All different compatibles seem to share the same functionality. > > Links to Orion documentations, including PCIe errata is available in > kernel documentation. So this could help to understand some details: > https://www.kernel.org/doc/html/latest/arm/marvell.html > > Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' > outputs from Orion? # lspci -nn -vv 0000:00:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] (rev 03) Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 0 Region 0: Memory at <ignored> (64-bit, prefetchable) Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE- DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s <256ns ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s (ok), Width x1 (ok) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- RootCap: CRSVisible- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- 0000:00:01.0 SCSI storage controller [0100]: Marvell Technology Group Ltd. 88SX7042 PCI-e 4-port SATA-II [11ab:7042] (rev 02) Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 12 Region 0: Memory at e0000000 (64-bit, non-prefetchable) [size=1M] Region 2: I/O ports at 1000 [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) Legacy Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <256ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Exit Latency L0s <256ns ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s (ok), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Kernel driver in use: sata_mv 0001:01:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] (rev 03) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B+ DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 0 BIST result: 00 Region 0: Memory at <unassigned> (64-bit, prefetchable) Region 2: Memory at <ignored> (64-bit, prefetchable) Region 4: Memory at <ignored> (64-bit, non-prefetchable) Expansion ROM at <ignored> [disabled] Capabilities: [40] Power Management version 2 Flags: PMEClk+ DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ Capabilities: [48] Vital Product Data Not readable Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] PCI-X non-bridge device Command: DPERE- ERO- RBC=512 OST=4 Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- DC=bridge DMMRBC=512 DMOST=4 DMCRS=8 RSCEM- 266MHz- 533MHz- Capabilities: [68] CompactPCI hot-swap <?> # lspci -nn -t -v -+-[0001:01]---00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] \-[0000:00]-+-00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] \-01.0 Marvell Technology Group Ltd. 88SX7042 PCI-e 4-port SATA-II [11ab:7042] > >> Thomas Petazzoni originally wrote the new driver, and I think he was >> planning at one point to use it for orion5x. I don't know if there were >> any major problems preventing this at the time, or if it just needs to >> get hooked up in the dtsi file. >> >> Arnd -- Mauri _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-05-08 19:34 ` Mauri Sandberg @ 2022-05-08 20:10 ` Pali Rohár -1 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-05-08 20:10 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Sunday 08 May 2022 22:34:19 Mauri Sandberg wrote: > On 08.05.22 18:22, Pali Rohár wrote: > > On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > > > On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > > On 28.4.2022 23.56, Arnd Bergmann wrote: > > > > > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > > > > On 27.4.2022 21.10, Arnd Bergmann wrote: > > > > > > > On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > > > > > > - sata_mv fails to initialise with -22 (-EINVAL) > > > > > > > > > > > > > > No idea, I'd try inserting a printk in every code path that can return -EINVAL > > > > > > > from there > > > > > > > > > > > > > > > With debugging the reason for -EINVAL remains a bit mystery. > > > > - sata_mv calls ata_host_activate() [1] > > > > - later on, in request_threaded_irq(), there are sanity checks [2] > > > > - that fail with irq_settings_can_request() returning 0 [3] > > > > > > > > I cannot really put my finger on why the irq cannot be requested in DT > > > > approach. > > > > > > Are you sure the marvell,orion-intc driver is successfully probed > > > at this point? If not, the interrupt won't be there. > > I made the pci setup to be the very last thing in the boot and > results are still the same. There are other devices that do get > their interrupts from intc. > > > > > > > I see that the "sata_mv" driver can be used either as a platform > > > driver for the orion5x on-chip controller, or as a PCI driver for > > > an add-on chip connected to the external bus. It sounds like > > > your system has both. Do you know which one fails? > > > > > > The PCI driver cannot work unless the PCI host works correctly, > > > and that in turn requires a correct devicetree description for it. > > > > > > > > > Is there a way to describe the PCIe bus in the > > > > > > device tree? The initalisation of that bus is done for rev A1 only. > > > > > > > > > > I'm not too familiar with the platform, but my interpretation is that the > > > > > DT support here is incomplete: > > > > > > > > > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > > > > > is not hooked up in orion5x.dtsi, and the traditional pci code does > > > > > not work with DT. > > > > > > > > Can the existing pci code still be used to init the PCI bus and describe > > > > the rest in the DT or is it a futile attempt? > > > > Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > > PCIe buses. This is not device tree driver. > > > > > > > I see that orion5x has two separate blocks -- a PCIe host that is > > > > > similar to the kirkwood one, and a legacy PCI host that needs > > > > > a completely separate driver. > > > > > > > > > > Which of the two do you actually need here? > > > > > > > > > > > > > I really cannot say which one is it. How can I tell? The functions given > > > > in struct hw_pci find their way to drivers/pci/probe.c eventually and > > > > use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > > > > kirkwood explicitly at least. > > > > > > > > Here's the output from lspci if the ids reveal anything. > > > > > > > > # lspci -v -k > > > > 00:00.0 Class 0580: 11ab:5181 > > > > 01:00.0 Class 0580: 11ab:5181 > > > > 00:01.0 Class 0100: 11ab:7042 sata_mv > > > > > > The first two seem to be the host bridges, but unfortunately they > > > seem both have the same device ID, despite being very different > > > devices. The first one (00:00.0) should be the PCIe driver, the > > > second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 > > > device is a PCIe device, and it's on the bus (00) of the first host > > > bridge. I think this should work with drivers/pci/controller/pci-mvebu.c > > > if you add the bits for probing. > > > > Last time when I looked on Orion PCIe controller registers, I though > > that they are same as in Kirkwood PCIe controller registers. And > > Kirkwood is already supported by pci-mvebu.c driver. > > > > I seemed that way to me too on the first glance. And it looks like there > are no devices using the PCI driver. I knocked off that part altogether and > the boot log looks pretty much the same it was. Perhaps I can do > with describing the PCIe bus only. > > > About PCI host bridge, I do not know. > > > > Beware that PCI Class Id and all PCI registers which are different for > > Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit > > Marvell SoCs. Those registers on Marvell SoCs have different meaning as > > what is defined in PCI and PCIe specs. So it means that lspci _may_ > > display bogus information about PCIe Root Port. pci-mvebu.c uses Root > > Port emulator which fills correct data to make kernel and lspci happy. > > > > If you are going to extend pci-mvebu.c to support also Orion PCIe > > controller, I could try to help with it. But I do not have any Orion > > hardware, so just basic help... > > I could make an attempt at this. Should I try to look at an existing > kirkwood based device first, say kirkwood-6281.dtsi? I didn't see > anything SoC-specific in pci-mvebu.c. All different compatibles seem > to share the same functionality. Yes, this could be a good starting point. But you will need new compatible string for orion, specially to implement workaround for accessing config space. > > > > Links to Orion documentations, including PCIe errata is available in > > kernel documentation. So this could help to understand some details: > > https://www.kernel.org/doc/html/latest/arm/marvell.html > > > > Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' > > outputs from Orion? > > # lspci -nn -vv > 0000:00:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 > [Orion-1] ARM SoC [11ab:5181] (rev 03) > Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ > Stepping- SERR+ FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 0 > Region 0: Memory at <ignored> (64-bit, prefetchable) > Capabilities: [40] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Capabilities: [60] Express (v1) Root Port (Slot-), MSI 00 > DevCap: MaxPayload 128 bytes, PhantFunc 0 > ExtTag- RBE- > DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 128 bytes, MaxReadReq 512 bytes > DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s > <256ns > ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- > LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s (ok), Width x1 (ok) > TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- > RootCap: CRSVisible- > RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- > RootSta: PME ReqID 0000, PMEStatus- PMEPending- > > 0000:00:01.0 SCSI storage controller [0100]: Marvell Technology Group Ltd. > 88SX7042 PCI-e 4-port SATA-II [11ab:7042] (rev 02) > Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ > Stepping- SERR+ FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 12 > Region 0: Memory at e0000000 (64-bit, non-prefetchable) [size=1M] > Region 2: I/O ports at 1000 [size=256] > Capabilities: [40] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Capabilities: [60] Express (v1) Legacy Endpoint, MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <256ns, L1 <1us > ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- > DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 128 bytes, MaxReadReq 512 bytes > DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Exit Latency L0s > <256ns > ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- > LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s (ok), Width x1 (downgraded) > TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- > Kernel driver in use: sata_mv > > 0001:01:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 > [Orion-1] ARM SoC [11ab:5181] (rev 03) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ > Stepping- SERR+ FastB2B+ DisINTx- > Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort+ >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 0 > BIST result: 00 > Region 0: Memory at <unassigned> (64-bit, prefetchable) > Region 2: Memory at <ignored> (64-bit, prefetchable) > Region 4: Memory at <ignored> (64-bit, non-prefetchable) > Expansion ROM at <ignored> [disabled] > Capabilities: [40] Power Management version 2 > Flags: PMEClk+ DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ > Capabilities: [48] Vital Product Data > Not readable > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Capabilities: [60] PCI-X non-bridge device > Command: DPERE- ERO- RBC=512 OST=4 > Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- DC=bridge DMMRBC=512 DMOST=4 > DMCRS=8 RSCEM- 266MHz- 533MHz- > Capabilities: [68] CompactPCI hot-swap <?> > > # lspci -nn -t -v > -+-[0001:01]---00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC > [11ab:5181] > \-[0000:00]-+-00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC > [11ab:5181] > \-01.0 Marvell Technology Group Ltd. 88SX7042 PCI-e 4-port > SATA-II [11ab:7042] Ok, so domain 0 is PCIe bus for sure. 0000:00:00.0 is PCIe Root Port (PCI-to-PCI bridge) incorrectly detected as Memory controller (known HW issue on all 32-bit Marvell SoCs). 0000:00:01.0 seems to be that SATA controller and this device is connected behind the PCIe Root Port. Topology is also incorrectly reports due to same known issue. Then there is domain 1 (first line in -t output) on which is just one device 0001:01:00.0 detected as Memory controller and has capability of "PCI-X non-bridge device". This seems to be PCI bus. I guess that Memory controller is also bogus information. What is "PCI-X non-bridge device"? I thought that "root" of the PCI bus should be Host Bridge. Anyway, there is my pending patch which should fix Class ID to not report incorrect Memory controller identification: https://lore.kernel.org/linux-pci/20211102171259.9590-1-pali@kernel.org/#Z31arch:arm:mach-orion5x:pci.c > > > > > Thomas Petazzoni originally wrote the new driver, and I think he was > > > planning at one point to use it for orion5x. I don't know if there were > > > any major problems preventing this at the time, or if it just needs to > > > get hooked up in the dtsi file. > > > > > > Arnd > > -- Mauri ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-08 20:10 ` Pali Rohár 0 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-05-08 20:10 UTC (permalink / raw) To: Mauri Sandberg Cc: Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On Sunday 08 May 2022 22:34:19 Mauri Sandberg wrote: > On 08.05.22 18:22, Pali Rohár wrote: > > On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: > > > On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > > On 28.4.2022 23.56, Arnd Bergmann wrote: > > > > > On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > > > > On 27.4.2022 21.10, Arnd Bergmann wrote: > > > > > > > On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: > > > > > > > > - sata_mv fails to initialise with -22 (-EINVAL) > > > > > > > > > > > > > > No idea, I'd try inserting a printk in every code path that can return -EINVAL > > > > > > > from there > > > > > > > > > > > > > > > With debugging the reason for -EINVAL remains a bit mystery. > > > > - sata_mv calls ata_host_activate() [1] > > > > - later on, in request_threaded_irq(), there are sanity checks [2] > > > > - that fail with irq_settings_can_request() returning 0 [3] > > > > > > > > I cannot really put my finger on why the irq cannot be requested in DT > > > > approach. > > > > > > Are you sure the marvell,orion-intc driver is successfully probed > > > at this point? If not, the interrupt won't be there. > > I made the pci setup to be the very last thing in the boot and > results are still the same. There are other devices that do get > their interrupts from intc. > > > > > > > I see that the "sata_mv" driver can be used either as a platform > > > driver for the orion5x on-chip controller, or as a PCI driver for > > > an add-on chip connected to the external bus. It sounds like > > > your system has both. Do you know which one fails? > > > > > > The PCI driver cannot work unless the PCI host works correctly, > > > and that in turn requires a correct devicetree description for it. > > > > > > > > > Is there a way to describe the PCIe bus in the > > > > > > device tree? The initalisation of that bus is done for rev A1 only. > > > > > > > > > > I'm not too familiar with the platform, but my interpretation is that the > > > > > DT support here is incomplete: > > > > > > > > > > The DT based PCI probe using drivers/pci/controller/pci-mvebu.c > > > > > is not hooked up in orion5x.dtsi, and the traditional pci code does > > > > > not work with DT. > > > > > > > > Can the existing pci code still be used to init the PCI bus and describe > > > > the rest in the DT or is it a futile attempt? > > > > Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and > > PCIe buses. This is not device tree driver. > > > > > > > I see that orion5x has two separate blocks -- a PCIe host that is > > > > > similar to the kirkwood one, and a legacy PCI host that needs > > > > > a completely separate driver. > > > > > > > > > > Which of the two do you actually need here? > > > > > > > > > > > > > I really cannot say which one is it. How can I tell? The functions given > > > > in struct hw_pci find their way to drivers/pci/probe.c eventually and > > > > use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or > > > > kirkwood explicitly at least. > > > > > > > > Here's the output from lspci if the ids reveal anything. > > > > > > > > # lspci -v -k > > > > 00:00.0 Class 0580: 11ab:5181 > > > > 01:00.0 Class 0580: 11ab:5181 > > > > 00:01.0 Class 0100: 11ab:7042 sata_mv > > > > > > The first two seem to be the host bridges, but unfortunately they > > > seem both have the same device ID, despite being very different > > > devices. The first one (00:00.0) should be the PCIe driver, the > > > second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 > > > device is a PCIe device, and it's on the bus (00) of the first host > > > bridge. I think this should work with drivers/pci/controller/pci-mvebu.c > > > if you add the bits for probing. > > > > Last time when I looked on Orion PCIe controller registers, I though > > that they are same as in Kirkwood PCIe controller registers. And > > Kirkwood is already supported by pci-mvebu.c driver. > > > > I seemed that way to me too on the first glance. And it looks like there > are no devices using the PCI driver. I knocked off that part altogether and > the boot log looks pretty much the same it was. Perhaps I can do > with describing the PCIe bus only. > > > About PCI host bridge, I do not know. > > > > Beware that PCI Class Id and all PCI registers which are different for > > Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit > > Marvell SoCs. Those registers on Marvell SoCs have different meaning as > > what is defined in PCI and PCIe specs. So it means that lspci _may_ > > display bogus information about PCIe Root Port. pci-mvebu.c uses Root > > Port emulator which fills correct data to make kernel and lspci happy. > > > > If you are going to extend pci-mvebu.c to support also Orion PCIe > > controller, I could try to help with it. But I do not have any Orion > > hardware, so just basic help... > > I could make an attempt at this. Should I try to look at an existing > kirkwood based device first, say kirkwood-6281.dtsi? I didn't see > anything SoC-specific in pci-mvebu.c. All different compatibles seem > to share the same functionality. Yes, this could be a good starting point. But you will need new compatible string for orion, specially to implement workaround for accessing config space. > > > > Links to Orion documentations, including PCIe errata is available in > > kernel documentation. So this could help to understand some details: > > https://www.kernel.org/doc/html/latest/arm/marvell.html > > > > Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' > > outputs from Orion? > > # lspci -nn -vv > 0000:00:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 > [Orion-1] ARM SoC [11ab:5181] (rev 03) > Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ > Stepping- SERR+ FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 0 > Region 0: Memory at <ignored> (64-bit, prefetchable) > Capabilities: [40] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Capabilities: [60] Express (v1) Root Port (Slot-), MSI 00 > DevCap: MaxPayload 128 bytes, PhantFunc 0 > ExtTag- RBE- > DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 128 bytes, MaxReadReq 512 bytes > DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s > <256ns > ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- > LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s (ok), Width x1 (ok) > TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- > RootCap: CRSVisible- > RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- > RootSta: PME ReqID 0000, PMEStatus- PMEPending- > > 0000:00:01.0 SCSI storage controller [0100]: Marvell Technology Group Ltd. > 88SX7042 PCI-e 4-port SATA-II [11ab:7042] (rev 02) > Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ > Stepping- SERR+ FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- > <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 12 > Region 0: Memory at e0000000 (64-bit, non-prefetchable) [size=1M] > Region 2: I/O ports at 1000 [size=256] > Capabilities: [40] Power Management version 2 > Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Capabilities: [60] Express (v1) Legacy Endpoint, MSI 00 > DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <256ns, L1 <1us > ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- > DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- > RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- > MaxPayload 128 bytes, MaxReadReq 512 bytes > DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Exit Latency L0s > <256ns > ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- > LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s (ok), Width x1 (downgraded) > TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- > Kernel driver in use: sata_mv > > 0001:01:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 > [Orion-1] ARM SoC [11ab:5181] (rev 03) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ > Stepping- SERR+ FastB2B+ DisINTx- > Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- > <MAbort+ >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 32 bytes > Interrupt: pin A routed to IRQ 0 > BIST result: 00 > Region 0: Memory at <unassigned> (64-bit, prefetchable) > Region 2: Memory at <ignored> (64-bit, prefetchable) > Region 4: Memory at <ignored> (64-bit, non-prefetchable) > Expansion ROM at <ignored> [disabled] > Capabilities: [40] Power Management version 2 > Flags: PMEClk+ DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ > Capabilities: [48] Vital Product Data > Not readable > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Address: 0000000000000000 Data: 0000 > Capabilities: [60] PCI-X non-bridge device > Command: DPERE- ERO- RBC=512 OST=4 > Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- DC=bridge DMMRBC=512 DMOST=4 > DMCRS=8 RSCEM- 266MHz- 533MHz- > Capabilities: [68] CompactPCI hot-swap <?> > > # lspci -nn -t -v > -+-[0001:01]---00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC > [11ab:5181] > \-[0000:00]-+-00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC > [11ab:5181] > \-01.0 Marvell Technology Group Ltd. 88SX7042 PCI-e 4-port > SATA-II [11ab:7042] Ok, so domain 0 is PCIe bus for sure. 0000:00:00.0 is PCIe Root Port (PCI-to-PCI bridge) incorrectly detected as Memory controller (known HW issue on all 32-bit Marvell SoCs). 0000:00:01.0 seems to be that SATA controller and this device is connected behind the PCIe Root Port. Topology is also incorrectly reports due to same known issue. Then there is domain 1 (first line in -t output) on which is just one device 0001:01:00.0 detected as Memory controller and has capability of "PCI-X non-bridge device". This seems to be PCI bus. I guess that Memory controller is also bogus information. What is "PCI-X non-bridge device"? I thought that "root" of the PCI bus should be Host Bridge. Anyway, there is my pending patch which should fix Class ID to not report incorrect Memory controller identification: https://lore.kernel.org/linux-pci/20211102171259.9590-1-pali@kernel.org/#Z31arch:arm:mach-orion5x:pci.c > > > > > Thomas Petazzoni originally wrote the new driver, and I think he was > > > planning at one point to use it for orion5x. I don't know if there were > > > any major problems preventing this at the time, or if it just needs to > > > get hooked up in the dtsi file. > > > > > > Arnd > > -- Mauri _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-05-08 20:10 ` Pali Rohár @ 2022-05-09 10:52 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-09 10:52 UTC (permalink / raw) To: Pali Rohár Cc: maukka, Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On 8.5.2022 23.10, Pali Rohár wrote: > On Sunday 08 May 2022 22:34:19 Mauri Sandberg wrote: >> On 08.05.22 18:22, Pali Rohár wrote: >>> On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: >>>> On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>> On 28.4.2022 23.56, Arnd Bergmann wrote: >>>>>> On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>>> On 27.4.2022 21.10, Arnd Bergmann wrote: >>>>>>>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>>>>> - sata_mv fails to initialise with -22 (-EINVAL) >>>>>>>> >>>>>>>> No idea, I'd try inserting a printk in every code path that can return -EINVAL >>>>>>>> from there >>>>>>>> >>>>> >>>>> With debugging the reason for -EINVAL remains a bit mystery. >>>>> - sata_mv calls ata_host_activate() [1] >>>>> - later on, in request_threaded_irq(), there are sanity checks [2] >>>>> - that fail with irq_settings_can_request() returning 0 [3] >>>>> >>>>> I cannot really put my finger on why the irq cannot be requested in DT >>>>> approach. >>>> >>>> Are you sure the marvell,orion-intc driver is successfully probed >>>> at this point? If not, the interrupt won't be there. >> >> I made the pci setup to be the very last thing in the boot and >> results are still the same. There are other devices that do get >> their interrupts from intc. >> >>>> >>>> I see that the "sata_mv" driver can be used either as a platform >>>> driver for the orion5x on-chip controller, or as a PCI driver for >>>> an add-on chip connected to the external bus. It sounds like >>>> your system has both. Do you know which one fails? >>>> >>>> The PCI driver cannot work unless the PCI host works correctly, >>>> and that in turn requires a correct devicetree description for it. >>>> >>>>>>> Is there a way to describe the PCIe bus in the >>>>>>> device tree? The initalisation of that bus is done for rev A1 only. >>>>>> >>>>>> I'm not too familiar with the platform, but my interpretation is that the >>>>>> DT support here is incomplete: >>>>>> >>>>>> The DT based PCI probe using drivers/pci/controller/pci-mvebu.c >>>>>> is not hooked up in orion5x.dtsi, and the traditional pci code does >>>>>> not work with DT. >>>>> >>>>> Can the existing pci code still be used to init the PCI bus and describe >>>>> the rest in the DT or is it a futile attempt? >>> >>> Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and >>> PCIe buses. This is not device tree driver. >>> >>>>>> I see that orion5x has two separate blocks -- a PCIe host that is >>>>>> similar to the kirkwood one, and a legacy PCI host that needs >>>>>> a completely separate driver. >>>>>> >>>>>> Which of the two do you actually need here? >>>>>> >>>>> >>>>> I really cannot say which one is it. How can I tell? The functions given >>>>> in struct hw_pci find their way to drivers/pci/probe.c eventually and >>>>> use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or >>>>> kirkwood explicitly at least. >>>>> >>>>> Here's the output from lspci if the ids reveal anything. >>>>> >>>>> # lspci -v -k >>>>> 00:00.0 Class 0580: 11ab:5181 >>>>> 01:00.0 Class 0580: 11ab:5181 >>>>> 00:01.0 Class 0100: 11ab:7042 sata_mv >>>> >>>> The first two seem to be the host bridges, but unfortunately they >>>> seem both have the same device ID, despite being very different >>>> devices. The first one (00:00.0) should be the PCIe driver, the >>>> second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 >>>> device is a PCIe device, and it's on the bus (00) of the first host >>>> bridge. I think this should work with drivers/pci/controller/pci-mvebu.c >>>> if you add the bits for probing. >>> >>> Last time when I looked on Orion PCIe controller registers, I though >>> that they are same as in Kirkwood PCIe controller registers. And >>> Kirkwood is already supported by pci-mvebu.c driver. >>> >> >> I seemed that way to me too on the first glance. And it looks like there >> are no devices using the PCI driver. I knocked off that part altogether and >> the boot log looks pretty much the same it was. Perhaps I can do >> with describing the PCIe bus only. >> >>> About PCI host bridge, I do not know. >>> >>> Beware that PCI Class Id and all PCI registers which are different for >>> Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit >>> Marvell SoCs. Those registers on Marvell SoCs have different meaning as >>> what is defined in PCI and PCIe specs. So it means that lspci _may_ >>> display bogus information about PCIe Root Port. pci-mvebu.c uses Root >>> Port emulator which fills correct data to make kernel and lspci happy. >>> >>> If you are going to extend pci-mvebu.c to support also Orion PCIe >>> controller, I could try to help with it. But I do not have any Orion >>> hardware, so just basic help... >> >> I could make an attempt at this. Should I try to look at an existing >> kirkwood based device first, say kirkwood-6281.dtsi? I didn't see >> anything SoC-specific in pci-mvebu.c. All different compatibles seem >> to share the same functionality. > > Yes, this could be a good starting point. But you will need new > compatible string for orion, specially to implement workaround for > accessing config space. > >>> >>> Links to Orion documentations, including PCIe errata is available in >>> kernel documentation. So this could help to understand some details: >>> https://www.kernel.org/doc/html/latest/arm/marvell.html >>> >>> Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' >>> outputs from Orion? >> >> # lspci -nn -vv >> 0000:00:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 >> [Orion-1] ARM SoC [11ab:5181] (rev 03) >> Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] >> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ >> Stepping- SERR+ FastB2B- DisINTx- >> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- >> <MAbort- >SERR- <PERR- INTx- >> Latency: 0, Cache Line Size: 32 bytes >> Interrupt: pin A routed to IRQ 0 >> Region 0: Memory at <ignored> (64-bit, prefetchable) >> Capabilities: [40] Power Management version 2 >> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) >> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- >> Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ >> Address: 0000000000000000 Data: 0000 >> Capabilities: [60] Express (v1) Root Port (Slot-), MSI 00 >> DevCap: MaxPayload 128 bytes, PhantFunc 0 >> ExtTag- RBE- >> DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- >> RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- >> MaxPayload 128 bytes, MaxReadReq 512 bytes >> DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- >> LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s >> <256ns >> ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- >> LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- >> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- >> LnkSta: Speed 2.5GT/s (ok), Width x1 (ok) >> TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- >> RootCap: CRSVisible- >> RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- >> RootSta: PME ReqID 0000, PMEStatus- PMEPending- >> >> 0000:00:01.0 SCSI storage controller [0100]: Marvell Technology Group Ltd. >> 88SX7042 PCI-e 4-port SATA-II [11ab:7042] (rev 02) >> Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] >> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ >> Stepping- SERR+ FastB2B- DisINTx- >> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- >> <MAbort- >SERR- <PERR- INTx- >> Latency: 0, Cache Line Size: 32 bytes >> Interrupt: pin A routed to IRQ 12 >> Region 0: Memory at e0000000 (64-bit, non-prefetchable) [size=1M] >> Region 2: I/O ports at 1000 [size=256] >> Capabilities: [40] Power Management version 2 >> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) >> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- >> Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ >> Address: 0000000000000000 Data: 0000 >> Capabilities: [60] Express (v1) Legacy Endpoint, MSI 00 >> DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <256ns, L1 <1us >> ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- >> DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- >> RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- >> MaxPayload 128 bytes, MaxReadReq 512 bytes >> DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- >> LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Exit Latency L0s >> <256ns >> ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- >> LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- >> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- >> LnkSta: Speed 2.5GT/s (ok), Width x1 (downgraded) >> TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- >> Kernel driver in use: sata_mv >> >> 0001:01:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 >> [Orion-1] ARM SoC [11ab:5181] (rev 03) >> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ >> Stepping- SERR+ FastB2B+ DisINTx- >> Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- >> <MAbort+ >SERR- <PERR- INTx- >> Latency: 0, Cache Line Size: 32 bytes >> Interrupt: pin A routed to IRQ 0 >> BIST result: 00 >> Region 0: Memory at <unassigned> (64-bit, prefetchable) >> Region 2: Memory at <ignored> (64-bit, prefetchable) >> Region 4: Memory at <ignored> (64-bit, non-prefetchable) >> Expansion ROM at <ignored> [disabled] >> Capabilities: [40] Power Management version 2 >> Flags: PMEClk+ DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) >> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ >> Capabilities: [48] Vital Product Data >> Not readable >> Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ >> Address: 0000000000000000 Data: 0000 >> Capabilities: [60] PCI-X non-bridge device >> Command: DPERE- ERO- RBC=512 OST=4 >> Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- DC=bridge DMMRBC=512 DMOST=4 >> DMCRS=8 RSCEM- 266MHz- 533MHz- >> Capabilities: [68] CompactPCI hot-swap <?> >> >> # lspci -nn -t -v >> -+-[0001:01]---00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC >> [11ab:5181] >> \-[0000:00]-+-00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC >> [11ab:5181] >> \-01.0 Marvell Technology Group Ltd. 88SX7042 PCI-e 4-port >> SATA-II [11ab:7042] > > Ok, so domain 0 is PCIe bus for sure. > 0000:00:00.0 is PCIe Root Port (PCI-to-PCI bridge) incorrectly detected > as Memory controller (known HW issue on all 32-bit Marvell SoCs). > 0000:00:01.0 seems to be that SATA controller and this device is > connected behind the PCIe Root Port. Topology is also incorrectly > reports due to same known issue. > > Then there is domain 1 (first line in -t output) on which is just one > device 0001:01:00.0 detected as Memory controller and has capability of > "PCI-X non-bridge device". This seems to be PCI bus. I guess that Memory > controller is also bogus information. > > What is "PCI-X non-bridge device"? I thought that "root" of the PCI bus > should be Host Bridge. > > Anyway, there is my pending patch which should fix Class ID to not > report incorrect Memory controller identification: > https://lore.kernel.org/linux-pci/20211102171259.9590-1-pali@kernel.org/#Z31arch:arm:mach-orion5x:pci.c With the patch the roots are identified as follows: # lspci -nn -vv 0000:00:00.0 Host bridge [0600]: Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] (rev 03) ... 0001:01:00.0 Host bridge [0600]: Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] (rev 03) Everything else remained the same. >>> >>>> Thomas Petazzoni originally wrote the new driver, and I think he was >>>> planning at one point to use it for orion5x. I don't know if there were >>>> any major problems preventing this at the time, or if it just needs to >>>> get hooked up in the dtsi file. >>>> >>>> Arnd >> >> -- Mauri ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-05-09 10:52 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-05-09 10:52 UTC (permalink / raw) To: Pali Rohár Cc: maukka, Arnd Bergmann, SoC Team, Linux ARM, DTML, Olof Johansson, Rob Herring, Krzysztof Kozlowski, Andrew Lunn, Sebastian Hesselbarth, Thomas Petazzoni On 8.5.2022 23.10, Pali Rohár wrote: > On Sunday 08 May 2022 22:34:19 Mauri Sandberg wrote: >> On 08.05.22 18:22, Pali Rohár wrote: >>> On Sunday 08 May 2022 17:02:17 Arnd Bergmann wrote: >>>> On Sun, May 8, 2022 at 4:06 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>> On 28.4.2022 23.56, Arnd Bergmann wrote: >>>>>> On Thu, Apr 28, 2022 at 10:01 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>>> On 27.4.2022 21.10, Arnd Bergmann wrote: >>>>>>>> On Wed, Apr 27, 2022 at 6:21 PM Mauri Sandberg <maukka@ext.kapsi.fi> wrote: >>>>>>>>> - sata_mv fails to initialise with -22 (-EINVAL) >>>>>>>> >>>>>>>> No idea, I'd try inserting a printk in every code path that can return -EINVAL >>>>>>>> from there >>>>>>>> >>>>> >>>>> With debugging the reason for -EINVAL remains a bit mystery. >>>>> - sata_mv calls ata_host_activate() [1] >>>>> - later on, in request_threaded_irq(), there are sanity checks [2] >>>>> - that fail with irq_settings_can_request() returning 0 [3] >>>>> >>>>> I cannot really put my finger on why the irq cannot be requested in DT >>>>> approach. >>>> >>>> Are you sure the marvell,orion-intc driver is successfully probed >>>> at this point? If not, the interrupt won't be there. >> >> I made the pci setup to be the very last thing in the boot and >> results are still the same. There are other devices that do get >> their interrupts from intc. >> >>>> >>>> I see that the "sata_mv" driver can be used either as a platform >>>> driver for the orion5x on-chip controller, or as a PCI driver for >>>> an add-on chip connected to the external bus. It sounds like >>>> your system has both. Do you know which one fails? >>>> >>>> The PCI driver cannot work unless the PCI host works correctly, >>>> and that in turn requires a correct devicetree description for it. >>>> >>>>>>> Is there a way to describe the PCIe bus in the >>>>>>> device tree? The initalisation of that bus is done for rev A1 only. >>>>>> >>>>>> I'm not too familiar with the platform, but my interpretation is that the >>>>>> DT support here is incomplete: >>>>>> >>>>>> The DT based PCI probe using drivers/pci/controller/pci-mvebu.c >>>>>> is not hooked up in orion5x.dtsi, and the traditional pci code does >>>>>> not work with DT. >>>>> >>>>> Can the existing pci code still be used to init the PCI bus and describe >>>>> the rest in the DT or is it a futile attempt? >>> >>> Hello! Orion uses arch/arm/mach-orion5x/pci.c driver for both PCI and >>> PCIe buses. This is not device tree driver. >>> >>>>>> I see that orion5x has two separate blocks -- a PCIe host that is >>>>>> similar to the kirkwood one, and a legacy PCI host that needs >>>>>> a completely separate driver. >>>>>> >>>>>> Which of the two do you actually need here? >>>>>> >>>>> >>>>> I really cannot say which one is it. How can I tell? The functions given >>>>> in struct hw_pci find their way to drivers/pci/probe.c eventually and >>>>> use pci_scan_root_bus_bridge(). Nothing seems to utilising mvebu or >>>>> kirkwood explicitly at least. >>>>> >>>>> Here's the output from lspci if the ids reveal anything. >>>>> >>>>> # lspci -v -k >>>>> 00:00.0 Class 0580: 11ab:5181 >>>>> 01:00.0 Class 0580: 11ab:5181 >>>>> 00:01.0 Class 0100: 11ab:7042 sata_mv >>>> >>>> The first two seem to be the host bridges, but unfortunately they >>>> seem both have the same device ID, despite being very different >>>> devices. The first one (00:00.0) should be the PCIe driver, the >>>> second one (01.00.0) the legacy PCI one. In this case, the 11ab:7042 >>>> device is a PCIe device, and it's on the bus (00) of the first host >>>> bridge. I think this should work with drivers/pci/controller/pci-mvebu.c >>>> if you add the bits for probing. >>> >>> Last time when I looked on Orion PCIe controller registers, I though >>> that they are same as in Kirkwood PCIe controller registers. And >>> Kirkwood is already supported by pci-mvebu.c driver. >>> >> >> I seemed that way to me too on the first glance. And it looks like there >> are no devices using the PCI driver. I knocked off that part altogether and >> the boot log looks pretty much the same it was. Perhaps I can do >> with describing the PCIe bus only. >> >>> About PCI host bridge, I do not know. >>> >>> Beware that PCI Class Id and all PCI registers which are different for >>> Type 0 and Type 1 are _broken_ on all PCIe Root Ports form all 32-bit >>> Marvell SoCs. Those registers on Marvell SoCs have different meaning as >>> what is defined in PCI and PCIe specs. So it means that lspci _may_ >>> display bogus information about PCIe Root Port. pci-mvebu.c uses Root >>> Port emulator which fills correct data to make kernel and lspci happy. >>> >>> If you are going to extend pci-mvebu.c to support also Orion PCIe >>> controller, I could try to help with it. But I do not have any Orion >>> hardware, so just basic help... >> >> I could make an attempt at this. Should I try to look at an existing >> kirkwood based device first, say kirkwood-6281.dtsi? I didn't see >> anything SoC-specific in pci-mvebu.c. All different compatibles seem >> to share the same functionality. > > Yes, this could be a good starting point. But you will need new > compatible string for orion, specially to implement workaround for > accessing config space. > >>> >>> Links to Orion documentations, including PCIe errata is available in >>> kernel documentation. So this could help to understand some details: >>> https://www.kernel.org/doc/html/latest/arm/marvell.html >>> >>> Anyway, could you please provide 'lspci -nn -vv' and 'lspci -nn -t -v' >>> outputs from Orion? >> >> # lspci -nn -vv >> 0000:00:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 >> [Orion-1] ARM SoC [11ab:5181] (rev 03) >> Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] >> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ >> Stepping- SERR+ FastB2B- DisINTx- >> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- >> <MAbort- >SERR- <PERR- INTx- >> Latency: 0, Cache Line Size: 32 bytes >> Interrupt: pin A routed to IRQ 0 >> Region 0: Memory at <ignored> (64-bit, prefetchable) >> Capabilities: [40] Power Management version 2 >> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) >> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- >> Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ >> Address: 0000000000000000 Data: 0000 >> Capabilities: [60] Express (v1) Root Port (Slot-), MSI 00 >> DevCap: MaxPayload 128 bytes, PhantFunc 0 >> ExtTag- RBE- >> DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- >> RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- >> MaxPayload 128 bytes, MaxReadReq 512 bytes >> DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- >> LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s >> <256ns >> ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- >> LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- >> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- >> LnkSta: Speed 2.5GT/s (ok), Width x1 (ok) >> TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- >> RootCap: CRSVisible- >> RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- >> RootSta: PME ReqID 0000, PMEStatus- PMEPending- >> >> 0000:00:01.0 SCSI storage controller [0100]: Marvell Technology Group Ltd. >> 88SX7042 PCI-e 4-port SATA-II [11ab:7042] (rev 02) >> Subsystem: Marvell Technology Group Ltd. Device [11ab:11ab] >> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ >> Stepping- SERR+ FastB2B- DisINTx- >> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- >> <MAbort- >SERR- <PERR- INTx- >> Latency: 0, Cache Line Size: 32 bytes >> Interrupt: pin A routed to IRQ 12 >> Region 0: Memory at e0000000 (64-bit, non-prefetchable) [size=1M] >> Region 2: I/O ports at 1000 [size=256] >> Capabilities: [40] Power Management version 2 >> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) >> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- >> Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ >> Address: 0000000000000000 Data: 0000 >> Capabilities: [60] Express (v1) Legacy Endpoint, MSI 00 >> DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <256ns, L1 <1us >> ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- >> DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- >> RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- >> MaxPayload 128 bytes, MaxReadReq 512 bytes >> DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- >> LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Exit Latency L0s >> <256ns >> ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- >> LnkCtl: ASPM Disabled; RCB 128 bytes, Disabled- CommClk- >> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- >> LnkSta: Speed 2.5GT/s (ok), Width x1 (downgraded) >> TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- >> Kernel driver in use: sata_mv >> >> 0001:01:00.0 Memory controller [0580]: Marvell Technology Group Ltd. 88f5181 >> [Orion-1] ARM SoC [11ab:5181] (rev 03) >> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ >> Stepping- SERR+ FastB2B+ DisINTx- >> Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- >> <MAbort+ >SERR- <PERR- INTx- >> Latency: 0, Cache Line Size: 32 bytes >> Interrupt: pin A routed to IRQ 0 >> BIST result: 00 >> Region 0: Memory at <unassigned> (64-bit, prefetchable) >> Region 2: Memory at <ignored> (64-bit, prefetchable) >> Region 4: Memory at <ignored> (64-bit, non-prefetchable) >> Expansion ROM at <ignored> [disabled] >> Capabilities: [40] Power Management version 2 >> Flags: PMEClk+ DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) >> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ >> Capabilities: [48] Vital Product Data >> Not readable >> Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ >> Address: 0000000000000000 Data: 0000 >> Capabilities: [60] PCI-X non-bridge device >> Command: DPERE- ERO- RBC=512 OST=4 >> Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- DC=bridge DMMRBC=512 DMOST=4 >> DMCRS=8 RSCEM- 266MHz- 533MHz- >> Capabilities: [68] CompactPCI hot-swap <?> >> >> # lspci -nn -t -v >> -+-[0001:01]---00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC >> [11ab:5181] >> \-[0000:00]-+-00.0 Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC >> [11ab:5181] >> \-01.0 Marvell Technology Group Ltd. 88SX7042 PCI-e 4-port >> SATA-II [11ab:7042] > > Ok, so domain 0 is PCIe bus for sure. > 0000:00:00.0 is PCIe Root Port (PCI-to-PCI bridge) incorrectly detected > as Memory controller (known HW issue on all 32-bit Marvell SoCs). > 0000:00:01.0 seems to be that SATA controller and this device is > connected behind the PCIe Root Port. Topology is also incorrectly > reports due to same known issue. > > Then there is domain 1 (first line in -t output) on which is just one > device 0001:01:00.0 detected as Memory controller and has capability of > "PCI-X non-bridge device". This seems to be PCI bus. I guess that Memory > controller is also bogus information. > > What is "PCI-X non-bridge device"? I thought that "root" of the PCI bus > should be Host Bridge. > > Anyway, there is my pending patch which should fix Class ID to not > report incorrect Memory controller identification: > https://lore.kernel.org/linux-pci/20211102171259.9590-1-pali@kernel.org/#Z31arch:arm:mach-orion5x:pci.c With the patch the roots are identified as follows: # lspci -nn -vv 0000:00:00.0 Host bridge [0600]: Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] (rev 03) ... 0001:01:00.0 Host bridge [0600]: Marvell Technology Group Ltd. 88f5181 [Orion-1] ARM SoC [11ab:5181] (rev 03) Everything else remained the same. >>> >>>> Thomas Petazzoni originally wrote the new driver, and I think he was >>>> planning at one point to use it for orion5x. I don't know if there were >>>> any major problems preventing this at the time, or if it just needs to >>>> get hooked up in the dtsi file. >>>> >>>> Arnd >> >> -- Mauri _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree 2022-04-27 16:21 ` Mauri Sandberg @ 2022-04-28 0:29 ` Andrew Lunn -1 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-04-28 0:29 UTC (permalink / raw) To: Mauri Sandberg Cc: soc, linux-arm-kernel, devicetree, arnd, olof, robh+dt, krzysztof.kozlowski+dt, sebastian.hesselbarth > - how to configure RTC to wake system from sleep? The st,m41t80 binding document has: Optional properties: - interrupts: rtc alarm interrupt. - clock-output-names: From common clock binding to override the default output clock name - wakeup-source: Enables wake up of host system on alarm which you don't appear to have in your DT files. Andrew ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree @ 2022-04-28 0:29 ` Andrew Lunn 0 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-04-28 0:29 UTC (permalink / raw) To: Mauri Sandberg Cc: soc, linux-arm-kernel, devicetree, arnd, olof, robh+dt, krzysztof.kozlowski+dt, sebastian.hesselbarth > - how to configure RTC to wake system from sleep? The st,m41t80 binding document has: Optional properties: - interrupts: rtc alarm interrupt. - clock-output-names: From common clock binding to override the default output clock name - wakeup-source: Enables wake up of host system on alarm which you don't appear to have in your DT files. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* [PATCH v2 0/3] ARM: orion5x: add D-Link DNS323 based on device treee 2022-04-27 16:21 ` Mauri Sandberg @ 2022-09-22 20:24 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-09-22 20:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg Hello all, This is the second iteration of my series to add D-Link DNS323 devices, which are based on a device tree. It adds the bindings, the device tree source files and a new board file to take care of initialising what little remains that cannot be done via device tree. The initialisation of MAC address will be neater once method for passing ASCII string based address is agreed on. Functionally this series has a dependency to Pali's mvebu pci series, which adds support for Orion PCIe and which should be scheduled for a merge window any time soon: https://lore.kernel.org/linux-pci/20220905192310.22786-1-pali@kernel.org/ What currently is tested and works in rev A1 - leds - keys - fan - temperature sensor - shutdown - reboot - mtd partitions - ethernet - PCIe and with that sata_mv And the variants B1 and C1 need testing still. Thanks, Mauri Mauri Sandberg (3): dt-bindings: arm: add DT binding for D-Link DNS-323 ARM: dts: orion5x: Add D-Link DNS-323 Device Tree ARM: orion5x: Add D-Link DNS-323 based on Device Tree .../bindings/arm/marvell/marvell,orion5x.txt | 12 + arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 215 ++++++++++++++++++ arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 44 ++++ arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 39 ++++ arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 81 +++++++ arch/arm/mach-orion5x/Kconfig | 7 + arch/arm/mach-orion5x/Makefile | 1 + arch/arm/mach-orion5x/board-dns323.c | 208 +++++++++++++++++ arch/arm/mach-orion5x/board-dt.c | 3 + arch/arm/mach-orion5x/common.h | 6 + 11 files changed, 619 insertions(+) create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts create mode 100644 arch/arm/mach-orion5x/board-dns323.c base-commit: c69cf88cda5faca0e411babb67ac0d8bfd8b4646 -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* [PATCH v2 0/3] ARM: orion5x: add D-Link DNS323 based on device treee @ 2022-09-22 20:24 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-09-22 20:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg Hello all, This is the second iteration of my series to add D-Link DNS323 devices, which are based on a device tree. It adds the bindings, the device tree source files and a new board file to take care of initialising what little remains that cannot be done via device tree. The initialisation of MAC address will be neater once method for passing ASCII string based address is agreed on. Functionally this series has a dependency to Pali's mvebu pci series, which adds support for Orion PCIe and which should be scheduled for a merge window any time soon: https://lore.kernel.org/linux-pci/20220905192310.22786-1-pali@kernel.org/ What currently is tested and works in rev A1 - leds - keys - fan - temperature sensor - shutdown - reboot - mtd partitions - ethernet - PCIe and with that sata_mv And the variants B1 and C1 need testing still. Thanks, Mauri Mauri Sandberg (3): dt-bindings: arm: add DT binding for D-Link DNS-323 ARM: dts: orion5x: Add D-Link DNS-323 Device Tree ARM: orion5x: Add D-Link DNS-323 based on Device Tree .../bindings/arm/marvell/marvell,orion5x.txt | 12 + arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 215 ++++++++++++++++++ arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 44 ++++ arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 39 ++++ arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 81 +++++++ arch/arm/mach-orion5x/Kconfig | 7 + arch/arm/mach-orion5x/Makefile | 1 + arch/arm/mach-orion5x/board-dns323.c | 208 +++++++++++++++++ arch/arm/mach-orion5x/board-dt.c | 3 + arch/arm/mach-orion5x/common.h | 6 + 11 files changed, 619 insertions(+) create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts create mode 100644 arch/arm/mach-orion5x/board-dns323.c base-commit: c69cf88cda5faca0e411babb67ac0d8bfd8b4646 -- 2.25.1 ^ permalink raw reply [flat|nested] 91+ messages in thread
* [PATCH v2 1/3] dt-bindings: arm: add DT binding for D-Link DNS-323 2022-09-22 20:24 ` Mauri Sandberg @ 2022-09-22 20:24 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-09-22 20:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg Add bindings for D-Link DNS-323. It introduces altogether four new compatibles: dlink,dns323, dlink,dns323a1, dlink,dns323b1 and dlink,dns323c1. One is for the common parts between the devices and then there is one for each three hardware variants. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> --- changes from v1: - split patches, this one adds bindings --- .../bindings/arm/marvell/marvell,orion5x.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt index 748a8f287462..ead80ed2262f 100644 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt @@ -23,3 +23,15 @@ board. Currently known boards are: "marvell,rd-88f5182-nas" "maxtor,shared-storage-2" "netgear,wnr854t" + +The D-Link DNS-323 has three different revisions. Their common parts are +collected in: + +"dlink,dns323" + +The three different variants (A1 being 88f5181, the two others being 88f5182) +are specified with compatibles: + +"dlink,dns323a1" +"dlink,dns323b1" +"dlink,dns323c1" -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH v2 1/3] dt-bindings: arm: add DT binding for D-Link DNS-323 @ 2022-09-22 20:24 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-09-22 20:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg Add bindings for D-Link DNS-323. It introduces altogether four new compatibles: dlink,dns323, dlink,dns323a1, dlink,dns323b1 and dlink,dns323c1. One is for the common parts between the devices and then there is one for each three hardware variants. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> --- changes from v1: - split patches, this one adds bindings --- .../bindings/arm/marvell/marvell,orion5x.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt index 748a8f287462..ead80ed2262f 100644 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt @@ -23,3 +23,15 @@ board. Currently known boards are: "marvell,rd-88f5182-nas" "maxtor,shared-storage-2" "netgear,wnr854t" + +The D-Link DNS-323 has three different revisions. Their common parts are +collected in: + +"dlink,dns323" + +The three different variants (A1 being 88f5181, the two others being 88f5182) +are specified with compatibles: + +"dlink,dns323a1" +"dlink,dns323b1" +"dlink,dns323c1" -- 2.25.1 ^ permalink raw reply related [flat|nested] 91+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: add DT binding for D-Link DNS-323 2022-09-22 20:24 ` Mauri Sandberg @ 2022-09-22 20:36 ` Andrew Lunn -1 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-22 20:36 UTC (permalink / raw) To: Mauri Sandberg Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel On Thu, Sep 22, 2022 at 11:24:56PM +0300, Mauri Sandberg wrote: > Add bindings for D-Link DNS-323. It introduces altogether four new > compatibles: dlink,dns323, dlink,dns323a1, dlink,dns323b1 and > dlink,dns323c1. One is for the common parts between the devices and > then there is one for each three hardware variants. > > Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: add DT binding for D-Link DNS-323 @ 2022-09-22 20:36 ` Andrew Lunn 0 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-22 20:36 UTC (permalink / raw) To: Mauri Sandberg Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel On Thu, Sep 22, 2022 at 11:24:56PM +0300, Mauri Sandberg wrote: > Add bindings for D-Link DNS-323. It introduces altogether four new > compatibles: dlink,dns323, dlink,dns323a1, dlink,dns323b1 and > dlink,dns323c1. One is for the common parts between the devices and > then there is one for each three hardware variants. > > Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: add DT binding for D-Link DNS-323 2022-09-22 20:24 ` Mauri Sandberg @ 2022-09-23 9:18 ` Krzysztof Kozlowski -1 siblings, 0 replies; 91+ messages in thread From: Krzysztof Kozlowski @ 2022-09-23 9:18 UTC (permalink / raw) To: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel On 22/09/2022 22:24, Mauri Sandberg wrote: > Add bindings for D-Link DNS-323. It introduces altogether four new > compatibles: dlink,dns323, dlink,dns323a1, dlink,dns323b1 and > dlink,dns323c1. One is for the common parts between the devices and > then there is one for each three hardware variants. > > Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: add DT binding for D-Link DNS-323 @ 2022-09-23 9:18 ` Krzysztof Kozlowski 0 siblings, 0 replies; 91+ messages in thread From: Krzysztof Kozlowski @ 2022-09-23 9:18 UTC (permalink / raw) To: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel On 22/09/2022 22:24, Mauri Sandberg wrote: > Add bindings for D-Link DNS-323. It introduces altogether four new > compatibles: dlink,dns323, dlink,dns323a1, dlink,dns323b1 and > dlink,dns323c1. One is for the common parts between the devices and > then there is one for each three hardware variants. > > Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree 2022-09-22 20:24 ` Mauri Sandberg @ 2022-09-22 20:24 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-09-22 20:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg Add a device tree for D-Link DNS-323. The device has three different variants; A1, B1 and C1. Common parts are included in a .dtsi file and each hardware variant has its own .dts file. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> --- changes from v1 - split patches, this one adds the device tree - set pciec and pcie1 nodes to 'okay' --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 215 +++++++++++++++++++ arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 44 ++++ arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 39 ++++ arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 81 +++++++ 5 files changed, 382 insertions(+) create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 05d8aef6e5d2..bc41749cd889 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -997,6 +997,9 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ dra71-evm.dtb \ dra76-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += \ + orion5x-dlink-dns323a1.dtb \ + orion5x-dlink-dns323b1.dtb \ + orion5x-dlink-dns323c1.dtb \ orion5x-kuroboxpro.dtb \ orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi new file mode 100644 index 000000000000..05b0b134edb3 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/ { + model = "D-Link DNS-323"; + compatible = "dlink,dns323", "marvell,orion5x"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, /* on-chip peripheral registers */ + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, /* SRAM for crypto */ + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>; /* device bus mapping (boot) */ + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_gpio_keys>; + pinctrl-names = "default"; + + key-0 { + label = "Power button"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + key-1 { + label = "Reset button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_gpio_leds>; + pinctrl-names = "default"; + + led-0 { + label = "amber:right"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "amber:left"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "blue:power"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; + + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + timeout-ms = <3000>; + }; +}; + +&devbus_bootcs { + status = "okay"; + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x800000>; + bank-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "MTD1"; + reg = <0x000000 0x010000>; + read-only; + }; + + partition@10000 { + label = "MTD2"; + reg = <0x010000 0x010000>; + read-only; + }; + + partition@20000 { + label = "Linux Kernel"; + reg = <0x020000 0x180000>; + }; + + partition@1a0000 { + label = "File System"; + reg = <0x1a0000 0x630000>; + }; + + uboot: partition@7d0000 { + label = "U-boot"; + reg = <0x7d0000 0x030000>; + read-only; + }; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + + /* fan speed PWM */ + fan@3e { + compatible = "g760a"; + reg = <0x3e>; + }; + + /* temp sensor and thermal watchdog */ + temperature-sensor@48 { + compatible = "gmt,g751"; + reg = <0x48>; + }; + + /* RTC w/ alarm */ + rtc@68 { + compatible = "st,m41t80"; + reg = <0x68>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +ð { + status = "okay"; + pinctrl-0 = <&pmx_ge>; + pinctrl-names = "default"; + clocks = <&core_clk 0>; +}; + +ðport { + phy-handle = <ðphy>; +}; + +&uart0 { + status = "okay"; +}; + +&pinctrl { + pmx_gpio_leds: pmx-gpio-leds { + marvell,pins = "mpp1", "mpp2", "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_misc: pmx-gpio-misc { + /* set marvell,pins in board file */ + marvell,function = "gpio"; + }; + + pmx_power_off: pmx-power-off { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_keys: pmx-gpio-keys { + marvell,pins = "mpp9", "mpp10"; + marvell,function = "gpio"; + }; + + pmx_ge: pmx-ge { + marvell,function = "ge"; + }; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts new file mode 100644 index 000000000000..235cc842f289 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "orion5x-mv88f5181.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + model = "D-Link DNS-323 rev A1"; + compatible = "dlink,dns323a1", "dlink,dns323", "marvell,orion5x-88f5181", + "marvell,orion5x"; +}; + +/delete-node/ &sata; + +&gpio0 { + pinctrl-0 = <&pmx_gpio_misc>; + pinctrl-names = "default"; + + /* The DNS323 rev A1 power LED requires GPIO 4 to be low. */ + pin_gpio0_4 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-high; + line-name = "Power led enable"; + }; +}; + +&pmx_gpio_misc { + marvell,pins = "mpp4"; +}; + +&pmx_ge { + marvell,pins = "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts new file mode 100644 index 000000000000..e01ba809ffca --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5182.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + model = "D-Link DNS-323 rev B1"; + compatible = "dlink,dns323b1", "dlink,dns323", "marvell,orion5x-88f5182", + "marvell,orion5x"; +}; + +&gpio0 { + pinctrl-0 = <&pmx_gpio_misc>; + pinctrl-names = "default"; + + /* The rev B1 has a flag to indicate the system is up. + * Without this flag set, power LED will flash and cannot be + * controlled via gpio-leds. + */ + pin_gpio0_3 { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-high; + line-name = "System up"; + }; +}; + +&pmx_gpio_misc { + marvell,pins = "mpp3"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts new file mode 100644 index 000000000000..c24da08bdc8f --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5182.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + model = "D-Link DNS-323 rev C1"; + compatible = "dlink,dns323c1", "dlink,dns323", "marvell,orion5x-88f5182", + "marvell,orion5x"; + + fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_gpio_fan>; + pinctrl-names = "default"; + + gpios = <&gpio0 19 GPIO_ACTIVE_LOW + &gpio0 18 GPIO_ACTIVE_LOW>; + + gpio-fan,speed-map = <0 0 + 1000 1 + 2000 2>; + alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + /delete-node/ key-1; + + key-0 { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + led-0 { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + led-1 { + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + led-2 { + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; + +}; + +&i2c { + /delete-node/ fan@3e; +}; + +&pinctrl { + /delete-node/ pmx-gpio-misc; + + pmx_gpio_fan: pmx-gpio-fan { + marvell,pins = "mpp10", "mpp18", "mpp19"; + marvell,function = "gpio"; + }; +}; + +&pmx_gpio_leds { + marvell,pins = "mpp8", "mpp9", "mpp17"; +}; + +&pmx_power_off { + marvell,pins = "mpp2"; +}; + +&pmx_gpio_keys { + marvell,pins = "mpp1"; +}; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree @ 2022-09-22 20:24 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-09-22 20:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg Add a device tree for D-Link DNS-323. The device has three different variants; A1, B1 and C1. Common parts are included in a .dtsi file and each hardware variant has its own .dts file. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> --- changes from v1 - split patches, this one adds the device tree - set pciec and pcie1 nodes to 'okay' --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/orion5x-dlink-dns323.dtsi | 215 +++++++++++++++++++ arch/arm/boot/dts/orion5x-dlink-dns323a1.dts | 44 ++++ arch/arm/boot/dts/orion5x-dlink-dns323b1.dts | 39 ++++ arch/arm/boot/dts/orion5x-dlink-dns323c1.dts | 81 +++++++ 5 files changed, 382 insertions(+) create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323.dtsi create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323a1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323b1.dts create mode 100644 arch/arm/boot/dts/orion5x-dlink-dns323c1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 05d8aef6e5d2..bc41749cd889 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -997,6 +997,9 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ dra71-evm.dtb \ dra76-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += \ + orion5x-dlink-dns323a1.dtb \ + orion5x-dlink-dns323b1.dtb \ + orion5x-dlink-dns323c1.dtb \ orion5x-kuroboxpro.dtb \ orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi new file mode 100644 index 000000000000..05b0b134edb3 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/ { + model = "D-Link DNS-323"; + compatible = "dlink,dns323", "marvell,orion5x"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, /* on-chip peripheral registers */ + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, /* SRAM for crypto */ + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>; /* device bus mapping (boot) */ + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_gpio_keys>; + pinctrl-names = "default"; + + key-0 { + label = "Power button"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + key-1 { + label = "Reset button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_gpio_leds>; + pinctrl-names = "default"; + + led-0 { + label = "amber:right"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + led-1 { + label = "amber:left"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led-2 { + label = "blue:power"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; + + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + timeout-ms = <3000>; + }; +}; + +&devbus_bootcs { + status = "okay"; + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x800000>; + bank-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "MTD1"; + reg = <0x000000 0x010000>; + read-only; + }; + + partition@10000 { + label = "MTD2"; + reg = <0x010000 0x010000>; + read-only; + }; + + partition@20000 { + label = "Linux Kernel"; + reg = <0x020000 0x180000>; + }; + + partition@1a0000 { + label = "File System"; + reg = <0x1a0000 0x630000>; + }; + + uboot: partition@7d0000 { + label = "U-boot"; + reg = <0x7d0000 0x030000>; + read-only; + }; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + + /* fan speed PWM */ + fan@3e { + compatible = "g760a"; + reg = <0x3e>; + }; + + /* temp sensor and thermal watchdog */ + temperature-sensor@48 { + compatible = "gmt,g751"; + reg = <0x48>; + }; + + /* RTC w/ alarm */ + rtc@68 { + compatible = "st,m41t80"; + reg = <0x68>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +ð { + status = "okay"; + pinctrl-0 = <&pmx_ge>; + pinctrl-names = "default"; + clocks = <&core_clk 0>; +}; + +ðport { + phy-handle = <ðphy>; +}; + +&uart0 { + status = "okay"; +}; + +&pinctrl { + pmx_gpio_leds: pmx-gpio-leds { + marvell,pins = "mpp1", "mpp2", "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_misc: pmx-gpio-misc { + /* set marvell,pins in board file */ + marvell,function = "gpio"; + }; + + pmx_power_off: pmx-power-off { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_keys: pmx-gpio-keys { + marvell,pins = "mpp9", "mpp10"; + marvell,function = "gpio"; + }; + + pmx_ge: pmx-ge { + marvell,function = "ge"; + }; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts new file mode 100644 index 000000000000..235cc842f289 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323a1.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "orion5x-mv88f5181.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + model = "D-Link DNS-323 rev A1"; + compatible = "dlink,dns323a1", "dlink,dns323", "marvell,orion5x-88f5181", + "marvell,orion5x"; +}; + +/delete-node/ &sata; + +&gpio0 { + pinctrl-0 = <&pmx_gpio_misc>; + pinctrl-names = "default"; + + /* The DNS323 rev A1 power LED requires GPIO 4 to be low. */ + pin_gpio0_4 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-high; + line-name = "Power led enable"; + }; +}; + +&pmx_gpio_misc { + marvell,pins = "mpp4"; +}; + +&pmx_ge { + marvell,pins = "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts new file mode 100644 index 000000000000..e01ba809ffca --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5182.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + model = "D-Link DNS-323 rev B1"; + compatible = "dlink,dns323b1", "dlink,dns323", "marvell,orion5x-88f5182", + "marvell,orion5x"; +}; + +&gpio0 { + pinctrl-0 = <&pmx_gpio_misc>; + pinctrl-names = "default"; + + /* The rev B1 has a flag to indicate the system is up. + * Without this flag set, power LED will flash and cannot be + * controlled via gpio-leds. + */ + pin_gpio0_3 { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-high; + line-name = "System up"; + }; +}; + +&pmx_gpio_misc { + marvell,pins = "mpp3"; +}; diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts new file mode 100644 index 000000000000..c24da08bdc8f --- /dev/null +++ b/arch/arm/boot/dts/orion5x-dlink-dns323c1.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "orion5x-mv88f5182.dtsi" +#include "orion5x-dlink-dns323.dtsi" + +/ { + model = "D-Link DNS-323 rev C1"; + compatible = "dlink,dns323c1", "dlink,dns323", "marvell,orion5x-88f5182", + "marvell,orion5x"; + + fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_gpio_fan>; + pinctrl-names = "default"; + + gpios = <&gpio0 19 GPIO_ACTIVE_LOW + &gpio0 18 GPIO_ACTIVE_LOW>; + + gpio-fan,speed-map = <0 0 + 1000 1 + 2000 2>; + alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + /delete-node/ key-1; + + key-0 { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + led-0 { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + led-1 { + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + led-2 { + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; + +}; + +&i2c { + /delete-node/ fan@3e; +}; + +&pinctrl { + /delete-node/ pmx-gpio-misc; + + pmx_gpio_fan: pmx-gpio-fan { + marvell,pins = "mpp10", "mpp18", "mpp19"; + marvell,function = "gpio"; + }; +}; + +&pmx_gpio_leds { + marvell,pins = "mpp8", "mpp9", "mpp17"; +}; + +&pmx_power_off { + marvell,pins = "mpp2"; +}; + +&pmx_gpio_keys { + marvell,pins = "mpp1"; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree 2022-09-22 20:24 ` Mauri Sandberg @ 2022-09-22 20:45 ` Andrew Lunn -1 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-22 20:45 UTC (permalink / raw) To: Mauri Sandberg Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel > + chosen { > + stdout-path = "serial0:115200n8"; > + bootargs = "console=ttyS0,115200n8 earlyprintk"; bootargs is generally not liked. Since you have stdout-path do you need console=ttyS0,115200n8? earlyprintk should not be needed now you have something which boots. > +&mdio { > + status = "okay"; > + > + ethphy: ethernet-phy { > + reg = <8>; Since you have a reg value, this should be ethernet-phy@9 Andrew ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree @ 2022-09-22 20:45 ` Andrew Lunn 0 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-22 20:45 UTC (permalink / raw) To: Mauri Sandberg Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel > + chosen { > + stdout-path = "serial0:115200n8"; > + bootargs = "console=ttyS0,115200n8 earlyprintk"; bootargs is generally not liked. Since you have stdout-path do you need console=ttyS0,115200n8? earlyprintk should not be needed now you have something which boots. > +&mdio { > + status = "okay"; > + > + ethphy: ethernet-phy { > + reg = <8>; Since you have a reg value, this should be ethernet-phy@9 Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree 2022-09-22 20:45 ` Andrew Lunn @ 2022-09-22 21:14 ` Pali Rohár -1 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-09-22 21:14 UTC (permalink / raw) To: Andrew Lunn Cc: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel, linux-arm-kernel On Thursday 22 September 2022 22:45:47 Andrew Lunn wrote: > > +&mdio { > > + status = "okay"; > > + > > + ethphy: ethernet-phy { > > + reg = <8>; > > Since you have a reg value, this should be ethernet-phy@9 ethernet-phy@8 no? ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree @ 2022-09-22 21:14 ` Pali Rohár 0 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-09-22 21:14 UTC (permalink / raw) To: Andrew Lunn Cc: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel, linux-arm-kernel On Thursday 22 September 2022 22:45:47 Andrew Lunn wrote: > > +&mdio { > > + status = "okay"; > > + > > + ethphy: ethernet-phy { > > + reg = <8>; > > Since you have a reg value, this should be ethernet-phy@9 ethernet-phy@8 no? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree 2022-09-22 21:14 ` Pali Rohár @ 2022-09-22 21:32 ` Andrew Lunn -1 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-22 21:32 UTC (permalink / raw) To: Pali Rohár Cc: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel, linux-arm-kernel On Thu, Sep 22, 2022 at 11:14:08PM +0200, Pali Rohár wrote: > On Thursday 22 September 2022 22:45:47 Andrew Lunn wrote: > > > +&mdio { > > > + status = "okay"; > > > + > > > + ethphy: ethernet-phy { > > > + reg = <8>; > > > > Since you have a reg value, this should be ethernet-phy@9 > > ethernet-phy@8 no? Yes, @8. Sorry. Andrew ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree @ 2022-09-22 21:32 ` Andrew Lunn 0 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-22 21:32 UTC (permalink / raw) To: Pali Rohár Cc: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel, linux-arm-kernel On Thu, Sep 22, 2022 at 11:14:08PM +0200, Pali Rohár wrote: > On Thursday 22 September 2022 22:45:47 Andrew Lunn wrote: > > > +&mdio { > > > + status = "okay"; > > > + > > > + ethphy: ethernet-phy { > > > + reg = <8>; > > > > Since you have a reg value, this should be ethernet-phy@9 > > ethernet-phy@8 no? Yes, @8. Sorry. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree 2022-09-22 20:24 ` Mauri Sandberg @ 2022-09-23 9:19 ` Krzysztof Kozlowski -1 siblings, 0 replies; 91+ messages in thread From: Krzysztof Kozlowski @ 2022-09-23 9:19 UTC (permalink / raw) To: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel On 22/09/2022 22:24, Mauri Sandberg wrote: > Add a device tree for D-Link DNS-323. The device has three different > variants; A1, B1 and C1. Common parts are included in a .dtsi file > and each hardware variant has its own .dts file. Thank you for your patch. There is something to discuss/improve. > + > +/delete-node/ &sata; > + > +&gpio0 { > + pinctrl-0 = <&pmx_gpio_misc>; > + pinctrl-names = "default"; > + > + /* The DNS323 rev A1 power LED requires GPIO 4 to be low. */ > + pin_gpio0_4 { No underscores in node names. > + gpio-hog; > + gpios = <4 GPIO_ACTIVE_LOW>; > + output-high; > + line-name = "Power led enable"; > + }; > +}; > + > +&pmx_gpio_misc { > + marvell,pins = "mpp4"; > +}; > + > +&pmx_ge { > + marvell,pins = "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", > + "mpp16", "mpp17", "mpp18", "mpp19"; > +}; > diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts > new file mode 100644 > index 000000000000..e01ba809ffca > --- /dev/null > +++ b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts > @@ -0,0 +1,39 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> > + * > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/leds/common.h> > +#include "orion5x-mv88f5182.dtsi" > +#include "orion5x-dlink-dns323.dtsi" > + > +/ { > + model = "D-Link DNS-323 rev B1"; > + compatible = "dlink,dns323b1", "dlink,dns323", "marvell,orion5x-88f5182", > + "marvell,orion5x"; > +}; > + > +&gpio0 { > + pinctrl-0 = <&pmx_gpio_misc>; > + pinctrl-names = "default"; > + > + /* The rev B1 has a flag to indicate the system is up. > + * Without this flag set, power LED will flash and cannot be > + * controlled via gpio-leds. > + */ > + pin_gpio0_3 { No underscores in node names. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree @ 2022-09-23 9:19 ` Krzysztof Kozlowski 0 siblings, 0 replies; 91+ messages in thread From: Krzysztof Kozlowski @ 2022-09-23 9:19 UTC (permalink / raw) To: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel On 22/09/2022 22:24, Mauri Sandberg wrote: > Add a device tree for D-Link DNS-323. The device has three different > variants; A1, B1 and C1. Common parts are included in a .dtsi file > and each hardware variant has its own .dts file. Thank you for your patch. There is something to discuss/improve. > + > +/delete-node/ &sata; > + > +&gpio0 { > + pinctrl-0 = <&pmx_gpio_misc>; > + pinctrl-names = "default"; > + > + /* The DNS323 rev A1 power LED requires GPIO 4 to be low. */ > + pin_gpio0_4 { No underscores in node names. > + gpio-hog; > + gpios = <4 GPIO_ACTIVE_LOW>; > + output-high; > + line-name = "Power led enable"; > + }; > +}; > + > +&pmx_gpio_misc { > + marvell,pins = "mpp4"; > +}; > + > +&pmx_ge { > + marvell,pins = "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", > + "mpp16", "mpp17", "mpp18", "mpp19"; > +}; > diff --git a/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts > new file mode 100644 > index 000000000000..e01ba809ffca > --- /dev/null > +++ b/arch/arm/boot/dts/orion5x-dlink-dns323b1.dts > @@ -0,0 +1,39 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> > + * > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/leds/common.h> > +#include "orion5x-mv88f5182.dtsi" > +#include "orion5x-dlink-dns323.dtsi" > + > +/ { > + model = "D-Link DNS-323 rev B1"; > + compatible = "dlink,dns323b1", "dlink,dns323", "marvell,orion5x-88f5182", > + "marvell,orion5x"; > +}; > + > +&gpio0 { > + pinctrl-0 = <&pmx_gpio_misc>; > + pinctrl-names = "default"; > + > + /* The rev B1 has a flag to indicate the system is up. > + * Without this flag set, power LED will flash and cannot be > + * controlled via gpio-leds. > + */ > + pin_gpio0_3 { No underscores in node names. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree 2022-09-22 20:24 ` Mauri Sandberg ` (2 preceding siblings ...) (?) @ 2022-09-27 11:26 ` kernel test robot -1 siblings, 0 replies; 91+ messages in thread From: kernel test robot @ 2022-09-27 11:26 UTC (permalink / raw) To: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: kbuild-all, pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg [-- Attachment #1: Type: text/plain, Size: 1852 bytes --] Hi Mauri, Thank you for the patch! Yet something to improve: [auto build test ERROR on soc/for-next] [also build test ERROR on robh/for-next linus/master v6.0-rc7 next-20220923] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Mauri-Sandberg/dt-bindings-arm-add-DT-binding-for-D-Link-DNS-323/20220923-052532 base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next config: arm-randconfig-r025-20220926 compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/0f6a5f2ac9a2b3e3cf1b2c1969a1ad077cd54d2c git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Mauri-Sandberg/dt-bindings-arm-add-DT-binding-for-D-Link-DNS-323/20220923-052532 git checkout 0f6a5f2ac9a2b3e3cf1b2c1969a1ad077cd54d2c # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): >> Error: arch/arm/boot/dts/orion5x-dlink-dns323.dtsi:209.1-7 Label or path pciec not found >> Error: arch/arm/boot/dts/orion5x-dlink-dns323.dtsi:213.1-7 Label or path pcie0 not found FATAL ERROR: Syntax error parsing input tree -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 131724 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/arm 6.0.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabi-gcc (GCC) 12.1.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=120100 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23800 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23800 CONFIG_LLD_VERSION=0 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_COMPILE_TEST=y # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_USELIB=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_CONTEXT_TRACKING=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_HZ_PERIODIC=y # CONFIG_NO_HZ_IDLE is not set CONFIG_CONTEXT_TRACKING_USER=y CONFIG_CONTEXT_TRACKING_USER_FORCE=y # CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem CONFIG_HAVE_EBPF_JIT=y # # BPF subsystem # # CONFIG_BPF_SYSCALL is not set # end of BPF subsystem CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_PREEMPT_COUNT=y # # CPU/Task time and stats accounting # CONFIG_VIRT_CPU_ACCOUNTING=y # CONFIG_TICK_CPU_ACCOUNTING is not set CONFIG_VIRT_CPU_ACCOUNTING_GEN=y # CONFIG_IRQ_TIME_ACCOUNTING is not set # CONFIG_PSI is not set # end of CPU/Task time and stats accounting # CONFIG_CPU_ISOLATION is not set # # RCU Subsystem # CONFIG_TINY_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TINY_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RUDE_RCU=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem CONFIG_IKCONFIG=m CONFIG_IKCONFIG_PROC=y CONFIG_IKHEADERS=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_PRINTK_INDEX=y CONFIG_GENERIC_SCHED_CLOCK=y # # Scheduler features # # end of Scheduler features CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y # CONFIG_CGROUPS is not set # CONFIG_CHECKPOINT_RESTORE is not set # CONFIG_SCHED_AUTOGROUP is not set CONFIG_SYSFS_DEPRECATED=y # CONFIG_SYSFS_DEPRECATED_V2 is not set CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_RD_GZIP is not set # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set CONFIG_RD_XZ=y CONFIG_RD_LZO=y # CONFIG_RD_LZ4 is not set # CONFIG_RD_ZSTD is not set CONFIG_BOOT_CONFIG=y # CONFIG_BOOT_CONFIG_EMBED is not set # CONFIG_INITRAMFS_PRESERVE_MTIME is not set # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_EXPERT=y # CONFIG_MULTIUSER is not set CONFIG_SGETMASK_SYSCALL=y # CONFIG_SYSFS_SYSCALL is not set # CONFIG_FHANDLE is not set # CONFIG_POSIX_TIMERS is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_BASE_FULL is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y # CONFIG_DEBUG_RSEQ is not set CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PC104=y # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y CONFIG_DEBUG_PERF_USE_VMALLOC=y # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y # end of General setup CONFIG_ARM=y CONFIG_ARM_DMA_USE_IOMMU=y CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_TCM=y CONFIG_HAVE_PROC_CPU=y CONFIG_NO_IOPORT_MAP=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_GENERIC_BUG=y CONFIG_PGTABLE_LEVELS=2 # # System Type # CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=15 CONFIG_ARCH_MULTIPLATFORM=y # # Platform selection # # # CPU Core family selection # CONFIG_ARCH_MULTI_V6=y # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MULTI_V6_V7=y # end of Platform selection CONFIG_ARCH_ASPEED=y CONFIG_MACH_ASPEED_G5=y # CONFIG_ARCH_BCM is not set CONFIG_ARCH_MXC=y # # ARM1136 platforms # # CONFIG_SOC_IMX31 is not set # CONFIG_SOC_IMX35 is not set # # TI OMAP/AM/DM/DRA Family # # CONFIG_ARCH_OMAP2 is not set # end of TI OMAP/AM/DM/DRA Family CONFIG_ARCH_OXNAS=y # CONFIG_MACH_OX820 is not set CONFIG_ARCH_S3C64XX=y CONFIG_CPU_S3C6410=y CONFIG_S3C64XX_PL080=y CONFIG_S3C64XX_SETUP_SDHCI=y CONFIG_S3C64XX_SETUP_I2C0=y CONFIG_S3C64XX_SETUP_I2C1=y CONFIG_S3C64XX_SETUP_IDE=y CONFIG_S3C64XX_SETUP_FB_24BPP=y CONFIG_S3C64XX_SETUP_KEYPAD=y CONFIG_S3C64XX_SETUP_SDHCI_GPIO=y CONFIG_S3C64XX_SETUP_SPI=y CONFIG_S3C64XX_SETUP_USB_PHY=y CONFIG_MACH_WLF_CRAGG_6410=y # CONFIG_MACH_S3C64XX_DT is not set CONFIG_PLAT_SAMSUNG=y CONFIG_SAMSUNG_PM=y # # Samsung Common options # # # Boot options # CONFIG_S3C_LOWLEVEL_UART_PORT=0 CONFIG_SAMSUNG_ATAGS=y CONFIG_S3C_GPIO_SPACE=0 CONFIG_S3C_GPIO_TRACK=y CONFIG_S3C_DEV_HSMMC=y CONFIG_S3C_DEV_HSMMC1=y CONFIG_S3C_DEV_HSMMC2=y CONFIG_S3C_DEV_I2C1=y CONFIG_S3C_DEV_FB=y CONFIG_S3C_DEV_USB_HOST=y CONFIG_S3C_DEV_USB_HSOTG=y CONFIG_S3C_DEV_WDT=y CONFIG_S3C_DEV_NAND=y CONFIG_S3C_DEV_RTC=y CONFIG_SAMSUNG_DEV_ADC=y CONFIG_S3C64XX_DEV_SPI0=y CONFIG_SAMSUNG_DEV_KEYPAD=y CONFIG_SAMSUNG_DEV_PWM=y CONFIG_GPIO_SAMSUNG=y CONFIG_SAMSUNG_PM_GPIO=y CONFIG_SAMSUNG_WAKEMASK=y # end of Samsung Common options CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_INTEGRATOR_IMPD1=y # CONFIG_INTEGRATOR_CM1136JFS is not set CONFIG_ARCH_INTEGRATOR_CP=y CONFIG_INTEGRATOR_CTB36=y CONFIG_ARCH_CINTEGRATOR=y CONFIG_ARCH_REALVIEW=y # CONFIG_MACH_REALVIEW_EB is not set # CONFIG_MACH_REALVIEW_PB11MP is not set # CONFIG_MACH_REALVIEW_PB1176 is not set # CONFIG_ARCH_WM8750 is not set CONFIG_PLAT_VERSATILE=y # # Processor Type # CONFIG_CPU_V6=y CONFIG_CPU_V6K=y CONFIG_CPU_THUMB_CAPABLE=y CONFIG_CPU_32v6=y CONFIG_CPU_32v6K=y CONFIG_CPU_ABRT_EV6=y CONFIG_CPU_PABRT_V6=y CONFIG_CPU_CACHE_V6=y CONFIG_CPU_CACHE_VIPT=y CONFIG_CPU_COPY_V6=y CONFIG_CPU_TLB_V6=y CONFIG_CPU_HAS_ASID=y CONFIG_CPU_CP15=y CONFIG_CPU_CP15_MMU=y # # Processor Features # # CONFIG_ARM_THUMB is not set CONFIG_CPU_LITTLE_ENDIAN=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_ICACHE_DISABLE=y CONFIG_CPU_DCACHE_DISABLE=y CONFIG_CPU_BPREDICT_DISABLE=y CONFIG_KUSER_HELPERS=y CONFIG_OUTER_CACHE=y CONFIG_OUTER_CACHE_SYNC=y CONFIG_MIGHT_HAVE_CACHE_L2X0=y CONFIG_CACHE_L2X0=y CONFIG_CACHE_L2X0_PMU=y # CONFIG_PL310_ERRATA_588369 is not set CONFIG_PL310_ERRATA_727915=y CONFIG_PL310_ERRATA_753970=y # CONFIG_PL310_ERRATA_769419 is not set CONFIG_ARM_L1_CACHE_SHIFT=5 # CONFIG_ARM_DMA_MEM_BUFFERABLE is not set CONFIG_ARM_HEAVY_MB=y CONFIG_ARM_ERRATA_326103=y # CONFIG_ARM_ERRATA_411920 is not set # CONFIG_ARM_ERRATA_364296 is not set # end of System Type # # Bus support # # end of Bus support # # Kernel Features # CONFIG_IRQSTACKS=y # CONFIG_VMSPLIT_3G is not set # CONFIG_VMSPLIT_3G_OPT is not set CONFIG_VMSPLIT_2G=y # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0x80000000 CONFIG_ARCH_NR_GPIO=1024 CONFIG_HZ_FIXED=0 # CONFIG_HZ_100 is not set # CONFIG_HZ_200 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_300 is not set CONFIG_HZ_500=y # CONFIG_HZ_1000 is not set CONFIG_HZ=500 CONFIG_SCHED_HRTICK=y CONFIG_AEABI=y CONFIG_OABI_COMPAT=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y # CONFIG_CPU_SW_DOMAIN_PAN is not set # CONFIG_ARM_MODULE_PLTS is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y # end of Kernel Features # # Boot options # CONFIG_USE_OF=y CONFIG_ATAGS=y # CONFIG_UNUSED_BOARD_FILES is not set CONFIG_DEPRECATED_PARAM_STRUCT=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y # CONFIG_ARM_ATAG_DTB_COMPAT is not set CONFIG_CMDLINE="" # CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set CONFIG_AUTO_ZRELADDR=y # CONFIG_EFI is not set # end of Boot options # # CPU Power Management # # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set # end of CPU Frequency scaling # # CPU Idle # # CONFIG_CPU_IDLE is not set # end of CPU Idle # end of CPU Power Management # # Floating point emulation # # # At least one emulation must be selected # # CONFIG_FPE_NWFPE is not set # CONFIG_FPE_FASTFPE is not set # CONFIG_VFP is not set # end of Floating point emulation # # Power management options # CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y # CONFIG_SUSPEND_SKIP_SYNC is not set CONFIG_PM_SLEEP=y CONFIG_PM_AUTOSLEEP=y # CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set CONFIG_APM_EMULATION=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y # CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_CPU_PM=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_SHA256_ARM=y # CONFIG_CRYPTO_SHA512_ARM is not set # CONFIG_CRYPTO_BLAKE2S_ARM is not set CONFIG_CRYPTO_AES_ARM=m # CONFIG_CRYPTO_CHACHA20_NEON is not set # CONFIG_CRYPTO_POLY1305_ARM is not set CONFIG_AS_VFP_VMRS_FPINST=y # # General architecture-dependent options # CONFIG_KPROBES=y # CONFIG_JUMP_LABEL is not set CONFIG_OPTPROBES=y CONFIG_UPROBES=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_KRETPROBES=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_NMI=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_SECCOMP=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y # CONFIG_STACKPROTECTOR_STRONG is not set CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y # CONFIG_STRICT_KERNEL_RWX is not set CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y CONFIG_LOCK_EVENT_COUNTS=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=1 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y CONFIG_MODULE_SIG_ALL=y # CONFIG_MODULE_SIG_SHA1 is not set # CONFIG_MODULE_SIG_SHA224 is not set CONFIG_MODULE_SIG_SHA256=y # CONFIG_MODULE_SIG_SHA384 is not set # CONFIG_MODULE_SIG_SHA512 is not set CONFIG_MODULE_SIG_HASH="sha256" # CONFIG_MODULE_COMPRESS_NONE is not set # CONFIG_MODULE_COMPRESS_GZIP is not set # CONFIG_MODULE_COMPRESS_XZ is not set CONFIG_MODULE_COMPRESS_ZSTD=y # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y # CONFIG_BLOCK is not set CONFIG_ASN1=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_FREEZER=y # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_ELF_FDPIC is not set CONFIG_ELFCORE=y CONFIG_BINFMT_SCRIPT=m CONFIG_ARCH_HAS_BINFMT_FLAT=y # CONFIG_BINFMT_FLAT is not set CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_BINFMT_MISC=y # CONFIG_COREDUMP is not set # end of Executable file formats # # Memory Management options # # # SLAB allocator options # # CONFIG_SLAB is not set # CONFIG_SLUB is not set CONFIG_SLOB=y # end of SLAB allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set CONFIG_COMPAT_BRK=y CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_STATIC=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MEMORY_BALLOON=y # CONFIG_COMPACTION is not set CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_NEED_PER_CPU_KM=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PERCPU_STATS=y # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y CONFIG_ANON_VMA_NAME=y CONFIG_USERFAULTFD=y # # Data Access Monitoring # # CONFIG_DAMON is not set # end of Data Access Monitoring # end of Memory Management options # CONFIG_NET is not set # # Device Drivers # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y # CONFIG_PCI is not set CONFIG_PCCARD=y CONFIG_PCMCIA=y CONFIG_PCMCIA_LOAD_CIS=y # # PC-card bridges # # CONFIG_OMAP_CF is not set # # Generic Driver Options # CONFIG_AUXILIARY_BUS=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y # CONFIG_STANDALONE is not set CONFIG_PREVENT_FIRMWARE_BUILD=y # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set # CONFIG_FW_LOADER_COMPRESS is not set CONFIG_FW_CACHE=y # CONFIG_FW_UPLOAD is not set # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y # CONFIG_ALLOW_DEV_COREDUMP is not set # CONFIG_DEBUG_DRIVER is not set CONFIG_DEBUG_DEVRES=y # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_SOC_BUS=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SPMI=y CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set # end of Generic Driver Options # # Bus devices # CONFIG_ARM_INTEGRATOR_LM=y CONFIG_BRCMSTB_GISB_ARB=m # CONFIG_BT1_APB is not set CONFIG_BT1_AXI=y CONFIG_HISILICON_LPC=y CONFIG_IMX_WEIM=y # CONFIG_INTEL_IXP4XX_EB is not set CONFIG_QCOM_EBI2=y # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_FSL_MC_BUS is not set CONFIG_MHI_BUS=m CONFIG_MHI_BUS_DEBUG=y CONFIG_MHI_BUS_EP=y # end of Bus devices # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # CONFIG_ARM_SCMI_PROTOCOL=m # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set # CONFIG_ARM_SCMI_POWER_DOMAIN is not set CONFIG_ARM_SCMI_POWER_CONTROL=m # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=m CONFIG_ARM_SCPI_POWER_DOMAIN=y CONFIG_FIRMWARE_MEMMAP=y CONFIG_MTK_ADSP_IPC=y CONFIG_QCOM_SCM=m # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set CONFIG_TURRIS_MOX_RWTM=y # CONFIG_BCM47XX_NVRAM is not set # CONFIG_TEE_BNXT_FW is not set CONFIG_GOOGLE_FIRMWARE=y CONFIG_GOOGLE_COREBOOT_TABLE=m CONFIG_GOOGLE_MEMCONSOLE=m CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m # CONFIG_GOOGLE_VPD is not set CONFIG_IMX_DSP=m # CONFIG_IMX_SCU is not set # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers CONFIG_GNSS=y CONFIG_GNSS_SERIAL=m # CONFIG_GNSS_MTK_SERIAL is not set CONFIG_GNSS_SIRF_SERIAL=m CONFIG_GNSS_UBX_SERIAL=m # CONFIG_MTD is not set CONFIG_DTC=y CONFIG_OF=y CONFIG_OF_UNITTEST=y CONFIG_OF_ALL_DTBS=y CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_DYNAMIC=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y CONFIG_OF_RESOLVE=y # CONFIG_OF_OVERLAY is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=y # CONFIG_PARPORT_PC_FIFO is not set CONFIG_PARPORT_PC_SUPERIO=y CONFIG_PARPORT_PC_PCMCIA=m CONFIG_PARPORT_AX88796=m # CONFIG_PARPORT_1284 is not set CONFIG_PARPORT_NOT_PC=y # # NVME Support # # end of NVME Support # # Misc devices # CONFIG_SENSORS_LIS3LV02D=y CONFIG_AD525X_DPOT=y # CONFIG_AD525X_DPOT_I2C is not set CONFIG_DUMMY_IRQ=m # CONFIG_ICS932S401 is not set # CONFIG_ATMEL_SSC is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_HI6421V600_IRQ=y CONFIG_QCOM_COINCELL=m CONFIG_QCOM_FASTRPC=m CONFIG_APDS9802ALS=y # CONFIG_ISL29003 is not set # CONFIG_ISL29020 is not set CONFIG_SENSORS_TSL2550=m CONFIG_SENSORS_BH1770=y # CONFIG_SENSORS_APDS990X is not set CONFIG_HMC6352=m CONFIG_DS1682=m CONFIG_SRAM=y CONFIG_SRAM_EXEC=y CONFIG_XILINX_SDFEC=y CONFIG_OPEN_DICE=y CONFIG_VCPU_STALL_DETECTOR=m CONFIG_C2PORT=y # # EEPROM support # CONFIG_EEPROM_AT24=y CONFIG_EEPROM_LEGACY=m # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_EEPROM_IDT_89HPESX is not set CONFIG_EEPROM_EE1004=y # end of EEPROM support # # Texas Instruments shared transport line discipline # # end of Texas Instruments shared transport line discipline CONFIG_SENSORS_LIS3_I2C=y CONFIG_ALTERA_STAPL=m CONFIG_ECHO=m CONFIG_UACCE=m CONFIG_PVPANIC=y CONFIG_PVPANIC_MMIO=m # end of Misc devices # # SCSI device support # CONFIG_SCSI_MOD=y # end of SCSI device support CONFIG_HAVE_PATA_PLATFORM=y # # IEEE 1394 (FireWire) support # CONFIG_FIREWIRE=m # end of IEEE 1394 (FireWire) support # # Input device support # CONFIG_INPUT=y CONFIG_INPUT_LEDS=m CONFIG_INPUT_FF_MEMLESS=m CONFIG_INPUT_SPARSEKMAP=m CONFIG_INPUT_MATRIXKMAP=y CONFIG_INPUT_VIVALDIFMAP=m # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=m CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_JOYDEV=m CONFIG_INPUT_EVDEV=m CONFIG_INPUT_EVBUG=y CONFIG_INPUT_APMPOWER=m # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ADP5588=m # CONFIG_KEYBOARD_ADP5589 is not set CONFIG_KEYBOARD_ATKBD=m CONFIG_KEYBOARD_QT1050=y # CONFIG_KEYBOARD_QT1070 is not set CONFIG_KEYBOARD_QT2160=m CONFIG_KEYBOARD_CLPS711X=m CONFIG_KEYBOARD_DLINK_DIR685=m CONFIG_KEYBOARD_LKKBD=m # CONFIG_KEYBOARD_EP93XX is not set # CONFIG_KEYBOARD_GPIO is not set CONFIG_KEYBOARD_GPIO_POLLED=y # CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_TCA8418 is not set # CONFIG_KEYBOARD_MATRIX is not set CONFIG_KEYBOARD_LM8323=y CONFIG_KEYBOARD_LM8333=y # CONFIG_KEYBOARD_MAX7359 is not set CONFIG_KEYBOARD_MCS=m CONFIG_KEYBOARD_MPR121=y # CONFIG_KEYBOARD_SNVS_PWRKEY is not set CONFIG_KEYBOARD_IMX=y # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set CONFIG_KEYBOARD_PMIC8XXX=m CONFIG_KEYBOARD_SAMSUNG=m # CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set CONFIG_KEYBOARD_STOWAWAY=m CONFIG_KEYBOARD_ST_KEYSCAN=y CONFIG_KEYBOARD_SUNKBD=y CONFIG_KEYBOARD_SH_KEYSC=m CONFIG_KEYBOARD_STMPE=y # CONFIG_KEYBOARD_IQS62X is not set CONFIG_KEYBOARD_OMAP4=m # CONFIG_KEYBOARD_TM2_TOUCHKEY is not set CONFIG_KEYBOARD_XTKBD=y # CONFIG_KEYBOARD_CROS_EC is not set CONFIG_KEYBOARD_CAP11XX=m CONFIG_KEYBOARD_BCM=m # CONFIG_KEYBOARD_MT6779 is not set CONFIG_KEYBOARD_MTK_PMIC=y CONFIG_KEYBOARD_CYPRESS_SF=m CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=m CONFIG_MOUSE_PS2_ALPS=y # CONFIG_MOUSE_PS2_BYD is not set # CONFIG_MOUSE_PS2_LOGIPS2PP is not set # CONFIG_MOUSE_PS2_SYNAPTICS is not set CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y CONFIG_MOUSE_PS2_CYPRESS=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set CONFIG_MOUSE_PS2_SENTELIC=y # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_PS2_FOCALTECH=y CONFIG_MOUSE_PS2_SMBUS=y # CONFIG_MOUSE_SERIAL is not set CONFIG_MOUSE_CYAPA=y # CONFIG_MOUSE_ELAN_I2C is not set # CONFIG_MOUSE_VSXXXAA is not set CONFIG_MOUSE_GPIO=y CONFIG_MOUSE_SYNAPTICS_I2C=y CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_ANALOG=y # CONFIG_JOYSTICK_A3D is not set CONFIG_JOYSTICK_ADI=m CONFIG_JOYSTICK_COBRA=y # CONFIG_JOYSTICK_GF2K is not set CONFIG_JOYSTICK_GRIP=y # CONFIG_JOYSTICK_GRIP_MP is not set # CONFIG_JOYSTICK_GUILLEMOT is not set CONFIG_JOYSTICK_INTERACT=y CONFIG_JOYSTICK_SIDEWINDER=y CONFIG_JOYSTICK_TMDC=m # CONFIG_JOYSTICK_IFORCE is not set CONFIG_JOYSTICK_WARRIOR=m CONFIG_JOYSTICK_MAGELLAN=m # CONFIG_JOYSTICK_SPACEORB is not set # CONFIG_JOYSTICK_SPACEBALL is not set # CONFIG_JOYSTICK_STINGER is not set CONFIG_JOYSTICK_TWIDJOY=m CONFIG_JOYSTICK_ZHENHUA=m # CONFIG_JOYSTICK_DB9 is not set # CONFIG_JOYSTICK_GAMECON is not set CONFIG_JOYSTICK_TURBOGRAFX=y CONFIG_JOYSTICK_AS5011=y # CONFIG_JOYSTICK_JOYDUMP is not set CONFIG_JOYSTICK_WALKERA0701=m CONFIG_JOYSTICK_QWIIC=y # CONFIG_JOYSTICK_FSIA6B is not set CONFIG_JOYSTICK_SENSEHAT=m # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set CONFIG_RMI4_CORE=m # CONFIG_RMI4_I2C is not set # CONFIG_RMI4_SMB is not set CONFIG_RMI4_F03=y CONFIG_RMI4_F03_SERIO=m CONFIG_RMI4_2D_SENSOR=y CONFIG_RMI4_F11=y CONFIG_RMI4_F12=y CONFIG_RMI4_F30=y CONFIG_RMI4_F34=y CONFIG_RMI4_F3A=y # CONFIG_RMI4_F54 is not set CONFIG_RMI4_F55=y # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_PARKBD=y # CONFIG_SERIO_AMBAKMI is not set CONFIG_SERIO_LIBPS2=m CONFIG_SERIO_RAW=m CONFIG_SERIO_ALTERA_PS2=y # CONFIG_SERIO_PS2MULT is not set CONFIG_SERIO_ARC_PS2=m CONFIG_SERIO_APBPS2=y CONFIG_SERIO_OLPC_APSP=m # CONFIG_SERIO_SUN4I_PS2 is not set # CONFIG_SERIO_GPIO_PS2 is not set CONFIG_USERIO=m CONFIG_GAMEPORT=y CONFIG_GAMEPORT_NS558=y CONFIG_GAMEPORT_L4=y # end of Hardware I/O ports # end of Input device support # # Character devices # # CONFIG_TTY is not set CONFIG_SERIAL_DEV_BUS=m # CONFIG_PRINTER is not set # CONFIG_PPDEV is not set # CONFIG_IPMI_HANDLER is not set CONFIG_IPMI_KCS_BMC=m # CONFIG_ASPEED_KCS_IPMI_BMC is not set CONFIG_NPCM7XX_KCS_IPMI_BMC=m CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m CONFIG_IPMI_KCS_BMC_SERIO=m # CONFIG_ASPEED_BT_IPMI_BMC is not set CONFIG_IPMB_DEVICE_INTERFACE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=y CONFIG_HW_RANDOM_ATMEL=y # CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_BCM2835=y # CONFIG_HW_RANDOM_IPROC_RNG200 is not set # CONFIG_HW_RANDOM_IXP4XX is not set CONFIG_HW_RANDOM_OMAP=m # CONFIG_HW_RANDOM_OMAP3_ROM is not set CONFIG_HW_RANDOM_VIRTIO=y CONFIG_HW_RANDOM_IMX_RNGC=y CONFIG_HW_RANDOM_NOMADIK=m # CONFIG_HW_RANDOM_STM32 is not set CONFIG_HW_RANDOM_MESON=m CONFIG_HW_RANDOM_MTK=m CONFIG_HW_RANDOM_EXYNOS=y # CONFIG_HW_RANDOM_NPCM is not set # CONFIG_HW_RANDOM_KEYSTONE is not set CONFIG_HW_RANDOM_CCTRNG=m CONFIG_HW_RANDOM_XIPHERA=y # # PCMCIA character devices # CONFIG_CARDMAN_4000=m # CONFIG_CARDMAN_4040 is not set # CONFIG_SCR24X is not set # end of PCMCIA character devices # CONFIG_DEVMEM is not set CONFIG_TCG_TPM=y # CONFIG_HW_RANDOM_TPM is not set CONFIG_TCG_TIS_CORE=y CONFIG_TCG_TIS=m CONFIG_TCG_TIS_I2C=y CONFIG_TCG_TIS_SYNQUACER=m # CONFIG_TCG_TIS_I2C_CR50 is not set CONFIG_TCG_TIS_I2C_ATMEL=m CONFIG_TCG_TIS_I2C_INFINEON=m CONFIG_TCG_TIS_I2C_NUVOTON=y # CONFIG_TCG_VTPM_PROXY is not set CONFIG_TCG_TIS_ST33ZP24=m CONFIG_TCG_TIS_ST33ZP24_I2C=m CONFIG_XILLYBUS_CLASS=m CONFIG_XILLYBUS=m CONFIG_XILLYBUS_OF=m CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices # # I2C support # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y # CONFIG_I2C_MUX is not set CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_SMBUS=m CONFIG_I2C_ALGOBIT=y # # I2C Hardware Bus support # # CONFIG_I2C_HIX5HD2 is not set # # I2C system bus drivers (mostly embedded / system-on-chip) # CONFIG_I2C_ALTERA=y CONFIG_I2C_ASPEED=y CONFIG_I2C_AT91=y # CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set CONFIG_I2C_AXXIA=y CONFIG_I2C_BCM2835=y CONFIG_I2C_BCM_IPROC=y # CONFIG_I2C_BCM_KONA is not set CONFIG_I2C_BRCMSTB=y CONFIG_I2C_CADENCE=m CONFIG_I2C_CBUS_GPIO=y # CONFIG_I2C_DAVINCI is not set CONFIG_I2C_DESIGNWARE_CORE=y CONFIG_I2C_DESIGNWARE_SLAVE=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_DIGICOLOR=m CONFIG_I2C_EMEV2=y CONFIG_I2C_EXYNOS5=y CONFIG_I2C_GPIO=y # CONFIG_I2C_GPIO_FAULT_INJECTOR is not set CONFIG_I2C_HIGHLANDER=y CONFIG_I2C_HISI=y CONFIG_I2C_IMG=m # CONFIG_I2C_IMX is not set CONFIG_I2C_IMX_LPI2C=m # CONFIG_I2C_IOP3XX is not set CONFIG_I2C_JZ4780=y CONFIG_I2C_LPC2K=y CONFIG_I2C_MESON=y CONFIG_I2C_MICROCHIP_CORE=y # CONFIG_I2C_MT65XX is not set CONFIG_I2C_MT7621=m CONFIG_I2C_MV64XXX=y CONFIG_I2C_MXS=m CONFIG_I2C_NOMADIK=m CONFIG_I2C_NPCM=y CONFIG_I2C_OCORES=y # CONFIG_I2C_OMAP is not set CONFIG_I2C_OWL=y # CONFIG_I2C_APPLE is not set # CONFIG_I2C_PCA_PLATFORM is not set CONFIG_I2C_PNX=m # CONFIG_I2C_PXA is not set CONFIG_I2C_QCOM_CCI=y CONFIG_I2C_QCOM_GENI=m CONFIG_I2C_QUP=y # CONFIG_I2C_RIIC is not set # CONFIG_I2C_RK3X is not set CONFIG_I2C_RZV2M=y # CONFIG_I2C_S3C2410 is not set CONFIG_I2C_SH_MOBILE=y # CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_SPRD is not set # CONFIG_I2C_ST is not set CONFIG_I2C_STM32F4=y CONFIG_I2C_STM32F7=m # CONFIG_I2C_SUN6I_P2WI is not set CONFIG_I2C_SYNQUACER=m # CONFIG_I2C_TEGRA is not set CONFIG_I2C_TEGRA_BPMP=m CONFIG_I2C_UNIPHIER=y CONFIG_I2C_UNIPHIER_F=y CONFIG_I2C_VERSATILE=y CONFIG_I2C_WMT=m CONFIG_I2C_XILINX=y CONFIG_I2C_XLP9XX=m # CONFIG_I2C_RCAR is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_PARPORT is not set # # Other I2C/SMBus bus drivers # # CONFIG_I2C_MLXCPLD is not set CONFIG_I2C_CROS_EC_TUNNEL=m CONFIG_I2C_VIRTIO=y # end of I2C Hardware Bus support # CONFIG_I2C_STUB is not set CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=y CONFIG_I2C_SLAVE_TESTUNIT=y # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # end of I2C support CONFIG_I3C=y CONFIG_CDNS_I3C_MASTER=m CONFIG_DW_I3C_MASTER=y CONFIG_SVC_I3C_MASTER=m CONFIG_MIPI_I3C_HCI=m # CONFIG_SPI is not set CONFIG_SPMI=y CONFIG_SPMI_HISI3670=y CONFIG_SPMI_MSM_PMIC_ARB=y CONFIG_SPMI_MTK_PMIF=y # CONFIG_HSI is not set CONFIG_PPS=m # CONFIG_PPS_DEBUG is not set # CONFIG_NTP_PPS is not set # # PPS clients support # CONFIG_PPS_CLIENT_KTIMER=m CONFIG_PPS_CLIENT_PARPORT=m CONFIG_PPS_CLIENT_GPIO=m # # PPS generators support # # # PTP clock support # CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # # end of PTP clock support CONFIG_PINCTRL=y CONFIG_GENERIC_PINCTRL_GROUPS=y CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set CONFIG_PINCTRL_AMD=y # CONFIG_PINCTRL_AS3722 is not set CONFIG_PINCTRL_AT91PIO4=y CONFIG_PINCTRL_AXP209=y # CONFIG_PINCTRL_BM1880 is not set CONFIG_PINCTRL_DA850_PUPD=m # CONFIG_PINCTRL_DA9062 is not set CONFIG_PINCTRL_EQUILIBRIUM=y # CONFIG_PINCTRL_INGENIC is not set CONFIG_PINCTRL_LPC18XX=y # CONFIG_PINCTRL_MAX77620 is not set CONFIG_PINCTRL_MCP23S08_I2C=y CONFIG_PINCTRL_MCP23S08=y # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set CONFIG_PINCTRL_OCELOT=m CONFIG_PINCTRL_OXNAS=y # CONFIG_PINCTRL_PALMAS is not set CONFIG_PINCTRL_PISTACHIO=y CONFIG_PINCTRL_RK805=y CONFIG_PINCTRL_ROCKCHIP=m CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_STARFIVE=y CONFIG_PINCTRL_STMFX=y # CONFIG_PINCTRL_SX150X is not set CONFIG_PINCTRL_OWL=y # CONFIG_PINCTRL_S500 is not set # CONFIG_PINCTRL_S700 is not set CONFIG_PINCTRL_S900=y CONFIG_PINCTRL_ASPEED=y # CONFIG_PINCTRL_ASPEED_G4 is not set CONFIG_PINCTRL_ASPEED_G5=y # CONFIG_PINCTRL_ASPEED_G6 is not set CONFIG_PINCTRL_BCM281XX=y # CONFIG_PINCTRL_BCM2835 is not set # CONFIG_PINCTRL_BCM4908 is not set CONFIG_PINCTRL_BCM63XX=y CONFIG_PINCTRL_BCM6318=y # CONFIG_PINCTRL_BCM6328 is not set CONFIG_PINCTRL_BCM6358=y # CONFIG_PINCTRL_BCM6362 is not set CONFIG_PINCTRL_BCM6368=y CONFIG_PINCTRL_BCM63268=y # CONFIG_PINCTRL_IPROC_GPIO is not set CONFIG_PINCTRL_CYGNUS_MUX=y CONFIG_PINCTRL_NS=y CONFIG_PINCTRL_NSP_GPIO=y # CONFIG_PINCTRL_NS2_MUX is not set # CONFIG_PINCTRL_NSP_MUX is not set # CONFIG_PINCTRL_AS370 is not set # CONFIG_PINCTRL_BERLIN_BG4CT is not set # CONFIG_PINCTRL_LOCHNAGAR is not set CONFIG_PINCTRL_MADERA=m CONFIG_PINCTRL_CS47L90=y CONFIG_PINCTRL_CS47L92=y CONFIG_PINCTRL_IMX=y CONFIG_PINCTRL_IMX8MM=y CONFIG_PINCTRL_IMX8MN=m CONFIG_PINCTRL_IMX8MP=m CONFIG_PINCTRL_IMX8MQ=m # CONFIG_PINCTRL_IMX8ULP is not set CONFIG_PINCTRL_IMXRT1050=y CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1170 is not set # # Intel pinctrl drivers # # end of Intel pinctrl drivers # # MediaTek pinctrl drivers # CONFIG_EINT_MTK=y CONFIG_PINCTRL_MTK=y CONFIG_PINCTRL_MTK_V2=y CONFIG_PINCTRL_MTK_MOORE=y CONFIG_PINCTRL_MTK_PARIS=y # CONFIG_PINCTRL_MT2701 is not set # CONFIG_PINCTRL_MT7623 is not set CONFIG_PINCTRL_MT7629=y # CONFIG_PINCTRL_MT8135 is not set # CONFIG_PINCTRL_MT8127 is not set CONFIG_PINCTRL_MT2712=y CONFIG_PINCTRL_MT6765=m # CONFIG_PINCTRL_MT6779 is not set CONFIG_PINCTRL_MT6795=y CONFIG_PINCTRL_MT6797=y CONFIG_PINCTRL_MT7622=y CONFIG_PINCTRL_MT7986=y # CONFIG_PINCTRL_MT8167 is not set CONFIG_PINCTRL_MT8173=y CONFIG_PINCTRL_MT8183=y # CONFIG_PINCTRL_MT8186 is not set CONFIG_PINCTRL_MT8192=y # CONFIG_PINCTRL_MT8195 is not set # CONFIG_PINCTRL_MT8365 is not set CONFIG_PINCTRL_MT8516=y CONFIG_PINCTRL_MT6397=y # end of MediaTek pinctrl drivers CONFIG_PINCTRL_MESON=y # CONFIG_PINCTRL_MESON8 is not set # CONFIG_PINCTRL_MESON8B is not set CONFIG_PINCTRL_WPCM450=m CONFIG_PINCTRL_NPCM7XX=y CONFIG_PINCTRL_PXA=y CONFIG_PINCTRL_PXA25X=y # CONFIG_PINCTRL_PXA27X is not set # CONFIG_PINCTRL_MSM is not set CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y # CONFIG_PINCTRL_LPASS_LPI is not set # # Renesas pinctrl drivers # # CONFIG_PINCTRL_RENESAS is not set CONFIG_PINCTRL_SH_PFC=y CONFIG_PINCTRL_SH_PFC_GPIO=y CONFIG_PINCTRL_SH_FUNC_GPIO=y CONFIG_PINCTRL_PFC_EMEV2=y # CONFIG_PINCTRL_PFC_R8A77995 is not set CONFIG_PINCTRL_PFC_R8A7794=y CONFIG_PINCTRL_PFC_R8A77990=y # CONFIG_PINCTRL_PFC_R8A7779 is not set CONFIG_PINCTRL_PFC_R8A7790=y CONFIG_PINCTRL_PFC_R8A77950=y # CONFIG_PINCTRL_PFC_R8A77951 is not set # CONFIG_PINCTRL_PFC_R8A7778 is not set CONFIG_PINCTRL_PFC_R8A7793=y # CONFIG_PINCTRL_PFC_R8A7791 is not set CONFIG_PINCTRL_PFC_R8A77965=y # CONFIG_PINCTRL_PFC_R8A77960 is not set CONFIG_PINCTRL_PFC_R8A77961=y CONFIG_PINCTRL_PFC_R8A779F0=y # CONFIG_PINCTRL_PFC_R8A7792 is not set # CONFIG_PINCTRL_PFC_R8A77980 is not set CONFIG_PINCTRL_PFC_R8A77970=y CONFIG_PINCTRL_PFC_R8A779A0=y CONFIG_PINCTRL_PFC_R8A779G0=y CONFIG_PINCTRL_PFC_R8A7740=y # CONFIG_PINCTRL_PFC_R8A73A4 is not set # CONFIG_PINCTRL_RZA1 is not set CONFIG_PINCTRL_RZA2=y CONFIG_PINCTRL_RZG2L=y # CONFIG_PINCTRL_PFC_R8A77470 is not set CONFIG_PINCTRL_PFC_R8A7745=y CONFIG_PINCTRL_PFC_R8A7742=y # CONFIG_PINCTRL_PFC_R8A7743 is not set # CONFIG_PINCTRL_PFC_R8A7744 is not set CONFIG_PINCTRL_PFC_R8A774C0=y CONFIG_PINCTRL_PFC_R8A774E1=y # CONFIG_PINCTRL_PFC_R8A774A1 is not set CONFIG_PINCTRL_PFC_R8A774B1=y CONFIG_PINCTRL_RZN1=y CONFIG_PINCTRL_RZV2M=y # CONFIG_PINCTRL_PFC_SH7203 is not set CONFIG_PINCTRL_PFC_SH7264=y # CONFIG_PINCTRL_PFC_SH7269 is not set # CONFIG_PINCTRL_PFC_SH7720 is not set CONFIG_PINCTRL_PFC_SH7722=y CONFIG_PINCTRL_PFC_SH7734=y CONFIG_PINCTRL_PFC_SH7757=y CONFIG_PINCTRL_PFC_SH7785=y CONFIG_PINCTRL_PFC_SH7786=y CONFIG_PINCTRL_PFC_SH73A0=y CONFIG_PINCTRL_PFC_SH7723=y # CONFIG_PINCTRL_PFC_SH7724 is not set CONFIG_PINCTRL_PFC_SHX3=y # end of Renesas pinctrl drivers CONFIG_PINCTRL_SAMSUNG=y CONFIG_PINCTRL_EXYNOS=y CONFIG_PINCTRL_EXYNOS_ARM=y # CONFIG_PINCTRL_EXYNOS_ARM64 is not set # CONFIG_PINCTRL_S3C24XX is not set CONFIG_PINCTRL_S3C64XX=y CONFIG_PINCTRL_SPRD=m CONFIG_PINCTRL_SPRD_SC9860=m CONFIG_PINCTRL_STM32=y CONFIG_PINCTRL_STM32F429=y # CONFIG_PINCTRL_STM32F469 is not set CONFIG_PINCTRL_STM32F746=y # CONFIG_PINCTRL_STM32F769 is not set CONFIG_PINCTRL_STM32H743=y # CONFIG_PINCTRL_STM32MP135 is not set # CONFIG_PINCTRL_STM32MP157 is not set CONFIG_PINCTRL_TI_IODELAY=y # CONFIG_PINCTRL_UNIPHIER is not set # CONFIG_PINCTRL_TMPV7700 is not set CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_CDEV is not set CONFIG_GPIO_GENERIC=y CONFIG_GPIO_REGMAP=y # # Memory mapped GPIO drivers # CONFIG_GPIO_74XX_MMIO=y CONFIG_GPIO_ALTERA=m CONFIG_GPIO_ASPEED=y # CONFIG_GPIO_ASPEED_SGPIO is not set CONFIG_GPIO_ATH79=y CONFIG_GPIO_RASPBERRYPI_EXP=m CONFIG_GPIO_BCM_KONA=y CONFIG_GPIO_BCM_XGS_IPROC=m # CONFIG_GPIO_BRCMSTB is not set # CONFIG_GPIO_CADENCE is not set CONFIG_GPIO_CLPS711X=y # CONFIG_GPIO_DWAPB is not set CONFIG_GPIO_EIC_SPRD=m CONFIG_GPIO_EM=y CONFIG_GPIO_FTGPIO010=y # CONFIG_GPIO_GENERIC_PLATFORM is not set CONFIG_GPIO_GRGPIO=m # CONFIG_GPIO_HISI is not set CONFIG_GPIO_HLWD=m CONFIG_GPIO_IOP=y # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_LPC18XX is not set CONFIG_GPIO_LPC32XX=y # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_MENZ127=y CONFIG_GPIO_MPC8XXX=y # CONFIG_GPIO_MT7621 is not set CONFIG_GPIO_MXC=y # CONFIG_GPIO_MXS is not set CONFIG_GPIO_OMAP=y CONFIG_GPIO_PL061=y CONFIG_GPIO_PMIC_EIC_SPRD=m CONFIG_GPIO_PXA=y # CONFIG_GPIO_RCAR is not set CONFIG_GPIO_RDA=y # CONFIG_GPIO_ROCKCHIP is not set # CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SNPS_CREG is not set CONFIG_GPIO_SPRD=y # CONFIG_GPIO_STP_XWAY is not set CONFIG_GPIO_SYSCON=m CONFIG_GPIO_TEGRA=m # CONFIG_GPIO_TEGRA186 is not set # CONFIG_GPIO_TS4800 is not set CONFIG_GPIO_UNIPHIER=m CONFIG_GPIO_VF610=y # CONFIG_GPIO_VISCONTI is not set CONFIG_GPIO_XGENE_SB=y CONFIG_GPIO_XILINX=m # CONFIG_GPIO_XLP is not set CONFIG_GPIO_ZEVIO=y # CONFIG_GPIO_AMD_FCH is not set CONFIG_GPIO_IDT3243X=y # end of Memory mapped GPIO drivers # # I2C GPIO expanders # CONFIG_GPIO_ADP5588=y CONFIG_GPIO_ADP5588_IRQ=y # CONFIG_GPIO_ADNP is not set CONFIG_GPIO_GW_PLD=m # CONFIG_GPIO_MAX7300 is not set CONFIG_GPIO_MAX732X=y CONFIG_GPIO_MAX732X_IRQ=y # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set CONFIG_GPIO_TPIC2810=m CONFIG_GPIO_TS4900=y # end of I2C GPIO expanders # # MFD GPIO expanders # CONFIG_GPIO_BD71815=m CONFIG_GPIO_BD71828=m CONFIG_GPIO_DA9052=y CONFIG_GPIO_DA9055=m CONFIG_HTC_EGPIO=y # CONFIG_GPIO_LP87565 is not set # CONFIG_GPIO_MADERA is not set # CONFIG_GPIO_MAX77620 is not set CONFIG_GPIO_MAX77650=y # CONFIG_GPIO_PALMAS is not set CONFIG_GPIO_RC5T583=y CONFIG_GPIO_SL28CPLD=m CONFIG_GPIO_STMPE=y CONFIG_GPIO_TPS65912=y CONFIG_GPIO_TWL6040=m # CONFIG_GPIO_WM8350 is not set CONFIG_GPIO_WM8994=m # end of MFD GPIO expanders # # Virtual GPIO drivers # CONFIG_GPIO_AGGREGATOR=y CONFIG_GPIO_MOCKUP=y CONFIG_GPIO_VIRTIO=y CONFIG_GPIO_SIM=y # end of Virtual GPIO drivers CONFIG_W1=y # # 1-wire Bus Masters # CONFIG_W1_MASTER_DS2482=y CONFIG_W1_MASTER_MXC=m CONFIG_W1_MASTER_DS1WM=y CONFIG_W1_MASTER_GPIO=y CONFIG_W1_MASTER_SGI=y # end of 1-wire Bus Masters # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=y # CONFIG_W1_SLAVE_SMEM is not set CONFIG_W1_SLAVE_DS2405=y CONFIG_W1_SLAVE_DS2408=m CONFIG_W1_SLAVE_DS2408_READBACK=y CONFIG_W1_SLAVE_DS2413=m CONFIG_W1_SLAVE_DS2406=m CONFIG_W1_SLAVE_DS2423=m CONFIG_W1_SLAVE_DS2805=y CONFIG_W1_SLAVE_DS2430=y # CONFIG_W1_SLAVE_DS2431 is not set # CONFIG_W1_SLAVE_DS2433 is not set CONFIG_W1_SLAVE_DS2438=y CONFIG_W1_SLAVE_DS250X=y CONFIG_W1_SLAVE_DS2780=m CONFIG_W1_SLAVE_DS2781=y CONFIG_W1_SLAVE_DS28E04=m CONFIG_W1_SLAVE_DS28E17=y # end of 1-wire Slaves CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_AS3722 is not set CONFIG_POWER_RESET_ATC260X=m # CONFIG_POWER_RESET_BRCMKONA is not set CONFIG_POWER_RESET_BRCMSTB=y CONFIG_POWER_RESET_GEMINI_POWEROFF=y CONFIG_POWER_RESET_GPIO=y # CONFIG_POWER_RESET_GPIO_RESTART is not set CONFIG_POWER_RESET_OCELOT_RESET=y CONFIG_POWER_RESET_OXNAS=y # CONFIG_POWER_RESET_LTC2952 is not set CONFIG_POWER_RESET_REGULATOR=y # CONFIG_POWER_RESET_RESTART is not set CONFIG_POWER_RESET_VERSATILE=y # CONFIG_POWER_RESET_KEYSTONE is not set CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_POWER_RESET_RMOBILE=y CONFIG_REBOOT_MODE=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_POWER_RESET_SC27XX=m CONFIG_NVMEM_REBOOT_MODE=y CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_DEBUG=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PDA_POWER=m # CONFIG_APM_POWER is not set # CONFIG_IP5XXX_POWER is not set CONFIG_MAX8925_POWER=m CONFIG_WM8350_POWER=y CONFIG_TEST_POWER=m CONFIG_CHARGER_ADP5061=y CONFIG_BATTERY_ACT8945A=m CONFIG_BATTERY_CW2015=y CONFIG_BATTERY_DS2760=m CONFIG_BATTERY_DS2780=m CONFIG_BATTERY_DS2781=m # CONFIG_BATTERY_DS2782 is not set CONFIG_BATTERY_SAMSUNG_SDI=y CONFIG_BATTERY_SBS=m CONFIG_CHARGER_SBS=y CONFIG_BATTERY_BQ27XXX=y # CONFIG_BATTERY_BQ27XXX_I2C is not set CONFIG_BATTERY_BQ27XXX_HDQ=m CONFIG_BATTERY_DA9052=m # CONFIG_BATTERY_DA9150 is not set CONFIG_BATTERY_MAX17040=m # CONFIG_BATTERY_MAX17042 is not set # CONFIG_BATTERY_MAX1721X is not set CONFIG_CHARGER_MAX8903=y CONFIG_CHARGER_LP8727=y CONFIG_CHARGER_GPIO=y CONFIG_CHARGER_MANAGER=y # CONFIG_CHARGER_LT3651 is not set CONFIG_CHARGER_LTC4162L=m CONFIG_CHARGER_MAX14577=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_MAX77650 is not set CONFIG_CHARGER_MAX77693=m CONFIG_CHARGER_MAX77976=y CONFIG_CHARGER_MAX8998=m # CONFIG_CHARGER_MT6360 is not set CONFIG_CHARGER_QCOM_SMBB=m CONFIG_CHARGER_BQ2415X=y CONFIG_CHARGER_BQ24190=m CONFIG_CHARGER_BQ24257=m # CONFIG_CHARGER_BQ24735 is not set # CONFIG_CHARGER_BQ2515X is not set CONFIG_CHARGER_BQ25890=y CONFIG_CHARGER_BQ25980=y CONFIG_CHARGER_BQ256XX=y CONFIG_CHARGER_SMB347=y CONFIG_CHARGER_TPS65090=m CONFIG_CHARGER_TPS65217=m CONFIG_BATTERY_GAUGE_LTC2941=m CONFIG_BATTERY_GOLDFISH=y # CONFIG_BATTERY_RT5033 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_CROS_USBPD is not set CONFIG_CHARGER_CROS_PCHG=m # CONFIG_CHARGER_SC2731 is not set CONFIG_CHARGER_UCS1002=m # CONFIG_CHARGER_BD99954 is not set CONFIG_BATTERY_UG3105=y CONFIG_HWMON=y CONFIG_HWMON_VID=y CONFIG_HWMON_DEBUG_CHIP=y # # Native drivers # CONFIG_SENSORS_AD7414=m # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set CONFIG_SENSORS_ADM1026=m CONFIG_SENSORS_ADM1029=m CONFIG_SENSORS_ADM1031=y CONFIG_SENSORS_ADM1177=m # CONFIG_SENSORS_ADM9240 is not set CONFIG_SENSORS_ADT7X10=y CONFIG_SENSORS_ADT7410=y CONFIG_SENSORS_ADT7411=m CONFIG_SENSORS_ADT7462=m CONFIG_SENSORS_ADT7470=m # CONFIG_SENSORS_ADT7475 is not set CONFIG_SENSORS_AHT10=m CONFIG_SENSORS_AS370=m CONFIG_SENSORS_ASC7621=y CONFIG_SENSORS_AXI_FAN_CONTROL=y CONFIG_SENSORS_ARM_SCMI=m CONFIG_SENSORS_ARM_SCPI=m CONFIG_SENSORS_ASB100=m CONFIG_SENSORS_ASPEED=y # CONFIG_SENSORS_ATXP1 is not set CONFIG_SENSORS_BT1_PVT=y # CONFIG_SENSORS_BT1_PVT_ALARMS is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set CONFIG_SENSORS_CORSAIR_PSU=m CONFIG_SENSORS_DS620=m # CONFIG_SENSORS_DS1621 is not set CONFIG_SENSORS_DA9052_ADC=y # CONFIG_SENSORS_DA9055 is not set # CONFIG_SENSORS_SPARX5 is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set CONFIG_SENSORS_F75375S=y # CONFIG_SENSORS_MC13783_ADC is not set CONFIG_SENSORS_FSCHMD=y CONFIG_SENSORS_FTSTEUTATES=m # CONFIG_SENSORS_GL518SM is not set CONFIG_SENSORS_GL520SM=m # CONFIG_SENSORS_G760A is not set CONFIG_SENSORS_G762=y CONFIG_SENSORS_GPIO_FAN=m CONFIG_SENSORS_HIH6130=y CONFIG_SENSORS_IT87=y # CONFIG_SENSORS_JC42 is not set CONFIG_SENSORS_POWR1220=y CONFIG_SENSORS_LAN966X=y CONFIG_SENSORS_LINEAGE=m CONFIG_SENSORS_LOCHNAGAR=m CONFIG_SENSORS_LTC2945=y CONFIG_SENSORS_LTC2947=y CONFIG_SENSORS_LTC2947_I2C=y # CONFIG_SENSORS_LTC2990 is not set CONFIG_SENSORS_LTC2992=m # CONFIG_SENSORS_LTC4151 is not set CONFIG_SENSORS_LTC4215=m CONFIG_SENSORS_LTC4222=y CONFIG_SENSORS_LTC4245=y CONFIG_SENSORS_LTC4260=y CONFIG_SENSORS_LTC4261=m CONFIG_SENSORS_MAX127=m CONFIG_SENSORS_MAX16065=m CONFIG_SENSORS_MAX1619=m CONFIG_SENSORS_MAX1668=y CONFIG_SENSORS_MAX197=y CONFIG_SENSORS_MAX31730=y # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set CONFIG_SENSORS_MAX6642=y # CONFIG_SENSORS_MAX6650 is not set CONFIG_SENSORS_MAX6697=y CONFIG_SENSORS_MAX31790=y CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set CONFIG_SENSORS_TC654=y CONFIG_SENSORS_TPS23861=m # CONFIG_SENSORS_MENF21BMC_HWMON is not set CONFIG_SENSORS_MR75203=m CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM73=y # CONFIG_SENSORS_LM75 is not set CONFIG_SENSORS_LM77=y CONFIG_SENSORS_LM78=m # CONFIG_SENSORS_LM80 is not set # CONFIG_SENSORS_LM83 is not set # CONFIG_SENSORS_LM85 is not set CONFIG_SENSORS_LM87=y # CONFIG_SENSORS_LM90 is not set CONFIG_SENSORS_LM92=y CONFIG_SENSORS_LM93=m CONFIG_SENSORS_LM95234=m CONFIG_SENSORS_LM95241=m CONFIG_SENSORS_LM95245=m CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=y CONFIG_SENSORS_NCT6683=m CONFIG_SENSORS_NCT6775_CORE=y CONFIG_SENSORS_NCT6775=m CONFIG_SENSORS_NCT6775_I2C=y CONFIG_SENSORS_NCT7802=y CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=y # CONFIG_SENSORS_NSA320 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set CONFIG_SENSORS_PECI_CPUTEMP=m CONFIG_SENSORS_PECI_DIMMTEMP=m CONFIG_SENSORS_PECI=m CONFIG_PMBUS=m CONFIG_SENSORS_PMBUS=m CONFIG_SENSORS_ADM1266=m CONFIG_SENSORS_ADM1275=m # CONFIG_SENSORS_BEL_PFE is not set CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m # CONFIG_SENSORS_FSP_3Y is not set CONFIG_SENSORS_IBM_CFFPS=m # CONFIG_SENSORS_DPS920AB is not set CONFIG_SENSORS_INSPUR_IPSPS=m # CONFIG_SENSORS_IR35221 is not set CONFIG_SENSORS_IR36021=m # CONFIG_SENSORS_IR38064 is not set CONFIG_SENSORS_IRPS5401=m # CONFIG_SENSORS_ISL68137 is not set CONFIG_SENSORS_LM25066=m CONFIG_SENSORS_LM25066_REGULATOR=y # CONFIG_SENSORS_LT7182S is not set CONFIG_SENSORS_LTC2978=m # CONFIG_SENSORS_LTC2978_REGULATOR is not set CONFIG_SENSORS_LTC3815=m CONFIG_SENSORS_MAX15301=m # CONFIG_SENSORS_MAX16064 is not set CONFIG_SENSORS_MAX16601=m CONFIG_SENSORS_MAX20730=m # CONFIG_SENSORS_MAX20751 is not set # CONFIG_SENSORS_MAX31785 is not set CONFIG_SENSORS_MAX34440=m CONFIG_SENSORS_MAX8688=m # CONFIG_SENSORS_MP2888 is not set CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP5023=m CONFIG_SENSORS_PIM4328=m CONFIG_SENSORS_PLI1209BC=m # CONFIG_SENSORS_PLI1209BC_REGULATOR is not set CONFIG_SENSORS_PM6764TR=m CONFIG_SENSORS_PXE1610=m CONFIG_SENSORS_Q54SJ108A2=m CONFIG_SENSORS_STPDDC60=m CONFIG_SENSORS_TPS40422=m CONFIG_SENSORS_TPS53679=m CONFIG_SENSORS_UCD9000=m CONFIG_SENSORS_UCD9200=m CONFIG_SENSORS_XDPE152=m CONFIG_SENSORS_XDPE122=m CONFIG_SENSORS_XDPE122_REGULATOR=y CONFIG_SENSORS_ZL6100=m # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_RASPBERRYPI_HWMON is not set # CONFIG_SENSORS_SL28CPLD is not set CONFIG_SENSORS_SBTSI=m # CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set CONFIG_SENSORS_SHT21=m # CONFIG_SENSORS_SHT3x is not set CONFIG_SENSORS_SHT4x=m # CONFIG_SENSORS_SHTC1 is not set # CONFIG_SENSORS_SY7636A is not set CONFIG_SENSORS_DME1737=y CONFIG_SENSORS_EMC1403=y CONFIG_SENSORS_EMC2103=m # CONFIG_SENSORS_EMC6W201 is not set CONFIG_SENSORS_SMSC47M1=y CONFIG_SENSORS_SMSC47M192=y CONFIG_SENSORS_SMSC47B397=y CONFIG_SENSORS_SCH56XX_COMMON=m CONFIG_SENSORS_SCH5627=m # CONFIG_SENSORS_SCH5636 is not set CONFIG_SENSORS_STTS751=y CONFIG_SENSORS_SMM665=m CONFIG_SENSORS_ADC128D818=m # CONFIG_SENSORS_ADS7828 is not set CONFIG_SENSORS_AMC6821=y CONFIG_SENSORS_INA209=m # CONFIG_SENSORS_INA2XX is not set CONFIG_SENSORS_INA238=y CONFIG_SENSORS_INA3221=y # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set CONFIG_SENSORS_TMP102=m CONFIG_SENSORS_TMP103=y # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set CONFIG_SENSORS_TMP421=m # CONFIG_SENSORS_TMP464 is not set # CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VT1211 is not set CONFIG_SENSORS_W83773G=y CONFIG_SENSORS_W83781D=m CONFIG_SENSORS_W83791D=y # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set CONFIG_SENSORS_W83795=m # CONFIG_SENSORS_W83795_FANCTRL is not set # CONFIG_SENSORS_W83L785TS is not set CONFIG_SENSORS_W83L786NG=m CONFIG_SENSORS_W83627HF=m CONFIG_SENSORS_W83627EHF=m CONFIG_SENSORS_WM8350=y CONFIG_THERMAL=y # CONFIG_THERMAL_STATISTICS is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 # CONFIG_THERMAL_HWMON is not set # CONFIG_THERMAL_OF is not set # CONFIG_THERMAL_WRITABLE_TRIPS is not set CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set # CONFIG_THERMAL_GOV_USER_SPACE is not set # CONFIG_DEVFREQ_THERMAL is not set # CONFIG_THERMAL_EMULATION is not set CONFIG_THERMAL_MMIO=m # CONFIG_HISI_THERMAL is not set CONFIG_IMX_THERMAL=y # CONFIG_IMX8MM_THERMAL is not set CONFIG_K3_THERMAL=y CONFIG_MAX77620_THERMAL=y CONFIG_SPEAR_THERMAL=y # CONFIG_SUN8I_THERMAL is not set # CONFIG_ROCKCHIP_THERMAL is not set # CONFIG_RCAR_THERMAL is not set # CONFIG_RCAR_GEN3_THERMAL is not set # CONFIG_RZG2L_THERMAL is not set CONFIG_KIRKWOOD_THERMAL=m # CONFIG_DOVE_THERMAL is not set CONFIG_ARMADA_THERMAL=m CONFIG_DA9062_THERMAL=y # CONFIG_MTK_THERMAL is not set # # Intel thermal drivers # # # ACPI INT340X thermal drivers # # end of ACPI INT340X thermal drivers # end of Intel thermal drivers # # Broadcom thermal drivers # # CONFIG_BRCMSTB_THERMAL is not set CONFIG_BCM_NS_THERMAL=m # CONFIG_BCM_SR_THERMAL is not set # end of Broadcom thermal drivers # # Texas Instruments thermal drivers # CONFIG_TI_SOC_THERMAL=m CONFIG_TI_THERMAL=y # CONFIG_OMAP3_THERMAL is not set # CONFIG_OMAP4_THERMAL is not set CONFIG_OMAP5_THERMAL=y CONFIG_DRA752_THERMAL=y # end of Texas Instruments thermal drivers # # Samsung thermal drivers # # end of Samsung thermal drivers # # NVIDIA Tegra thermal drivers # # CONFIG_TEGRA_SOCTHERM is not set CONFIG_TEGRA_BPMP_THERMAL=m CONFIG_TEGRA30_TSENSOR=y # end of NVIDIA Tegra thermal drivers # # Qualcomm thermal drivers # CONFIG_QCOM_TSENS=y # end of Qualcomm thermal drivers CONFIG_SPRD_THERMAL=y CONFIG_KHADAS_MCU_FAN_THERMAL=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set # CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is not set CONFIG_WATCHDOG_OPEN_TIMEOUT=0 CONFIG_WATCHDOG_SYSFS=y CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y # # Watchdog Pretimeout Governors # # CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set # # Watchdog Device Drivers # CONFIG_SOFT_WATCHDOG=m CONFIG_BD957XMUF_WATCHDOG=m CONFIG_DA9052_WATCHDOG=y CONFIG_DA9055_WATCHDOG=y CONFIG_DA9063_WATCHDOG=y CONFIG_DA9062_WATCHDOG=y # CONFIG_GPIO_WATCHDOG is not set CONFIG_MENF21BMC_WATCHDOG=m # CONFIG_MENZ069_WATCHDOG is not set CONFIG_WM8350_WATCHDOG=y CONFIG_XILINX_WATCHDOG=y CONFIG_ZIIRAVE_WATCHDOG=m CONFIG_RAVE_SP_WATCHDOG=m CONFIG_MLX_WDT=m CONFIG_SL28CPLD_WATCHDOG=y CONFIG_ARM_SP805_WATCHDOG=m CONFIG_ARMADA_37XX_WATCHDOG=y CONFIG_ASM9260_WATCHDOG=m CONFIG_AT91RM9200_WATCHDOG=m # CONFIG_AT91SAM9X_WATCHDOG is not set CONFIG_SAMA5D4_WATCHDOG=y # CONFIG_CADENCE_WATCHDOG is not set CONFIG_977_WATCHDOG=m CONFIG_FTWDT010_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y CONFIG_DW_WATCHDOG=m CONFIG_EP93XX_WATCHDOG=m # CONFIG_OMAP_WATCHDOG is not set CONFIG_PNX4008_WATCHDOG=y CONFIG_DAVINCI_WATCHDOG=y CONFIG_K3_RTI_WATCHDOG=m CONFIG_ORION_WATCHDOG=m CONFIG_RN5T618_WATCHDOG=m CONFIG_SUNXI_WATCHDOG=m # CONFIG_NPCM7XX_WATCHDOG is not set CONFIG_STMP3XXX_RTC_WATCHDOG=y # CONFIG_TS4800_WATCHDOG is not set CONFIG_TS72XX_WATCHDOG=m CONFIG_MAX63XX_WATCHDOG=y CONFIG_MAX77620_WATCHDOG=y CONFIG_IMX2_WDT=m # CONFIG_IMX7ULP_WDT is not set # CONFIG_RETU_WATCHDOG is not set CONFIG_MOXART_WDT=y # CONFIG_ST_LPC_WATCHDOG is not set # CONFIG_TEGRA_WATCHDOG is not set CONFIG_QCOM_WDT=y # CONFIG_MESON_GXBB_WATCHDOG is not set # CONFIG_MESON_WATCHDOG is not set CONFIG_MEDIATEK_WATCHDOG=m # CONFIG_DIGICOLOR_WATCHDOG is not set CONFIG_LPC18XX_WATCHDOG=y # CONFIG_RENESAS_WDT is not set # CONFIG_RENESAS_RZAWDT is not set CONFIG_RENESAS_RZN1WDT=m CONFIG_RENESAS_RZG2LWDT=y CONFIG_ASPEED_WATCHDOG=y # CONFIG_UNIPHIER_WATCHDOG is not set CONFIG_RTD119X_WATCHDOG=y # CONFIG_REALTEK_OTTO_WDT is not set CONFIG_SPRD_WATCHDOG=y CONFIG_VISCONTI_WATCHDOG=m # CONFIG_MSC313E_WATCHDOG is not set CONFIG_APPLE_WATCHDOG=m CONFIG_SUNPLUS_WATCHDOG=m CONFIG_SC520_WDT=y # CONFIG_ATH79_WDT is not set CONFIG_BCM47XX_WDT=y CONFIG_BCM2835_WDT=m # CONFIG_BCM_KONA_WDT is not set CONFIG_BCM7038_WDT=y # CONFIG_IMGPDC_WDT is not set # CONFIG_MPC5200_WDT is not set CONFIG_MEN_A21_WDT=m CONFIG_UML_WATCHDOG=m CONFIG_SSB_POSSIBLE=y CONFIG_SSB=y CONFIG_SSB_SPROM=y CONFIG_SSB_PCMCIAHOST_POSSIBLE=y CONFIG_SSB_PCMCIAHOST=y CONFIG_SSB_DRIVER_GPIO=y CONFIG_BCMA_POSSIBLE=y CONFIG_BCMA=y # CONFIG_BCMA_HOST_SOC is not set CONFIG_BCMA_DRIVER_MIPS=y CONFIG_BCMA_PFLASH=y CONFIG_BCMA_NFLASH=y CONFIG_BCMA_DRIVER_GMAC_CMN=y CONFIG_BCMA_DRIVER_GPIO=y # CONFIG_BCMA_DEBUG is not set # # Multifunction device drivers # CONFIG_MFD_CORE=y CONFIG_MFD_ACT8945A=m CONFIG_MFD_SUN4I_GPADC=m # CONFIG_MFD_AS3711 is not set CONFIG_MFD_AS3722=y # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_AT91_USART is not set CONFIG_MFD_ATMEL_FLEXCOM=y CONFIG_MFD_ATMEL_HLCDC=m CONFIG_MFD_BCM590XX=m # CONFIG_MFD_BD9571MWV is not set CONFIG_MFD_AXP20X=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_CROS_EC_DEV=m CONFIG_MFD_MADERA=m # CONFIG_MFD_MADERA_I2C is not set # CONFIG_MFD_CS47L15 is not set # CONFIG_MFD_CS47L35 is not set # CONFIG_MFD_CS47L85 is not set CONFIG_MFD_CS47L90=y CONFIG_MFD_CS47L92=y # CONFIG_MFD_ASIC3 is not set # CONFIG_PMIC_DA903X is not set CONFIG_PMIC_DA9052=y CONFIG_MFD_DA9052_I2C=y CONFIG_MFD_DA9055=y CONFIG_MFD_DA9062=m CONFIG_MFD_DA9063=m CONFIG_MFD_DA9150=y CONFIG_MFD_ENE_KB3930=y CONFIG_MFD_EXYNOS_LPASS=m # CONFIG_MFD_GATEWORKS_GSC is not set CONFIG_MFD_MC13XXX=y CONFIG_MFD_MC13XXX_I2C=y CONFIG_MFD_MP2629=y CONFIG_MFD_MXS_LRADC=y # CONFIG_MFD_MX25_TSADC is not set CONFIG_MFD_HI6421_PMIC=y CONFIG_MFD_HI6421_SPMI=y # CONFIG_MFD_HI655X_PMIC is not set # CONFIG_HTC_PASIC3 is not set CONFIG_HTC_I2CPLD=y CONFIG_MFD_IQS62X=m # CONFIG_MFD_KEMPLD is not set CONFIG_MFD_88PM800=y CONFIG_MFD_88PM805=y # CONFIG_MFD_88PM860X is not set CONFIG_MFD_MAX14577=m CONFIG_MFD_MAX77620=y CONFIG_MFD_MAX77650=y # CONFIG_MFD_MAX77686 is not set CONFIG_MFD_MAX77693=m CONFIG_MFD_MAX77714=m CONFIG_MFD_MAX77843=y CONFIG_MFD_MAX8907=m CONFIG_MFD_MAX8925=y CONFIG_MFD_MAX8997=y CONFIG_MFD_MAX8998=y CONFIG_MFD_MT6360=m # CONFIG_MFD_MT6397 is not set CONFIG_MFD_MENF21BMC=y CONFIG_MFD_NTXEC=y CONFIG_MFD_RETU=y # CONFIG_MFD_PCF50633 is not set CONFIG_MFD_PM8XXX=m # CONFIG_MFD_SPMI_PMIC is not set # CONFIG_MFD_RT4831 is not set CONFIG_MFD_RT5033=m CONFIG_MFD_RC5T583=y CONFIG_MFD_RK808=y CONFIG_MFD_RN5T618=y CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set CONFIG_MFD_SIMPLE_MFD_I2C=y CONFIG_MFD_SL28CPLD=y # CONFIG_MFD_SM501 is not set CONFIG_MFD_SKY81452=m # CONFIG_ABX500_CORE is not set CONFIG_MFD_STMPE=y # # STMicroelectronics STMPE Interface Drivers # CONFIG_STMPE_I2C=y # end of STMicroelectronics STMPE Interface Drivers # CONFIG_MFD_SUN6I_PRCM is not set CONFIG_MFD_SYSCON=y CONFIG_MFD_TI_AM335X_TSCADC=m # CONFIG_MFD_LP3943 is not set # CONFIG_MFD_LP8788 is not set # CONFIG_MFD_TI_LMU is not set CONFIG_MFD_PALMAS=y # CONFIG_TPS6105X is not set # CONFIG_TPS65010 is not set # CONFIG_TPS6507X is not set # CONFIG_MFD_TPS65086 is not set CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS65217=m # CONFIG_MFD_TI_LP873X is not set CONFIG_MFD_TI_LP87565=m # CONFIG_MFD_TPS65218 is not set # CONFIG_MFD_TPS6586X is not set # CONFIG_MFD_TPS65910 is not set CONFIG_MFD_TPS65912=y CONFIG_MFD_TPS65912_I2C=y # CONFIG_TWL4030_CORE is not set CONFIG_TWL6040_CORE=y # CONFIG_MFD_WL1273_CORE is not set CONFIG_MFD_LM3533=y # CONFIG_MFD_TC3589X is not set CONFIG_MFD_TMIO=y # CONFIG_MFD_T7L66XB is not set CONFIG_MFD_TC6387XB=y # CONFIG_MFD_TC6393XB is not set CONFIG_MFD_TQMX86=y CONFIG_MFD_LOCHNAGAR=y # CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X_I2C is not set CONFIG_MFD_WM8350=y CONFIG_MFD_WM8350_I2C=y CONFIG_MFD_WM8994=m # CONFIG_MFD_STW481X is not set CONFIG_MFD_ROHM_BD718XX=m CONFIG_MFD_ROHM_BD71828=m CONFIG_MFD_ROHM_BD957XMUF=m CONFIG_MFD_STM32_LPTIMER=m # CONFIG_MFD_STM32_TIMERS is not set # CONFIG_MFD_STPMIC1 is not set CONFIG_MFD_STMFX=y CONFIG_MFD_ATC260X=m CONFIG_MFD_ATC260X_I2C=m CONFIG_MFD_KHADAS_MCU=y # CONFIG_MFD_ACER_A500_EC is not set CONFIG_MFD_QCOM_PM8008=y CONFIG_RAVE_SP_CORE=m # CONFIG_MFD_RSMU_I2C is not set # end of Multifunction device drivers CONFIG_REGULATOR=y CONFIG_REGULATOR_DEBUG=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=m CONFIG_REGULATOR_USERSPACE_CONSUMER=y CONFIG_REGULATOR_88PG86X=y CONFIG_REGULATOR_88PM800=y CONFIG_REGULATOR_ACT8865=y # CONFIG_REGULATOR_ACT8945A is not set CONFIG_REGULATOR_AD5398=y # CONFIG_REGULATOR_ANATOP is not set # CONFIG_REGULATOR_ARM_SCMI is not set # CONFIG_REGULATOR_AS3722 is not set # CONFIG_REGULATOR_ATC260X is not set CONFIG_REGULATOR_AXP20X=m CONFIG_REGULATOR_BCM590XX=m CONFIG_REGULATOR_BD71815=m # CONFIG_REGULATOR_BD71828 is not set CONFIG_REGULATOR_BD718XX=m CONFIG_REGULATOR_BD957XMUF=m CONFIG_REGULATOR_CROS_EC=m CONFIG_REGULATOR_DA9052=m # CONFIG_REGULATOR_DA9055 is not set # CONFIG_REGULATOR_DA9062 is not set # CONFIG_REGULATOR_DA9063 is not set CONFIG_REGULATOR_DA9121=y CONFIG_REGULATOR_DA9210=m # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set CONFIG_REGULATOR_FAN53880=y # CONFIG_REGULATOR_GPIO is not set # CONFIG_REGULATOR_HI6421 is not set CONFIG_REGULATOR_HI6421V530=m CONFIG_REGULATOR_HI6421V600=m CONFIG_REGULATOR_ISL9305=m CONFIG_REGULATOR_ISL6271A=y CONFIG_REGULATOR_LOCHNAGAR=m CONFIG_REGULATOR_LP3971=y CONFIG_REGULATOR_LP3972=m CONFIG_REGULATOR_LP872X=m CONFIG_REGULATOR_LP8755=m # CONFIG_REGULATOR_LP87565 is not set # CONFIG_REGULATOR_LTC3589 is not set CONFIG_REGULATOR_LTC3676=y CONFIG_REGULATOR_MAX14577=m CONFIG_REGULATOR_MAX1586=m CONFIG_REGULATOR_MAX77620=m CONFIG_REGULATOR_MAX77650=m CONFIG_REGULATOR_MAX8649=m CONFIG_REGULATOR_MAX8660=y CONFIG_REGULATOR_MAX8893=m CONFIG_REGULATOR_MAX8907=m CONFIG_REGULATOR_MAX8925=m CONFIG_REGULATOR_MAX8952=m # CONFIG_REGULATOR_MAX8997 is not set CONFIG_REGULATOR_MAX8998=m CONFIG_REGULATOR_MAX20086=m CONFIG_REGULATOR_MAX77686=y # CONFIG_REGULATOR_MAX77693 is not set CONFIG_REGULATOR_MAX77802=y # CONFIG_REGULATOR_MAX77826 is not set CONFIG_REGULATOR_MC13XXX_CORE=y CONFIG_REGULATOR_MC13783=y # CONFIG_REGULATOR_MC13892 is not set CONFIG_REGULATOR_MCP16502=y # CONFIG_REGULATOR_MP5416 is not set CONFIG_REGULATOR_MP8859=m CONFIG_REGULATOR_MP886X=y CONFIG_REGULATOR_MPQ7920=m # CONFIG_REGULATOR_MT6311 is not set CONFIG_REGULATOR_MT6315=y CONFIG_REGULATOR_MT6360=m CONFIG_REGULATOR_MT6380=m CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_PBIAS=m CONFIG_REGULATOR_PCA9450=y CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=y CONFIG_REGULATOR_PV88060=y # CONFIG_REGULATOR_PV88080 is not set CONFIG_REGULATOR_PV88090=m CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_QCOM_RPMH is not set CONFIG_REGULATOR_QCOM_SMD_RPM=y # CONFIG_REGULATOR_QCOM_SPMI is not set CONFIG_REGULATOR_QCOM_USB_VBUS=y CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y # CONFIG_REGULATOR_RC5T583 is not set # CONFIG_REGULATOR_RK808 is not set CONFIG_REGULATOR_RN5T618=y CONFIG_REGULATOR_ROHM=m CONFIG_REGULATOR_RT4801=y CONFIG_REGULATOR_RT5033=m CONFIG_REGULATOR_RT5190A=y # CONFIG_REGULATOR_RT5759 is not set CONFIG_REGULATOR_RT6160=y CONFIG_REGULATOR_RT6245=y CONFIG_REGULATOR_RTQ2134=m # CONFIG_REGULATOR_RTMV20 is not set CONFIG_REGULATOR_RTQ6752=y # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y # CONFIG_REGULATOR_S5M8767 is not set CONFIG_REGULATOR_SC2731=y CONFIG_REGULATOR_SKY81452=m # CONFIG_REGULATOR_SLG51000 is not set CONFIG_REGULATOR_STM32_BOOSTER=y CONFIG_REGULATOR_STM32_VREFBUF=y CONFIG_REGULATOR_STM32_PWR=y CONFIG_REGULATOR_TI_ABB=y # CONFIG_REGULATOR_STW481X_VMMC is not set # CONFIG_REGULATOR_SY7636A is not set CONFIG_REGULATOR_SY8106A=y CONFIG_REGULATOR_SY8824X=m CONFIG_REGULATOR_SY8827N=m # CONFIG_REGULATOR_TPS51632 is not set CONFIG_REGULATOR_TPS62360=y CONFIG_REGULATOR_TPS6286X=y # CONFIG_REGULATOR_TPS65023 is not set CONFIG_REGULATOR_TPS6507X=m CONFIG_REGULATOR_TPS65090=y # CONFIG_REGULATOR_TPS65132 is not set CONFIG_REGULATOR_TPS65217=m # CONFIG_REGULATOR_TPS65912 is not set CONFIG_REGULATOR_TPS68470=y # CONFIG_REGULATOR_UNIPHIER is not set # CONFIG_REGULATOR_VCTRL is not set # CONFIG_REGULATOR_WM8350 is not set # CONFIG_REGULATOR_WM8994 is not set CONFIG_REGULATOR_QCOM_LABIBB=y # CONFIG_RC_CORE is not set CONFIG_CEC_CORE=y CONFIG_CEC_PIN=y # # CEC support # # CONFIG_CEC_PIN_ERROR_INJ is not set # CONFIG_MEDIA_CEC_SUPPORT is not set # end of CEC support CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_SUPPORT_FILTER=y # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set # # Media device types # # CONFIG_MEDIA_CAMERA_SUPPORT is not set CONFIG_MEDIA_ANALOG_TV_SUPPORT=y # CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set CONFIG_MEDIA_RADIO_SUPPORT=y CONFIG_MEDIA_SDR_SUPPORT=y CONFIG_MEDIA_PLATFORM_SUPPORT=y # CONFIG_MEDIA_TEST_SUPPORT is not set # end of Media device types CONFIG_VIDEO_DEV=y CONFIG_MEDIA_CONTROLLER=y # # Video4Linux options # CONFIG_VIDEO_V4L2_I2C=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_V4L2_JPEG_HELPER=m CONFIG_V4L2_H264=m CONFIG_V4L2_MEM2MEM_DEV=y # CONFIG_V4L2_FLASH_LED_CLASS is not set CONFIG_V4L2_FWNODE=y CONFIG_V4L2_ASYNC=y # end of Video4Linux options # # Media controller options # CONFIG_MEDIA_CONTROLLER_REQUEST_API=y # end of Media controller options # # Media drivers # # # Drivers filtered as selected at 'Filter media drivers' # # # Media drivers # # CONFIG_RADIO_ADAPTERS is not set CONFIG_MEDIA_PLATFORM_DRIVERS=y # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_SDR_PLATFORM_DRIVERS is not set CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y # # Allegro DVT media platform drivers # CONFIG_VIDEO_ALLEGRO_DVT=y # # Amlogic media platform drivers # CONFIG_VIDEO_MESON_GE2D=y # # Amphion drivers # CONFIG_VIDEO_AMPHION_VPU=y # # Aspeed media platform drivers # # # Atmel media platform drivers # # # Cadence media platform drivers # CONFIG_VIDEO_CADENCE_CSI2RX=y CONFIG_VIDEO_CADENCE_CSI2TX=m # # Chips&Media media platform drivers # CONFIG_VIDEO_CODA=m CONFIG_VIDEO_IMX_VDOA=m # # Intel media platform drivers # # # Marvell media platform drivers # # # Mediatek media platform drivers # # CONFIG_VIDEO_MEDIATEK_JPEG is not set CONFIG_VIDEO_MEDIATEK_MDP=y # CONFIG_VIDEO_MEDIATEK_VCODEC is not set CONFIG_VIDEO_MEDIATEK_VPU=y # # NVidia media platform drivers # CONFIG_VIDEO_TEGRA_VDE=m # # NXP media platform drivers # CONFIG_VIDEO_IMX_MIPI_CSIS=m CONFIG_VIDEO_IMX_PXP=m # CONFIG_VIDEO_MX2_EMMAPRP is not set CONFIG_VIDEO_IMX8_JPEG=m # # Qualcomm media platform drivers # # # Renesas media platform drivers # # CONFIG_VIDEO_RENESAS_FCP is not set CONFIG_VIDEO_RENESAS_FDP1=m CONFIG_VIDEO_RENESAS_JPU=y # CONFIG_VIDEO_RENESAS_VSP1 is not set # # Rockchip media platform drivers # CONFIG_VIDEO_ROCKCHIP_RGA=y # # Samsung media platform drivers # CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m # CONFIG_VIDEO_SAMSUNG_S5P_G2D is not set # CONFIG_VIDEO_SAMSUNG_S5P_JPEG is not set CONFIG_VIDEO_SAMSUNG_S5P_MFC=y # # STMicroelectronics media platform drivers # CONFIG_VIDEO_STI_BDISP=m CONFIG_VIDEO_STI_DELTA=y CONFIG_VIDEO_STI_DELTA_MJPEG=y CONFIG_VIDEO_STI_DELTA_DRIVER=y CONFIG_VIDEO_STI_HVA=y # CONFIG_VIDEO_STI_HVA_DEBUGFS is not set # CONFIG_VIDEO_STM32_DMA2D is not set # # Sunxi media platform drivers # CONFIG_VIDEO_SUN8I_DEINTERLACE=y # CONFIG_VIDEO_SUN8I_ROTATE is not set # # Texas Instruments drivers # # CONFIG_VIDEO_TI_VPE is not set # # VIA media platform drivers # # # Xilinx media platform drivers # CONFIG_VIDEOBUF2_CORE=y CONFIG_VIDEOBUF2_V4L2=y CONFIG_VIDEOBUF2_MEMOPS=y CONFIG_VIDEOBUF2_DMA_CONTIG=y CONFIG_VIDEOBUF2_VMALLOC=y CONFIG_VIDEOBUF2_DMA_SG=y # end of Media drivers # # Media ancillary drivers # CONFIG_MEDIA_ATTACH=y # # Audio decoders, processors and mixers # CONFIG_VIDEO_CS3308=m # CONFIG_VIDEO_CS5345 is not set # CONFIG_VIDEO_CS53L32A is not set # CONFIG_VIDEO_MSP3400 is not set CONFIG_VIDEO_SONY_BTF_MPX=y # CONFIG_VIDEO_TDA7432 is not set # CONFIG_VIDEO_TDA9840 is not set CONFIG_VIDEO_TEA6415C=y CONFIG_VIDEO_TEA6420=m # CONFIG_VIDEO_TLV320AIC23B is not set CONFIG_VIDEO_TVAUDIO=m CONFIG_VIDEO_UDA1342=y CONFIG_VIDEO_VP27SMPX=m CONFIG_VIDEO_WM8739=y CONFIG_VIDEO_WM8775=y # end of Audio decoders, processors and mixers # # RDS decoders # CONFIG_VIDEO_SAA6588=y # end of RDS decoders # # Video decoders # CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_ADV7183=m CONFIG_VIDEO_ADV748X=y CONFIG_VIDEO_ADV7604=y # CONFIG_VIDEO_ADV7604_CEC is not set # CONFIG_VIDEO_ADV7842 is not set CONFIG_VIDEO_BT819=m CONFIG_VIDEO_BT856=m # CONFIG_VIDEO_BT866 is not set CONFIG_VIDEO_ISL7998X=y # CONFIG_VIDEO_KS0127 is not set # CONFIG_VIDEO_ML86V7667 is not set CONFIG_VIDEO_SAA7110=m # CONFIG_VIDEO_SAA711X is not set # CONFIG_VIDEO_TC358743 is not set # CONFIG_VIDEO_TVP514X is not set CONFIG_VIDEO_TVP5150=y CONFIG_VIDEO_TVP7002=y CONFIG_VIDEO_TW2804=m CONFIG_VIDEO_TW9903=m # CONFIG_VIDEO_TW9906 is not set CONFIG_VIDEO_TW9910=y CONFIG_VIDEO_VPX3220=m # # Video and audio decoders # CONFIG_VIDEO_SAA717X=y CONFIG_VIDEO_CX25840=y # end of Video decoders # # Video encoders # CONFIG_VIDEO_AD9389B=y # CONFIG_VIDEO_ADV7170 is not set # CONFIG_VIDEO_ADV7175 is not set # CONFIG_VIDEO_ADV7343 is not set CONFIG_VIDEO_ADV7393=m CONFIG_VIDEO_ADV7511=m CONFIG_VIDEO_ADV7511_CEC=y CONFIG_VIDEO_AK881X=y CONFIG_VIDEO_SAA7127=y # CONFIG_VIDEO_SAA7185 is not set CONFIG_VIDEO_THS8200=y # end of Video encoders # # Video improvement chips # # CONFIG_VIDEO_UPD64031A is not set CONFIG_VIDEO_UPD64083=y # end of Video improvement chips # # Audio/Video compression chips # CONFIG_VIDEO_SAA6752HS=m # end of Audio/Video compression chips # # SDR tuner chips # CONFIG_SDR_MAX2175=m # end of SDR tuner chips # # Miscellaneous helper chips # CONFIG_VIDEO_I2C=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_ST_MIPID02=m CONFIG_VIDEO_THS7303=y # end of Miscellaneous helper chips CONFIG_MEDIA_TUNER=y # # Customize TV tuners # CONFIG_MEDIA_TUNER_E4000=m # CONFIG_MEDIA_TUNER_FC0011 is not set CONFIG_MEDIA_TUNER_FC0012=y CONFIG_MEDIA_TUNER_FC0013=y # CONFIG_MEDIA_TUNER_FC2580 is not set CONFIG_MEDIA_TUNER_IT913X=m # CONFIG_MEDIA_TUNER_M88RS6000T is not set CONFIG_MEDIA_TUNER_MAX2165=y CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_MEDIA_TUNER_MT2060=m CONFIG_MEDIA_TUNER_MT2063=m CONFIG_MEDIA_TUNER_MT20XX=y # CONFIG_MEDIA_TUNER_MT2131 is not set # CONFIG_MEDIA_TUNER_MT2266 is not set # CONFIG_MEDIA_TUNER_MXL301RF is not set # CONFIG_MEDIA_TUNER_MXL5005S is not set CONFIG_MEDIA_TUNER_MXL5007T=m CONFIG_MEDIA_TUNER_QM1D1B0004=y CONFIG_MEDIA_TUNER_QM1D1C0042=m CONFIG_MEDIA_TUNER_QT1010=y CONFIG_MEDIA_TUNER_R820T=y # CONFIG_MEDIA_TUNER_SI2157 is not set CONFIG_MEDIA_TUNER_SIMPLE=m CONFIG_MEDIA_TUNER_TDA18212=y CONFIG_MEDIA_TUNER_TDA18218=y CONFIG_MEDIA_TUNER_TDA18250=y CONFIG_MEDIA_TUNER_TDA18271=m CONFIG_MEDIA_TUNER_TDA827X=m CONFIG_MEDIA_TUNER_TDA8290=m CONFIG_MEDIA_TUNER_TDA9887=m CONFIG_MEDIA_TUNER_TEA5761=m CONFIG_MEDIA_TUNER_TEA5767=y CONFIG_MEDIA_TUNER_TUA9001=y CONFIG_MEDIA_TUNER_XC2028=m CONFIG_MEDIA_TUNER_XC4000=m CONFIG_MEDIA_TUNER_XC5000=y # end of Customize TV tuners # end of Media ancillary drivers # # Graphics support # CONFIG_APERTURE_HELPERS=y CONFIG_TEGRA_HOST1X_CONTEXT_BUS=y CONFIG_TEGRA_HOST1X=y # CONFIG_TEGRA_HOST1X_FIREWALL is not set # CONFIG_IMX_IPUV3_CORE is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_DEBUG_MM=y CONFIG_DRM_DEBUG_SELFTEST=y CONFIG_DRM_KMS_HELPER=y # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DP_AUX_BUS=y CONFIG_DRM_DISPLAY_HELPER=y CONFIG_DRM_DISPLAY_DP_HELPER=y CONFIG_DRM_DISPLAY_HDCP_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y CONFIG_DRM_DP_AUX_CHARDEV=y # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_BUDDY=y CONFIG_DRM_GEM_CMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_SCHED=y # # I2C encoder or helper chips # # CONFIG_DRM_I2C_CH7006 is not set CONFIG_DRM_I2C_SIL164=y # CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_I2C_NXP_TDA9950 is not set # end of I2C encoder or helper chips # # ARM devices # # CONFIG_DRM_HDLCD is not set # CONFIG_DRM_MALI_DISPLAY is not set CONFIG_DRM_KOMEDA=m # end of ARM devices CONFIG_DRM_KMB_DISPLAY=y CONFIG_DRM_VGEM=m CONFIG_DRM_VKMS=m CONFIG_DRM_EXYNOS=y # # CRTCs # # CONFIG_DRM_EXYNOS_FIMD is not set # CONFIG_DRM_EXYNOS5433_DECON is not set # CONFIG_DRM_EXYNOS7_DECON is not set # CONFIG_DRM_EXYNOS_MIXER is not set # CONFIG_DRM_EXYNOS_VIDI is not set # # Encoders and Bridges # # # Sub-drivers # # CONFIG_DRM_EXYNOS_G2D is not set CONFIG_DRM_EXYNOS_IPP=y CONFIG_DRM_EXYNOS_FIMC=y # CONFIG_DRM_EXYNOS_ROTATOR is not set CONFIG_DRM_EXYNOS_SCALER=y # CONFIG_DRM_EXYNOS_GSC is not set CONFIG_DRM_ROCKCHIP=y # CONFIG_ROCKCHIP_VOP is not set CONFIG_ROCKCHIP_VOP2=y # CONFIG_ROCKCHIP_CDN_DP is not set # CONFIG_ROCKCHIP_DW_HDMI is not set # CONFIG_ROCKCHIP_DW_MIPI_DSI is not set # CONFIG_ROCKCHIP_INNO_HDMI is not set # CONFIG_ROCKCHIP_LVDS is not set CONFIG_ROCKCHIP_RGB=y # CONFIG_ROCKCHIP_RK3066_HDMI is not set CONFIG_DRM_ARMADA=m # CONFIG_DRM_ATMEL_HLCDC is not set # CONFIG_DRM_RCAR_DU is not set # CONFIG_DRM_RCAR_DW_HDMI is not set # CONFIG_DRM_RCAR_USE_LVDS is not set CONFIG_DRM_RCAR_MIPI_DSI=m CONFIG_DRM_SHMOBILE=m CONFIG_DRM_SUN4I=m CONFIG_DRM_SUN4I_HDMI=m CONFIG_DRM_SUN4I_HDMI_CEC=y CONFIG_DRM_SUN4I_BACKEND=m CONFIG_DRM_SUN6I_DSI=m CONFIG_DRM_SUN8I_DW_HDMI=m CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_SUN8I_TCON_TOP=m CONFIG_DRM_OMAP=y # CONFIG_OMAP2_DSS_DEBUG is not set # CONFIG_OMAP2_DSS_DEBUGFS is not set CONFIG_OMAP2_DSS_DPI=y CONFIG_OMAP2_DSS_VENC=y CONFIG_OMAP2_DSS_HDMI_COMMON=y CONFIG_OMAP4_DSS_HDMI=y CONFIG_OMAP4_DSS_HDMI_CEC=y # CONFIG_OMAP5_DSS_HDMI is not set # CONFIG_OMAP2_DSS_SDI is not set CONFIG_OMAP2_DSS_DSI=y CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y CONFIG_DRM_TILCDC=m CONFIG_DRM_VIRTIO_GPU=y CONFIG_DRM_MSM=m CONFIG_DRM_MSM_GPU_STATE=y CONFIG_DRM_MSM_GPU_SUDO=y # CONFIG_DRM_MSM_MDP4 is not set # CONFIG_DRM_MSM_MDP5 is not set # CONFIG_DRM_MSM_DPU is not set CONFIG_DRM_MSM_DP=y CONFIG_DRM_MSM_DSI=y CONFIG_DRM_MSM_DSI_28NM_PHY=y CONFIG_DRM_MSM_DSI_20NM_PHY=y CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y # CONFIG_DRM_MSM_DSI_14NM_PHY is not set # CONFIG_DRM_MSM_DSI_10NM_PHY is not set # CONFIG_DRM_MSM_DSI_7NM_PHY is not set # CONFIG_DRM_MSM_HDMI is not set CONFIG_DRM_FSL_DCU=y # CONFIG_DRM_TEGRA is not set CONFIG_DRM_STM=y CONFIG_DRM_STM_DSI=y CONFIG_DRM_PANEL=y # # Display Panels # CONFIG_DRM_PANEL_ARM_VERSATILE=y CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m CONFIG_DRM_PANEL_BOE_HIMAX8279D=m CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m CONFIG_DRM_PANEL_DSI_CM=y # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set CONFIG_DRM_PANEL_EDP=y # CONFIG_DRM_PANEL_EBBG_FT8719 is not set CONFIG_DRM_PANEL_ELIDA_KD35T133=y CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y CONFIG_DRM_PANEL_JDI_LT070ME05000=y CONFIG_DRM_PANEL_JDI_R63452=y CONFIG_DRM_PANEL_KHADAS_TS050=y CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=y # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set CONFIG_DRM_PANEL_NOVATEK_NT35560=y # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=y CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y CONFIG_DRM_PANEL_RAYDIUM_RM67191=y CONFIG_DRM_PANEL_RAYDIUM_RM68200=y CONFIG_DRM_PANEL_RONBO_RB070D30=y CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y # CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m CONFIG_DRM_PANEL_SHARP_LS043T1LE01=y CONFIG_DRM_PANEL_SHARP_LS060T1SX01=y # CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set CONFIG_DRM_PANEL_TDO_TL070WSH30=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=y CONFIG_DRM_PANEL_VISIONOX_RM69299=m CONFIG_DRM_PANEL_XINPENG_XPP055C272=m # end of Display Panels CONFIG_DRM_BRIDGE=y CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set CONFIG_DRM_CHIPONE_ICN6211=y # CONFIG_DRM_CHRONTEL_CH7033 is not set # CONFIG_DRM_CROS_EC_ANX7688 is not set CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_FSL_LDB=y CONFIG_DRM_ITE_IT6505=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9211=m CONFIG_DRM_LONTIUM_LT9611=y CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_ITE_IT66121=y CONFIG_DRM_LVDS_CODEC=y CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=y CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_NXP_PTN3460=m CONFIG_DRM_PARADE_PS8622=m CONFIG_DRM_PARADE_PS8640=y CONFIG_DRM_SIL_SII8620=y # CONFIG_DRM_SII902X is not set # CONFIG_DRM_SII9234 is not set # CONFIG_DRM_SIMPLE_BRIDGE is not set CONFIG_DRM_THINE_THC63LVD1024=m CONFIG_DRM_TOSHIBA_TC358762=m CONFIG_DRM_TOSHIBA_TC358764=m CONFIG_DRM_TOSHIBA_TC358767=m # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set CONFIG_DRM_TI_DLPC3433=y CONFIG_DRM_TI_TFP410=m CONFIG_DRM_TI_SN65DSI83=y # CONFIG_DRM_TI_SN65DSI86 is not set CONFIG_DRM_TI_TPD12S015=m # CONFIG_DRM_ANALOGIX_ANX6345 is not set CONFIG_DRM_ANALOGIX_ANX78XX=m CONFIG_DRM_ANALOGIX_DP=m CONFIG_DRM_ANALOGIX_ANX7625=y CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_I2C_ADV7511_CEC=y # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_IMX8QM_LDB=y CONFIG_DRM_IMX8QXP_LDB=y CONFIG_DRM_IMX8QXP_PIXEL_COMBINER=m CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=y CONFIG_DRM_DW_HDMI=m # CONFIG_DRM_DW_HDMI_CEC is not set CONFIG_DRM_DW_MIPI_DSI=y # end of Display Interface Bridges CONFIG_DRM_STI=y CONFIG_DRM_INGENIC=m CONFIG_DRM_INGENIC_IPU=y # CONFIG_DRM_V3D is not set CONFIG_DRM_ETNAVIV=y # CONFIG_DRM_ETNAVIV_THERMAL is not set # CONFIG_DRM_LOGICVC is not set CONFIG_DRM_MXS=y CONFIG_DRM_MXSFB=m CONFIG_DRM_IMX_LCDIF=m # CONFIG_DRM_MESON is not set # CONFIG_DRM_ARCPGU is not set CONFIG_DRM_SIMPLEDRM=m CONFIG_DRM_PL111=y CONFIG_DRM_TVE200=y CONFIG_DRM_LIMA=m CONFIG_DRM_PANFROST=m CONFIG_DRM_ASPEED_GFX=y CONFIG_DRM_MCDE=y # CONFIG_DRM_TIDSS is not set CONFIG_DRM_SSD130X=m CONFIG_DRM_SSD130X_I2C=m # CONFIG_DRM_SPRD is not set CONFIG_DRM_LEGACY=y CONFIG_DRM_EXPORT_FOR_TESTS=y CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y CONFIG_DRM_NOMODESET=y CONFIG_DRM_LIB_RANDOM=y # # Frame buffer Devices # CONFIG_FB_CMDLINE=y # CONFIG_FB is not set CONFIG_MMP_DISP=m CONFIG_MMP_DISP_CONTROLLER=y # end of Frame buffer Devices # # Backlight & LCD device support # # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_LM3533 is not set # CONFIG_BACKLIGHT_OMAP1 is not set CONFIG_BACKLIGHT_PWM=y # CONFIG_BACKLIGHT_DA9052 is not set # CONFIG_BACKLIGHT_MAX8925 is not set # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set CONFIG_BACKLIGHT_ADP8870=y # CONFIG_BACKLIGHT_LM3630A is not set CONFIG_BACKLIGHT_LM3639=y CONFIG_BACKLIGHT_LP855X=m CONFIG_BACKLIGHT_SKY81452=m CONFIG_BACKLIGHT_TPS65217=m # CONFIG_BACKLIGHT_GPIO is not set # CONFIG_BACKLIGHT_LV5207LP is not set CONFIG_BACKLIGHT_BD6107=m CONFIG_BACKLIGHT_ARCXCNN=m CONFIG_BACKLIGHT_RAVE_SP=m CONFIG_BACKLIGHT_LED=m # end of Backlight & LCD device support CONFIG_VIDEOMODE_HELPERS=y CONFIG_HDMI=y # end of Graphics support # CONFIG_SOUND is not set # # HID support # CONFIG_HID=m # CONFIG_HID_BATTERY_STRENGTH is not set CONFIG_HIDRAW=y CONFIG_UHID=m # CONFIG_HID_GENERIC is not set # # Special HID drivers # CONFIG_HID_A4TECH=m # CONFIG_HID_ACRUX is not set CONFIG_HID_APPLE=m CONFIG_HID_AUREAL=m # CONFIG_HID_BELKIN is not set CONFIG_HID_CHERRY=m CONFIG_HID_COUGAR=m CONFIG_HID_MACALLY=m # CONFIG_HID_CMEDIA is not set CONFIG_HID_CYPRESS=m # CONFIG_HID_DRAGONRISE is not set CONFIG_HID_EMS_FF=m CONFIG_HID_ELECOM=m CONFIG_HID_EZKEY=m # CONFIG_HID_GEMBIRD is not set CONFIG_HID_GFRM=m CONFIG_HID_GLORIOUS=m # CONFIG_HID_VIVALDI is not set CONFIG_HID_KEYTOUCH=m # CONFIG_HID_KYE is not set CONFIG_HID_WALTOP=m CONFIG_HID_VIEWSONIC=m CONFIG_HID_XIAOMI=m CONFIG_HID_GYRATION=m CONFIG_HID_ICADE=m # CONFIG_HID_ITE is not set CONFIG_HID_JABRA=m CONFIG_HID_TWINHAN=m CONFIG_HID_KENSINGTON=m # CONFIG_HID_LCPOWER is not set CONFIG_HID_LED=m # CONFIG_HID_LENOVO is not set CONFIG_HID_MAGICMOUSE=m # CONFIG_HID_MALTRON is not set # CONFIG_HID_MAYFLASH is not set CONFIG_HID_REDRAGON=m # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set CONFIG_HID_MULTITOUCH=m # CONFIG_HID_NINTENDO is not set CONFIG_HID_NTI=m CONFIG_HID_ORTEK=m CONFIG_HID_PANTHERLORD=m CONFIG_PANTHERLORD_FF=y CONFIG_HID_PETALYNX=m # CONFIG_HID_PICOLCD is not set CONFIG_HID_PLANTRONICS=m CONFIG_HID_PLAYSTATION=m # CONFIG_PLAYSTATION_FF is not set CONFIG_HID_RAZER=m CONFIG_HID_PRIMAX=m CONFIG_HID_SAITEK=m CONFIG_HID_SEMITEK=m CONFIG_HID_SPEEDLINK=m # CONFIG_HID_STEAM is not set CONFIG_HID_STEELSERIES=m CONFIG_HID_SUNPLUS=m # CONFIG_HID_RMI is not set # CONFIG_HID_GREENASIA is not set CONFIG_HID_SMARTJOYPLUS=m CONFIG_SMARTJOYPLUS_FF=y # CONFIG_HID_TIVO is not set # CONFIG_HID_TOPSEED is not set CONFIG_HID_THINGM=m # CONFIG_HID_UDRAW_PS3 is not set # CONFIG_HID_WIIMOTE is not set CONFIG_HID_XINMO=m # CONFIG_HID_ZEROPLUS is not set CONFIG_HID_ZYDACRON=m CONFIG_HID_SENSOR_HUB=m CONFIG_HID_SENSOR_CUSTOM_SENSOR=m # CONFIG_HID_ALPS is not set # end of Special HID drivers # # I2C HID support # # CONFIG_I2C_HID_OF is not set # CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_LEDS_GPIO_REGISTER=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=y CONFIG_LEDS_CLASS_MULTICOLOR=m # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # # LED drivers # CONFIG_LEDS_AN30259A=m # CONFIG_LEDS_ARIEL is not set # CONFIG_LEDS_AW2013 is not set CONFIG_LEDS_BCM6328=y CONFIG_LEDS_BCM6358=y # CONFIG_LEDS_TURRIS_OMNIA is not set CONFIG_LEDS_LM3530=m CONFIG_LEDS_LM3532=m CONFIG_LEDS_LM3533=y CONFIG_LEDS_LM3642=m CONFIG_LEDS_LM3692X=y # CONFIG_LEDS_S3C24XX is not set CONFIG_LEDS_COBALT_QUBE=m CONFIG_LEDS_COBALT_RAQ=y # CONFIG_LEDS_PCA9532 is not set CONFIG_LEDS_GPIO=m # CONFIG_LEDS_LP3944 is not set CONFIG_LEDS_LP3952=m # CONFIG_LEDS_LP50XX is not set CONFIG_LEDS_LP55XX_COMMON=m CONFIG_LEDS_LP5521=m CONFIG_LEDS_LP5523=m # CONFIG_LEDS_LP5562 is not set CONFIG_LEDS_LP8501=m # CONFIG_LEDS_LP8860 is not set CONFIG_LEDS_PCA955X=m CONFIG_LEDS_PCA955X_GPIO=y CONFIG_LEDS_PCA963X=m CONFIG_LEDS_WM8350=m CONFIG_LEDS_DA9052=m CONFIG_LEDS_PWM=m CONFIG_LEDS_REGULATOR=y # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_LT3593 is not set CONFIG_LEDS_MC13783=m CONFIG_LEDS_NS2=m CONFIG_LEDS_NETXBIG=y # CONFIG_LEDS_TCA6507 is not set CONFIG_LEDS_TLC591XX=y # CONFIG_LEDS_MAX77650 is not set CONFIG_LEDS_MAX8997=y CONFIG_LEDS_LM355x=y # CONFIG_LEDS_OT200 is not set CONFIG_LEDS_MENF21BMC=m # CONFIG_LEDS_IS31FL319X is not set CONFIG_LEDS_IS31FL32XX=y # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # CONFIG_LEDS_BLINKM=y CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_PM8058 is not set CONFIG_LEDS_MLXREG=y # CONFIG_LEDS_USER is not set CONFIG_LEDS_TI_LMU_COMMON=m CONFIG_LEDS_LM3697=m CONFIG_LEDS_IP30=y CONFIG_LEDS_BCM63138=m # CONFIG_LEDS_LGM is not set # # Flash and Torch LED drivers # CONFIG_LEDS_AAT1290=m CONFIG_LEDS_AS3645A=m CONFIG_LEDS_KTD2692=y CONFIG_LEDS_LM3601X=y CONFIG_LEDS_MAX77693=m CONFIG_LEDS_MT6360=m CONFIG_LEDS_RT4505=m CONFIG_LEDS_RT8515=m CONFIG_LEDS_SGM3140=m # # RGB LED drivers # CONFIG_LEDS_PWM_MULTICOLOR=m CONFIG_LEDS_QCOM_LPG=m # # LED Triggers # CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=m # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=m CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m # # iptables trigger is under Netfilter config (LED target) # # CONFIG_LEDS_TRIGGER_TRANSIENT is not set # CONFIG_LEDS_TRIGGER_CAMERA is not set CONFIG_LEDS_TRIGGER_PANIC=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # # Simple LED drivers # # CONFIG_ACCESSIBILITY is not set CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_EDAC=m # CONFIG_EDAC_LEGACY_SYSFS is not set # CONFIG_EDAC_DEBUG is not set # CONFIG_EDAC_AL_MC is not set CONFIG_EDAC_SYNOPSYS=m # CONFIG_EDAC_XGENE is not set # CONFIG_EDAC_ASPEED is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set # # DMA Devices # CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y CONFIG_DMA_ENGINE=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DMA_OF=y # CONFIG_ALTERA_MSGDMA is not set CONFIG_AMBA_PL08X=y # CONFIG_APPLE_ADMAC is not set CONFIG_AXI_DMAC=m CONFIG_DMA_JZ4780=y CONFIG_DMA_SA11X0=m # CONFIG_DMA_SUN6I is not set CONFIG_DW_AXI_DMAC=m # CONFIG_EP93XX_DMA is not set CONFIG_FSL_EDMA=y CONFIG_FSL_QDMA=y CONFIG_IMG_MDC_DMA=y # CONFIG_IMX_DMA is not set # CONFIG_IMX_SDMA is not set # CONFIG_INTEL_IDMA64 is not set # CONFIG_INTEL_IOP_ADMA is not set # CONFIG_K3_DMA is not set # CONFIG_LPC18XX_DMAMUX is not set CONFIG_MCF_EDMA=y CONFIG_MILBEAUT_HDMAC=m CONFIG_MILBEAUT_XDMAC=y # CONFIG_MMP_PDMA is not set # CONFIG_MMP_TDMA is not set CONFIG_MV_XOR=y # CONFIG_MXS_DMA is not set # CONFIG_MX3_IPU is not set CONFIG_NBPFAXI_DMA=y CONFIG_PL330_DMA=y # CONFIG_STM32_DMA is not set # CONFIG_STM32_DMAMUX is not set CONFIG_STM32_MDMA=y # CONFIG_SPRD_DMA is not set CONFIG_S3C24XX_DMAC=y # CONFIG_TEGRA20_APB_DMA is not set CONFIG_TEGRA210_ADMA=m # CONFIG_TIMB_DMA is not set CONFIG_UNIPHIER_MDMAC=m CONFIG_UNIPHIER_XDMAC=y CONFIG_XGENE_DMA=m # CONFIG_XILINX_ZYNQMP_DMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_MTK_HSDMA is not set CONFIG_MTK_CQDMA=m CONFIG_QCOM_ADM=y CONFIG_QCOM_BAM_DMA=m CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=m CONFIG_DW_DMAC_CORE=y CONFIG_DW_DMAC=y CONFIG_RZN1_DMAMUX=m # CONFIG_SF_PDMA is not set CONFIG_RENESAS_DMA=y CONFIG_SH_DMAE_BASE=y CONFIG_SH_DMAE=m CONFIG_RCAR_DMAC=y # CONFIG_RENESAS_USB_DMAC is not set # CONFIG_RZ_DMAC is not set # CONFIG_TI_EDMA is not set # CONFIG_DMA_OMAP is not set CONFIG_INTEL_LDMA=y # # DMA Clients # # CONFIG_ASYNC_TX_DMA is not set # CONFIG_DMATEST is not set CONFIG_DMA_ENGINE_RAID=y # # DMABUF options # CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set CONFIG_UDMABUF=y CONFIG_DMABUF_MOVE_NOTIFY=y CONFIG_DMABUF_DEBUG=y CONFIG_DMABUF_SELFTESTS=m # CONFIG_DMABUF_HEAPS is not set # CONFIG_DMABUF_SYSFS_STATS is not set # end of DMABUF options CONFIG_AUXDISPLAY=y CONFIG_CHARLCD=y CONFIG_LINEDISP=y CONFIG_HD44780_COMMON=y CONFIG_HD44780=y CONFIG_KS0108=m CONFIG_KS0108_PORT=0x378 CONFIG_KS0108_DELAY=2 CONFIG_IMG_ASCII_LCD=m CONFIG_LCD2S=m # CONFIG_ARM_CHARLCD is not set CONFIG_PARPORT_PANEL=y CONFIG_PANEL_PARPORT=0 CONFIG_PANEL_PROFILE=5 # CONFIG_PANEL_CHANGE_MESSAGE is not set CONFIG_CHARLCD_BL_OFF=y # CONFIG_CHARLCD_BL_ON is not set # CONFIG_CHARLCD_BL_FLASH is not set CONFIG_PANEL=y CONFIG_UIO=m CONFIG_UIO_PDRV_GENIRQ=m CONFIG_UIO_DMEM_GENIRQ=m CONFIG_UIO_PRUSS=m CONFIG_VFIO=y CONFIG_VFIO_IOMMU_TYPE1=y CONFIG_VFIO_VIRQFD=m # CONFIG_VFIO_NOIOMMU is not set CONFIG_VFIO_PLATFORM=m # CONFIG_VFIO_AMBA is not set CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m CONFIG_VFIO_PLATFORM_BCMFLEXRM_RESET=m CONFIG_VFIO_MDEV=m # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y CONFIG_VIRTIO_DMA_SHARED_BUFFER=y # CONFIG_VHOST_MENU is not set # # Microsoft Hyper-V guest support # # end of Microsoft Hyper-V guest support CONFIG_GREYBUS=m # CONFIG_COMEDI is not set # CONFIG_STAGING is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=m # CONFIG_CROS_EC_I2C is not set CONFIG_CROS_EC_RPMSG=m CONFIG_CROS_EC_PROTO=y CONFIG_CROS_KBD_LED_BACKLIGHT=m # CONFIG_CROS_EC_CHARDEV is not set # CONFIG_CROS_EC_LIGHTBAR is not set # CONFIG_CROS_EC_VBC is not set CONFIG_CROS_EC_DEBUGFS=m CONFIG_CROS_EC_SENSORHUB=m CONFIG_CROS_EC_SYSFS=m CONFIG_CROS_USBPD_NOTIFY=m CONFIG_MELLANOX_PLATFORM=y CONFIG_MLXREG_HOTPLUG=m # CONFIG_MLXREG_IO is not set CONFIG_MLXREG_LC=m CONFIG_NVSW_SN2201=m CONFIG_OLPC_XO175=y CONFIG_SURFACE_PLATFORMS=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y # # Clock driver for ARM Reference designs # CONFIG_CLK_ICST=y CONFIG_CLK_SP810=y # end of Clock driver for ARM Reference designs # CONFIG_CLK_HSDK is not set CONFIG_COMMON_CLK_APPLE_NCO=m # CONFIG_COMMON_CLK_MAX77686 is not set CONFIG_COMMON_CLK_MAX9485=y CONFIG_COMMON_CLK_RK808=m CONFIG_COMMON_CLK_HI655X=m CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=m # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set CONFIG_COMMON_CLK_SI514=y # CONFIG_COMMON_CLK_SI544 is not set CONFIG_COMMON_CLK_SI570=m CONFIG_COMMON_CLK_BM1880=y CONFIG_COMMON_CLK_CDCE706=m CONFIG_COMMON_CLK_TPS68470=y CONFIG_COMMON_CLK_CDCE925=y # CONFIG_COMMON_CLK_CS2000_CP is not set # CONFIG_COMMON_CLK_EN7523 is not set # CONFIG_COMMON_CLK_FSL_FLEXSPI is not set CONFIG_COMMON_CLK_FSL_SAI=y # CONFIG_COMMON_CLK_GEMINI is not set # CONFIG_COMMON_CLK_LAN966X is not set CONFIG_COMMON_CLK_ASPEED=y # CONFIG_COMMON_CLK_S2MPS11 is not set CONFIG_CLK_TWL6040=m CONFIG_COMMON_CLK_AXI_CLKGEN=m # CONFIG_CLK_QORIQ is not set # CONFIG_CLK_LS1028A_PLLDIG is not set # CONFIG_COMMON_CLK_XGENE is not set CONFIG_COMMON_CLK_LOCHNAGAR=y CONFIG_COMMON_CLK_PALMAS=m CONFIG_COMMON_CLK_PWM=y CONFIG_COMMON_CLK_OXNAS=y # CONFIG_COMMON_CLK_RS9_PCIE is not set CONFIG_COMMON_CLK_VC5=m # CONFIG_COMMON_CLK_MMP2_AUDIO is not set CONFIG_COMMON_CLK_BD718XX=m # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_CLK_ACTIONS=y # CONFIG_CLK_OWL_S500 is not set # CONFIG_CLK_OWL_S700 is not set CONFIG_CLK_OWL_S900=y # CONFIG_CLK_BAIKAL_T1 is not set CONFIG_CLK_BCM2711_DVP=y # CONFIG_CLK_BCM2835 is not set # CONFIG_CLK_BCM_63XX is not set CONFIG_CLK_BCM_63XX_GATE=y # CONFIG_CLK_BCM_KONA is not set CONFIG_COMMON_CLK_IPROC=y CONFIG_CLK_BCM_CYGNUS=y # CONFIG_CLK_BCM_HR2 is not set CONFIG_CLK_BCM_NSP=y # CONFIG_CLK_BCM_NS2 is not set CONFIG_CLK_BCM_SR=y # CONFIG_CLK_RASPBERRYPI is not set CONFIG_COMMON_CLK_HI3516CV300=y # CONFIG_COMMON_CLK_HI3519 is not set CONFIG_COMMON_CLK_HI3559A=y # CONFIG_COMMON_CLK_HI3660 is not set CONFIG_COMMON_CLK_HI3670=y # CONFIG_COMMON_CLK_HI3798CV200 is not set CONFIG_COMMON_CLK_HI6220=y CONFIG_RESET_HISI=y CONFIG_STUB_CLK_HI6220=y # CONFIG_STUB_CLK_HI3660 is not set CONFIG_COMMON_CLK_BOSTON=y CONFIG_MXC_CLK=y # CONFIG_CLK_IMX8MM is not set CONFIG_CLK_IMX8MN=m # CONFIG_CLK_IMX8MP is not set # CONFIG_CLK_IMX8MQ is not set # CONFIG_CLK_IMX8ULP is not set CONFIG_CLK_IMX93=m # # Ingenic SoCs drivers # CONFIG_INGENIC_CGU_COMMON=y CONFIG_INGENIC_CGU_JZ4740=y CONFIG_INGENIC_CGU_JZ4725B=y CONFIG_INGENIC_CGU_JZ4760=y # CONFIG_INGENIC_CGU_JZ4770 is not set # CONFIG_INGENIC_CGU_JZ4780 is not set # CONFIG_INGENIC_CGU_X1000 is not set CONFIG_INGENIC_CGU_X1830=y CONFIG_INGENIC_TCU_CLK=y # end of Ingenic SoCs drivers CONFIG_COMMON_CLK_KEYSTONE=m # CONFIG_TI_SYSCON_CLK is not set # # Clock driver for MediaTek SoC # CONFIG_COMMON_CLK_MEDIATEK=y # CONFIG_COMMON_CLK_MT2701 is not set # CONFIG_COMMON_CLK_MT2712 is not set CONFIG_COMMON_CLK_MT6765=y CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y CONFIG_COMMON_CLK_MT6765_CAMSYS=y # CONFIG_COMMON_CLK_MT6765_GCESYS is not set # CONFIG_COMMON_CLK_MT6765_MMSYS is not set # CONFIG_COMMON_CLK_MT6765_IMGSYS is not set CONFIG_COMMON_CLK_MT6765_VCODECSYS=y CONFIG_COMMON_CLK_MT6765_MFGSYS=y # CONFIG_COMMON_CLK_MT6765_MIPI0ASYS is not set # CONFIG_COMMON_CLK_MT6765_MIPI0BSYS is not set # CONFIG_COMMON_CLK_MT6765_MIPI1ASYS is not set # CONFIG_COMMON_CLK_MT6765_MIPI1BSYS is not set # CONFIG_COMMON_CLK_MT6765_MIPI2ASYS is not set CONFIG_COMMON_CLK_MT6765_MIPI2BSYS=y # CONFIG_COMMON_CLK_MT6779 is not set CONFIG_COMMON_CLK_MT6797=y # CONFIG_COMMON_CLK_MT6797_MMSYS is not set # CONFIG_COMMON_CLK_MT6797_IMGSYS is not set CONFIG_COMMON_CLK_MT6797_VDECSYS=y CONFIG_COMMON_CLK_MT6797_VENCSYS=y # CONFIG_COMMON_CLK_MT7622 is not set CONFIG_COMMON_CLK_MT7629=y CONFIG_COMMON_CLK_MT7629_ETHSYS=y # CONFIG_COMMON_CLK_MT7629_HIFSYS is not set CONFIG_COMMON_CLK_MT7986=y # CONFIG_COMMON_CLK_MT7986_ETHSYS is not set # CONFIG_COMMON_CLK_MT8135 is not set # CONFIG_COMMON_CLK_MT8167 is not set CONFIG_COMMON_CLK_MT8173=y # CONFIG_COMMON_CLK_MT8173_MMSYS is not set CONFIG_COMMON_CLK_MT8183=y CONFIG_COMMON_CLK_MT8183_AUDIOSYS=y CONFIG_COMMON_CLK_MT8183_CAMSYS=y # CONFIG_COMMON_CLK_MT8183_IMGSYS is not set # CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set # CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set CONFIG_COMMON_CLK_MT8183_IPU_ADL=y CONFIG_COMMON_CLK_MT8183_IPU_CONN=y CONFIG_COMMON_CLK_MT8183_MFGCFG=y # CONFIG_COMMON_CLK_MT8183_MMSYS is not set # CONFIG_COMMON_CLK_MT8183_VDECSYS is not set # CONFIG_COMMON_CLK_MT8183_VENCSYS is not set CONFIG_COMMON_CLK_MT8186=y CONFIG_COMMON_CLK_MT8192=y CONFIG_COMMON_CLK_MT8192_AUDSYS=y # CONFIG_COMMON_CLK_MT8192_CAMSYS is not set CONFIG_COMMON_CLK_MT8192_IMGSYS=y # CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP is not set # CONFIG_COMMON_CLK_MT8192_IPESYS is not set # CONFIG_COMMON_CLK_MT8192_MDPSYS is not set # CONFIG_COMMON_CLK_MT8192_MFGCFG is not set CONFIG_COMMON_CLK_MT8192_MMSYS=y CONFIG_COMMON_CLK_MT8192_MSDC=y CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y # CONFIG_COMMON_CLK_MT8192_VDECSYS is not set CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_MT8195=y # CONFIG_COMMON_CLK_MT8516 is not set # end of Clock driver for MediaTek SoC # # Clock support for Amlogic platforms # # CONFIG_COMMON_CLK_MESON8B is not set # end of Clock support for Amlogic platforms # CONFIG_MSTAR_MSC313_MPLL is not set CONFIG_MCHP_CLK_MPFS=y CONFIG_COMMON_CLK_PISTACHIO=y CONFIG_QCOM_GDSC=y CONFIG_QCOM_RPMCC=y CONFIG_COMMON_CLK_QCOM=m CONFIG_QCOM_A53PLL=m # CONFIG_QCOM_A7PLL is not set CONFIG_QCOM_CLK_APCS_MSM8916=m # CONFIG_QCOM_CLK_APCS_SDX55 is not set CONFIG_QCOM_CLK_SMD_RPM=m # CONFIG_QCOM_CLK_RPMH is not set CONFIG_APQ_GCC_8084=m # CONFIG_APQ_MMCC_8084 is not set CONFIG_IPQ_APSS_PLL=m CONFIG_IPQ_APSS_6018=m # CONFIG_IPQ_GCC_4019 is not set CONFIG_IPQ_GCC_6018=m # CONFIG_IPQ_GCC_806X is not set # CONFIG_IPQ_LCC_806X is not set CONFIG_IPQ_GCC_8074=m CONFIG_MSM_GCC_8660=m # CONFIG_MSM_GCC_8916 is not set # CONFIG_MSM_GCC_8939 is not set CONFIG_MSM_GCC_8960=m CONFIG_MSM_LCC_8960=m CONFIG_MDM_GCC_9607=m CONFIG_MDM_GCC_9615=m # CONFIG_MDM_LCC_9615 is not set # CONFIG_MSM_MMCC_8960 is not set # CONFIG_MSM_GCC_8953 is not set # CONFIG_MSM_GCC_8974 is not set # CONFIG_MSM_MMCC_8974 is not set CONFIG_MSM_GCC_8976=m CONFIG_MSM_MMCC_8994=m CONFIG_MSM_GCC_8994=m # CONFIG_MSM_GCC_8996 is not set # CONFIG_MSM_MMCC_8996 is not set CONFIG_MSM_GCC_8998=m # CONFIG_MSM_GPUCC_8998 is not set CONFIG_MSM_MMCC_8998=m # CONFIG_QCM_GCC_2290 is not set # CONFIG_QCM_DISPCC_2290 is not set CONFIG_QCS_GCC_404=m CONFIG_SC_CAMCC_7180=m # CONFIG_SC_CAMCC_7280 is not set CONFIG_SC_DISPCC_7180=m CONFIG_SC_DISPCC_7280=m CONFIG_SC_GCC_7180=m CONFIG_SC_GCC_7280=m CONFIG_SC_GCC_8180X=m # CONFIG_SC_GCC_8280XP is not set # CONFIG_SC_GPUCC_7180 is not set CONFIG_SC_GPUCC_7280=m CONFIG_SC_LPASSCC_7280=m # CONFIG_SC_LPASS_CORECC_7180 is not set # CONFIG_SC_LPASS_CORECC_7280 is not set # CONFIG_SC_MSS_7180 is not set # CONFIG_SC_VIDEOCC_7180 is not set CONFIG_SC_VIDEOCC_7280=m CONFIG_SDM_CAMCC_845=m CONFIG_SDM_GCC_660=m CONFIG_SDM_MMCC_660=m # CONFIG_SDM_GPUCC_660 is not set CONFIG_QCS_TURING_404=m CONFIG_QCS_Q6SSTOP_404=m CONFIG_SDM_GCC_845=m CONFIG_SDM_GPUCC_845=m CONFIG_SDM_VIDEOCC_845=m CONFIG_SDM_DISPCC_845=m # CONFIG_SDM_LPASSCC_845 is not set CONFIG_SDX_GCC_55=m CONFIG_SDX_GCC_65=m CONFIG_SM_CAMCC_8250=m CONFIG_SM_CAMCC_8450=m CONFIG_SM_DISPCC_8250=m # CONFIG_SM_DISPCC_6350 is not set # CONFIG_SM_GCC_6115 is not set # CONFIG_SM_GCC_6125 is not set CONFIG_SM_GCC_6350=m CONFIG_SM_GCC_8150=m CONFIG_SM_GCC_8250=m CONFIG_SM_GCC_8350=m CONFIG_SM_GCC_8450=m CONFIG_SM_GPUCC_6350=m CONFIG_SM_GPUCC_8150=m # CONFIG_SM_GPUCC_8250 is not set # CONFIG_SM_GPUCC_8350 is not set CONFIG_SM_VIDEOCC_8150=m CONFIG_SM_VIDEOCC_8250=m CONFIG_SPMI_PMIC_CLKDIV=m # CONFIG_QCOM_HFPLL is not set CONFIG_KPSS_XCC=m # CONFIG_KRAITCC is not set # CONFIG_CLK_GFM_LPASS_SM8250 is not set # CONFIG_CLK_MT7621 is not set CONFIG_CLK_RENESAS=y CONFIG_CLK_EMEV2=y CONFIG_CLK_RZA1=y # CONFIG_CLK_R7S9210 is not set # CONFIG_CLK_R8A73A4 is not set CONFIG_CLK_R8A7740=y # CONFIG_CLK_R8A7742 is not set # CONFIG_CLK_R8A7743 is not set # CONFIG_CLK_R8A7745 is not set CONFIG_CLK_R8A77470=y CONFIG_CLK_R8A774A1=y # CONFIG_CLK_R8A774B1 is not set CONFIG_CLK_R8A774C0=y # CONFIG_CLK_R8A774E1 is not set CONFIG_CLK_R8A7778=y # CONFIG_CLK_R8A7779 is not set # CONFIG_CLK_R8A7790 is not set # CONFIG_CLK_R8A7791 is not set CONFIG_CLK_R8A7792=y CONFIG_CLK_R8A7794=y CONFIG_CLK_R8A7795=y CONFIG_CLK_R8A77960=y CONFIG_CLK_R8A77961=y CONFIG_CLK_R8A77965=y # CONFIG_CLK_R8A77970 is not set # CONFIG_CLK_R8A77980 is not set # CONFIG_CLK_R8A77990 is not set # CONFIG_CLK_R8A77995 is not set CONFIG_CLK_R8A779A0=y CONFIG_CLK_R8A779F0=y # CONFIG_CLK_R8A779G0 is not set # CONFIG_CLK_R9A06G032 is not set # CONFIG_CLK_R9A07G043 is not set # CONFIG_CLK_R9A07G044 is not set CONFIG_CLK_R9A07G054=y CONFIG_CLK_R9A09G011=y CONFIG_CLK_SH73A0=y CONFIG_CLK_RCAR_CPG_LIB=y CONFIG_CLK_RCAR_GEN2_CPG=y CONFIG_CLK_RCAR_GEN3_CPG=y CONFIG_CLK_RCAR_GEN4_CPG=y CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y CONFIG_CLK_RZG2L=y CONFIG_CLK_RENESAS_CPG_MSSR=y CONFIG_CLK_RENESAS_CPG_MSTP=y CONFIG_CLK_RENESAS_DIV6=y CONFIG_COMMON_CLK_SAMSUNG=y CONFIG_S3C64XX_COMMON_CLK=y CONFIG_S5PV210_COMMON_CLK=y CONFIG_EXYNOS_3250_COMMON_CLK=y # CONFIG_EXYNOS_4_COMMON_CLK is not set CONFIG_EXYNOS_5250_COMMON_CLK=y # CONFIG_EXYNOS_5260_COMMON_CLK is not set # CONFIG_EXYNOS_5410_COMMON_CLK is not set CONFIG_EXYNOS_5420_COMMON_CLK=y CONFIG_EXYNOS_ARM64_COMMON_CLK=y # CONFIG_EXYNOS_AUDSS_CLK_CON is not set CONFIG_EXYNOS_CLKOUT=m # CONFIG_S3C2410_COMMON_CLK is not set # CONFIG_S3C2412_COMMON_CLK is not set # CONFIG_S3C2443_COMMON_CLK is not set # CONFIG_TESLA_FSD_COMMON_CLK is not set # CONFIG_CLK_SIFIVE is not set # CONFIG_CLK_INTEL_SOCFPGA is not set CONFIG_SPRD_COMMON_CLK=y # CONFIG_SPRD_SC9860_CLK is not set # CONFIG_SPRD_SC9863A_CLK is not set # CONFIG_CLK_STARFIVE_JH7100 is not set CONFIG_CLK_SUNXI=y CONFIG_CLK_SUNXI_CLOCKS=y CONFIG_CLK_SUNXI_PRCM_SUN6I=y # CONFIG_CLK_SUNXI_PRCM_SUN8I is not set # CONFIG_CLK_SUNXI_PRCM_SUN9I is not set CONFIG_SUNXI_CCU=m CONFIG_SUNIV_F1C100S_CCU=m CONFIG_SUN20I_D1_CCU=m CONFIG_SUN20I_D1_R_CCU=m # CONFIG_SUN50I_A64_CCU is not set CONFIG_SUN50I_A100_CCU=m CONFIG_SUN50I_A100_R_CCU=m CONFIG_SUN50I_H6_CCU=m CONFIG_SUN50I_H616_CCU=m CONFIG_SUN50I_H6_R_CCU=m # CONFIG_SUN4I_A10_CCU is not set CONFIG_SUN6I_A31_CCU=m CONFIG_SUN6I_RTC_CCU=m CONFIG_SUN8I_A23_CCU=m # CONFIG_SUN8I_A33_CCU is not set # CONFIG_SUN8I_A83T_CCU is not set CONFIG_SUN8I_H3_CCU=m CONFIG_SUN8I_V3S_CCU=m # CONFIG_SUN8I_DE2_CCU is not set # CONFIG_SUN8I_R40_CCU is not set # CONFIG_SUN9I_A80_CCU is not set # CONFIG_SUN8I_R_CCU is not set CONFIG_COMMON_CLK_TI_ADPLL=m # CONFIG_CLK_UNIPHIER is not set CONFIG_COMMON_CLK_VISCONTI=y # CONFIG_CLK_LGM_CGU is not set # CONFIG_XILINX_VCU is not set # CONFIG_COMMON_CLK_ZYNQMP is not set # CONFIG_HWSPINLOCK is not set # # Clock Source drivers # CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_MMIO=y CONFIG_BCM2835_TIMER=y CONFIG_BCM_KONA_TIMER=y # CONFIG_DAVINCI_TIMER is not set # CONFIG_DIGICOLOR_TIMER is not set # CONFIG_OMAP_DM_TIMER is not set CONFIG_DW_APB_TIMER=y CONFIG_FTTMR010_TIMER=y CONFIG_IXP4XX_TIMER=y # CONFIG_ROCKCHIP_TIMER is not set # CONFIG_ARMADA_370_XP_TIMER is not set # CONFIG_MESON6_TIMER is not set CONFIG_ORION_TIMER=y # CONFIG_OWL_TIMER is not set # CONFIG_RDA_TIMER is not set CONFIG_SUN4I_TIMER=y # CONFIG_SUN5I_HSTIMER is not set CONFIG_TEGRA_TIMER=y # CONFIG_TEGRA186_TIMER is not set # CONFIG_VT8500_TIMER is not set CONFIG_NPCM7XX_TIMER=y CONFIG_CADENCE_TTC_TIMER=y # CONFIG_ASM9260_TIMER is not set # CONFIG_CLKSRC_NOMADIK_MTU is not set CONFIG_CLKSRC_DBX500_PRCMU=y CONFIG_CLPS711X_TIMER=y CONFIG_MXS_TIMER=y # CONFIG_NSPIRE_TIMER is not set CONFIG_KEYSTONE_TIMER=y CONFIG_INTEGRATOR_AP_TIMER=y # CONFIG_CLKSRC_LPC32XX is not set # CONFIG_CLKSRC_PISTACHIO is not set # CONFIG_CLKSRC_TI_32K is not set # CONFIG_CLKSRC_STM32 is not set CONFIG_CLKSRC_STM32_LP=y # CONFIG_CLKSRC_MPS2 is not set CONFIG_ARC_TIMERS=y CONFIG_ARC_TIMERS_64BIT=y CONFIG_ARM_GLOBAL_TIMER=y CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1 CONFIG_ARM_TIMER_SP804=y CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y # CONFIG_ARMV7M_SYSTICK is not set CONFIG_ATMEL_PIT=y CONFIG_ATMEL_ST=y CONFIG_ATMEL_TCB_CLKSRC=y # CONFIG_CLKSRC_EXYNOS_MCT is not set CONFIG_CLKSRC_SAMSUNG_PWM=y # CONFIG_FSL_FTM_TIMER is not set CONFIG_OXNAS_RPS_TIMER=y # CONFIG_MTK_TIMER is not set CONFIG_SPRD_TIMER=y CONFIG_CLKSRC_JCORE_PIT=y # CONFIG_SH_TIMER_CMT is not set # CONFIG_SH_TIMER_MTU2 is not set # CONFIG_RENESAS_OSTM is not set CONFIG_SH_TIMER_TMU=y CONFIG_EM_TIMER_STI=y # CONFIG_CLKSRC_QCOM is not set CONFIG_CLKSRC_VERSATILE=y # CONFIG_CLKSRC_PXA is not set CONFIG_CLKSRC_IMX_GPT=y CONFIG_CLKSRC_IMX_TPM=y # CONFIG_TIMER_IMX_SYS_CTR is not set # CONFIG_CLKSRC_ST_LPC is not set CONFIG_GXP_TIMER=y CONFIG_MILBEAUT_TIMER=y # CONFIG_MSC313E_TIMER is not set CONFIG_INGENIC_TIMER=y # CONFIG_INGENIC_SYSOST is not set # CONFIG_INGENIC_OST is not set CONFIG_MICROCHIP_PIT64B=y # end of Clock Source drivers CONFIG_MAILBOX=y # CONFIG_ARM_MHU is not set CONFIG_ARM_MHU_V2=m CONFIG_IMX_MBOX=m CONFIG_PLATFORM_MHU=m # CONFIG_PL320_MBOX is not set CONFIG_ARMADA_37XX_RWTM_MBOX=y # CONFIG_ROCKCHIP_MBOX is not set CONFIG_ALTERA_MBOX=y CONFIG_HI3660_MBOX=y CONFIG_HI6220_MBOX=m CONFIG_MAILBOX_TEST=m CONFIG_POLARFIRE_SOC_MAILBOX=m CONFIG_QCOM_APCS_IPC=m CONFIG_BCM_PDC_MBOX=y CONFIG_STM32_IPCC=y CONFIG_MTK_ADSP_MBOX=y CONFIG_MTK_CMDQ_MBOX=m CONFIG_SUN6I_MSGBOX=y CONFIG_SPRD_MBOX=y CONFIG_QCOM_IPCC=y CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # CONFIG_IOMMU_IO_PGTABLE=y CONFIG_IOMMU_IO_PGTABLE_LPAE=y CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST=y CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y # CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set CONFIG_IOMMU_DEFAULT_DMA_STRICT=y # CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_MSM_IOMMU=y # CONFIG_OMAP_IOMMU is not set CONFIG_ROCKCHIP_IOMMU=y # CONFIG_SUN50I_IOMMU is not set # CONFIG_EXYNOS_IOMMU is not set CONFIG_ARM_SMMU=m CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y CONFIG_S390_CCW_IOMMU=y # CONFIG_S390_AP_IOMMU is not set CONFIG_MTK_IOMMU=y CONFIG_MTK_IOMMU_V1=y CONFIG_SPRD_IOMMU=m # # Remoteproc drivers # # CONFIG_REMOTEPROC is not set # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=y # CONFIG_RPMSG_CTRL is not set # CONFIG_RPMSG_NS is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # end of Rpmsg drivers CONFIG_SOUNDWIRE=y # # SoundWire Devices # # # SOC (System On Chip) specific Drivers # CONFIG_OWL_PM_DOMAINS_HELPER=y CONFIG_OWL_PM_DOMAINS=y # # Amlogic SoC drivers # # CONFIG_MESON_CANVAS is not set # CONFIG_MESON_CLK_MEASURE is not set # CONFIG_MESON_GX_SOCINFO is not set CONFIG_MESON_GX_PM_DOMAINS=y CONFIG_MESON_EE_PM_DOMAINS=y CONFIG_MESON_MX_SOCINFO=y # end of Amlogic SoC drivers # # Apple SoC drivers # # CONFIG_APPLE_PMGR_PWRSTATE is not set # CONFIG_APPLE_RTKIT is not set CONFIG_APPLE_SART=y # end of Apple SoC drivers # # ASPEED SoC drivers # CONFIG_ASPEED_LPC_CTRL=y CONFIG_ASPEED_LPC_SNOOP=y # CONFIG_ASPEED_UART_ROUTING is not set CONFIG_ASPEED_P2A_CTRL=y CONFIG_ASPEED_SOCINFO=y # end of ASPEED SoC drivers # CONFIG_AT91_SOC_ID is not set # CONFIG_AT91_SOC_SFR is not set # # Broadcom SoC drivers # CONFIG_BCM2835_POWER=y # CONFIG_SOC_BCM63XX is not set # CONFIG_SOC_BRCMSTB is not set # CONFIG_BCM_PMB is not set # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # # CONFIG_QUICC_ENGINE is not set # CONFIG_DPAA2_CONSOLE is not set # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # CONFIG_IMX_GPCV2_PM_DOMAINS=y CONFIG_SOC_IMX8M=y # end of i.MX SoC drivers # # IXP4xx SoC drivers # CONFIG_IXP4XX_QMGR=m # CONFIG_IXP4XX_NPE is not set # end of IXP4xx SoC drivers # # Enable LiteX SoC Builder specific drivers # # CONFIG_LITEX_SOC_CONTROLLER is not set # end of Enable LiteX SoC Builder specific drivers # # MediaTek SoC drivers # CONFIG_MTK_CMDQ=m # CONFIG_MTK_DEVAPC is not set CONFIG_MTK_INFRACFG=y CONFIG_MTK_PMIC_WRAP=y CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y # CONFIG_MTK_MMSYS is not set # CONFIG_MTK_SVS is not set # end of MediaTek SoC drivers # CONFIG_POLARFIRE_SOC_SYS_CTRL is not set # # Qualcomm SoC drivers # CONFIG_QCOM_AOSS_QMP=y CONFIG_QCOM_COMMAND_DB=m CONFIG_QCOM_GENI_SE=m # CONFIG_QCOM_GSBI is not set CONFIG_QCOM_LLCC=y CONFIG_QCOM_RPMH=m # CONFIG_QCOM_RPMHPD is not set CONFIG_QCOM_RPMPD=m CONFIG_QCOM_SMD_RPM=y # CONFIG_QCOM_SPM is not set CONFIG_QCOM_WCNSS_CTRL=y CONFIG_QCOM_ICC_BWMON=m # end of Qualcomm SoC drivers CONFIG_SOC_RENESAS=y CONFIG_RST_RCAR=y CONFIG_SYSC_RCAR=y CONFIG_SYSC_RCAR_GEN4=y # CONFIG_SYSC_R8A77995 is not set CONFIG_SYSC_R8A7794=y CONFIG_SYSC_R8A77990=y # CONFIG_SYSC_R8A7779 is not set CONFIG_SYSC_R8A7790=y CONFIG_SYSC_R8A7795=y CONFIG_SYSC_R8A7791=y # CONFIG_SYSC_R8A77965 is not set # CONFIG_SYSC_R8A77960 is not set # CONFIG_SYSC_R8A77961 is not set # CONFIG_SYSC_R8A779F0 is not set CONFIG_SYSC_R8A7792=y # CONFIG_SYSC_R8A77980 is not set # CONFIG_SYSC_R8A77970 is not set # CONFIG_SYSC_R8A779A0 is not set CONFIG_SYSC_R8A779G0=y CONFIG_SYSC_RMOBILE=y CONFIG_SYSC_R8A77470=y CONFIG_SYSC_R8A7745=y CONFIG_SYSC_R8A7742=y # CONFIG_SYSC_R8A7743 is not set CONFIG_SYSC_R8A774C0=y # CONFIG_SYSC_R8A774E1 is not set CONFIG_SYSC_R8A774A1=y # CONFIG_SYSC_R8A774B1 is not set CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y # CONFIG_ROCKCHIP_PM_DOMAINS is not set CONFIG_SOC_SAMSUNG=y CONFIG_EXYNOS_ASV_ARM=y CONFIG_EXYNOS_CHIPID=m CONFIG_EXYNOS_USI=m CONFIG_EXYNOS_PMU=y # CONFIG_EXYNOS_PMU_ARM_DRIVERS is not set # CONFIG_EXYNOS_PM_DOMAINS is not set # CONFIG_SAMSUNG_PM_CHECK is not set CONFIG_EXYNOS_REGULATOR_COUPLER=y # CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER is not set # CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER is not set # CONFIG_SOC_TI is not set # CONFIG_UX500_SOC_ID is not set CONFIG_SOC_INTEGRATOR_CM=y CONFIG_SOC_REALVIEW=y # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_PERFORMANCE=y # CONFIG_DEVFREQ_GOV_POWERSAVE is not set CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y CONFIG_ARM_IMX_BUS_DEVFREQ=m # CONFIG_ARM_TEGRA_DEVFREQ is not set # CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set # CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set CONFIG_PM_DEVFREQ_EVENT=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=y CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y CONFIG_EXTCON=y # # Extcon Device Drivers # # CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX14577 is not set CONFIG_EXTCON_MAX3355=y CONFIG_EXTCON_MAX77693=m CONFIG_EXTCON_MAX77843=m # CONFIG_EXTCON_MAX8997 is not set CONFIG_EXTCON_PALMAS=m CONFIG_EXTCON_PTN5150=y CONFIG_EXTCON_QCOM_SPMI_MISC=m CONFIG_EXTCON_RT8973A=y # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y # CONFIG_EXTCON_USBC_CROS_EC is not set # CONFIG_EXTCON_USBC_TUSB320 is not set CONFIG_MEMORY=y CONFIG_DDR=y CONFIG_ARM_PL172_MPMC=y CONFIG_ATMEL_SDRAMC=y # CONFIG_ATMEL_EBI is not set CONFIG_BRCMSTB_DPFE=y # CONFIG_BRCMSTB_MEMC is not set CONFIG_BT1_L2_CTL=y CONFIG_TI_AEMIF=y CONFIG_TI_EMIF=m # CONFIG_OMAP_GPMC is not set CONFIG_MVEBU_DEVBUS=y # CONFIG_FSL_CORENET_CF is not set # CONFIG_FSL_IFC is not set # CONFIG_JZ4780_NEMC is not set CONFIG_MTK_SMI=y CONFIG_DA8XX_DDRCTL=y CONFIG_PL353_SMC=m CONFIG_RENESAS_RPCIF=m # CONFIG_STM32_FMC2_EBI is not set CONFIG_SAMSUNG_MC=y CONFIG_EXYNOS5422_DMC=y CONFIG_EXYNOS_SROM=y CONFIG_TEGRA_MC=y CONFIG_TEGRA20_EMC=m CONFIG_TEGRA30_EMC=m CONFIG_TEGRA124_EMC=y CONFIG_TEGRA210_EMC_TABLE=y CONFIG_TEGRA210_EMC=m # CONFIG_IIO is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y CONFIG_PWM_DEBUG=y CONFIG_PWM_ATMEL=y CONFIG_PWM_ATMEL_HLCDC_PWM=m CONFIG_PWM_ATMEL_TCB=y CONFIG_PWM_BCM_IPROC=y CONFIG_PWM_BCM_KONA=y CONFIG_PWM_BCM2835=y CONFIG_PWM_BERLIN=y CONFIG_PWM_BRCMSTB=m # CONFIG_PWM_CLK is not set CONFIG_PWM_CLPS711X=m # CONFIG_PWM_CROS_EC is not set # CONFIG_PWM_EP93XX is not set CONFIG_PWM_FSL_FTM=m # CONFIG_PWM_HIBVT is not set CONFIG_PWM_IMG=y # CONFIG_PWM_IMX1 is not set # CONFIG_PWM_IMX27 is not set CONFIG_PWM_IMX_TPM=m CONFIG_PWM_INTEL_LGM=m CONFIG_PWM_IQS620A=y CONFIG_PWM_JZ4740=y CONFIG_PWM_KEEMBAY=m # CONFIG_PWM_LPC18XX_SCT is not set # CONFIG_PWM_LPC32XX is not set CONFIG_PWM_LPSS=m CONFIG_PWM_LPSS_PLATFORM=m CONFIG_PWM_MESON=y CONFIG_PWM_MTK_DISP=y CONFIG_PWM_MEDIATEK=m CONFIG_PWM_MXS=m # CONFIG_PWM_NTXEC is not set CONFIG_PWM_OMAP_DMTIMER=y # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_PXA=y # CONFIG_PWM_RASPBERRYPI_POE is not set CONFIG_PWM_RCAR=y # CONFIG_PWM_RENESAS_TPU is not set CONFIG_PWM_ROCKCHIP=m CONFIG_PWM_SAMSUNG=m # CONFIG_PWM_SIFIVE is not set CONFIG_PWM_SL28CPLD=m # CONFIG_PWM_SPEAR is not set # CONFIG_PWM_SPRD is not set # CONFIG_PWM_STI is not set CONFIG_PWM_STM32=y # CONFIG_PWM_STM32_LP is not set # CONFIG_PWM_STMPE is not set # CONFIG_PWM_SUN4I is not set # CONFIG_PWM_SUNPLUS is not set CONFIG_PWM_TEGRA=y CONFIG_PWM_TIECAP=m CONFIG_PWM_TIEHRPWM=y # CONFIG_PWM_VISCONTI is not set CONFIG_PWM_VT8500=m CONFIG_PWM_XILINX=y # # IRQ chip support # CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=2 CONFIG_ARM_VIC=y CONFIG_ARM_VIC_NR=2 CONFIG_AL_FIC=y CONFIG_MADERA_IRQ=m # CONFIG_JCORE_AIC is not set CONFIG_RENESAS_INTC_IRQPIN=y # CONFIG_RENESAS_IRQC is not set CONFIG_RENESAS_RZA1_IRQC=y # CONFIG_RENESAS_RZG2L_IRQC is not set # CONFIG_SL28CPLD_INTC is not set # CONFIG_TS4800_IRQ is not set CONFIG_VERSATILE_FPGA_IRQ=y CONFIG_VERSATILE_FPGA_IRQ_NR=4 # CONFIG_XILINX_INTC is not set # CONFIG_INGENIC_TCU_IRQ is not set CONFIG_IRQ_UNIPHIER_AIDET=y # CONFIG_MESON_IRQ_GPIO is not set CONFIG_IMX_IRQSTEER=y # CONFIG_IMX_INTMUX is not set CONFIG_EXYNOS_IRQ_COMBINER=y CONFIG_MST_IRQ=y # CONFIG_MCHP_EIC is not set # CONFIG_SUNPLUS_SP7021_INTC is not set # end of IRQ chip support CONFIG_IPACK_BUS=y CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_A10SR=y CONFIG_RESET_ATH79=y CONFIG_RESET_AXS10X=y CONFIG_RESET_BCM6345=y CONFIG_RESET_BERLIN=y # CONFIG_RESET_BRCMSTB is not set CONFIG_RESET_BRCMSTB_RESCAL=m CONFIG_RESET_HSDK=y # CONFIG_RESET_IMX7 is not set # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_K210 is not set CONFIG_RESET_LANTIQ=y CONFIG_RESET_LPC18XX=y # CONFIG_RESET_MCHP_SPARX5 is not set CONFIG_RESET_MESON=y CONFIG_RESET_MESON_AUDIO_ARB=m # CONFIG_RESET_NPCM is not set CONFIG_RESET_OXNAS=y # CONFIG_RESET_PISTACHIO is not set # CONFIG_RESET_QCOM_AOSS is not set CONFIG_RESET_QCOM_PDC=y CONFIG_RESET_RASPBERRYPI=m # CONFIG_RESET_RZG2L_USBPHY_CTRL is not set CONFIG_RESET_SCMI=y CONFIG_RESET_SIMPLE=y # CONFIG_RESET_SOCFPGA is not set # CONFIG_RESET_STARFIVE_JH7100 is not set # CONFIG_RESET_SUNPLUS is not set # CONFIG_RESET_SUNXI is not set CONFIG_RESET_TI_SCI=y CONFIG_RESET_TI_SYSCON=m CONFIG_RESET_TI_TPS380X=y CONFIG_RESET_TN48M_CPLD=m # CONFIG_RESET_UNIPHIER is not set CONFIG_RESET_UNIPHIER_GLUE=y # CONFIG_RESET_ZYNQ is not set CONFIG_COMMON_RESET_HI3660=m CONFIG_COMMON_RESET_HI6220=y # # PHY Subsystem # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y CONFIG_PHY_LPC18XX_USB_OTG=m CONFIG_PHY_PISTACHIO_USB=y CONFIG_PHY_XGENE=m CONFIG_PHY_CAN_TRANSCEIVER=m CONFIG_PHY_SUN6I_MIPI_DPHY=m CONFIG_PHY_SUN50I_USB3=m # CONFIG_PHY_MESON8_HDMI_TX is not set CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=y CONFIG_PHY_MESON_G12A_USB2=y CONFIG_PHY_MESON_G12A_USB3_PCIE=y CONFIG_PHY_MESON_AXG_PCIE=m # CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set CONFIG_PHY_MESON_AXG_MIPI_DPHY=m # # PHY drivers for Broadcom platforms # CONFIG_PHY_BCM63XX_USBH=m CONFIG_PHY_CYGNUS_PCIE=y CONFIG_PHY_BCM_SR_USB=m # CONFIG_BCM_KONA_USB2_PHY is not set CONFIG_PHY_BCM_NS_USB2=y # CONFIG_PHY_NS2_USB_DRD is not set CONFIG_PHY_BRCM_SATA=m # CONFIG_PHY_BRCM_USB is not set CONFIG_PHY_BCM_SR_PCIE=y # end of PHY drivers for Broadcom platforms # CONFIG_PHY_CADENCE_TORRENT is not set CONFIG_PHY_CADENCE_DPHY=y CONFIG_PHY_CADENCE_DPHY_RX=m # CONFIG_PHY_CADENCE_SIERRA is not set CONFIG_PHY_CADENCE_SALVO=m CONFIG_PHY_FSL_IMX8MQ_USB=m # CONFIG_PHY_MIXEL_LVDS_PHY is not set CONFIG_PHY_MIXEL_MIPI_DPHY=m CONFIG_PHY_FSL_IMX8M_PCIE=m # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_HI6220_USB is not set CONFIG_PHY_HI3660_USB=y CONFIG_PHY_HI3670_USB=m # CONFIG_PHY_HI3670_PCIE is not set CONFIG_PHY_HISTB_COMBPHY=m # CONFIG_PHY_HISI_INNO_USB2 is not set CONFIG_PHY_LANTIQ_VRX200_PCIE=m # CONFIG_PHY_LANTIQ_RCU_USB2 is not set CONFIG_ARMADA375_USBCLUSTER_PHY=y # CONFIG_PHY_BERLIN_SATA is not set CONFIG_PHY_BERLIN_USB=y CONFIG_PHY_MVEBU_A3700_UTMI=m # CONFIG_PHY_MVEBU_A38X_COMPHY is not set CONFIG_PHY_PXA_28NM_HSIC=m CONFIG_PHY_PXA_28NM_USB2=y CONFIG_PHY_PXA_USB=y # CONFIG_PHY_MMP3_USB is not set CONFIG_PHY_MMP3_HSIC=y CONFIG_PHY_MTK_PCIE=m CONFIG_PHY_MTK_TPHY=m CONFIG_PHY_MTK_UFS=y # CONFIG_PHY_MTK_XSPHY is not set CONFIG_PHY_MTK_HDMI=y # CONFIG_PHY_MTK_MIPI_DSI is not set CONFIG_PHY_MTK_DP=m CONFIG_PHY_SPARX5_SERDES=m CONFIG_PHY_LAN966X_SERDES=y CONFIG_PHY_OCELOT_SERDES=m # CONFIG_PHY_ATH79_USB is not set CONFIG_PHY_QCOM_EDP=m CONFIG_PHY_QCOM_IPQ4019_USB=y CONFIG_PHY_QCOM_PCIE2=y CONFIG_PHY_QCOM_QMP=m CONFIG_PHY_QCOM_QUSB2=m CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y CONFIG_PHY_QCOM_USB_HS_28NM=m # CONFIG_PHY_QCOM_USB_SS is not set CONFIG_PHY_QCOM_IPQ806X_USB=m # CONFIG_PHY_MT7621_PCI is not set CONFIG_PHY_RALINK_USB=y CONFIG_PHY_RCAR_GEN3_USB3=m # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m # CONFIG_PHY_ROCKCHIP_PCIE is not set CONFIG_PHY_ROCKCHIP_TYPEC=m CONFIG_PHY_EXYNOS_DP_VIDEO=y CONFIG_PHY_EXYNOS_MIPI_VIDEO=m CONFIG_PHY_EXYNOS_PCIE=y # CONFIG_PHY_SAMSUNG_UFS is not set CONFIG_PHY_SAMSUNG_USB2=y CONFIG_PHY_S5PV210_USB2=y CONFIG_PHY_UNIPHIER_USB2=m # CONFIG_PHY_UNIPHIER_USB3 is not set CONFIG_PHY_UNIPHIER_PCIE=y CONFIG_PHY_UNIPHIER_AHCI=y # CONFIG_PHY_ST_SPEAR1310_MIPHY is not set # CONFIG_PHY_ST_SPEAR1340_MIPHY is not set CONFIG_PHY_STIH407_USB=m # CONFIG_PHY_STM32_USBPHYC is not set CONFIG_PHY_TEGRA194_P2U=y CONFIG_PHY_DA8XX_USB=y CONFIG_PHY_AM654_SERDES=y # CONFIG_PHY_J721E_WIZ is not set CONFIG_OMAP_CONTROL_PHY=m CONFIG_TI_PIPE3=m CONFIG_PHY_INTEL_KEEMBAY_EMMC=m CONFIG_PHY_INTEL_KEEMBAY_USB=y CONFIG_PHY_INTEL_LGM_COMBO=y # CONFIG_PHY_INTEL_LGM_EMMC is not set CONFIG_PHY_INTEL_THUNDERBAY_EMMC=y # CONFIG_PHY_XILINX_ZYNQMP is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set CONFIG_MCB=y CONFIG_MCB_LPC=y # # Performance monitor support # CONFIG_ARM_CCN=y # CONFIG_ARM_CMN is not set # CONFIG_ARM_PMU is not set CONFIG_FSL_IMX8_DDR_PMU=y CONFIG_ARM_DMC620_PMU=m # end of Performance monitor support CONFIG_RAS=y # # Android # # CONFIG_ANDROID_BINDER_IPC is not set # end of Android CONFIG_DAX=m CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_IMX_IIM=m CONFIG_NVMEM_IMX_OCOTP=y # CONFIG_JZ4780_EFUSE is not set # CONFIG_NVMEM_LPC18XX_EEPROM is not set # CONFIG_NVMEM_LPC18XX_OTP is not set CONFIG_NVMEM_MXS_OCOTP=y CONFIG_MTK_EFUSE=m CONFIG_MICROCHIP_OTPC=y # CONFIG_NVMEM_NINTENDO_OTP is not set CONFIG_QCOM_QFPROM=y # CONFIG_NVMEM_SPMI_SDAM is not set # CONFIG_ROCKCHIP_EFUSE is not set CONFIG_ROCKCHIP_OTP=y CONFIG_NVMEM_BCM_OCOTP=m CONFIG_NVMEM_STM32_ROMEM=y # CONFIG_UNIPHIER_EFUSE is not set CONFIG_NVMEM_VF610_OCOTP=m CONFIG_MESON_MX_EFUSE=m # CONFIG_NVMEM_SNVS_LPGPR is not set CONFIG_RAVE_SP_EEPROM=m CONFIG_SC27XX_EFUSE=y # CONFIG_SPRD_EFUSE is not set CONFIG_NVMEM_RMEM=m CONFIG_NVMEM_BRCM_NVRAM=m CONFIG_NVMEM_LAYERSCAPE_SFP=y # CONFIG_NVMEM_SUNPLUS_OCOTP is not set # CONFIG_NVMEM_APPLE_EFUSES is not set # # HW tracing support # CONFIG_STM=y CONFIG_STM_PROTO_BASIC=m # CONFIG_STM_PROTO_SYS_T is not set CONFIG_STM_DUMMY=m CONFIG_STM_SOURCE_CONSOLE=m CONFIG_STM_SOURCE_HEARTBEAT=y CONFIG_STM_SOURCE_FTRACE=y CONFIG_INTEL_TH=m CONFIG_INTEL_TH_GTH=m # CONFIG_INTEL_TH_STH is not set CONFIG_INTEL_TH_MSU=m CONFIG_INTEL_TH_PTI=m CONFIG_INTEL_TH_DEBUG=y # end of HW tracing support CONFIG_FPGA=m CONFIG_FPGA_MGR_SOCFPGA=m # CONFIG_FPGA_MGR_SOCFPGA_A10 is not set CONFIG_ALTERA_PR_IP_CORE=m CONFIG_ALTERA_PR_IP_CORE_PLAT=m CONFIG_FPGA_MGR_ZYNQ_FPGA=m # CONFIG_FPGA_BRIDGE is not set # CONFIG_FPGA_DFL is not set CONFIG_FPGA_MGR_ZYNQMP_FPGA=m CONFIG_FPGA_MGR_VERSAL_FPGA=m # CONFIG_FSI is not set CONFIG_TEE=y CONFIG_MULTIPLEXER=y # # Multiplexer drivers # # CONFIG_MUX_ADG792A is not set CONFIG_MUX_GPIO=y CONFIG_MUX_MMIO=y # end of Multiplexer drivers CONFIG_PM_OPP=y # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set CONFIG_INTERCONNECT=y # CONFIG_INTERCONNECT_IMX is not set CONFIG_INTERCONNECT_QCOM_OSM_L3=y CONFIG_INTERCONNECT_SAMSUNG=y CONFIG_INTERCONNECT_EXYNOS=y CONFIG_COUNTER=m # CONFIG_104_QUAD_8 is not set CONFIG_INTERRUPT_CNT=m CONFIG_STM32_TIMER_CNT=m CONFIG_STM32_LPTIMER_CNT=m CONFIG_TI_EQEP=m # CONFIG_FTM_QUADDEC is not set CONFIG_MICROCHIP_TCB_CAPTURE=m # CONFIG_MOST is not set CONFIG_PECI=y CONFIG_PECI_CPU=m # CONFIG_PECI_ASPEED is not set CONFIG_HTE=y # end of Device Drivers # # File systems # CONFIG_DCACHE_WORD_ACCESS=y # CONFIG_VALIDATE_FS_PARSER is not set CONFIG_EXPORTFS=m # CONFIG_EXPORTFS_BLOCK_OPS is not set # CONFIG_FILE_LOCKING is not set CONFIG_FS_ENCRYPTION=y CONFIG_FS_VERITY=y CONFIG_FS_VERITY_DEBUG=y CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_FANOTIFY is not set CONFIG_QUOTA=y # CONFIG_PRINT_QUOTA_WARNING is not set # CONFIG_QUOTA_DEBUG is not set CONFIG_QUOTA_TREE=m CONFIG_QFMT_V1=y CONFIG_QFMT_V2=m CONFIG_QUOTACTL=y # CONFIG_AUTOFS4_FS is not set CONFIG_AUTOFS_FS=m # CONFIG_FUSE_FS is not set CONFIG_OVERLAY_FS=m CONFIG_OVERLAY_FS_REDIRECT_DIR=y CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set # CONFIG_OVERLAY_FS_METACOPY is not set # # Caches # CONFIG_NETFS_SUPPORT=y CONFIG_NETFS_STATS=y CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_DEBUG is not set # end of Caches # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_PROC_CHILDREN=y CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set CONFIG_TMPFS_XATTR=y CONFIG_MEMFD_CREATE=y CONFIG_CONFIGFS_FS=y # end of Pseudo filesystems # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_737=y # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_852 is not set CONFIG_NLS_CODEPAGE_855=y CONFIG_NLS_CODEPAGE_857=y CONFIG_NLS_CODEPAGE_860=y # CONFIG_NLS_CODEPAGE_861 is not set CONFIG_NLS_CODEPAGE_862=y CONFIG_NLS_CODEPAGE_863=y # CONFIG_NLS_CODEPAGE_864 is not set CONFIG_NLS_CODEPAGE_865=y # CONFIG_NLS_CODEPAGE_866 is not set CONFIG_NLS_CODEPAGE_869=m CONFIG_NLS_CODEPAGE_936=y # CONFIG_NLS_CODEPAGE_950 is not set CONFIG_NLS_CODEPAGE_932=y CONFIG_NLS_CODEPAGE_949=y # CONFIG_NLS_CODEPAGE_874 is not set CONFIG_NLS_ISO8859_8=m # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set CONFIG_NLS_ASCII=m CONFIG_NLS_ISO8859_1=m CONFIG_NLS_ISO8859_2=y # CONFIG_NLS_ISO8859_3 is not set CONFIG_NLS_ISO8859_4=y CONFIG_NLS_ISO8859_5=m CONFIG_NLS_ISO8859_6=y CONFIG_NLS_ISO8859_7=y CONFIG_NLS_ISO8859_9=y CONFIG_NLS_ISO8859_13=y CONFIG_NLS_ISO8859_14=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m # CONFIG_NLS_MAC_ROMAN is not set CONFIG_NLS_MAC_CELTIC=y # CONFIG_NLS_MAC_CENTEURO is not set CONFIG_NLS_MAC_CROATIAN=m # CONFIG_NLS_MAC_CYRILLIC is not set CONFIG_NLS_MAC_GAELIC=m CONFIG_NLS_MAC_GREEK=m CONFIG_NLS_MAC_ICELAND=m # CONFIG_NLS_MAC_INUIT is not set # CONFIG_NLS_MAC_ROMANIAN is not set # CONFIG_NLS_MAC_TURKISH is not set # CONFIG_NLS_UTF8 is not set # CONFIG_UNICODE is not set CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y # CONFIG_KEYS_REQUEST_CACHE is not set CONFIG_PERSISTENT_KEYRINGS=y # CONFIG_TRUSTED_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set # CONFIG_KEY_DH_OPERATIONS is not set CONFIG_SECURITY_DMESG_RESTRICT=y # CONFIG_SECURITYFS is not set CONFIG_FORTIFY_SOURCE=y # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" # # Kernel hardening options # # # Memory initialization # CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INIT_STACK_ALL_PATTERN=y # CONFIG_INIT_STACK_ALL_ZERO is not set # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # CONFIG_ZERO_CALL_USED_REGS is not set # end of Memory initialization # CONFIG_RANDSTRUCT_NONE is not set CONFIG_RANDSTRUCT_FULL=y # CONFIG_RANDSTRUCT_PERFORMANCE is not set CONFIG_RANDSTRUCT=y CONFIG_GCC_PLUGIN_RANDSTRUCT=y # end of Kernel hardening options # end of Security options CONFIG_XOR_BLOCKS=y CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y CONFIG_CRYPTO_TEST=y # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=m # CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=y CONFIG_CRYPTO_ECDSA=m CONFIG_CRYPTO_ECRDSA=y CONFIG_CRYPTO_SM2=y # CONFIG_CRYPTO_CURVE25519 is not set # # Authenticated Encryption with Associated Data # CONFIG_CRYPTO_CCM=y # CONFIG_CRYPTO_GCM is not set CONFIG_CRYPTO_CHACHA20POLY1305=m CONFIG_CRYPTO_AEGIS128=m CONFIG_CRYPTO_SEQIV=m CONFIG_CRYPTO_ECHAINIV=m # # Block modes # # CONFIG_CRYPTO_CBC is not set CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_LRW=m # CONFIG_CRYPTO_OFB is not set CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XCTR=m CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_KEYWRAP=y CONFIG_CRYPTO_NHPOLY1305=y CONFIG_CRYPTO_ADIANTUM=y CONFIG_CRYPTO_HCTR2=m CONFIG_CRYPTO_ESSIV=y # # Hash modes # # CONFIG_CRYPTO_CMAC is not set CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_VMAC is not set # # Digest # CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_CRC32 is not set CONFIG_CRYPTO_XXHASH=m CONFIG_CRYPTO_BLAKE2B=y CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRC64_ROCKSOFT=m CONFIG_CRYPTO_GHASH=m CONFIG_CRYPTO_POLYVAL=m CONFIG_CRYPTO_POLY1305=y CONFIG_CRYPTO_MD4=m # CONFIG_CRYPTO_MD5 is not set # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_RMD160 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_SM3=y CONFIG_CRYPTO_SM3_GENERIC=y CONFIG_CRYPTO_STREEBOG=y CONFIG_CRYPTO_WP512=y # # Ciphers # CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_AES_TI=m # CONFIG_CRYPTO_BLOWFISH is not set CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST_COMMON=y CONFIG_CRYPTO_CAST5=y CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_FCRYPT=y CONFIG_CRYPTO_CHACHA20=y # CONFIG_CRYPTO_ARIA is not set CONFIG_CRYPTO_SERPENT=y # CONFIG_CRYPTO_SM4_GENERIC is not set # CONFIG_CRYPTO_TWOFISH is not set # # Compression # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_842=m CONFIG_CRYPTO_LZ4=y # CONFIG_CRYPTO_LZ4HC is not set CONFIG_CRYPTO_ZSTD=y # # Random Number Generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_HASH=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_HASH_INFO=y # CONFIG_CRYPTO_HW is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS8_PRIVATE_KEY_PARSER=y CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=m # CONFIG_SIGNED_PE_FILE_VERIFICATION is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" CONFIG_MODULE_SIG_KEY_TYPE_RSA=y # CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" CONFIG_SYSTEM_EXTRA_CERTIFICATE=y CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 # CONFIG_SECONDARY_TRUSTED_KEYRING is not set CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" # CONFIG_SYSTEM_REVOCATION_LIST is not set CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y # # Library routines # CONFIG_LINEAR_RANGES=y CONFIG_PACKING=y CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y # CONFIG_CORDIC is not set CONFIG_PRIME_NUMBERS=y CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_STMP_DEVICE=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA=m # CONFIG_CRYPTO_LIB_CURVE25519 is not set CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=y CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines CONFIG_LIB_MEMNEQ=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y # CONFIG_CRC64_ROCKSOFT is not set CONFIG_CRC_ITU_T=y CONFIG_CRC32=y CONFIG_CRC32_SELFTEST=m CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set CONFIG_CRC64=m # CONFIG_CRC4 is not set CONFIG_CRC7=m CONFIG_LIBCRC32C=m CONFIG_CRC8=m CONFIG_XXHASH=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_842_COMPRESS=m CONFIG_842_DECOMPRESS=m CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y # CONFIG_XZ_DEC_POWERPC is not set # CONFIG_XZ_DEC_IA64 is not set CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y # CONFIG_XZ_DEC_SPARC is not set CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_BCJ=y CONFIG_XZ_DEC_TEST=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_CMA=y # CONFIG_DMA_PERNUMA_CMA is not set # # Default contiguous memory area size: # CONFIG_CMA_SIZE_PERCENTAGE=10 # CONFIG_CMA_SIZE_SEL_MBYTES is not set CONFIG_CMA_SIZE_SEL_PERCENTAGE=y # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 CONFIG_DMA_API_DEBUG=y # CONFIG_DMA_API_DEBUG_SG is not set CONFIG_DMA_MAP_BENCHMARK=y CONFIG_SGL_ALLOC=y CONFIG_GLOB=y CONFIG_GLOB_SELFTEST=y CONFIG_GENERIC_ATOMIC64=y CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_STACKDEPOT=y # CONFIG_PARMAN is not set # CONFIG_OBJAGG is not set # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_POLYNOMIAL=y # # Kernel hacking # # # printk and dmesg options # CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set CONFIG_STACKTRACE_BUILD_ID=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_DYNAMIC_DEBUG_CORE is not set CONFIG_SYMBOLIC_ERRNAME=y # CONFIG_DEBUG_BUGVERBOSE is not set # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_MISC is not set # # Compile-time checks and compiler options # CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_NONE is not set CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_DEBUG_INFO_REDUCED=y # CONFIG_DEBUG_INFO_COMPRESSED is not set CONFIG_DEBUG_INFO_SPLIT=y CONFIG_PAHOLE_HAS_SPLIT_BTF=y CONFIG_GDB_SCRIPTS=y CONFIG_FRAME_WARN=1024 CONFIG_STRIP_ASM_SYMS=y # CONFIG_READABLE_ASM is not set CONFIG_HEADERS_INSTALL=y CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_VMLINUX_MAP=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # # CONFIG_MAGIC_SYSRQ is not set CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set CONFIG_UBSAN=y CONFIG_CC_HAS_UBSAN_BOUNDS=y # CONFIG_UBSAN_BOUNDS is not set # CONFIG_UBSAN_SHIFT is not set CONFIG_UBSAN_DIV_ZERO=y # CONFIG_UBSAN_UNREACHABLE is not set CONFIG_UBSAN_BOOL=y CONFIG_UBSAN_ENUM=y CONFIG_TEST_UBSAN=m CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments # # Networking Debugging # # CONFIG_NET_DEV_REFCNT_TRACKER is not set # CONFIG_NET_NS_REFCNT_TRACKER is not set # end of Networking Debugging # # Memory Debugging # CONFIG_PAGE_EXTENSION=y # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_PAGE_OWNER=y CONFIG_PAGE_POISONING=y # CONFIG_DEBUG_PAGE_REF is not set CONFIG_DEBUG_WX=y # CONFIG_DEBUG_OBJECTS is not set CONFIG_SHRINKER_DEBUG=y CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set CONFIG_DEBUG_STACK_USAGE=y # CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_DEBUG_VM=y CONFIG_DEBUG_VM_VMACACHE=y CONFIG_DEBUG_VM_RB=y # CONFIG_DEBUG_VM_PGFLAGS is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y CONFIG_DEBUG_VIRTUAL=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_DEBUG_KMAP_LOCAL=y CONFIG_DEBUG_HIGHMEM=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y CONFIG_HAVE_ARCH_KFENCE=y # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y # # Debug Oops, Lockups and Hangs # CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_ON_OOPS_VALUE=1 CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y # CONFIG_WQ_WATCHDOG is not set CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y # end of Scheduler Debugging CONFIG_DEBUG_TIMEKEEPING=y # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_PROVE_LOCKING is not set # CONFIG_LOCK_STAT is not set CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y CONFIG_LOCKDEP_BITS=15 CONFIG_LOCKDEP_CHAINS_BITS=16 CONFIG_LOCKDEP_STACK_TRACE_BITS=19 CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 CONFIG_DEBUG_LOCKDEP=y CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set CONFIG_LOCK_TORTURE_TEST=y CONFIG_WW_MUTEX_SELFTEST=m CONFIG_SCF_TORTURE_TEST=m # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_DEBUG_IRQFLAGS=y CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set # # Debug kernel data structures # # CONFIG_DEBUG_LIST is not set CONFIG_DEBUG_PLIST=y # CONFIG_DEBUG_SG is not set CONFIG_DEBUG_NOTIFIERS=y # CONFIG_BUG_ON_DATA_CORRUPTION is not set # end of Debug kernel data structures # CONFIG_DEBUG_CREDENTIALS is not set # # RCU Debugging # CONFIG_TORTURE_TEST=y CONFIG_RCU_SCALE_TEST=m # CONFIG_RCU_TORTURE_TEST is not set CONFIG_RCU_REF_SCALE_TEST=y # CONFIG_RCU_TRACE is not set CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging CONFIG_DEBUG_WQ_FORCE_RR_CPU=y # CONFIG_LATENCYTOP is not set CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_TRACING=y CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y CONFIG_BOOTTIME_TRACING=y CONFIG_FUNCTION_TRACER=y # CONFIG_FUNCTION_GRAPH_TRACER is not set CONFIG_DYNAMIC_FTRACE=y CONFIG_DYNAMIC_FTRACE_WITH_REGS=y # CONFIG_FUNCTION_PROFILER is not set # CONFIG_STACK_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set CONFIG_HWLAT_TRACER=y CONFIG_OSNOISE_TRACER=y CONFIG_TIMERLAT_TRACER=y # CONFIG_FTRACE_SYSCALLS is not set # CONFIG_TRACER_SNAPSHOT is not set CONFIG_TRACE_BRANCH_PROFILING=y # CONFIG_BRANCH_PROFILE_NONE is not set CONFIG_PROFILE_ANNOTATED_BRANCHES=y CONFIG_TRACING_BRANCHES=y CONFIG_BRANCH_TRACER=y CONFIG_KPROBE_EVENTS=y CONFIG_KPROBE_EVENTS_ON_NOTRACE=y CONFIG_UPROBE_EVENTS=y CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y CONFIG_FTRACE_MCOUNT_RECORD=y CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y CONFIG_SYNTH_EVENTS=y CONFIG_USER_EVENTS=y # CONFIG_HIST_TRIGGERS is not set # CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set CONFIG_RING_BUFFER_BENCHMARK=y CONFIG_TRACE_EVAL_MAP_FILE=y # CONFIG_FTRACE_RECORD_RECURSION is not set # CONFIG_FTRACE_STARTUP_TEST is not set CONFIG_FTRACE_SORT_STARTUP_TEST=y # CONFIG_RING_BUFFER_STARTUP_TEST is not set CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS=y CONFIG_PREEMPTIRQ_DELAY_TEST=m CONFIG_SYNTH_EVENT_GEN_TEST=y CONFIG_KPROBE_EVENT_GEN_TEST=y CONFIG_DA_MON_EVENTS=y CONFIG_DA_MON_EVENTS_ID=y CONFIG_RV=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PRINTK=y CONFIG_RV_REACT_PANIC=y # CONFIG_SAMPLES is not set # # arm Debugging # CONFIG_ARM_PTDUMP_CORE=y # CONFIG_ARM_PTDUMP_DEBUGFS is not set # CONFIG_UNWINDER_FRAME_POINTER is not set CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y # CONFIG_BACKTRACE_VERBOSE is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_INTEGRATOR=y # CONFIG_DEBUG_REALVIEW_STD_PORT is not set # CONFIG_DEBUG_S3C_UART0 is not set # CONFIG_DEBUG_S3C_UART1 is not set # CONFIG_DEBUG_S3C_UART2 is not set # CONFIG_DEBUG_ICEDCC is not set # CONFIG_DEBUG_SEMIHOSTING is not set # CONFIG_DEBUG_LL_UART_8250 is not set # CONFIG_DEBUG_LL_UART_PL01X is not set CONFIG_DEBUG_UART_FLOW_CONTROL=y CONFIG_DEBUG_LL_INCLUDE="debug/pl01x.S" CONFIG_DEBUG_UART_PL01X=y CONFIG_DEBUG_UART_PHYS=0x16000000 CONFIG_DEBUG_UART_VIRT=0xf1600000 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" # CONFIG_EARLY_PRINTK is not set # CONFIG_ARM_KPROBES_TEST is not set # CONFIG_PID_IN_CONTEXTIDR is not set CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINKS_AND_SINKS=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m CONFIG_CORESIGHT_CATU=m # CONFIG_CORESIGHT_SINK_TPIU is not set CONFIG_CORESIGHT_SINK_ETBV10=m CONFIG_CORESIGHT_SOURCE_ETM3X=m CONFIG_CORESIGHT_STM=y CONFIG_CORESIGHT_CPU_DEBUG=m CONFIG_CORESIGHT_CPU_DEBUG_DEFAULT_ON=y CONFIG_CORESIGHT_CTI=m CONFIG_CORESIGHT_CTI_INTEGRATION_REGS=y # end of arm Debugging # # Kernel Testing and Coverage # # CONFIG_KUNIT is not set CONFIG_NOTIFIER_ERROR_INJECTION=m CONFIG_PM_NOTIFIER_ERROR_INJECT=m CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=m # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_KCOV=y CONFIG_KCOV_ENABLE_COMPARISONS=y CONFIG_KCOV_INSTRUMENT_ALL=y CONFIG_KCOV_IRQ_AREA_SIZE=0x40000 # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # CONFIG_WARN_MISSING_DOCUMENTS is not set CONFIG_WARN_ABI_ERRORS=y # end of Kernel hacking ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree 2022-09-22 20:24 ` Mauri Sandberg ` (3 preceding siblings ...) (?) @ 2022-09-27 22:56 ` kernel test robot -1 siblings, 0 replies; 91+ messages in thread From: kernel test robot @ 2022-09-27 22:56 UTC (permalink / raw) To: Mauri Sandberg, robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: llvm, kbuild-all, pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg [-- Attachment #1: Type: text/plain, Size: 2035 bytes --] Hi Mauri, Thank you for the patch! Yet something to improve: [auto build test ERROR on soc/for-next] [also build test ERROR on robh/for-next linus/master v6.0-rc7 next-20220927] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Mauri-Sandberg/dt-bindings-arm-add-DT-binding-for-D-Link-DNS-323/20220923-052532 base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next config: arm-buildonly-randconfig-r004-20220925 compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi # https://github.com/intel-lab-lkp/linux/commit/0f6a5f2ac9a2b3e3cf1b2c1969a1ad077cd54d2c git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Mauri-Sandberg/dt-bindings-arm-add-DT-binding-for-D-Link-DNS-323/20220923-052532 git checkout 0f6a5f2ac9a2b3e3cf1b2c1969a1ad077cd54d2c # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): Error: arch/arm/boot/dts/orion5x-dlink-dns323.dtsi:209.1-7 Label or path pciec not found Error: arch/arm/boot/dts/orion5x-dlink-dns323.dtsi:213.1-7 Label or path pcie0 not found >> FATAL ERROR: Syntax error parsing input tree -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 144349 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/arm 6.0.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="clang version 16.0.0 (git://gitmirror/llvm_project 791a7ae1ba3efd6bca96338e10ffde557ba83920)" CONFIG_GCC_VERSION=0 CONFIG_CC_IS_CLANG=y CONFIG_CLANG_VERSION=160000 CONFIG_AS_IS_LLVM=y CONFIG_AS_VERSION=160000 CONFIG_LD_VERSION=0 CONFIG_LD_IS_LLD=y CONFIG_LLD_VERSION=160000 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_TOOLS_SUPPORT_RELR=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_COMPILE_TEST=y # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y # CONFIG_KERNEL_GZIP is not set CONFIG_KERNEL_LZMA=y # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_WATCH_QUEUE is not set # CONFIG_CROSS_MEMORY_ATTACH is not set # CONFIG_USELIB is not set CONFIG_AUDIT=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_IRQ_INJECTION=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y CONFIG_GENERIC_IRQ_DEBUGFS=y # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_TIME_KUNIT_TEST=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem CONFIG_BPF=y CONFIG_HAVE_EBPF_JIT=y # # BPF subsystem # CONFIG_BPF_SYSCALL=y CONFIG_BPF_JIT=y CONFIG_BPF_JIT_ALWAYS_ON=y CONFIG_BPF_JIT_DEFAULT_ON=y CONFIG_BPF_UNPRIV_DEFAULT_OFF=y CONFIG_USERMODE_DRIVER=y # end of BPF subsystem CONFIG_PREEMPT_VOLUNTARY_BUILD=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set CONFIG_PREEMPT_COUNT=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_IRQ_TIME_ACCOUNTING is not set CONFIG_PSI=y # CONFIG_PSI_DEFAULT_DISABLED is not set # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TINY_RCU=y CONFIG_RCU_EXPERT=y CONFIG_SRCU=y CONFIG_TINY_SRCU=y CONFIG_TASKS_RCU_GENERIC=y # CONFIG_FORCE_TASKS_RCU is not set # CONFIG_FORCE_TASKS_RUDE_RCU is not set CONFIG_FORCE_TASKS_TRACE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_TASKS_TRACE_RCU_READ_MB=y # end of RCU Subsystem CONFIG_IKCONFIG=m # CONFIG_IKCONFIG_PROC is not set CONFIG_IKHEADERS=y CONFIG_GENERIC_SCHED_CLOCK=y # # Scheduler features # # end of Scheduler features CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_CGROUP_FAVOR_DYNMODS=y CONFIG_MEMCG=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y # CONFIG_CFS_BANDWIDTH is not set # CONFIG_RT_GROUP_SCHED is not set # CONFIG_CGROUP_PIDS is not set CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_DEVICE=y # CONFIG_CGROUP_CPUACCT is not set CONFIG_CGROUP_PERF=y # CONFIG_CGROUP_BPF is not set CONFIG_CGROUP_MISC=y # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y # CONFIG_RD_LZMA is not set CONFIG_RD_XZ=y CONFIG_RD_LZO=y # CONFIG_RD_LZ4 is not set # CONFIG_RD_ZSTD is not set # CONFIG_BOOT_CONFIG is not set CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_EXPERT=y # CONFIG_MULTIUSER is not set CONFIG_SGETMASK_SYSCALL=y # CONFIG_SYSFS_SYSCALL is not set # CONFIG_FHANDLE is not set # CONFIG_POSIX_TIMERS is not set # CONFIG_PRINTK is not set CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y # CONFIG_AIO is not set # CONFIG_IO_URING is not set CONFIG_ADVISE_SYSCALLS=y # CONFIG_MEMBARRIER is not set CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y # CONFIG_RSEQ is not set CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y # CONFIG_PC104 is not set # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y # CONFIG_PROFILING is not set # end of General setup CONFIG_ARM=y CONFIG_ARM_DMA_USE_IOMMU=y CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_TCM=y CONFIG_HAVE_PROC_CPU=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_GENERIC_BUG=y CONFIG_PGTABLE_LEVELS=2 # # System Type # CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y # # Platform selection # # # CPU Core family selection # # CONFIG_ARCH_MULTI_V4 is not set # CONFIG_ARCH_MULTI_V4T is not set CONFIG_ARCH_MULTI_V5=y CONFIG_ARCH_MULTI_V4_V5=y # CONFIG_ARCH_MULTI_V6 is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MULTI_CPU_AUTO=y # end of Platform selection # CONFIG_MACH_ASM9260 is not set # CONFIG_ARCH_ASPEED is not set CONFIG_ARCH_AT91=y CONFIG_SOC_AT91SAM9=y # CONFIG_SOC_SAM9X60 is not set # # Clocksource driver selection # # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set # CONFIG_ATMEL_CLOCKSOURCE_TCB is not set CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y CONFIG_HAVE_AT91_UTMI=y CONFIG_HAVE_AT91_USB_CLK=y CONFIG_COMMON_CLK_AT91=y CONFIG_HAVE_AT91_SMD=y CONFIG_SOC_SAM_V4_V5=y CONFIG_ATMEL_PM=y # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_HISI=y # # Hisilicon platform type # CONFIG_ARCH_SD5203=y # end of Hisilicon platform type # CONFIG_ARCH_MXC is not set CONFIG_ARCH_LPC32XX=y CONFIG_ARCH_MMP=y # # Marvell PXA168/910/MMP2 Implementations # CONFIG_MACH_MMP_DT=y # end of Marvell PXA168/910/MMP2 Implementations # CONFIG_ARCH_MVEBU is not set CONFIG_SOC_IMX23=y CONFIG_SOC_IMX28=y CONFIG_ARCH_MXS=y # CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_NPCM is not set # CONFIG_ARCH_ORION5X is not set CONFIG_ARCH_OXNAS=y # CONFIG_MACH_OX810SE is not set # CONFIG_ARCH_PXA is not set CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR3XX=y CONFIG_MACH_SPEAR300=y CONFIG_MACH_SPEAR310=y # CONFIG_MACH_SPEAR320 is not set # CONFIG_ARCH_SPEAR6XX is not set CONFIG_ARCH_SUNXI=y # CONFIG_MACH_SUNIV is not set CONFIG_ARCH_VERSATILE=y # CONFIG_ARCH_INTEGRATOR is not set CONFIG_ARCH_REALVIEW=y CONFIG_MACH_REALVIEW_EB=y # CONFIG_ARCH_WM8505 is not set CONFIG_PLAT_VERSATILE=y # # Processor Type # CONFIG_CPU_ARM926T=y CONFIG_CPU_MOHAWK=y CONFIG_CPU_THUMB_CAPABLE=y CONFIG_CPU_32v5=y CONFIG_CPU_ABRT_EV5T=y CONFIG_CPU_ABRT_EV5TJ=y CONFIG_CPU_PABRT_LEGACY=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_COPY_V4WB=y CONFIG_CPU_TLB_V4WBI=y CONFIG_CPU_CP15=y CONFIG_CPU_CP15_MMU=y CONFIG_CPU_USE_DOMAINS=y # # Processor Features # CONFIG_ARM_THUMB=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_ICACHE_DISABLE=y # CONFIG_CPU_DCACHE_DISABLE is not set CONFIG_CPU_DCACHE_WRITETHROUGH=y CONFIG_CPU_CACHE_ROUND_ROBIN=y CONFIG_CPU_BPREDICT_DISABLE=y CONFIG_NEED_KUSER_HELPERS=y CONFIG_KUSER_HELPERS=y # CONFIG_CACHE_TAUROS2 is not set CONFIG_ARM_L1_CACHE_SHIFT=5 CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_IWMMXT=y # end of System Type # # Bus support # # end of Bus support # # Kernel Features # CONFIG_IRQSTACKS=y CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_3G_OPT is not set # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_ARCH_NR_GPIO=416 CONFIG_HZ_FIXED=0 # CONFIG_HZ_100 is not set # CONFIG_HZ_200 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_500 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 CONFIG_SCHED_HRTICK=y CONFIG_AEABI=y CONFIG_OABI_COMPAT=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y # CONFIG_HIGHMEM is not set CONFIG_CPU_SW_DOMAIN_PAN=y CONFIG_ARM_MODULE_PLTS=y CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set CONFIG_PARAVIRT=y CONFIG_PARAVIRT_TIME_ACCOUNTING=y CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y # end of Kernel Features # # Boot options # CONFIG_USE_OF=y # CONFIG_ATAGS is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y # CONFIG_ARM_ATAG_DTB_COMPAT is not set CONFIG_CMDLINE="" CONFIG_KEXEC=y CONFIG_CRASH_DUMP=y CONFIG_AUTO_ZRELADDR=y CONFIG_EFI_STUB=y CONFIG_EFI=y # CONFIG_DMI is not set # end of Boot options # # CPU Power Management # # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set # end of CPU Frequency scaling # # CPU Idle # CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set CONFIG_DT_IDLE_STATES=y # # ARM CPU Idle Drivers # CONFIG_ARM_CPUIDLE=y # CONFIG_ARM_CLPS711X_CPUIDLE is not set CONFIG_ARM_KIRKWOOD_CPUIDLE=y CONFIG_ARM_ZYNQ_CPUIDLE=y CONFIG_ARM_AT91_CPUIDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y CONFIG_ARM_MVEBU_V7_CPUIDLE=y CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_ARM_QCOM_SPM_CPUIDLE=y # end of ARM CPU Idle Drivers # end of CPU Idle # end of CPU Power Management # # Floating point emulation # # # At least one emulation must be selected # # CONFIG_FPE_NWFPE is not set # CONFIG_FPE_FASTFPE is not set # CONFIG_VFP is not set # end of Floating point emulation # # Power management options # # CONFIG_SUSPEND is not set CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y CONFIG_DPM_WATCHDOG=y CONFIG_DPM_WATCHDOG_TIMEOUT=120 # CONFIG_APM_EMULATION is not set CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y # CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_CPU_PM=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options CONFIG_ARM_CRYPTO=y # CONFIG_CRYPTO_SHA1_ARM is not set CONFIG_CRYPTO_SHA256_ARM=m # CONFIG_CRYPTO_SHA512_ARM is not set CONFIG_CRYPTO_BLAKE2S_ARM=y # CONFIG_CRYPTO_AES_ARM is not set CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_CRYPTO_POLY1305_ARM=m CONFIG_AS_VFP_VMRS_FPINST=y # # General architecture-dependent options # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_OPTPROBES=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_KRETPROBES=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_HAVE_NMI=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_SECCOMP=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y # CONFIG_COMPAT_32BIT_TIME is not set CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y # CONFIG_STRICT_MODULE_RWX is not set # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y # CONFIG_MODULE_UNLOAD is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y # CONFIG_MODULE_SIG_ALL is not set # # Do not forget to sign required modules with scripts/sign-file # # CONFIG_MODULE_SIG_SHA1 is not set # CONFIG_MODULE_SIG_SHA224 is not set # CONFIG_MODULE_SIG_SHA256 is not set CONFIG_MODULE_SIG_SHA384=y # CONFIG_MODULE_SIG_SHA512 is not set CONFIG_MODULE_SIG_HASH="sha384" # CONFIG_MODULE_COMPRESS_NONE is not set # CONFIG_MODULE_COMPRESS_GZIP is not set CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_DECOMPRESS is not set CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y # CONFIG_BLOCK is not set CONFIG_ASN1=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_FREEZER=y # # Executable file formats # CONFIG_BINFMT_ELF=y CONFIG_BINFMT_ELF_KUNIT_TEST=y # CONFIG_BINFMT_ELF_FDPIC is not set CONFIG_ELFCORE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_BINFMT_SCRIPT is not set CONFIG_ARCH_HAS_BINFMT_FLAT=y # CONFIG_BINFMT_FLAT is not set CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_BINFMT_MISC=m CONFIG_COREDUMP=y # end of Executable file formats # # Memory Management options # # # SLAB allocator options # # CONFIG_SLAB is not set # CONFIG_SLUB is not set CONFIG_SLOB=y # end of SLAB allocator options CONFIG_SHUFFLE_PAGE_ALLOCATOR=y # CONFIG_COMPAT_BRK is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_SPLIT_PTLOCK_CPUS=999999 CONFIG_MEMORY_BALLOON=y # CONFIG_COMPACTION is not set CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_NEED_PER_CPU_KM=y CONFIG_CMA=y CONFIG_CMA_DEBUG=y CONFIG_CMA_DEBUGFS=y CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_PAGE_IDLE_FLAG=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set CONFIG_GUP_TEST=y CONFIG_ANON_VMA_NAME=y # CONFIG_USERFAULTFD is not set # # Data Access Monitoring # CONFIG_DAMON=y CONFIG_DAMON_KUNIT_TEST=y # CONFIG_DAMON_VADDR is not set CONFIG_DAMON_PADDR=y # CONFIG_DAMON_SYSFS is not set # CONFIG_DAMON_RECLAIM is not set CONFIG_DAMON_LRU_SORT=y # end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y CONFIG_NET_REDIRECT=y CONFIG_SKB_EXTENSIONS=y # # Networking options # CONFIG_PACKET=y CONFIG_PACKET_DIAG=m CONFIG_UNIX=m CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set CONFIG_TLS=y # CONFIG_TLS_DEVICE is not set CONFIG_TLS_TOE=y CONFIG_XFRM=y CONFIG_XFRM_OFFLOAD=y CONFIG_XFRM_ALGO=y # CONFIG_XFRM_USER is not set CONFIG_XFRM_INTERFACE=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set CONFIG_XFRM_STATISTICS=y CONFIG_XFRM_AH=m CONFIG_XFRM_ESP=y CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=m # CONFIG_NET_KEY_MIGRATE is not set CONFIG_SMC=m CONFIG_SMC_DIAG=m CONFIG_XDP_SOCKETS=y CONFIG_XDP_SOCKETS_DIAG=m CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set CONFIG_NET_IPIP=y CONFIG_NET_IPGRE_DEMUX=y CONFIG_NET_IP_TUNNEL=y CONFIG_NET_IPGRE=m CONFIG_SYN_COOKIES=y # CONFIG_NET_IPVTI is not set CONFIG_NET_UDP_TUNNEL=y CONFIG_NET_FOU=m # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_INET_AH is not set CONFIG_INET_ESP=y CONFIG_INET_ESP_OFFLOAD=m # CONFIG_INET_ESPINTCP is not set # CONFIG_INET_IPCOMP is not set CONFIG_INET_TUNNEL=y CONFIG_INET_DIAG=m CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m CONFIG_INET_RAW_DIAG=m # CONFIG_INET_DIAG_DESTROY is not set CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=m CONFIG_TCP_CONG_CUBIC=m CONFIG_TCP_CONG_WESTWOOD=m # CONFIG_TCP_CONG_HTCP is not set # CONFIG_TCP_CONG_HSTCP is not set CONFIG_TCP_CONG_HYBLA=y CONFIG_TCP_CONG_VEGAS=m CONFIG_TCP_CONG_NV=m CONFIG_TCP_CONG_SCALABLE=m # CONFIG_TCP_CONG_LP is not set # CONFIG_TCP_CONG_VENO is not set CONFIG_TCP_CONG_YEAH=m CONFIG_TCP_CONG_ILLINOIS=m CONFIG_TCP_CONG_DCTCP=y CONFIG_TCP_CONG_CDG=y # CONFIG_TCP_CONG_BBR is not set CONFIG_DEFAULT_HYBLA=y # CONFIG_DEFAULT_DCTCP is not set # CONFIG_DEFAULT_CDG is not set # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="hybla" # CONFIG_TCP_MD5SIG is not set CONFIG_IPV6=m # CONFIG_IPV6_ROUTER_PREF is not set CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_ESP_OFFLOAD=m # CONFIG_INET6_ESPINTCP is not set CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m # CONFIG_IPV6_ILA is not set CONFIG_INET6_XFRM_TUNNEL=m CONFIG_INET6_TUNNEL=m CONFIG_IPV6_VTI=m # CONFIG_IPV6_SIT is not set CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_GRE=m CONFIG_IPV6_FOU=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y # CONFIG_IPV6_MROUTE is not set CONFIG_IPV6_SEG6_LWTUNNEL=y CONFIG_IPV6_SEG6_HMAC=y CONFIG_IPV6_RPL_LWTUNNEL=y CONFIG_IPV6_IOAM6_LWTUNNEL=y CONFIG_MPTCP=y CONFIG_INET_MPTCP_DIAG=m CONFIG_MPTCP_KUNIT_TEST=y # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=m # # Core Netfilter Configuration # # CONFIG_NETFILTER_INGRESS is not set # CONFIG_NETFILTER_EGRESS is not set CONFIG_NETFILTER_NETLINK=y CONFIG_NETFILTER_FAMILY_BRIDGE=y CONFIG_NETFILTER_FAMILY_ARP=y # CONFIG_NETFILTER_NETLINK_HOOK is not set CONFIG_NETFILTER_NETLINK_ACCT=m CONFIG_NETFILTER_NETLINK_QUEUE=y # CONFIG_NETFILTER_NETLINK_LOG is not set CONFIG_NETFILTER_NETLINK_OSF=y CONFIG_NF_CONNTRACK=m CONFIG_NF_LOG_SYSLOG=y CONFIG_NETFILTER_CONNCOUNT=m CONFIG_NF_CONNTRACK_MARK=y # CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y # CONFIG_NF_CONNTRACK_TIMEOUT is not set # CONFIG_NF_CONNTRACK_TIMESTAMP is not set CONFIG_NF_CONNTRACK_LABELS=y # CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_GRE=y CONFIG_NF_CT_PROTO_SCTP=y # CONFIG_NF_CT_PROTO_UDPLITE is not set CONFIG_NF_CONNTRACK_AMANDA=m CONFIG_NF_CONNTRACK_FTP=m # CONFIG_NF_CONNTRACK_H323 is not set CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_BROADCAST=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m # CONFIG_NF_CONNTRACK_SIP is not set CONFIG_NF_CONNTRACK_TFTP=m # CONFIG_NF_CT_NETLINK is not set CONFIG_NF_NAT=m CONFIG_NF_NAT_AMANDA=m CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_IRC=m CONFIG_NF_NAT_TFTP=m CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m # CONFIG_NF_TABLES_INET is not set CONFIG_NF_TABLES_NETDEV=y # CONFIG_NFT_NUMGEN is not set CONFIG_NFT_CT=m CONFIG_NFT_CONNLIMIT=m # CONFIG_NFT_LOG is not set CONFIG_NFT_LIMIT=m # CONFIG_NFT_MASQ is not set CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m # CONFIG_NFT_TUNNEL is not set CONFIG_NFT_OBJREF=m CONFIG_NFT_QUEUE=m CONFIG_NFT_QUOTA=m # CONFIG_NFT_REJECT is not set CONFIG_NFT_COMPAT=m CONFIG_NFT_HASH=m CONFIG_NFT_FIB=m CONFIG_NFT_XFRM=m # CONFIG_NFT_SOCKET is not set # CONFIG_NFT_OSF is not set # CONFIG_NFT_TPROXY is not set CONFIG_NFT_SYNPROXY=m CONFIG_NF_DUP_NETDEV=m CONFIG_NFT_DUP_NETDEV=m CONFIG_NFT_FWD_NETDEV=m CONFIG_NETFILTER_XTABLES=y # # Xtables combined modules # CONFIG_NETFILTER_XT_MARK=y CONFIG_NETFILTER_XT_CONNMARK=m # # Xtables targets # # CONFIG_NETFILTER_XT_TARGET_AUDIT is not set # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m CONFIG_NETFILTER_XT_TARGET_LED=m # CONFIG_NETFILTER_XT_TARGET_LOG is not set CONFIG_NETFILTER_XT_TARGET_MARK=y CONFIG_NETFILTER_XT_NAT=m CONFIG_NETFILTER_XT_TARGET_NETMAP=m # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set CONFIG_NETFILTER_XT_TARGET_RATEEST=y CONFIG_NETFILTER_XT_TARGET_REDIRECT=m CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m # # Xtables matches # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y # CONFIG_NETFILTER_XT_MATCH_BPF is not set CONFIG_NETFILTER_XT_MATCH_CGROUP=y # CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set CONFIG_NETFILTER_XT_MATCH_COMMENT=m # CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set # CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m # CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set CONFIG_NETFILTER_XT_MATCH_CPU=y # CONFIG_NETFILTER_XT_MATCH_DCCP is not set # CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set CONFIG_NETFILTER_XT_MATCH_DSCP=y CONFIG_NETFILTER_XT_MATCH_ECN=m CONFIG_NETFILTER_XT_MATCH_ESP=y # CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_HL=y CONFIG_NETFILTER_XT_MATCH_IPCOMP=y CONFIG_NETFILTER_XT_MATCH_IPRANGE=m # CONFIG_NETFILTER_XT_MATCH_L2TP is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=y # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set CONFIG_NETFILTER_XT_MATCH_MAC=y CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y CONFIG_NETFILTER_XT_MATCH_NFACCT=m CONFIG_NETFILTER_XT_MATCH_OSF=y # CONFIG_NETFILTER_XT_MATCH_OWNER is not set CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set CONFIG_NETFILTER_XT_MATCH_QUOTA=y # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set CONFIG_NETFILTER_XT_MATCH_RECENT=m CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=y CONFIG_NETFILTER_XT_MATCH_STRING=y # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m # end of Core Netfilter Configuration # CONFIG_IP_SET is not set # CONFIG_IP_VS is not set # # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_SOCKET_IPV4=m CONFIG_NF_TPROXY_IPV4=y CONFIG_NF_TABLES_IPV4=y CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y CONFIG_NF_DUP_IPV4=m CONFIG_NF_LOG_ARP=y CONFIG_NF_LOG_IPV4=y CONFIG_NF_REJECT_IPV4=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PPTP=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m # CONFIG_IP_NF_MATCH_RPFILTER is not set CONFIG_IP_NF_MATCH_TTL=m # CONFIG_IP_NF_FILTER is not set CONFIG_IP_NF_TARGET_SYNPROXY=m CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m # CONFIG_IP_NF_MANGLE is not set CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=y # CONFIG_IP_NF_ARPFILTER is not set # CONFIG_IP_NF_ARP_MANGLE is not set # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # CONFIG_NF_SOCKET_IPV6=m CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y # CONFIG_NFT_DUP_IPV6 is not set # CONFIG_NFT_FIB_IPV6 is not set CONFIG_NF_DUP_IPV6=m CONFIG_NF_REJECT_IPV6=m CONFIG_NF_LOG_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m # CONFIG_IP6_NF_MATCH_OPTS is not set # CONFIG_IP6_NF_MATCH_HL is not set # CONFIG_IP6_NF_MATCH_IPV6HEADER is not set # CONFIG_IP6_NF_MATCH_MH is not set CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_MATCH_SRH=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m # CONFIG_IP6_NF_TARGET_SYNPROXY is not set # CONFIG_IP6_NF_MANGLE is not set # CONFIG_IP6_NF_RAW is not set CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m # end of IPv6: Netfilter Configuration CONFIG_NF_DEFRAG_IPV6=m # CONFIG_NF_TABLES_BRIDGE is not set CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m # CONFIG_BRIDGE_EBT_BROUTE is not set CONFIG_BRIDGE_EBT_T_FILTER=m # CONFIG_BRIDGE_EBT_T_NAT is not set CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m # CONFIG_BRIDGE_EBT_ARP is not set # CONFIG_BRIDGE_EBT_IP is not set CONFIG_BRIDGE_EBT_IP6=m CONFIG_BRIDGE_EBT_LIMIT=m CONFIG_BRIDGE_EBT_MARK=m CONFIG_BRIDGE_EBT_PKTTYPE=m # CONFIG_BRIDGE_EBT_STP is not set CONFIG_BRIDGE_EBT_VLAN=m CONFIG_BRIDGE_EBT_ARPREPLY=m CONFIG_BRIDGE_EBT_DNAT=m CONFIG_BRIDGE_EBT_MARK_T=m CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m # CONFIG_BRIDGE_EBT_NFLOG is not set CONFIG_BPFILTER=y CONFIG_IP_DCCP=m CONFIG_INET_DCCP_DIAG=m # # DCCP CCIDs Configuration # CONFIG_IP_DCCP_CCID2_DEBUG=y CONFIG_IP_DCCP_CCID3=y CONFIG_IP_DCCP_CCID3_DEBUG=y CONFIG_IP_DCCP_TFRC_LIB=y CONFIG_IP_DCCP_TFRC_DEBUG=y # end of DCCP CCIDs Configuration # # DCCP Kernel Hacking # CONFIG_IP_DCCP_DEBUG=y # end of DCCP Kernel Hacking CONFIG_IP_SCTP=m # CONFIG_SCTP_DBG_OBJCNT is not set CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set CONFIG_SCTP_COOKIE_HMAC_MD5=y # CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set CONFIG_INET_SCTP_DIAG=m CONFIG_RDS=m # CONFIG_RDS_TCP is not set # CONFIG_RDS_DEBUG is not set CONFIG_TIPC=m # CONFIG_TIPC_MEDIA_IB is not set CONFIG_TIPC_MEDIA_UDP=y # CONFIG_TIPC_CRYPTO is not set CONFIG_TIPC_DIAG=m # CONFIG_ATM is not set # CONFIG_L2TP is not set CONFIG_STP=m CONFIG_MRP=y CONFIG_BRIDGE=m # CONFIG_BRIDGE_IGMP_SNOOPING is not set CONFIG_BRIDGE_VLAN_FILTERING=y # CONFIG_BRIDGE_MRP is not set # CONFIG_BRIDGE_CFM is not set CONFIG_NET_DSA=m CONFIG_NET_DSA_TAG_AR9331=m CONFIG_NET_DSA_TAG_BRCM_COMMON=m CONFIG_NET_DSA_TAG_BRCM=m CONFIG_NET_DSA_TAG_BRCM_LEGACY=m CONFIG_NET_DSA_TAG_BRCM_PREPEND=m # CONFIG_NET_DSA_TAG_HELLCREEK is not set CONFIG_NET_DSA_TAG_GSWIP=m CONFIG_NET_DSA_TAG_DSA_COMMON=m CONFIG_NET_DSA_TAG_DSA=m CONFIG_NET_DSA_TAG_EDSA=m CONFIG_NET_DSA_TAG_MTK=m CONFIG_NET_DSA_TAG_KSZ=m CONFIG_NET_DSA_TAG_OCELOT=m CONFIG_NET_DSA_TAG_OCELOT_8021Q=m CONFIG_NET_DSA_TAG_QCA=m CONFIG_NET_DSA_TAG_RTL4_A=m CONFIG_NET_DSA_TAG_RTL8_4=m CONFIG_NET_DSA_TAG_RZN1_A5PSW=m CONFIG_NET_DSA_TAG_LAN9303=m # CONFIG_NET_DSA_TAG_SJA1105 is not set # CONFIG_NET_DSA_TAG_TRAILER is not set CONFIG_NET_DSA_TAG_XRS700X=m CONFIG_VLAN_8021Q=y # CONFIG_VLAN_8021Q_GVRP is not set CONFIG_VLAN_8021Q_MVRP=y # CONFIG_DECNET is not set CONFIG_LLC=y # CONFIG_LLC2 is not set CONFIG_ATALK=y CONFIG_DEV_APPLETALK=y CONFIG_IPDDP=y # CONFIG_IPDDP_ENCAP is not set CONFIG_X25=m CONFIG_LAPB=y # CONFIG_PHONET is not set CONFIG_6LOWPAN=m # CONFIG_6LOWPAN_DEBUGFS is not set # CONFIG_6LOWPAN_NHC is not set CONFIG_IEEE802154=y # CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set CONFIG_IEEE802154_SOCKET=m # CONFIG_IEEE802154_6LOWPAN is not set CONFIG_MAC802154=m # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set # CONFIG_DNS_RESOLVER is not set CONFIG_BATMAN_ADV=y # CONFIG_BATMAN_ADV_BLA is not set CONFIG_BATMAN_ADV_DAT=y CONFIG_BATMAN_ADV_NC=y # CONFIG_BATMAN_ADV_DEBUG is not set CONFIG_OPENVSWITCH=m # CONFIG_OPENVSWITCH_GRE is not set CONFIG_OPENVSWITCH_VXLAN=m CONFIG_OPENVSWITCH_GENEVE=m CONFIG_VSOCKETS=y CONFIG_VSOCKETS_DIAG=m # CONFIG_VSOCKETS_LOOPBACK is not set # CONFIG_VIRTIO_VSOCKETS is not set CONFIG_NETLINK_DIAG=m CONFIG_MPLS=y CONFIG_NET_MPLS_GSO=m CONFIG_MPLS_ROUTING=y CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m # CONFIG_HSR is not set CONFIG_NET_SWITCHDEV=y CONFIG_NET_L3_MASTER_DEV=y # CONFIG_QRTR is not set CONFIG_NET_NCSI=y CONFIG_NCSI_OEM_CMD_GET_MAC=y # CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set # CONFIG_CGROUP_NET_PRIO is not set CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y # # Network testing # CONFIG_NET_PKTGEN=y # end of Network testing # end of Networking options # CONFIG_HAMRADIO is not set CONFIG_CAN=y # CONFIG_CAN_RAW is not set CONFIG_CAN_BCM=y CONFIG_CAN_GW=y CONFIG_CAN_J1939=m # CONFIG_CAN_ISOTP is not set CONFIG_BT=y # CONFIG_BT_BREDR is not set CONFIG_BT_LE=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y CONFIG_BT_AOSPEXT=y CONFIG_BT_DEBUGFS=y # CONFIG_BT_SELFTEST is not set # CONFIG_BT_FEATURE_DEBUG is not set # # Bluetooth device drivers # CONFIG_BT_QCA=m CONFIG_BT_MTK=m # CONFIG_BT_HCIBTSDIO is not set CONFIG_BT_HCIDTL1=m # CONFIG_BT_HCIBT3C is not set CONFIG_BT_HCIBLUECARD=m CONFIG_BT_HCIVHCI=y CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m CONFIG_BT_MTKSDIO=m CONFIG_BT_MTKUART=m CONFIG_BT_QCOMSMD=m CONFIG_BT_VIRTIO=m # end of Bluetooth device drivers CONFIG_AF_RXRPC=m # CONFIG_AF_RXRPC_IPV6 is not set CONFIG_AF_RXRPC_INJECT_LOSS=y CONFIG_AF_RXRPC_DEBUG=y CONFIG_RXKAD=y CONFIG_AF_KCM=y CONFIG_STREAM_PARSER=y # CONFIG_MCTP is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y CONFIG_CFG80211=m CONFIG_NL80211_TESTMODE=y # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set CONFIG_CFG80211_CERTIFICATION_ONUS=y # CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set # CONFIG_CFG80211_REG_CELLULAR_HINTS is not set # CONFIG_CFG80211_REG_RELAX_NO_IR is not set CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_DEBUGFS is not set # CONFIG_CFG80211_CRDA_SUPPORT is not set CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m # CONFIG_MAC80211_RC_MINSTREL is not set CONFIG_MAC80211_RC_DEFAULT="" # # Some wireless drivers require a rate control algorithm # CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_DEBUGFS is not set CONFIG_MAC80211_MESSAGE_TRACING=y # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_GPIO=m # CONFIG_NET_9P is not set CONFIG_CAIF=m # CONFIG_CAIF_DEBUG is not set CONFIG_CAIF_NETDEV=m CONFIG_CAIF_USB=m CONFIG_CEPH_LIB=m # CONFIG_CEPH_LIB_PRETTYDEBUG is not set # CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set CONFIG_NFC=m # CONFIG_NFC_DIGITAL is not set CONFIG_NFC_NCI=m CONFIG_NFC_HCI=m CONFIG_NFC_SHDLC=y # # Near Field Communication (NFC) devices # CONFIG_NFC_VIRTUAL_NCI=m # CONFIG_NFC_FDP is not set CONFIG_NFC_PN544=m CONFIG_NFC_PN544_I2C=m CONFIG_NFC_PN533=m # CONFIG_NFC_PN533_I2C is not set CONFIG_NFC_PN532_UART=m # CONFIG_NFC_MICROREAD_I2C is not set CONFIG_NFC_ST21NFCA=m CONFIG_NFC_ST21NFCA_I2C=m CONFIG_NFC_ST_NCI=m CONFIG_NFC_ST_NCI_I2C=m CONFIG_NFC_NXP_NCI=m CONFIG_NFC_NXP_NCI_I2C=m CONFIG_NFC_S3FWRN5=m CONFIG_NFC_S3FWRN5_I2C=m CONFIG_NFC_S3FWRN82_UART=m # end of Near Field Communication (NFC) devices CONFIG_PSAMPLE=y CONFIG_NET_IFE=y CONFIG_LWTUNNEL=y # CONFIG_LWTUNNEL_BPF is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y CONFIG_NET_SELFTESTS=m CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y CONFIG_PAGE_POOL_STATS=y CONFIG_FAILOVER=y # CONFIG_ETHTOOL_NETLINK is not set CONFIG_NETDEV_ADDR_LIST_TEST=y # # Device Drivers # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y # CONFIG_PCI is not set CONFIG_PCCARD=m CONFIG_PCMCIA=m # CONFIG_PCMCIA_LOAD_CIS is not set # # PC-card bridges # CONFIG_OMAP_CF=m # # Generic Driver Options # CONFIG_AUXILIARY_BUS=y # CONFIG_UEVENT_HELPER is not set # CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set CONFIG_FW_LOADER_COMPRESS=y CONFIG_FW_LOADER_COMPRESS_XZ=y CONFIG_FW_LOADER_COMPRESS_ZSTD=y CONFIG_FW_UPLOAD=y # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEV_COREDUMP=y # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set CONFIG_DEBUG_TEST_DRIVER_REMOVE=y CONFIG_PM_QOS_KUNIT_TEST=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_DRIVER_PE_KUNIT_TEST=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_SOC_BUS=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SPMI=y CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_I3C=m CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set # end of Generic Driver Options # # Bus devices # CONFIG_ARM_INTEGRATOR_LM=y # CONFIG_BRCMSTB_GISB_ARB is not set CONFIG_BT1_APB=y CONFIG_BT1_AXI=y CONFIG_HISILICON_LPC=y # CONFIG_INTEL_IXP4XX_EB is not set CONFIG_QCOM_EBI2=y CONFIG_SUN50I_DE2_BUS=y # CONFIG_SUNXI_RSB is not set # CONFIG_VEXPRESS_CONFIG is not set CONFIG_FSL_MC_BUS=y # CONFIG_FSL_MC_UAPI_SUPPORT is not set CONFIG_MHI_BUS=m # CONFIG_MHI_BUS_DEBUG is not set CONFIG_MHI_BUS_EP=m # end of Bus devices # CONFIG_CONNECTOR is not set # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # CONFIG_ARM_SCMI_PROTOCOL=m # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set # CONFIG_ARM_SCMI_POWER_DOMAIN is not set # CONFIG_ARM_SCMI_POWER_CONTROL is not set # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=m CONFIG_ARM_SCPI_POWER_DOMAIN=m CONFIG_FIRMWARE_MEMMAP=y CONFIG_FW_CFG_SYSFS=y CONFIG_FW_CFG_SYSFS_CMDLINE=y CONFIG_QCOM_SCM=y CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT=y # CONFIG_SYSFB_SIMPLEFB is not set CONFIG_TURRIS_MOX_RWTM=m # CONFIG_BCM47XX_NVRAM is not set CONFIG_TEE_BNXT_FW=m # CONFIG_GOOGLE_FIRMWARE is not set # # EFI (Extensible Firmware Interface) Support # CONFIG_EFI_ESRT=y CONFIG_EFI_VARS_PSTORE=m # CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set CONFIG_EFI_PARAMS_FROM_FDT=y CONFIG_EFI_RUNTIME_WRAPPERS=y CONFIG_EFI_GENERIC_STUB=y # CONFIG_EFI_ARMSTUB_DTB_LOADER is not set CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y CONFIG_EFI_BOOTLOADER_CONTROL=m CONFIG_EFI_CAPSULE_LOADER=m CONFIG_EFI_TEST=y # CONFIG_RESET_ATTACK_MITIGATION is not set CONFIG_EFI_RCI2_TABLE=y # CONFIG_EFI_DISABLE_PCI_DMA is not set CONFIG_EFI_DISABLE_RUNTIME=y # CONFIG_EFI_COCO_SECRET is not set # end of EFI (Extensible Firmware Interface) Support CONFIG_IMX_DSP=m # CONFIG_IMX_SCU is not set # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers # CONFIG_GNSS is not set # CONFIG_MTD is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set CONFIG_OF_ALL_DTBS=y CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_DYNAMIC=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y CONFIG_OF_RESOLVE=y CONFIG_OF_OVERLAY=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=y # CONFIG_PARPORT_PC_FIFO is not set CONFIG_PARPORT_PC_SUPERIO=y CONFIG_PARPORT_PC_PCMCIA=m CONFIG_PARPORT_AX88796=y # CONFIG_PARPORT_1284 is not set CONFIG_PARPORT_NOT_PC=y # # NVME Support # # end of NVME Support # # Misc devices # # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set CONFIG_ICS932S401=m CONFIG_ATMEL_SSC=m # CONFIG_ENCLOSURE_SERVICES is not set CONFIG_HI6421V600_IRQ=m CONFIG_QCOM_COINCELL=m # CONFIG_QCOM_FASTRPC is not set CONFIG_APDS9802ALS=m # CONFIG_ISL29003 is not set CONFIG_ISL29020=y CONFIG_SENSORS_TSL2550=y CONFIG_SENSORS_BH1770=y CONFIG_SENSORS_APDS990X=m # CONFIG_HMC6352 is not set CONFIG_DS1682=m CONFIG_SRAM=y CONFIG_SRAM_EXEC=y CONFIG_XILINX_SDFEC=m CONFIG_OPEN_DICE=m # CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # # EEPROM support # # CONFIG_EEPROM_AT24 is not set CONFIG_EEPROM_LEGACY=m CONFIG_EEPROM_MAX6875=y # CONFIG_EEPROM_93CX6 is not set CONFIG_EEPROM_IDT_89HPESX=y CONFIG_EEPROM_EE1004=m # end of EEPROM support # # Texas Instruments shared transport line discipline # # end of Texas Instruments shared transport line discipline CONFIG_ALTERA_STAPL=m # CONFIG_ECHO is not set CONFIG_UACCE=y CONFIG_PVPANIC=y CONFIG_PVPANIC_MMIO=y # end of Misc devices # # SCSI device support # CONFIG_SCSI_MOD=y # end of SCSI device support CONFIG_HAVE_PATA_PLATFORM=y # # IEEE 1394 (FireWire) support # CONFIG_FIREWIRE=y CONFIG_FIREWIRE_NET=y # end of IEEE 1394 (FireWire) support CONFIG_NETDEVICES=y CONFIG_NET_CORE=y CONFIG_BONDING=m CONFIG_DUMMY=y CONFIG_WIREGUARD=m CONFIG_WIREGUARD_DEBUG=y # CONFIG_EQUALIZER is not set CONFIG_IFB=m CONFIG_NET_TEAM=y # CONFIG_NET_TEAM_MODE_BROADCAST is not set CONFIG_NET_TEAM_MODE_ROUNDROBIN=m # CONFIG_NET_TEAM_MODE_RANDOM is not set CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m CONFIG_NET_TEAM_MODE_LOADBALANCE=m # CONFIG_MACVLAN is not set # CONFIG_IPVLAN is not set CONFIG_VXLAN=y CONFIG_GENEVE=m CONFIG_BAREUDP=m CONFIG_GTP=m CONFIG_MACSEC=m CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_NETPOLL=y CONFIG_NET_POLL_CONTROLLER=y CONFIG_TUN=m # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=y CONFIG_VIRTIO_NET=y CONFIG_NLMON=y CONFIG_MHI_NET=m CONFIG_ARCNET=m CONFIG_ARCNET_1201=m # CONFIG_ARCNET_1051 is not set CONFIG_ARCNET_RAW=m # CONFIG_ARCNET_CAP is not set # CONFIG_ARCNET_COM90xx is not set CONFIG_ARCNET_COM90xxIO=m # CONFIG_ARCNET_RIM_I is not set # CONFIG_ARCNET_COM20020 is not set CONFIG_CAIF_DRIVERS=y # CONFIG_CAIF_VIRTIO is not set # # Distributed Switch Architecture drivers # CONFIG_B53=m CONFIG_B53_MDIO_DRIVER=m CONFIG_B53_MMAP_DRIVER=m CONFIG_B53_SRAB_DRIVER=m # CONFIG_B53_SERDES is not set # CONFIG_NET_DSA_BCM_SF2 is not set # CONFIG_NET_DSA_LOOP is not set # CONFIG_NET_DSA_LANTIQ_GSWIP is not set CONFIG_NET_DSA_MT7530=m # CONFIG_NET_DSA_MV88E6060 is not set CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m CONFIG_NET_DSA_MV88E6XXX=m CONFIG_NET_DSA_AR9331=m # CONFIG_NET_DSA_QCA8K is not set CONFIG_NET_DSA_XRS700X=m CONFIG_NET_DSA_XRS700X_I2C=m # CONFIG_NET_DSA_XRS700X_MDIO is not set CONFIG_NET_DSA_REALTEK=m CONFIG_NET_DSA_REALTEK_MDIO=m CONFIG_NET_DSA_REALTEK_SMI=m CONFIG_NET_DSA_REALTEK_RTL8365MB=m CONFIG_NET_DSA_REALTEK_RTL8366RB=m # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set # CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set CONFIG_NET_DSA_VITESSE_VSC73XX=m CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m # end of Distributed Switch Architecture drivers # CONFIG_ETHERNET is not set CONFIG_PHYLINK=m CONFIG_PHYLIB=m CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set CONFIG_FIXED_PHY=m CONFIG_SFP=m # # MII PHY device drivers # CONFIG_AMD_PHY=m # CONFIG_MESON_GXL_PHY is not set CONFIG_ADIN_PHY=m CONFIG_ADIN1100_PHY=m CONFIG_AQUANTIA_PHY=m CONFIG_AX88796B_PHY=m # CONFIG_BROADCOM_PHY is not set CONFIG_BCM54140_PHY=m # CONFIG_BCM63XX_PHY is not set # CONFIG_BCM7XXX_PHY is not set CONFIG_BCM84881_PHY=m CONFIG_BCM87XX_PHY=m CONFIG_BCM_NET_PHYLIB=m # CONFIG_CICADA_PHY is not set CONFIG_CORTINA_PHY=m # CONFIG_DAVICOM_PHY is not set # CONFIG_ICPLUS_PHY is not set CONFIG_LXT_PHY=m CONFIG_INTEL_XWAY_PHY=m # CONFIG_LSI_ET1011C_PHY is not set CONFIG_MARVELL_PHY=m # CONFIG_MARVELL_10G_PHY is not set CONFIG_MARVELL_88X2222_PHY=m CONFIG_MAXLINEAR_GPHY=m CONFIG_MEDIATEK_GE_PHY=m CONFIG_MICREL_PHY=m # CONFIG_MICROCHIP_PHY is not set # CONFIG_MICROCHIP_T1_PHY is not set CONFIG_MICROSEMI_PHY=m CONFIG_MOTORCOMM_PHY=m # CONFIG_NATIONAL_PHY is not set # CONFIG_NXP_C45_TJA11XX_PHY is not set CONFIG_AT803X_PHY=m CONFIG_QSEMI_PHY=m CONFIG_REALTEK_PHY=m # CONFIG_RENESAS_PHY is not set CONFIG_ROCKCHIP_PHY=m CONFIG_SMSC_PHY=m CONFIG_STE10XP=m CONFIG_TERANETICS_PHY=m CONFIG_DP83822_PHY=m # CONFIG_DP83TC811_PHY is not set # CONFIG_DP83848_PHY is not set CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set # CONFIG_DP83TD510_PHY is not set CONFIG_VITESSE_PHY=m # CONFIG_XILINX_GMII2RGMII is not set CONFIG_CAN_DEV=m CONFIG_CAN_VCAN=m CONFIG_CAN_VXCAN=m CONFIG_CAN_NETLINK=y CONFIG_CAN_CALC_BITTIMING=y CONFIG_CAN_RX_OFFLOAD=y # CONFIG_CAN_AT91 is not set # CONFIG_CAN_FLEXCAN is not set # CONFIG_CAN_GRCAN is not set CONFIG_CAN_SUN4I=m CONFIG_CAN_TI_HECC=m CONFIG_CAN_XILINXCAN=m CONFIG_CAN_C_CAN=m # CONFIG_CAN_C_CAN_PLATFORM is not set # CONFIG_CAN_CC770 is not set CONFIG_CAN_CTUCANFD=m # CONFIG_CAN_CTUCANFD_PLATFORM is not set # CONFIG_CAN_IFI_CANFD is not set CONFIG_CAN_M_CAN=m # CONFIG_CAN_M_CAN_PLATFORM is not set # CONFIG_CAN_RCAR is not set CONFIG_CAN_RCAR_CANFD=m CONFIG_CAN_SJA1000=m # CONFIG_CAN_EMS_PCMCIA is not set CONFIG_CAN_PEAK_PCMCIA=m CONFIG_CAN_SJA1000_ISA=m CONFIG_CAN_SJA1000_PLATFORM=m # CONFIG_CAN_SOFTING is not set # CONFIG_CAN_DEBUG_DEVICES is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=m CONFIG_FWNODE_MDIO=m CONFIG_OF_MDIO=m CONFIG_MDIO_DEVRES=m # CONFIG_MDIO_SUN4I is not set # CONFIG_MDIO_XGENE is not set CONFIG_MDIO_ASPEED=m CONFIG_MDIO_BITBANG=m # CONFIG_MDIO_BCM_IPROC is not set # CONFIG_MDIO_BCM_UNIMAC is not set CONFIG_MDIO_CAVIUM=m CONFIG_MDIO_GPIO=m CONFIG_MDIO_HISI_FEMAC=m CONFIG_MDIO_I2C=m CONFIG_MDIO_MSCC_MIIM=m CONFIG_MDIO_MOXART=m CONFIG_MDIO_OCTEON=m CONFIG_MDIO_IPQ4019=m CONFIG_MDIO_IPQ8064=m # # MDIO Multiplexers # CONFIG_MDIO_BUS_MUX=m CONFIG_MDIO_BUS_MUX_MESON_G12A=m CONFIG_MDIO_BUS_MUX_BCM6368=m CONFIG_MDIO_BUS_MUX_BCM_IPROC=m # CONFIG_MDIO_BUS_MUX_GPIO is not set # CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set CONFIG_MDIO_BUS_MUX_MMIOREG=m # # PCS device drivers # CONFIG_PCS_RZN1_MIIC=y # end of PCS device drivers CONFIG_PLIP=m CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m # CONFIG_PPP_DEFLATE is not set CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPP_MULTILINK=y # CONFIG_PPPOE is not set CONFIG_PPTP=m CONFIG_SLHC=m # # Host-side USB support is needed for USB Network Adapter support # # CONFIG_WLAN is not set CONFIG_WAN=y # CONFIG_HDLC is not set # CONFIG_LAPBETHER is not set CONFIG_IEEE802154_DRIVERS=m # CONFIG_IEEE802154_FAKELB is not set # CONFIG_IEEE802154_HWSIM is not set # # Wireless WAN # # CONFIG_WWAN is not set # end of Wireless WAN CONFIG_NETDEVSIM=m CONFIG_NET_FAILOVER=y CONFIG_ISDN=y CONFIG_ISDN_CAPI=y CONFIG_MISDN=m # CONFIG_MISDN_DSP is not set CONFIG_MISDN_L1OIP=m # # mISDN hardware drivers # # # Input device support # # CONFIG_INPUT is not set # # Hardware I/O ports # # CONFIG_SERIO is not set CONFIG_GAMEPORT=y CONFIG_GAMEPORT_NS558=y CONFIG_GAMEPORT_L4=m # end of Hardware I/O ports # end of Input device support # # Character devices # # CONFIG_TTY is not set CONFIG_SERIAL_DEV_BUS=m # CONFIG_PRINTER is not set # CONFIG_PPDEV is not set CONFIG_IPMI_HANDLER=m # CONFIG_IPMI_PANIC_EVENT is not set CONFIG_IPMI_DEVICE_INTERFACE=m # CONFIG_IPMI_SI is not set CONFIG_IPMI_SSIF=m CONFIG_IPMI_IPMB=m CONFIG_IPMI_WATCHDOG=m CONFIG_IPMI_POWEROFF=m CONFIG_IPMI_KCS_BMC=y # CONFIG_ASPEED_KCS_IPMI_BMC is not set CONFIG_NPCM7XX_KCS_IPMI_BMC=y CONFIG_IPMI_KCS_BMC_CDEV_IPMI=y CONFIG_ASPEED_BT_IPMI_BMC=m CONFIG_IPMB_DEVICE_INTERFACE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=y CONFIG_HW_RANDOM_ATMEL=y # CONFIG_HW_RANDOM_BA431 is not set # CONFIG_HW_RANDOM_BCM2835 is not set # CONFIG_HW_RANDOM_IPROC_RNG200 is not set CONFIG_HW_RANDOM_IXP4XX=y # CONFIG_HW_RANDOM_OMAP is not set # CONFIG_HW_RANDOM_OMAP3_ROM is not set CONFIG_HW_RANDOM_VIRTIO=y CONFIG_HW_RANDOM_IMX_RNGC=m CONFIG_HW_RANDOM_NOMADIK=y CONFIG_HW_RANDOM_HISI=m CONFIG_HW_RANDOM_STM32=y CONFIG_HW_RANDOM_POLARFIRE_SOC=y # CONFIG_HW_RANDOM_MESON is not set CONFIG_HW_RANDOM_MTK=m # CONFIG_HW_RANDOM_EXYNOS is not set CONFIG_HW_RANDOM_NPCM=y CONFIG_HW_RANDOM_KEYSTONE=y CONFIG_HW_RANDOM_CCTRNG=y CONFIG_HW_RANDOM_XIPHERA=m # # PCMCIA character devices # CONFIG_CARDMAN_4000=m # CONFIG_CARDMAN_4040 is not set CONFIG_SCR24X=m # end of PCMCIA character devices # CONFIG_DEVMEM is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_RANDOM_TRUST_CPU is not set # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices # # I2C support # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y # # Multiplexer I2C Chip support # # CONFIG_I2C_ARB_GPIO_CHALLENGE is not set CONFIG_I2C_MUX_GPIO=y # CONFIG_I2C_MUX_GPMUX is not set CONFIG_I2C_MUX_LTC4306=y CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y # CONFIG_I2C_MUX_PINCTRL is not set CONFIG_I2C_MUX_REG=m CONFIG_I2C_DEMUX_PINCTRL=m # CONFIG_I2C_MUX_MLXCPLD is not set # end of Multiplexer I2C Chip support CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_SMBUS=y CONFIG_I2C_ALGOBIT=y CONFIG_I2C_ALGOPCA=m # # I2C Hardware Bus support # CONFIG_I2C_HIX5HD2=m # # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_ALTERA is not set CONFIG_I2C_ASPEED=m # CONFIG_I2C_AT91 is not set # CONFIG_I2C_AXXIA is not set # CONFIG_I2C_BCM2835 is not set # CONFIG_I2C_BCM_IPROC is not set CONFIG_I2C_BCM_KONA=m CONFIG_I2C_BRCMSTB=m CONFIG_I2C_CADENCE=y CONFIG_I2C_CBUS_GPIO=m # CONFIG_I2C_DAVINCI is not set CONFIG_I2C_DESIGNWARE_CORE=y # CONFIG_I2C_DESIGNWARE_SLAVE is not set CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_DIGICOLOR=m # CONFIG_I2C_EMEV2 is not set CONFIG_I2C_EXYNOS5=y CONFIG_I2C_GPIO=m CONFIG_I2C_GPIO_FAULT_INJECTOR=y CONFIG_I2C_HIGHLANDER=y CONFIG_I2C_HISI=m CONFIG_I2C_IMG=m CONFIG_I2C_IMX=y # CONFIG_I2C_IMX_LPI2C is not set CONFIG_I2C_IOP3XX=y CONFIG_I2C_JZ4780=m CONFIG_I2C_KEMPLD=y # CONFIG_I2C_LPC2K is not set CONFIG_I2C_MESON=m # CONFIG_I2C_MICROCHIP_CORE is not set CONFIG_I2C_MT65XX=m CONFIG_I2C_MT7621=y CONFIG_I2C_MV64XXX=m CONFIG_I2C_MXS=y # CONFIG_I2C_NOMADIK is not set CONFIG_I2C_NPCM=y CONFIG_I2C_OCORES=m # CONFIG_I2C_OMAP is not set # CONFIG_I2C_OWL is not set # CONFIG_I2C_APPLE is not set CONFIG_I2C_PCA_PLATFORM=m CONFIG_I2C_PNX=m # CONFIG_I2C_PXA is not set CONFIG_I2C_QCOM_CCI=y CONFIG_I2C_QCOM_GENI=m CONFIG_I2C_QUP=m CONFIG_I2C_RIIC=m CONFIG_I2C_RK3X=y CONFIG_I2C_RZV2M=m CONFIG_I2C_S3C2410=y CONFIG_I2C_SH_MOBILE=y # CONFIG_I2C_SIMTEC is not set CONFIG_I2C_SPRD=m CONFIG_I2C_ST=m CONFIG_I2C_STM32F4=m # CONFIG_I2C_STM32F7 is not set CONFIG_I2C_SUN6I_P2WI=y CONFIG_I2C_SYNQUACER=m CONFIG_I2C_TEGRA=m CONFIG_I2C_TEGRA_BPMP=y # CONFIG_I2C_UNIPHIER is not set CONFIG_I2C_UNIPHIER_F=m # CONFIG_I2C_VERSATILE is not set CONFIG_I2C_WMT=m # CONFIG_I2C_XILINX is not set # CONFIG_I2C_XLP9XX is not set CONFIG_I2C_RCAR=m # # External I2C/SMBus adapter drivers # CONFIG_I2C_PARPORT=m # # Other I2C/SMBus bus drivers # CONFIG_I2C_MLXCPLD=y CONFIG_I2C_CROS_EC_TUNNEL=m # CONFIG_I2C_FSI is not set CONFIG_I2C_VIRTIO=m # end of I2C Hardware Bus support CONFIG_I2C_STUB=m CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=m # CONFIG_I2C_SLAVE_TESTUNIT is not set # CONFIG_I2C_DEBUG_CORE is not set CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y # end of I2C support CONFIG_I3C=m # CONFIG_CDNS_I3C_MASTER is not set CONFIG_DW_I3C_MASTER=m # CONFIG_SVC_I3C_MASTER is not set CONFIG_MIPI_I3C_HCI=m # CONFIG_SPI is not set CONFIG_SPMI=y CONFIG_SPMI_HISI3670=y CONFIG_SPMI_MSM_PMIC_ARB=m # CONFIG_SPMI_MTK_PMIF is not set # CONFIG_HSI is not set # CONFIG_PPS is not set # # PTP clock support # CONFIG_PTP_1588_CLOCK_OPTIONAL=y # end of PTP clock support CONFIG_PINCTRL=y CONFIG_GENERIC_PINCTRL_GROUPS=y CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set CONFIG_PINCTRL_AMD=y # CONFIG_PINCTRL_AS3722 is not set CONFIG_PINCTRL_AT91=y CONFIG_PINCTRL_AT91PIO4=y # CONFIG_PINCTRL_BM1880 is not set CONFIG_PINCTRL_DA850_PUPD=y CONFIG_PINCTRL_DA9062=m CONFIG_PINCTRL_EQUILIBRIUM=m # CONFIG_PINCTRL_INGENIC is not set # CONFIG_PINCTRL_LPC18XX is not set CONFIG_PINCTRL_MAX77620=m CONFIG_PINCTRL_MCP23S08_I2C=m CONFIG_PINCTRL_MCP23S08=m CONFIG_PINCTRL_MICROCHIP_SGPIO=y CONFIG_PINCTRL_OCELOT=m CONFIG_PINCTRL_OXNAS=y CONFIG_PINCTRL_PISTACHIO=y CONFIG_PINCTRL_RK805=m # CONFIG_PINCTRL_ROCKCHIP is not set CONFIG_PINCTRL_SINGLE=y # CONFIG_PINCTRL_STARFIVE is not set CONFIG_PINCTRL_STMFX=y # CONFIG_PINCTRL_SX150X is not set CONFIG_PINCTRL_OWL=y CONFIG_PINCTRL_S500=y CONFIG_PINCTRL_S700=y # CONFIG_PINCTRL_S900 is not set CONFIG_PINCTRL_ASPEED=y CONFIG_PINCTRL_ASPEED_G4=y CONFIG_PINCTRL_ASPEED_G5=y CONFIG_PINCTRL_ASPEED_G6=y CONFIG_PINCTRL_BCM281XX=y CONFIG_PINCTRL_BCM2835=y CONFIG_PINCTRL_BCM4908=m CONFIG_PINCTRL_BCM63XX=y CONFIG_PINCTRL_BCM6318=y CONFIG_PINCTRL_BCM6328=y CONFIG_PINCTRL_BCM6358=y CONFIG_PINCTRL_BCM6362=y CONFIG_PINCTRL_BCM6368=y CONFIG_PINCTRL_BCM63268=y # CONFIG_PINCTRL_IPROC_GPIO is not set CONFIG_PINCTRL_CYGNUS_MUX=y CONFIG_PINCTRL_NS=y CONFIG_PINCTRL_NSP_GPIO=y # CONFIG_PINCTRL_NS2_MUX is not set # CONFIG_PINCTRL_NSP_MUX is not set # CONFIG_PINCTRL_AS370 is not set # CONFIG_PINCTRL_BERLIN_BG4CT is not set # CONFIG_PINCTRL_LOCHNAGAR is not set CONFIG_PINCTRL_MADERA=y CONFIG_PINCTRL_CS47L35=y CONFIG_PINCTRL_CS47L85=y CONFIG_PINCTRL_CS47L90=y CONFIG_PINCTRL_CS47L92=y CONFIG_PINCTRL_MXS=y CONFIG_PINCTRL_IMX23=y CONFIG_PINCTRL_IMX28=y # # Intel pinctrl drivers # # end of Intel pinctrl drivers # # MediaTek pinctrl drivers # CONFIG_EINT_MTK=y CONFIG_PINCTRL_MTK=y CONFIG_PINCTRL_MTK_V2=y CONFIG_PINCTRL_MTK_MOORE=y CONFIG_PINCTRL_MTK_PARIS=y CONFIG_PINCTRL_MT2701=y # CONFIG_PINCTRL_MT7623 is not set CONFIG_PINCTRL_MT7629=y CONFIG_PINCTRL_MT8135=y CONFIG_PINCTRL_MT8127=y # CONFIG_PINCTRL_MT2712 is not set # CONFIG_PINCTRL_MT6765 is not set CONFIG_PINCTRL_MT6779=m CONFIG_PINCTRL_MT6795=y CONFIG_PINCTRL_MT6797=y # CONFIG_PINCTRL_MT7622 is not set CONFIG_PINCTRL_MT7986=y CONFIG_PINCTRL_MT8167=y # CONFIG_PINCTRL_MT8173 is not set CONFIG_PINCTRL_MT8183=y # CONFIG_PINCTRL_MT8186 is not set # CONFIG_PINCTRL_MT8192 is not set CONFIG_PINCTRL_MT8195=y # CONFIG_PINCTRL_MT8365 is not set CONFIG_PINCTRL_MT8516=y # CONFIG_PINCTRL_MT6397 is not set # end of MediaTek pinctrl drivers # CONFIG_PINCTRL_MESON is not set CONFIG_PINCTRL_WPCM450=y CONFIG_PINCTRL_NPCM7XX=y CONFIG_PINCTRL_PXA=y # CONFIG_PINCTRL_PXA25X is not set CONFIG_PINCTRL_PXA27X=m CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_APQ8064=m CONFIG_PINCTRL_APQ8084=y CONFIG_PINCTRL_IPQ4019=m CONFIG_PINCTRL_IPQ8064=m CONFIG_PINCTRL_IPQ8074=y # CONFIG_PINCTRL_IPQ6018 is not set CONFIG_PINCTRL_MSM8226=y # CONFIG_PINCTRL_MSM8660 is not set CONFIG_PINCTRL_MSM8960=y # CONFIG_PINCTRL_MDM9607 is not set CONFIG_PINCTRL_MDM9615=y CONFIG_PINCTRL_MSM8X74=y CONFIG_PINCTRL_MSM8909=m CONFIG_PINCTRL_MSM8916=y # CONFIG_PINCTRL_MSM8953 is not set CONFIG_PINCTRL_MSM8976=m CONFIG_PINCTRL_MSM8994=y # CONFIG_PINCTRL_MSM8996 is not set CONFIG_PINCTRL_MSM8998=y CONFIG_PINCTRL_QCM2290=m # CONFIG_PINCTRL_QCS404 is not set CONFIG_PINCTRL_QCOM_SPMI_PMIC=m CONFIG_PINCTRL_QCOM_SSBI_PMIC=y # CONFIG_PINCTRL_SC7180 is not set CONFIG_PINCTRL_SC7280=m # CONFIG_PINCTRL_SC8180X is not set CONFIG_PINCTRL_SC8280XP=m # CONFIG_PINCTRL_SDM660 is not set CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SDX55=m # CONFIG_PINCTRL_SM6115 is not set CONFIG_PINCTRL_SM6125=m # CONFIG_PINCTRL_SM6350 is not set CONFIG_PINCTRL_SM6375=y CONFIG_PINCTRL_SDX65=y # CONFIG_PINCTRL_SM8150 is not set # CONFIG_PINCTRL_SM8250 is not set # CONFIG_PINCTRL_SM8350 is not set # CONFIG_PINCTRL_SM8450 is not set # CONFIG_PINCTRL_LPASS_LPI is not set # # Renesas pinctrl drivers # # CONFIG_PINCTRL_RENESAS is not set CONFIG_PINCTRL_SH_PFC=y CONFIG_PINCTRL_SH_PFC_GPIO=y CONFIG_PINCTRL_SH_FUNC_GPIO=y CONFIG_PINCTRL_PFC_EMEV2=y CONFIG_PINCTRL_PFC_R8A77995=y # CONFIG_PINCTRL_PFC_R8A7794 is not set # CONFIG_PINCTRL_PFC_R8A77990 is not set CONFIG_PINCTRL_PFC_R8A7779=y # CONFIG_PINCTRL_PFC_R8A7790 is not set CONFIG_PINCTRL_PFC_R8A77950=y # CONFIG_PINCTRL_PFC_R8A77951 is not set # CONFIG_PINCTRL_PFC_R8A7778 is not set CONFIG_PINCTRL_PFC_R8A7793=y # CONFIG_PINCTRL_PFC_R8A7791 is not set CONFIG_PINCTRL_PFC_R8A77965=y CONFIG_PINCTRL_PFC_R8A77960=y CONFIG_PINCTRL_PFC_R8A77961=y CONFIG_PINCTRL_PFC_R8A779F0=y CONFIG_PINCTRL_PFC_R8A7792=y # CONFIG_PINCTRL_PFC_R8A77980 is not set CONFIG_PINCTRL_PFC_R8A77970=y CONFIG_PINCTRL_PFC_R8A779A0=y # CONFIG_PINCTRL_PFC_R8A779G0 is not set # CONFIG_PINCTRL_PFC_R8A7740 is not set # CONFIG_PINCTRL_PFC_R8A73A4 is not set CONFIG_PINCTRL_RZA1=y CONFIG_PINCTRL_RZA2=y # CONFIG_PINCTRL_RZG2L is not set # CONFIG_PINCTRL_PFC_R8A77470 is not set CONFIG_PINCTRL_PFC_R8A7745=y CONFIG_PINCTRL_PFC_R8A7742=y # CONFIG_PINCTRL_PFC_R8A7743 is not set # CONFIG_PINCTRL_PFC_R8A7744 is not set # CONFIG_PINCTRL_PFC_R8A774C0 is not set # CONFIG_PINCTRL_PFC_R8A774E1 is not set CONFIG_PINCTRL_PFC_R8A774A1=y # CONFIG_PINCTRL_PFC_R8A774B1 is not set CONFIG_PINCTRL_RZN1=y CONFIG_PINCTRL_RZV2M=y CONFIG_PINCTRL_PFC_SH7203=y # CONFIG_PINCTRL_PFC_SH7264 is not set CONFIG_PINCTRL_PFC_SH7269=y # CONFIG_PINCTRL_PFC_SH7720 is not set CONFIG_PINCTRL_PFC_SH7722=y # CONFIG_PINCTRL_PFC_SH7734 is not set CONFIG_PINCTRL_PFC_SH7757=y # CONFIG_PINCTRL_PFC_SH7785 is not set CONFIG_PINCTRL_PFC_SH7786=y # CONFIG_PINCTRL_PFC_SH73A0 is not set # CONFIG_PINCTRL_PFC_SH7723 is not set # CONFIG_PINCTRL_PFC_SH7724 is not set CONFIG_PINCTRL_PFC_SHX3=y # end of Renesas pinctrl drivers CONFIG_PINCTRL_SAMSUNG=y CONFIG_PINCTRL_EXYNOS=y # CONFIG_PINCTRL_EXYNOS_ARM is not set # CONFIG_PINCTRL_EXYNOS_ARM64 is not set # CONFIG_PINCTRL_S3C24XX is not set # CONFIG_PINCTRL_S3C64XX is not set CONFIG_PINCTRL_SPEAR=y CONFIG_PINCTRL_SPEAR3XX=y CONFIG_PINCTRL_SPEAR300=y CONFIG_PINCTRL_SPEAR310=y CONFIG_PINCTRL_SPEAR_PLGPIO=y # CONFIG_PINCTRL_SPRD_SC9860 is not set CONFIG_PINCTRL_STM32=y CONFIG_PINCTRL_STM32F429=y CONFIG_PINCTRL_STM32F469=y CONFIG_PINCTRL_STM32F746=y # CONFIG_PINCTRL_STM32F769 is not set # CONFIG_PINCTRL_STM32H743 is not set # CONFIG_PINCTRL_STM32MP135 is not set # CONFIG_PINCTRL_STM32MP157 is not set CONFIG_PINCTRL_SUNXI=y CONFIG_PINCTRL_SUN4I_A10=y CONFIG_PINCTRL_SUN5I=y # CONFIG_PINCTRL_SUN6I_A31 is not set CONFIG_PINCTRL_SUN6I_A31_R=y # CONFIG_PINCTRL_SUN8I_A23 is not set # CONFIG_PINCTRL_SUN8I_A33 is not set # CONFIG_PINCTRL_SUN8I_A83T is not set CONFIG_PINCTRL_SUN8I_A83T_R=y # CONFIG_PINCTRL_SUN8I_A23_R is not set CONFIG_PINCTRL_SUN8I_H3=y # CONFIG_PINCTRL_SUN8I_H3_R is not set # CONFIG_PINCTRL_SUN8I_V3S is not set # CONFIG_PINCTRL_SUN9I_A80 is not set CONFIG_PINCTRL_SUN9I_A80_R=y # CONFIG_PINCTRL_SUN20I_D1 is not set # CONFIG_PINCTRL_SUN50I_A64 is not set CONFIG_PINCTRL_SUN50I_A64_R=y # CONFIG_PINCTRL_SUN50I_A100 is not set # CONFIG_PINCTRL_SUN50I_A100_R is not set # CONFIG_PINCTRL_SUN50I_H5 is not set CONFIG_PINCTRL_SUN50I_H6=y CONFIG_PINCTRL_SUN50I_H6_R=y # CONFIG_PINCTRL_SUN50I_H616 is not set # CONFIG_PINCTRL_SUN50I_H616_R is not set # CONFIG_PINCTRL_TI_IODELAY is not set CONFIG_PINCTRL_UNIPHIER=y # CONFIG_PINCTRL_UNIPHIER_LD4 is not set # CONFIG_PINCTRL_UNIPHIER_PRO4 is not set # CONFIG_PINCTRL_UNIPHIER_SLD8 is not set CONFIG_PINCTRL_UNIPHIER_PRO5=y # CONFIG_PINCTRL_UNIPHIER_PXS2 is not set CONFIG_PINCTRL_UNIPHIER_LD6B=y CONFIG_PINCTRL_UNIPHIER_LD11=y # CONFIG_PINCTRL_UNIPHIER_LD20 is not set # CONFIG_PINCTRL_UNIPHIER_PXS3 is not set CONFIG_PINCTRL_UNIPHIER_NX1=y CONFIG_PINCTRL_VISCONTI=y CONFIG_PINCTRL_TMPV7700=y CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y # CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_REGMAP=y # # Memory mapped GPIO drivers # # CONFIG_GPIO_74XX_MMIO is not set CONFIG_GPIO_ALTERA=m CONFIG_GPIO_ASPEED=y CONFIG_GPIO_ASPEED_SGPIO=y # CONFIG_GPIO_ATH79 is not set # CONFIG_GPIO_RASPBERRYPI_EXP is not set # CONFIG_GPIO_BCM_KONA is not set CONFIG_GPIO_BCM_XGS_IPROC=m CONFIG_GPIO_BRCMSTB=m CONFIG_GPIO_CADENCE=y CONFIG_GPIO_CLPS711X=y CONFIG_GPIO_DWAPB=m CONFIG_GPIO_EIC_SPRD=y CONFIG_GPIO_EM=y CONFIG_GPIO_FTGPIO010=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_GRGPIO=y # CONFIG_GPIO_HISI is not set CONFIG_GPIO_HLWD=y CONFIG_GPIO_IOP=m # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_LPC18XX is not set CONFIG_GPIO_LPC32XX=y CONFIG_GPIO_MB86S7X=m CONFIG_GPIO_MENZ127=y CONFIG_GPIO_MPC8XXX=y # CONFIG_GPIO_MT7621 is not set # CONFIG_GPIO_MXC is not set CONFIG_GPIO_MXS=y CONFIG_GPIO_OMAP=y CONFIG_GPIO_PL061=y CONFIG_GPIO_PMIC_EIC_SPRD=m CONFIG_GPIO_PXA=y CONFIG_GPIO_RCAR=y # CONFIG_GPIO_RDA is not set CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_SAMA5D2_PIOBU is not set CONFIG_GPIO_SIFIVE=y CONFIG_GPIO_SIOX=y CONFIG_GPIO_SNPS_CREG=y # CONFIG_GPIO_SPEAR_SPICS is not set CONFIG_GPIO_SPRD=m CONFIG_GPIO_STP_XWAY=y CONFIG_GPIO_SYSCON=m CONFIG_GPIO_TEGRA=m # CONFIG_GPIO_TEGRA186 is not set CONFIG_GPIO_TS4800=m CONFIG_GPIO_UNIPHIER=m # CONFIG_GPIO_VISCONTI is not set # CONFIG_GPIO_XGENE_SB is not set CONFIG_GPIO_XILINX=m # CONFIG_GPIO_XLP is not set # CONFIG_GPIO_ZEVIO is not set CONFIG_GPIO_AMD_FCH=y CONFIG_GPIO_IDT3243X=m # end of Memory mapped GPIO drivers # # I2C GPIO expanders # CONFIG_GPIO_ADP5588=y CONFIG_GPIO_ADP5588_IRQ=y CONFIG_GPIO_ADNP=m # CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PCA9570=m # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_TPIC2810 is not set # CONFIG_GPIO_TS4900 is not set # end of I2C GPIO expanders # # MFD GPIO expanders # CONFIG_GPIO_ARIZONA=m CONFIG_GPIO_DA9052=y # CONFIG_HTC_EGPIO is not set CONFIG_GPIO_KEMPLD=m CONFIG_GPIO_LP3943=y CONFIG_GPIO_LP873X=m CONFIG_GPIO_MADERA=m CONFIG_GPIO_MAX77620=y CONFIG_GPIO_MAX77650=y # CONFIG_GPIO_RC5T583 is not set CONFIG_GPIO_SL28CPLD=m # CONFIG_GPIO_STMPE is not set CONFIG_GPIO_TPS65086=m # CONFIG_GPIO_TPS65218 is not set # CONFIG_GPIO_TPS65910 is not set CONFIG_GPIO_TPS65912=m CONFIG_GPIO_TQMX86=m CONFIG_GPIO_TWL4030=y CONFIG_GPIO_TWL6040=y CONFIG_GPIO_WM831X=m CONFIG_GPIO_WM8994=y # end of MFD GPIO expanders # # Virtual GPIO drivers # CONFIG_GPIO_AGGREGATOR=m CONFIG_GPIO_MOCKUP=y CONFIG_GPIO_VIRTIO=y CONFIG_GPIO_SIM=y # end of Virtual GPIO drivers CONFIG_W1=y # # 1-wire Bus Masters # CONFIG_W1_MASTER_DS2482=m CONFIG_W1_MASTER_MXC=y CONFIG_W1_MASTER_DS1WM=m # CONFIG_W1_MASTER_GPIO is not set CONFIG_W1_MASTER_SGI=m # end of 1-wire Bus Masters # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=y CONFIG_W1_SLAVE_SMEM=y # CONFIG_W1_SLAVE_DS2405 is not set CONFIG_W1_SLAVE_DS2408=y # CONFIG_W1_SLAVE_DS2408_READBACK is not set # CONFIG_W1_SLAVE_DS2413 is not set CONFIG_W1_SLAVE_DS2406=y # CONFIG_W1_SLAVE_DS2423 is not set CONFIG_W1_SLAVE_DS2805=m CONFIG_W1_SLAVE_DS2430=y CONFIG_W1_SLAVE_DS2431=m # CONFIG_W1_SLAVE_DS2433 is not set CONFIG_W1_SLAVE_DS2438=y CONFIG_W1_SLAVE_DS250X=m CONFIG_W1_SLAVE_DS2780=y CONFIG_W1_SLAVE_DS2781=m CONFIG_W1_SLAVE_DS28E04=y CONFIG_W1_SLAVE_DS28E17=y # end of 1-wire Slaves CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_AS3722 is not set CONFIG_POWER_RESET_AT91_POWEROFF=y # CONFIG_POWER_RESET_AT91_RESET is not set CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y CONFIG_POWER_RESET_ATC260X=m CONFIG_POWER_RESET_BRCMKONA=y # CONFIG_POWER_RESET_BRCMSTB is not set CONFIG_POWER_RESET_GEMINI_POWEROFF=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_HISI=y # CONFIG_POWER_RESET_LINKSTATION is not set # CONFIG_POWER_RESET_OCELOT_RESET is not set CONFIG_POWER_RESET_OXNAS=y # CONFIG_POWER_RESET_LTC2952 is not set # CONFIG_POWER_RESET_MT6323 is not set CONFIG_POWER_RESET_REGULATOR=y CONFIG_POWER_RESET_RESTART=y CONFIG_POWER_RESET_TPS65086=y CONFIG_POWER_RESET_VERSATILE=y # CONFIG_POWER_RESET_KEYSTONE is not set # CONFIG_POWER_RESET_SYSCON is not set CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_POWER_RESET_RMOBILE=m CONFIG_REBOOT_MODE=m CONFIG_SYSCON_REBOOT_MODE=m CONFIG_POWER_RESET_SC27XX=y # CONFIG_NVMEM_REBOOT_MODE is not set CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_DEBUG=y # CONFIG_PDA_POWER is not set CONFIG_GENERIC_ADC_BATTERY=y CONFIG_IP5XXX_POWER=y CONFIG_WM831X_BACKUP=m CONFIG_WM831X_POWER=m # CONFIG_TEST_POWER is not set CONFIG_BATTERY_88PM860X=y # CONFIG_CHARGER_ADP5061 is not set # CONFIG_BATTERY_ACT8945A is not set CONFIG_BATTERY_CW2015=y CONFIG_BATTERY_DS2760=y CONFIG_BATTERY_DS2780=y CONFIG_BATTERY_DS2781=m CONFIG_BATTERY_DS2782=m # CONFIG_BATTERY_LEGO_EV3 is not set CONFIG_BATTERY_SAMSUNG_SDI=y # CONFIG_BATTERY_INGENIC is not set CONFIG_BATTERY_SBS=m # CONFIG_CHARGER_SBS is not set CONFIG_MANAGER_SBS=y CONFIG_BATTERY_BQ27XXX=m # CONFIG_BATTERY_BQ27XXX_I2C is not set CONFIG_BATTERY_BQ27XXX_HDQ=m CONFIG_BATTERY_DA9052=m CONFIG_CHARGER_DA9150=m # CONFIG_BATTERY_DA9150 is not set CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=y # CONFIG_BATTERY_MAX1721X is not set # CONFIG_CHARGER_88PM860X is not set CONFIG_CHARGER_PCF50633=m # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_TWL4030 is not set # CONFIG_CHARGER_LP8727 is not set CONFIG_CHARGER_LP8788=m # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set CONFIG_CHARGER_LT3651=m # CONFIG_CHARGER_LTC4162L is not set CONFIG_CHARGER_MAX14577=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_MAX77650 is not set CONFIG_CHARGER_MAX77693=m CONFIG_CHARGER_MAX77976=y CONFIG_CHARGER_MP2629=m # CONFIG_CHARGER_MT6360 is not set CONFIG_CHARGER_QCOM_SMBB=m CONFIG_CHARGER_BQ2415X=y CONFIG_CHARGER_BQ24190=m CONFIG_CHARGER_BQ24257=m CONFIG_CHARGER_BQ24735=y # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set CONFIG_CHARGER_BQ256XX=m CONFIG_CHARGER_SMB347=y CONFIG_CHARGER_TPS65090=m CONFIG_CHARGER_TPS65217=y CONFIG_BATTERY_GAUGE_LTC2941=m # CONFIG_BATTERY_GOLDFISH is not set CONFIG_BATTERY_RT5033=y CONFIG_CHARGER_RT9455=y CONFIG_CHARGER_CROS_USBPD=m CONFIG_CHARGER_CROS_PCHG=m CONFIG_CHARGER_SC2731=m # CONFIG_FUEL_GAUGE_SC27XX is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set CONFIG_BATTERY_ACER_A500=m CONFIG_BATTERY_UG3105=y # CONFIG_HWMON is not set # CONFIG_THERMAL is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 CONFIG_WATCHDOG_SYSFS=y CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y # # Watchdog Pretimeout Governors # CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m # CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y # # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set # CONFIG_DA9052_WATCHDOG is not set CONFIG_DA9055_WATCHDOG=m CONFIG_DA9063_WATCHDOG=m # CONFIG_DA9062_WATCHDOG is not set CONFIG_GPIO_WATCHDOG=m # CONFIG_MENF21BMC_WATCHDOG is not set # CONFIG_MENZ069_WATCHDOG is not set # CONFIG_WM831X_WATCHDOG is not set CONFIG_XILINX_WATCHDOG=m CONFIG_ZIIRAVE_WATCHDOG=y CONFIG_MLX_WDT=y CONFIG_SL28CPLD_WATCHDOG=m # CONFIG_ARM_SP805_WATCHDOG is not set CONFIG_ARMADA_37XX_WATCHDOG=m # CONFIG_ASM9260_WATCHDOG is not set # CONFIG_AT91RM9200_WATCHDOG is not set CONFIG_AT91SAM9X_WATCHDOG=y CONFIG_SAMA5D4_WATCHDOG=m CONFIG_CADENCE_WATCHDOG=m # CONFIG_977_WATCHDOG is not set CONFIG_FTWDT010_WATCHDOG=m CONFIG_S3C2410_WATCHDOG=m CONFIG_DW_WATCHDOG=y # CONFIG_EP93XX_WATCHDOG is not set # CONFIG_OMAP_WATCHDOG is not set # CONFIG_PNX4008_WATCHDOG is not set CONFIG_DAVINCI_WATCHDOG=y # CONFIG_K3_RTI_WATCHDOG is not set # CONFIG_ORION_WATCHDOG is not set CONFIG_RN5T618_WATCHDOG=y CONFIG_SUNXI_WATCHDOG=y # CONFIG_NPCM7XX_WATCHDOG is not set CONFIG_TWL4030_WATCHDOG=y CONFIG_STMP3XXX_RTC_WATCHDOG=y CONFIG_TS4800_WATCHDOG=y CONFIG_TS72XX_WATCHDOG=y CONFIG_MAX63XX_WATCHDOG=y CONFIG_MAX77620_WATCHDOG=m # CONFIG_IMX2_WDT is not set # CONFIG_IMX7ULP_WDT is not set CONFIG_MOXART_WDT=y # CONFIG_ST_LPC_WATCHDOG is not set # CONFIG_TEGRA_WATCHDOG is not set CONFIG_QCOM_WDT=m # CONFIG_MESON_GXBB_WATCHDOG is not set # CONFIG_MESON_WATCHDOG is not set CONFIG_MEDIATEK_WATCHDOG=y CONFIG_DIGICOLOR_WATCHDOG=y CONFIG_LPC18XX_WATCHDOG=y # CONFIG_RENESAS_WDT is not set CONFIG_RENESAS_RZAWDT=y CONFIG_RENESAS_RZN1WDT=y CONFIG_RENESAS_RZG2LWDT=m # CONFIG_ASPEED_WATCHDOG is not set CONFIG_STPMIC1_WATCHDOG=m # CONFIG_UNIPHIER_WATCHDOG is not set CONFIG_RTD119X_WATCHDOG=y # CONFIG_REALTEK_OTTO_WDT is not set CONFIG_SPRD_WATCHDOG=m CONFIG_PM8916_WATCHDOG=y # CONFIG_VISCONTI_WATCHDOG is not set CONFIG_MSC313E_WATCHDOG=y CONFIG_APPLE_WATCHDOG=m # CONFIG_SUNPLUS_WATCHDOG is not set CONFIG_SC520_WDT=m # CONFIG_KEMPLD_WDT is not set CONFIG_ATH79_WDT=y CONFIG_BCM47XX_WDT=m CONFIG_BCM2835_WDT=y # CONFIG_BCM_KONA_WDT is not set CONFIG_BCM7038_WDT=m CONFIG_IMGPDC_WDT=y # CONFIG_MPC5200_WDT is not set # CONFIG_MEN_A21_WDT is not set CONFIG_UML_WATCHDOG=y CONFIG_SSB_POSSIBLE=y CONFIG_SSB=y CONFIG_SSB_SDIOHOST_POSSIBLE=y CONFIG_SSB_SDIOHOST=y # CONFIG_SSB_DRIVER_GPIO is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMA is not set # # Multifunction device drivers # CONFIG_MFD_CORE=y # CONFIG_MFD_ACT8945A is not set CONFIG_MFD_SUN4I_GPADC=y CONFIG_MFD_AS3711=y CONFIG_MFD_AS3722=y # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_AT91_USART is not set # CONFIG_MFD_ATMEL_FLEXCOM is not set CONFIG_MFD_ATMEL_HLCDC=y CONFIG_MFD_ATMEL_SMC=y CONFIG_MFD_BCM590XX=m # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set CONFIG_MFD_CROS_EC_DEV=m CONFIG_MFD_MADERA=y # CONFIG_MFD_MADERA_I2C is not set # CONFIG_MFD_CS47L15 is not set CONFIG_MFD_CS47L35=y CONFIG_MFD_CS47L85=y CONFIG_MFD_CS47L90=y CONFIG_MFD_CS47L92=y CONFIG_MFD_ASIC3=y # CONFIG_PMIC_DA903X is not set CONFIG_PMIC_DA9052=y CONFIG_MFD_DA9052_I2C=y # CONFIG_MFD_DA9055 is not set CONFIG_MFD_DA9062=m CONFIG_MFD_DA9063=m CONFIG_MFD_DA9150=m CONFIG_MFD_ENE_KB3930=y # CONFIG_MFD_EXYNOS_LPASS is not set CONFIG_MFD_GATEWORKS_GSC=m # CONFIG_MFD_MC13XXX_I2C is not set CONFIG_MFD_MP2629=y CONFIG_MFD_MXS_LRADC=y # CONFIG_MFD_MX25_TSADC is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_MFD_HI6421_SPMI is not set # CONFIG_MFD_HI655X_PMIC is not set CONFIG_HTC_PASIC3=m # CONFIG_HTC_I2CPLD is not set CONFIG_MFD_IQS62X=y CONFIG_MFD_KEMPLD=y # CONFIG_MFD_88PM800 is not set CONFIG_MFD_88PM805=y CONFIG_MFD_88PM860X=y CONFIG_MFD_MAX14577=y CONFIG_MFD_MAX77620=y CONFIG_MFD_MAX77650=y CONFIG_MFD_MAX77686=y CONFIG_MFD_MAX77693=y CONFIG_MFD_MAX77714=y # CONFIG_MFD_MAX77843 is not set CONFIG_MFD_MAX8907=y # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set CONFIG_MFD_MT6360=m CONFIG_MFD_MT6397=m # CONFIG_MFD_MENF21BMC is not set # CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set CONFIG_MFD_PCF50633=m # CONFIG_PCF50633_ADC is not set CONFIG_PCF50633_GPIO=m CONFIG_MFD_PM8XXX=y CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_RT4831=y # CONFIG_MFD_RT5033 is not set CONFIG_MFD_RC5T583=y CONFIG_MFD_RK808=m # CONFIG_MFD_RN5T618 is not set # CONFIG_MFD_SEC_CORE is not set # CONFIG_MFD_SI476X_CORE is not set CONFIG_MFD_SIMPLE_MFD_I2C=y CONFIG_MFD_SL28CPLD=y CONFIG_MFD_SM501=y CONFIG_MFD_SM501_GPIO=y CONFIG_MFD_SKY81452=y CONFIG_ABX500_CORE=y CONFIG_MFD_STMPE=y # # STMicroelectronics STMPE Interface Drivers # # CONFIG_STMPE_I2C is not set # end of STMicroelectronics STMPE Interface Drivers # CONFIG_MFD_SUN6I_PRCM is not set CONFIG_MFD_SYSCON=y CONFIG_MFD_TI_AM335X_TSCADC=y CONFIG_MFD_LP3943=y CONFIG_MFD_LP8788=y # CONFIG_MFD_TI_LMU is not set # CONFIG_MFD_PALMAS is not set CONFIG_TPS6105X=y CONFIG_TPS65010=y CONFIG_TPS6507X=y CONFIG_MFD_TPS65086=m CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TI_LP873X=m # CONFIG_MFD_TI_LP87565 is not set CONFIG_MFD_TPS65218=m # CONFIG_MFD_TPS6586X is not set CONFIG_MFD_TPS65910=y CONFIG_MFD_TPS65912=m CONFIG_MFD_TPS65912_I2C=m CONFIG_TWL4030_CORE=y # CONFIG_TWL4030_POWER is not set CONFIG_MFD_TWL4030_AUDIO=y CONFIG_TWL6040_CORE=y CONFIG_MFD_WL1273_CORE=m CONFIG_MFD_LM3533=m # CONFIG_MFD_TC3589X is not set CONFIG_MFD_TMIO=y # CONFIG_MFD_T7L66XB is not set CONFIG_MFD_TC6387XB=y CONFIG_MFD_TC6393XB=y CONFIG_MFD_TQMX86=m CONFIG_MFD_LOCHNAGAR=y CONFIG_MFD_ARIZONA=y CONFIG_MFD_ARIZONA_I2C=y CONFIG_MFD_CS47L24=y # CONFIG_MFD_WM5102 is not set # CONFIG_MFD_WM5110 is not set # CONFIG_MFD_WM8997 is not set CONFIG_MFD_WM8998=y CONFIG_MFD_WM8400=y CONFIG_MFD_WM831X=y CONFIG_MFD_WM831X_I2C=y # CONFIG_MFD_WM8350_I2C is not set CONFIG_MFD_WM8994=y # CONFIG_MFD_STW481X is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set CONFIG_MFD_STM32_LPTIMER=m CONFIG_MFD_STM32_TIMERS=y CONFIG_MFD_STPMIC1=m CONFIG_MFD_STMFX=y # CONFIG_MFD_WCD934X is not set CONFIG_MFD_ATC260X=m CONFIG_MFD_ATC260X_I2C=m # CONFIG_MFD_KHADAS_MCU is not set CONFIG_MFD_ACER_A500_EC=m CONFIG_MFD_QCOM_PM8008=y # CONFIG_RAVE_SP_CORE is not set CONFIG_MFD_RSMU_I2C=y # end of Multifunction device drivers CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_88PG86X is not set CONFIG_REGULATOR_88PM8607=m # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ANATOP=y # CONFIG_REGULATOR_ARM_SCMI is not set # CONFIG_REGULATOR_AS3711 is not set CONFIG_REGULATOR_AS3722=y CONFIG_REGULATOR_ATC260X=m # CONFIG_REGULATOR_BCM590XX is not set # CONFIG_REGULATOR_CROS_EC is not set CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_DA9062=m # CONFIG_REGULATOR_DA9063 is not set CONFIG_REGULATOR_DA9121=y # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set CONFIG_REGULATOR_FAN53555=m # CONFIG_REGULATOR_FAN53880 is not set CONFIG_REGULATOR_GPIO=m CONFIG_REGULATOR_ISL9305=m CONFIG_REGULATOR_ISL6271A=y # CONFIG_REGULATOR_LOCHNAGAR is not set # CONFIG_REGULATOR_LP3971 is not set CONFIG_REGULATOR_LP3972=m # CONFIG_REGULATOR_LP872X is not set CONFIG_REGULATOR_LP873X=m CONFIG_REGULATOR_LP8755=m # CONFIG_REGULATOR_LP8788 is not set CONFIG_REGULATOR_LTC3589=m # CONFIG_REGULATOR_LTC3676 is not set # CONFIG_REGULATOR_MAX14577 is not set CONFIG_REGULATOR_MAX1586=y CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX77650=m CONFIG_REGULATOR_MAX8649=y # CONFIG_REGULATOR_MAX8660 is not set CONFIG_REGULATOR_MAX8893=y CONFIG_REGULATOR_MAX8907=y # CONFIG_REGULATOR_MAX8952 is not set CONFIG_REGULATOR_MAX20086=m CONFIG_REGULATOR_MAX77686=m CONFIG_REGULATOR_MAX77693=y CONFIG_REGULATOR_MAX77802=y # CONFIG_REGULATOR_MAX77826 is not set CONFIG_REGULATOR_MCP16502=m CONFIG_REGULATOR_MP5416=y CONFIG_REGULATOR_MP8859=m # CONFIG_REGULATOR_MP886X is not set CONFIG_REGULATOR_MPQ7920=m CONFIG_REGULATOR_MT6311=m # CONFIG_REGULATOR_MT6315 is not set CONFIG_REGULATOR_MT6323=m CONFIG_REGULATOR_MT6358=m CONFIG_REGULATOR_MT6359=m CONFIG_REGULATOR_MT6360=m CONFIG_REGULATOR_MT6380=m CONFIG_REGULATOR_MT6397=m CONFIG_REGULATOR_PBIAS=m # CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PCF50633 is not set # CONFIG_REGULATOR_PF8X00 is not set CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88060 is not set CONFIG_REGULATOR_PV88080=m # CONFIG_REGULATOR_PV88090 is not set # CONFIG_REGULATOR_QCOM_RPMH is not set CONFIG_REGULATOR_QCOM_SMD_RPM=m CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_QCOM_USB_VBUS=m CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m CONFIG_REGULATOR_RC5T583=m CONFIG_REGULATOR_RK808=m CONFIG_REGULATOR_RT4801=y CONFIG_REGULATOR_RT4831=m CONFIG_REGULATOR_RT5190A=y # CONFIG_REGULATOR_RT5759 is not set CONFIG_REGULATOR_RT6160=m # CONFIG_REGULATOR_RT6245 is not set CONFIG_REGULATOR_RTQ2134=m CONFIG_REGULATOR_RTMV20=y # CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=m CONFIG_REGULATOR_SC2731=y CONFIG_REGULATOR_SKY81452=m # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_STM32_BOOSTER is not set # CONFIG_REGULATOR_STM32_VREFBUF is not set # CONFIG_REGULATOR_STM32_PWR is not set CONFIG_REGULATOR_STPMIC1=m CONFIG_REGULATOR_TI_ABB=m CONFIG_REGULATOR_STW481X_VMMC=y # CONFIG_REGULATOR_SY7636A is not set # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set CONFIG_REGULATOR_SY8827N=y CONFIG_REGULATOR_TPS51632=m CONFIG_REGULATOR_TPS6105X=y CONFIG_REGULATOR_TPS62360=m CONFIG_REGULATOR_TPS6286X=m # CONFIG_REGULATOR_TPS65023 is not set # CONFIG_REGULATOR_TPS6507X is not set CONFIG_REGULATOR_TPS65086=m CONFIG_REGULATOR_TPS65090=y CONFIG_REGULATOR_TPS65132=y # CONFIG_REGULATOR_TPS65217 is not set CONFIG_REGULATOR_TPS65218=m CONFIG_REGULATOR_TPS65910=m # CONFIG_REGULATOR_TPS65912 is not set CONFIG_REGULATOR_TPS68470=y # CONFIG_REGULATOR_TWL4030 is not set # CONFIG_REGULATOR_UNIPHIER is not set CONFIG_REGULATOR_VCTRL=y CONFIG_REGULATOR_WM831X=y CONFIG_REGULATOR_WM8400=m CONFIG_REGULATOR_WM8994=m # CONFIG_REGULATOR_QCOM_LABIBB is not set CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y CONFIG_CEC_PIN=y # # CEC support # CONFIG_CEC_PIN_ERROR_INJ=y CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_CEC_CH7322=m # CONFIG_CEC_CROS_EC is not set # CONFIG_CEC_MESON_AO is not set # CONFIG_CEC_MESON_G12A_AO is not set CONFIG_CEC_GPIO=m # CONFIG_CEC_SAMSUNG_S5P is not set CONFIG_CEC_STI=m CONFIG_CEC_STM32=y CONFIG_CEC_TEGRA=y # end of CEC support # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # CONFIG_HAVE_FB_ATMEL=y CONFIG_TEGRA_HOST1X_CONTEXT_BUS=y CONFIG_TEGRA_HOST1X=m # CONFIG_TEGRA_HOST1X_FIREWALL is not set CONFIG_IMX_IPUV3_CORE=m CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set CONFIG_DRM_DEBUG_SELFTEST=m CONFIG_DRM_KUNIT_TEST=y CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS=y # CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DP_AUX_BUS=y CONFIG_DRM_DISPLAY_HELPER=y CONFIG_DRM_DISPLAY_DP_HELPER=y CONFIG_DRM_DISPLAY_HDCP_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_BUDDY=m CONFIG_DRM_GEM_CMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_SCHED=y # # I2C encoder or helper chips # CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_SIL164 is not set CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_I2C_NXP_TDA9950=m # end of I2C encoder or helper chips # # ARM devices # CONFIG_DRM_HDLCD=y CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y CONFIG_DRM_MALI_DISPLAY=m CONFIG_DRM_KOMEDA=m # end of ARM devices # CONFIG_DRM_KMB_DISPLAY is not set CONFIG_DRM_VGEM=y CONFIG_DRM_VKMS=y CONFIG_DRM_EXYNOS=y # # CRTCs # # CONFIG_DRM_EXYNOS_FIMD is not set CONFIG_DRM_EXYNOS5433_DECON=y # CONFIG_DRM_EXYNOS7_DECON is not set # CONFIG_DRM_EXYNOS_MIXER is not set CONFIG_DRM_EXYNOS_VIDI=y # # Encoders and Bridges # CONFIG_DRM_EXYNOS_DSI=y CONFIG_DRM_EXYNOS_HDMI=y # CONFIG_DRM_EXYNOS_MIC is not set # # Sub-drivers # # CONFIG_DRM_EXYNOS_G2D is not set CONFIG_DRM_EXYNOS_IPP=y # CONFIG_DRM_EXYNOS_FIMC is not set CONFIG_DRM_EXYNOS_ROTATOR=y # CONFIG_DRM_EXYNOS_SCALER is not set CONFIG_DRM_EXYNOS_GSC=y CONFIG_DRM_ARMADA=m CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_RCAR_DU=m CONFIG_DRM_RCAR_USE_CMM=y CONFIG_DRM_RCAR_CMM=m CONFIG_DRM_RCAR_DW_HDMI=m CONFIG_DRM_RCAR_USE_LVDS=y CONFIG_DRM_RCAR_LVDS=m CONFIG_DRM_RCAR_MIPI_DSI=y CONFIG_DRM_SHMOBILE=m CONFIG_DRM_SUN4I=m # CONFIG_DRM_SUN4I_HDMI is not set CONFIG_DRM_SUN4I_BACKEND=m # CONFIG_DRM_SUN6I_DSI is not set # CONFIG_DRM_SUN8I_DW_HDMI is not set CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_SUN8I_TCON_TOP=m CONFIG_DRM_OMAP=m CONFIG_OMAP2_DSS_DEBUG=y # CONFIG_OMAP2_DSS_DEBUGFS is not set CONFIG_OMAP2_DSS_DPI=y CONFIG_OMAP2_DSS_VENC=y # CONFIG_OMAP4_DSS_HDMI is not set # CONFIG_OMAP5_DSS_HDMI is not set CONFIG_OMAP2_DSS_SDI=y CONFIG_OMAP2_DSS_DSI=y CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 # CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET is not set CONFIG_DRM_TILCDC=y CONFIG_DRM_VIRTIO_GPU=y # CONFIG_DRM_MSM is not set CONFIG_DRM_FSL_DCU=m CONFIG_DRM_TEGRA=m CONFIG_DRM_TEGRA_DEBUG=y CONFIG_DRM_STM=m # CONFIG_DRM_STM_DSI is not set CONFIG_DRM_PANEL=y # # Display Panels # CONFIG_DRM_PANEL_ARM_VERSATILE=m CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=y CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=y CONFIG_DRM_PANEL_DSI_CM=y # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_EDP is not set # CONFIG_DRM_PANEL_EBBG_FT8719 is not set CONFIG_DRM_PANEL_ELIDA_KD35T133=y CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=y CONFIG_DRM_PANEL_ILITEK_ILI9881C=m CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_JDI_R63452 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=y CONFIG_DRM_PANEL_NOVATEK_NT35510=y # CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set CONFIG_DRM_PANEL_NOVATEK_NT35950=y CONFIG_DRM_PANEL_NOVATEK_NT36672A=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m CONFIG_DRM_PANEL_RAYDIUM_RM67191=m # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=y # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m # CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=y # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set CONFIG_DRM_PANEL_XINPENG_XPP055C272=m # end of Display Panels CONFIG_DRM_BRIDGE=y CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # CONFIG_DRM_CDNS_DSI=y # CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_CROS_EC_ANX7688=m CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_FSL_LDB=y CONFIG_DRM_ITE_IT6505=y # CONFIG_DRM_LONTIUM_LT8912B is not set # CONFIG_DRM_LONTIUM_LT9211 is not set CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_ITE_IT66121=m # CONFIG_DRM_LVDS_CODEC is not set CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=y # CONFIG_DRM_NWL_MIPI_DSI is not set CONFIG_DRM_NXP_PTN3460=m CONFIG_DRM_PARADE_PS8622=y # CONFIG_DRM_PARADE_PS8640 is not set CONFIG_DRM_SIL_SII8620=m CONFIG_DRM_SII902X=m CONFIG_DRM_SII9234=y CONFIG_DRM_SIMPLE_BRIDGE=y # CONFIG_DRM_THINE_THC63LVD1024 is not set # CONFIG_DRM_TOSHIBA_TC358762 is not set # CONFIG_DRM_TOSHIBA_TC358764 is not set CONFIG_DRM_TOSHIBA_TC358767=y CONFIG_DRM_TOSHIBA_TC358768=y CONFIG_DRM_TOSHIBA_TC358775=m CONFIG_DRM_TI_DLPC3433=m CONFIG_DRM_TI_TFP410=m # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set CONFIG_DRM_TI_TPD12S015=m CONFIG_DRM_ANALOGIX_ANX6345=y CONFIG_DRM_ANALOGIX_ANX78XX=m CONFIG_DRM_ANALOGIX_DP=y # CONFIG_DRM_ANALOGIX_ANX7625 is not set CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_I2C_ADV7511_CEC=y CONFIG_DRM_CDNS_MHDP8546=y # CONFIG_DRM_CDNS_MHDP8546_J721E is not set CONFIG_DRM_IMX8QM_LDB=m # CONFIG_DRM_IMX8QXP_LDB is not set # CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=m CONFIG_DRM_DW_HDMI=y # CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set CONFIG_DRM_DW_HDMI_CEC=y # end of Display Interface Bridges CONFIG_DRM_STI=y # CONFIG_DRM_IMX is not set # CONFIG_DRM_INGENIC is not set # CONFIG_DRM_V3D is not set CONFIG_DRM_ETNAVIV=y # CONFIG_DRM_ETNAVIV_THERMAL is not set # CONFIG_DRM_LOGICVC is not set CONFIG_DRM_MXS=y CONFIG_DRM_MXSFB=m CONFIG_DRM_IMX_LCDIF=y CONFIG_DRM_MESON=y CONFIG_DRM_MESON_DW_HDMI=y CONFIG_DRM_ARCPGU=y # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_DRM_PL111 is not set CONFIG_DRM_TVE200=m CONFIG_DRM_LIMA=y CONFIG_DRM_PANFROST=y # CONFIG_DRM_ASPEED_GFX is not set CONFIG_DRM_MCDE=y CONFIG_DRM_TIDSS=m CONFIG_DRM_SSD130X=m CONFIG_DRM_SSD130X_I2C=m # CONFIG_DRM_SPRD is not set CONFIG_DRM_LEGACY=y CONFIG_DRM_EXPORT_FOR_TESTS=y CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y CONFIG_DRM_NOMODESET=y CONFIG_DRM_LIB_RANDOM=y # # Frame buffer Devices # CONFIG_FB_CMDLINE=y # CONFIG_FB is not set # CONFIG_FB_OMAP_LCD_H3 is not set CONFIG_MMP_DISP=m # CONFIG_MMP_DISP_CONTROLLER is not set # end of Frame buffer Devices # # Backlight & LCD device support # CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_PLATFORM is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_LM3533 is not set CONFIG_BACKLIGHT_OMAP1=m CONFIG_BACKLIGHT_DA9052=m CONFIG_BACKLIGHT_QCOM_WLED=m # CONFIG_BACKLIGHT_RT4831 is not set CONFIG_BACKLIGHT_WM831X=m CONFIG_BACKLIGHT_ADP8860=y CONFIG_BACKLIGHT_ADP8870=m # CONFIG_BACKLIGHT_88PM860X is not set CONFIG_BACKLIGHT_PCF50633=m CONFIG_BACKLIGHT_LM3639=y # CONFIG_BACKLIGHT_PANDORA is not set CONFIG_BACKLIGHT_SKY81452=y # CONFIG_BACKLIGHT_TPS65217 is not set # CONFIG_BACKLIGHT_AS3711 is not set CONFIG_BACKLIGHT_GPIO=y CONFIG_BACKLIGHT_LV5207LP=y CONFIG_BACKLIGHT_BD6107=m CONFIG_BACKLIGHT_ARCXCNN=y CONFIG_BACKLIGHT_LED=y # end of Backlight & LCD device support CONFIG_VIDEOMODE_HELPERS=y CONFIG_HDMI=y # end of Graphics support # CONFIG_SOUND is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=m # CONFIG_PWRSEQ_SD8787 is not set # CONFIG_PWRSEQ_SIMPLE is not set CONFIG_MMC_TEST=y # # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_ARMMMCI is not set CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y # CONFIG_MMC_SDHCI_OF_ASPEED is not set # CONFIG_MMC_SDHCI_OF_AT91 is not set CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_MMC_SDHCI_OF_DWCMSHC=m # CONFIG_MMC_SDHCI_OF_SPARX5 is not set CONFIG_MMC_SDHCI_CADENCE=y # CONFIG_MMC_SDHCI_CNS3XXX is not set CONFIG_MMC_SDHCI_ESDHC_IMX=m # CONFIG_MMC_SDHCI_DOVE is not set # CONFIG_MMC_SDHCI_TEGRA is not set # CONFIG_MMC_SDHCI_S3C is not set # CONFIG_MMC_SDHCI_PXAV3 is not set CONFIG_MMC_SDHCI_PXAV2=m CONFIG_MMC_SDHCI_SPEAR=m CONFIG_MMC_SDHCI_BCM_KONA=m CONFIG_MMC_SDHCI_F_SDH30=y CONFIG_MMC_SDHCI_MILBEAUT=y CONFIG_MMC_SDHCI_IPROC=y # CONFIG_MMC_MESON_GX is not set CONFIG_MMC_MESON_MX_SDHC=y # CONFIG_MMC_MESON_MX_SDIO is not set # CONFIG_MMC_MOXART is not set CONFIG_MMC_SDHCI_ST=y # CONFIG_MMC_OMAP_HS is not set CONFIG_MMC_ATMELMCI=y # CONFIG_MMC_SDHCI_MSM is not set CONFIG_MMC_MXS=m CONFIG_MMC_MVSDIO=y CONFIG_MMC_DAVINCI=y CONFIG_MMC_S3C=y CONFIG_MMC_S3C_HW_SDIO_IRQ=y # CONFIG_MMC_S3C_PIO is not set CONFIG_MMC_S3C_DMA=y CONFIG_MMC_SDHCI_SPRD=y CONFIG_MMC_TMIO_CORE=y CONFIG_MMC_TMIO=y # CONFIG_MMC_SDHI is not set # CONFIG_MMC_UNIPHIER is not set # CONFIG_MMC_DW is not set CONFIG_MMC_SH_MMCIF=m # CONFIG_MMC_USDHI6ROL0 is not set CONFIG_MMC_CQHCI=y CONFIG_MMC_HSQ=y CONFIG_MMC_BCM2835=m # CONFIG_MMC_MTK is not set CONFIG_MMC_SDHCI_XENON=y # CONFIG_MMC_SDHCI_OMAP is not set CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_OWL=y # CONFIG_MMC_LITEX is not set CONFIG_MEMSTICK=m CONFIG_MEMSTICK_DEBUG=y # # MemoryStick drivers # CONFIG_MEMSTICK_UNSAFE_RESUME=y # # MemoryStick Host Controller Drivers # CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y # # LED drivers # CONFIG_LEDS_88PM860X=m # CONFIG_LEDS_AN30259A is not set # CONFIG_LEDS_ARIEL is not set # CONFIG_LEDS_AW2013 is not set CONFIG_LEDS_BCM6328=m CONFIG_LEDS_BCM6358=m # CONFIG_LEDS_TURRIS_OMNIA is not set CONFIG_LEDS_LM3530=y # CONFIG_LEDS_LM3532 is not set CONFIG_LEDS_LM3533=m CONFIG_LEDS_LM3642=y CONFIG_LEDS_LM3692X=y # CONFIG_LEDS_MT6323 is not set CONFIG_LEDS_S3C24XX=y # CONFIG_LEDS_COBALT_QUBE is not set # CONFIG_LEDS_COBALT_RAQ is not set CONFIG_LEDS_GPIO=y CONFIG_LEDS_LP3944=y CONFIG_LEDS_LP3952=y CONFIG_LEDS_LP50XX=m # CONFIG_LEDS_LP55XX_COMMON is not set CONFIG_LEDS_LP8788=y CONFIG_LEDS_LP8860=y CONFIG_LEDS_PCA955X=y # CONFIG_LEDS_PCA955X_GPIO is not set CONFIG_LEDS_PCA963X=m CONFIG_LEDS_WM831X_STATUS=m # CONFIG_LEDS_DA9052 is not set CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_BD2802=m # CONFIG_LEDS_LT3593 is not set CONFIG_LEDS_NS2=y CONFIG_LEDS_NETXBIG=y CONFIG_LEDS_ASIC3=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_MAX77650 is not set # CONFIG_LEDS_LM355x is not set CONFIG_LEDS_OT200=y CONFIG_LEDS_IS31FL319X=m CONFIG_LEDS_IS31FL32XX=y # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # CONFIG_LEDS_BLINKM=m CONFIG_LEDS_SYSCON=y CONFIG_LEDS_PM8058=m CONFIG_LEDS_MLXREG=m CONFIG_LEDS_USER=m CONFIG_LEDS_TI_LMU_COMMON=m CONFIG_LEDS_LM3697=m # CONFIG_LEDS_TPS6105X is not set # CONFIG_LEDS_IP30 is not set # CONFIG_LEDS_ACER_A500 is not set # CONFIG_LEDS_BCM63138 is not set # CONFIG_LEDS_LGM is not set # # Flash and Torch LED drivers # # # RGB LED drivers # # # LED Triggers # CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_ONESHOT=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m # # iptables trigger is under Netfilter config (LED target) # # CONFIG_LEDS_TRIGGER_TRANSIENT is not set CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_LEDS_TRIGGER_PANIC=y # CONFIG_LEDS_TRIGGER_NETDEV is not set CONFIG_LEDS_TRIGGER_PATTERN=y # CONFIG_LEDS_TRIGGER_AUDIO is not set # # Simple LED drivers # # CONFIG_ACCESSIBILITY is not set CONFIG_INFINIBAND=m # CONFIG_INFINIBAND_USER_MAD is not set # CONFIG_INFINIBAND_USER_ACCESS is not set # CONFIG_INFINIBAND_ADDR_TRANS is not set CONFIG_INFINIBAND_VIRT_DMA=y # CONFIG_RDMA_SIW is not set CONFIG_INFINIBAND_IPOIB=m CONFIG_INFINIBAND_IPOIB_CM=y CONFIG_INFINIBAND_IPOIB_DEBUG=y # CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set CONFIG_DMADEVICES=y CONFIG_DMADEVICES_DEBUG=y # CONFIG_DMADEVICES_VDEBUG is not set # # DMA Devices # CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y CONFIG_DMA_ENGINE=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DMA_OF=y # CONFIG_ALTERA_MSGDMA is not set CONFIG_AMBA_PL08X=y # CONFIG_APPLE_ADMAC is not set # CONFIG_AT_HDMAC is not set # CONFIG_AT_XDMAC is not set # CONFIG_AXI_DMAC is not set CONFIG_DMA_JZ4780=m CONFIG_DMA_SA11X0=m CONFIG_DMA_SUN6I=m CONFIG_DW_AXI_DMAC=m CONFIG_EP93XX_DMA=y # CONFIG_FSL_EDMA is not set CONFIG_FSL_QDMA=m CONFIG_IMG_MDC_DMA=y CONFIG_INTEL_IDMA64=m # CONFIG_INTEL_IOP_ADMA is not set # CONFIG_K3_DMA is not set CONFIG_LPC18XX_DMAMUX=y CONFIG_MCF_EDMA=m CONFIG_MILBEAUT_HDMAC=m # CONFIG_MILBEAUT_XDMAC is not set # CONFIG_MMP_PDMA is not set CONFIG_MMP_TDMA=y CONFIG_MV_XOR=y CONFIG_MXS_DMA=y CONFIG_NBPFAXI_DMA=y CONFIG_PL330_DMA=y CONFIG_PXA_DMA=y CONFIG_STM32_DMA=y # CONFIG_STM32_DMAMUX is not set CONFIG_STM32_MDMA=y CONFIG_SPRD_DMA=m CONFIG_S3C24XX_DMAC=y CONFIG_TEGRA20_APB_DMA=y CONFIG_TEGRA210_ADMA=y # CONFIG_TIMB_DMA is not set # CONFIG_UNIPHIER_MDMAC is not set # CONFIG_UNIPHIER_XDMAC is not set CONFIG_XGENE_DMA=y CONFIG_XILINX_ZYNQMP_DMA=y # CONFIG_XILINX_ZYNQMP_DPDMA is not set CONFIG_MTK_HSDMA=m CONFIG_MTK_CQDMA=m CONFIG_QCOM_ADM=m CONFIG_QCOM_BAM_DMA=y CONFIG_QCOM_HIDMA_MGMT=m CONFIG_QCOM_HIDMA=y # CONFIG_DW_DMAC is not set CONFIG_SF_PDMA=m CONFIG_RENESAS_DMA=y # CONFIG_SH_DMAE_BASE is not set CONFIG_RCAR_DMAC=y CONFIG_RENESAS_USB_DMAC=y # CONFIG_RZ_DMAC is not set CONFIG_TI_EDMA=m CONFIG_DMA_OMAP=m CONFIG_TI_DMA_CROSSBAR=y CONFIG_INTEL_LDMA=y # # DMA Clients # # CONFIG_ASYNC_TX_DMA is not set # CONFIG_DMATEST is not set CONFIG_DMA_ENGINE_RAID=y # # DMABUF options # CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set CONFIG_UDMABUF=y CONFIG_DMABUF_MOVE_NOTIFY=y CONFIG_DMABUF_DEBUG=y CONFIG_DMABUF_SELFTESTS=m # CONFIG_DMABUF_HEAPS is not set # CONFIG_DMABUF_SYSFS_STATS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set # CONFIG_PANEL is not set CONFIG_UIO=m # CONFIG_UIO_PDRV_GENIRQ is not set CONFIG_UIO_DMEM_GENIRQ=m # CONFIG_UIO_PRUSS is not set # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_MENU=y # CONFIG_VIRTIO_VDPA is not set CONFIG_VIRTIO_BALLOON=m CONFIG_VIRTIO_MMIO=y # CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set CONFIG_VIRTIO_DMA_SHARED_BUFFER=y CONFIG_VDPA=y # CONFIG_VDPA_SIM is not set CONFIG_VDPA_USER=y CONFIG_VHOST_IOTLB=y # CONFIG_VHOST_MENU is not set # # Microsoft Hyper-V guest support # # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set CONFIG_COMEDI=m CONFIG_COMEDI_DEBUG=y CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 CONFIG_COMEDI_MISC_DRIVERS=y CONFIG_COMEDI_BOND=m # CONFIG_COMEDI_TEST is not set CONFIG_COMEDI_PARPORT=m # CONFIG_COMEDI_SSV_DNP is not set # CONFIG_COMEDI_ISA_DRIVERS is not set CONFIG_COMEDI_PCMCIA_DRIVERS=m CONFIG_COMEDI_CB_DAS16_CS=m CONFIG_COMEDI_DAS08_CS=m CONFIG_COMEDI_NI_DAQ_700_CS=m # CONFIG_COMEDI_NI_DAQ_DIO24_CS is not set CONFIG_COMEDI_NI_LABPC_CS=m CONFIG_COMEDI_NI_MIO_CS=m CONFIG_COMEDI_QUATECH_DAQP_CS=m CONFIG_COMEDI_8254=m CONFIG_COMEDI_8255=m CONFIG_COMEDI_8255_SA=m CONFIG_COMEDI_KCOMEDILIB=m CONFIG_COMEDI_DAS08=m CONFIG_COMEDI_NI_LABPC=m CONFIG_COMEDI_NI_TIO=m CONFIG_COMEDI_NI_ROUTING=m # CONFIG_COMEDI_TESTS is not set # CONFIG_STAGING is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=m CONFIG_CROS_EC_I2C=m CONFIG_CROS_EC_RPMSG=m CONFIG_CROS_EC_PROTO=y CONFIG_CROS_KBD_LED_BACKLIGHT=m CONFIG_CROS_EC_CHARDEV=m # CONFIG_CROS_EC_LIGHTBAR is not set CONFIG_CROS_EC_VBC=m CONFIG_CROS_EC_DEBUGFS=m # CONFIG_CROS_EC_SENSORHUB is not set CONFIG_CROS_EC_SYSFS=m # CONFIG_CROS_USBPD_LOGGER is not set CONFIG_CROS_USBPD_NOTIFY=m CONFIG_CROS_KUNIT=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_OLPC_XO175 is not set CONFIG_SURFACE_PLATFORMS=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_WM831X is not set # # Clock driver for ARM Reference designs # CONFIG_CLK_ICST=y CONFIG_CLK_SP810=y # end of Clock driver for ARM Reference designs CONFIG_CLK_HSDK=y CONFIG_COMMON_CLK_APPLE_NCO=m CONFIG_COMMON_CLK_MAX77686=y CONFIG_COMMON_CLK_MAX9485=m CONFIG_COMMON_CLK_RK808=m CONFIG_COMMON_CLK_HI655X=m # CONFIG_COMMON_CLK_SCMI is not set CONFIG_COMMON_CLK_SCPI=m CONFIG_COMMON_CLK_SI5341=y CONFIG_COMMON_CLK_SI5351=y CONFIG_COMMON_CLK_SI514=m CONFIG_COMMON_CLK_SI544=m # CONFIG_COMMON_CLK_SI570 is not set # CONFIG_COMMON_CLK_BM1880 is not set # CONFIG_COMMON_CLK_CDCE706 is not set CONFIG_COMMON_CLK_TPS68470=y # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set # CONFIG_COMMON_CLK_EN7523 is not set CONFIG_COMMON_CLK_FSL_FLEXSPI=m # CONFIG_COMMON_CLK_FSL_SAI is not set # CONFIG_COMMON_CLK_GEMINI is not set CONFIG_COMMON_CLK_LAN966X=y CONFIG_COMMON_CLK_ASPEED=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_TWL6040=m # CONFIG_COMMON_CLK_AXI_CLKGEN is not set CONFIG_CLK_QORIQ=y CONFIG_CLK_LS1028A_PLLDIG=y # CONFIG_COMMON_CLK_XGENE is not set CONFIG_COMMON_CLK_LOCHNAGAR=y CONFIG_COMMON_CLK_NXP=y CONFIG_COMMON_CLK_OXNAS=y CONFIG_COMMON_CLK_RS9_PCIE=m CONFIG_COMMON_CLK_VC5=y # CONFIG_COMMON_CLK_MMP2_AUDIO is not set CONFIG_COMMON_CLK_FIXED_MMIO=y CONFIG_CLK_ACTIONS=y CONFIG_CLK_OWL_S500=y # CONFIG_CLK_OWL_S700 is not set CONFIG_CLK_OWL_S900=y # CONFIG_CLK_BAIKAL_T1 is not set CONFIG_CLK_BCM2711_DVP=y CONFIG_CLK_BCM2835=y CONFIG_CLK_BCM_63XX=y # CONFIG_CLK_BCM_63XX_GATE is not set # CONFIG_CLK_BCM_KONA is not set CONFIG_COMMON_CLK_IPROC=y CONFIG_CLK_BCM_CYGNUS=y CONFIG_CLK_BCM_HR2=y CONFIG_CLK_BCM_NSP=y CONFIG_CLK_BCM_NS2=y # CONFIG_CLK_BCM_SR is not set CONFIG_CLK_RASPBERRYPI=m CONFIG_COMMON_CLK_HI3516CV300=y CONFIG_COMMON_CLK_HI3519=m # CONFIG_COMMON_CLK_HI3559A is not set # CONFIG_COMMON_CLK_HI3660 is not set # CONFIG_COMMON_CLK_HI3670 is not set CONFIG_COMMON_CLK_HI3798CV200=y CONFIG_COMMON_CLK_HI6220=y CONFIG_RESET_HISI=y CONFIG_STUB_CLK_HI6220=y CONFIG_STUB_CLK_HI3660=y # CONFIG_COMMON_CLK_BOSTON is not set CONFIG_MXC_CLK=y # CONFIG_CLK_IMX8MM is not set CONFIG_CLK_IMX8MN=m CONFIG_CLK_IMX8MP=m CONFIG_CLK_IMX8MQ=m CONFIG_CLK_IMX8ULP=y # CONFIG_CLK_IMX93 is not set # # Ingenic SoCs drivers # CONFIG_INGENIC_CGU_COMMON=y # CONFIG_INGENIC_CGU_JZ4740 is not set CONFIG_INGENIC_CGU_JZ4725B=y # CONFIG_INGENIC_CGU_JZ4760 is not set # CONFIG_INGENIC_CGU_JZ4770 is not set # CONFIG_INGENIC_CGU_JZ4780 is not set # CONFIG_INGENIC_CGU_X1000 is not set CONFIG_INGENIC_CGU_X1830=y # CONFIG_INGENIC_TCU_CLK is not set # end of Ingenic SoCs drivers CONFIG_COMMON_CLK_KEYSTONE=m # CONFIG_TI_SYSCON_CLK is not set # # Clock driver for MediaTek SoC # CONFIG_COMMON_CLK_MEDIATEK=y CONFIG_COMMON_CLK_MT2701=y # CONFIG_COMMON_CLK_MT2701_MMSYS is not set # CONFIG_COMMON_CLK_MT2701_IMGSYS is not set CONFIG_COMMON_CLK_MT2701_VDECSYS=y CONFIG_COMMON_CLK_MT2701_HIFSYS=y # CONFIG_COMMON_CLK_MT2701_ETHSYS is not set # CONFIG_COMMON_CLK_MT2701_BDPSYS is not set CONFIG_COMMON_CLK_MT2701_AUDSYS=y CONFIG_COMMON_CLK_MT2701_G3DSYS=y # CONFIG_COMMON_CLK_MT2712 is not set # CONFIG_COMMON_CLK_MT6765 is not set CONFIG_COMMON_CLK_MT6779=y CONFIG_COMMON_CLK_MT6779_MMSYS=y CONFIG_COMMON_CLK_MT6779_IMGSYS=m CONFIG_COMMON_CLK_MT6779_IPESYS=y # CONFIG_COMMON_CLK_MT6779_CAMSYS is not set CONFIG_COMMON_CLK_MT6779_VDECSYS=m CONFIG_COMMON_CLK_MT6779_VENCSYS=m CONFIG_COMMON_CLK_MT6779_MFGCFG=m # CONFIG_COMMON_CLK_MT6779_AUDSYS is not set CONFIG_COMMON_CLK_MT6797=y # CONFIG_COMMON_CLK_MT6797_MMSYS is not set CONFIG_COMMON_CLK_MT6797_IMGSYS=y # CONFIG_COMMON_CLK_MT6797_VDECSYS is not set CONFIG_COMMON_CLK_MT6797_VENCSYS=y CONFIG_COMMON_CLK_MT7622=y # CONFIG_COMMON_CLK_MT7622_ETHSYS is not set CONFIG_COMMON_CLK_MT7622_HIFSYS=y CONFIG_COMMON_CLK_MT7622_AUDSYS=y CONFIG_COMMON_CLK_MT7629=y CONFIG_COMMON_CLK_MT7629_ETHSYS=y CONFIG_COMMON_CLK_MT7629_HIFSYS=y CONFIG_COMMON_CLK_MT7986=y CONFIG_COMMON_CLK_MT7986_ETHSYS=y CONFIG_COMMON_CLK_MT8135=y # CONFIG_COMMON_CLK_MT8167 is not set # CONFIG_COMMON_CLK_MT8173 is not set # CONFIG_COMMON_CLK_MT8183 is not set # CONFIG_COMMON_CLK_MT8186 is not set # CONFIG_COMMON_CLK_MT8192 is not set CONFIG_COMMON_CLK_MT8195=y CONFIG_COMMON_CLK_MT8516=y # CONFIG_COMMON_CLK_MT8516_AUDSYS is not set # end of Clock driver for MediaTek SoC # # Clock support for Amlogic platforms # # CONFIG_COMMON_CLK_MESON8B is not set # end of Clock support for Amlogic platforms CONFIG_MSTAR_MSC313_MPLL=y # CONFIG_MCHP_CLK_MPFS is not set # CONFIG_COMMON_CLK_PISTACHIO is not set # CONFIG_COMMON_CLK_QCOM is not set CONFIG_CLK_MT7621=y CONFIG_CLK_RENESAS=y # CONFIG_CLK_EMEV2 is not set # CONFIG_CLK_RZA1 is not set # CONFIG_CLK_R7S9210 is not set CONFIG_CLK_R8A73A4=y # CONFIG_CLK_R8A7740 is not set CONFIG_CLK_R8A7742=y CONFIG_CLK_R8A7743=y # CONFIG_CLK_R8A7745 is not set CONFIG_CLK_R8A77470=y # CONFIG_CLK_R8A774A1 is not set CONFIG_CLK_R8A774B1=y CONFIG_CLK_R8A774C0=y # CONFIG_CLK_R8A774E1 is not set CONFIG_CLK_R8A7778=y # CONFIG_CLK_R8A7779 is not set # CONFIG_CLK_R8A7790 is not set CONFIG_CLK_R8A7791=y CONFIG_CLK_R8A7792=y CONFIG_CLK_R8A7794=y CONFIG_CLK_R8A7795=y CONFIG_CLK_R8A77960=y CONFIG_CLK_R8A77961=y # CONFIG_CLK_R8A77965 is not set # CONFIG_CLK_R8A77970 is not set # CONFIG_CLK_R8A77980 is not set # CONFIG_CLK_R8A77990 is not set # CONFIG_CLK_R8A77995 is not set # CONFIG_CLK_R8A779A0 is not set # CONFIG_CLK_R8A779F0 is not set # CONFIG_CLK_R8A779G0 is not set CONFIG_CLK_R9A06G032=y # CONFIG_CLK_R9A07G043 is not set CONFIG_CLK_R9A07G044=y CONFIG_CLK_R9A07G054=y # CONFIG_CLK_R9A09G011 is not set # CONFIG_CLK_SH73A0 is not set CONFIG_CLK_RCAR_CPG_LIB=y CONFIG_CLK_RCAR_GEN2_CPG=y CONFIG_CLK_RCAR_GEN3_CPG=y CONFIG_CLK_RCAR_GEN4_CPG=y # CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set CONFIG_CLK_RZG2L=y CONFIG_CLK_RENESAS_CPG_MSSR=y CONFIG_CLK_RENESAS_CPG_MSTP=y CONFIG_CLK_RENESAS_DIV6=y CONFIG_COMMON_CLK_SAMSUNG=y # CONFIG_S3C64XX_COMMON_CLK is not set # CONFIG_S5PV210_COMMON_CLK is not set CONFIG_EXYNOS_3250_COMMON_CLK=y CONFIG_EXYNOS_4_COMMON_CLK=y # CONFIG_EXYNOS_5250_COMMON_CLK is not set CONFIG_EXYNOS_5260_COMMON_CLK=y # CONFIG_EXYNOS_5410_COMMON_CLK is not set # CONFIG_EXYNOS_5420_COMMON_CLK is not set # CONFIG_EXYNOS_ARM64_COMMON_CLK is not set CONFIG_EXYNOS_AUDSS_CLK_CON=y CONFIG_EXYNOS_CLKOUT=y # CONFIG_S3C2410_COMMON_CLK is not set CONFIG_S3C2412_COMMON_CLK=y # CONFIG_S3C2443_COMMON_CLK is not set # CONFIG_CLK_SIFIVE is not set CONFIG_CLK_INTEL_SOCFPGA=y CONFIG_CLK_INTEL_SOCFPGA32=y CONFIG_CLK_INTEL_SOCFPGA64=y CONFIG_SPRD_COMMON_CLK=m CONFIG_SPRD_SC9860_CLK=m # CONFIG_SPRD_SC9863A_CLK is not set # CONFIG_CLK_STARFIVE_JH7100 is not set # CONFIG_CLK_SUNXI is not set # CONFIG_SUNXI_CCU is not set # CONFIG_COMMON_CLK_TI_ADPLL is not set # CONFIG_CLK_UNIPHIER is not set CONFIG_COMMON_CLK_VISCONTI=y CONFIG_CLK_LGM_CGU=y CONFIG_XILINX_VCU=m CONFIG_COMMON_CLK_ZYNQMP=y CONFIG_CLK_KUNIT_TEST=y CONFIG_CLK_GATE_KUNIT_TEST=y CONFIG_HWSPINLOCK=y # CONFIG_HWSPINLOCK_OMAP is not set CONFIG_HWSPINLOCK_QCOM=m CONFIG_HWSPINLOCK_SPRD=y CONFIG_HWSPINLOCK_STM32=m CONFIG_HWSPINLOCK_SUN6I=m CONFIG_HSEM_U8500=y # # Clock Source drivers # CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_MMIO=y # CONFIG_BCM2835_TIMER is not set # CONFIG_BCM_KONA_TIMER is not set CONFIG_DAVINCI_TIMER=y CONFIG_DIGICOLOR_TIMER=y # CONFIG_OMAP_DM_TIMER is not set CONFIG_DW_APB_TIMER=y # CONFIG_FTTMR010_TIMER is not set CONFIG_IXP4XX_TIMER=y # CONFIG_ROCKCHIP_TIMER is not set CONFIG_ARMADA_370_XP_TIMER=y # CONFIG_MESON6_TIMER is not set # CONFIG_ORION_TIMER is not set CONFIG_OWL_TIMER=y # CONFIG_RDA_TIMER is not set CONFIG_SUN4I_TIMER=y # CONFIG_SUN5I_HSTIMER is not set CONFIG_TEGRA_TIMER=y CONFIG_TEGRA186_TIMER=y CONFIG_VT8500_TIMER=y CONFIG_NPCM7XX_TIMER=y CONFIG_CADENCE_TTC_TIMER=y CONFIG_ASM9260_TIMER=y CONFIG_CLKSRC_NOMADIK_MTU=y # CONFIG_CLKSRC_DBX500_PRCMU is not set CONFIG_CLPS711X_TIMER=y CONFIG_MXS_TIMER=y # CONFIG_NSPIRE_TIMER is not set CONFIG_KEYSTONE_TIMER=y CONFIG_INTEGRATOR_AP_TIMER=y CONFIG_CLKSRC_LPC32XX=y # CONFIG_CLKSRC_PISTACHIO is not set CONFIG_CLKSRC_TI_32K=y # CONFIG_CLKSRC_STM32 is not set # CONFIG_CLKSRC_STM32_LP is not set CONFIG_CLKSRC_MPS2=y # CONFIG_ARC_TIMERS is not set # CONFIG_ARM_GLOBAL_TIMER is not set CONFIG_ARM_TIMER_SP804=y CONFIG_ARMV7M_SYSTICK=y # CONFIG_ATMEL_PIT is not set # CONFIG_ATMEL_ST is not set CONFIG_ATMEL_TCB_CLKSRC=y # CONFIG_CLKSRC_EXYNOS_MCT is not set # CONFIG_CLKSRC_SAMSUNG_PWM is not set # CONFIG_FSL_FTM_TIMER is not set CONFIG_OXNAS_RPS_TIMER=y CONFIG_MTK_TIMER=y CONFIG_SPRD_TIMER=y # CONFIG_CLKSRC_JCORE_PIT is not set # CONFIG_SH_TIMER_CMT is not set CONFIG_SH_TIMER_MTU2=y # CONFIG_RENESAS_OSTM is not set # CONFIG_SH_TIMER_TMU is not set # CONFIG_EM_TIMER_STI is not set # CONFIG_CLKSRC_QCOM is not set CONFIG_CLKSRC_VERSATILE=y CONFIG_CLKSRC_PXA=y CONFIG_CLKSRC_IMX_GPT=y CONFIG_CLKSRC_IMX_TPM=y # CONFIG_TIMER_IMX_SYS_CTR is not set # CONFIG_CLKSRC_ST_LPC is not set CONFIG_GXP_TIMER=y # CONFIG_MILBEAUT_TIMER is not set # CONFIG_MSC313E_TIMER is not set # CONFIG_INGENIC_TIMER is not set # CONFIG_INGENIC_SYSOST is not set CONFIG_INGENIC_OST=y CONFIG_MICROCHIP_PIT64B=y # end of Clock Source drivers CONFIG_MAILBOX=y CONFIG_ARM_MHU=m CONFIG_ARM_MHU_V2=m CONFIG_IMX_MBOX=y CONFIG_PLATFORM_MHU=m CONFIG_PL320_MBOX=y CONFIG_ARMADA_37XX_RWTM_MBOX=m CONFIG_ROCKCHIP_MBOX=y CONFIG_ALTERA_MBOX=y # CONFIG_HI3660_MBOX is not set CONFIG_HI6220_MBOX=y # CONFIG_MAILBOX_TEST is not set CONFIG_POLARFIRE_SOC_MAILBOX=y # CONFIG_QCOM_APCS_IPC is not set CONFIG_BCM_PDC_MBOX=y CONFIG_STM32_IPCC=y # CONFIG_MTK_ADSP_MBOX is not set CONFIG_MTK_CMDQ_MBOX=y CONFIG_SUN6I_MSGBOX=y CONFIG_SPRD_MBOX=y # CONFIG_QCOM_IPCC is not set CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # CONFIG_IOMMU_IO_PGTABLE=y CONFIG_IOMMU_IO_PGTABLE_LPAE=y CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST=y # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set # CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y CONFIG_OF_IOMMU=y # CONFIG_MSM_IOMMU is not set CONFIG_OMAP_IOMMU=y CONFIG_OMAP_IOMMU_DEBUG=y # CONFIG_ROCKCHIP_IOMMU is not set CONFIG_SUN50I_IOMMU=y CONFIG_EXYNOS_IOMMU=y CONFIG_EXYNOS_IOMMU_DEBUG=y CONFIG_ARM_SMMU=y CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS=y CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y CONFIG_S390_CCW_IOMMU=y CONFIG_S390_AP_IOMMU=y # CONFIG_MTK_IOMMU is not set CONFIG_MTK_IOMMU_V1=y # CONFIG_SPRD_IOMMU is not set # # Remoteproc drivers # # CONFIG_REMOTEPROC is not set # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=m CONFIG_RPMSG_CHAR=m CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_NS=m CONFIG_RPMSG_QCOM_GLINK=m CONFIG_RPMSG_QCOM_GLINK_RPM=m CONFIG_RPMSG_VIRTIO=m # end of Rpmsg drivers CONFIG_SOUNDWIRE=m # # SoundWire Devices # # # SOC (System On Chip) specific Drivers # CONFIG_OWL_PM_DOMAINS_HELPER=y CONFIG_OWL_PM_DOMAINS=y # # Amlogic SoC drivers # CONFIG_MESON_CANVAS=y CONFIG_MESON_CLK_MEASURE=y # CONFIG_MESON_GX_SOCINFO is not set CONFIG_MESON_GX_PM_DOMAINS=y CONFIG_MESON_EE_PM_DOMAINS=y # CONFIG_MESON_MX_SOCINFO is not set # end of Amlogic SoC drivers # # Apple SoC drivers # # CONFIG_APPLE_PMGR_PWRSTATE is not set CONFIG_APPLE_RTKIT=m CONFIG_APPLE_SART=m # end of Apple SoC drivers # # ASPEED SoC drivers # CONFIG_ASPEED_LPC_CTRL=y CONFIG_ASPEED_LPC_SNOOP=m CONFIG_ASPEED_UART_ROUTING=m CONFIG_ASPEED_P2A_CTRL=y # CONFIG_ASPEED_SOCINFO is not set # end of ASPEED SoC drivers CONFIG_AT91_SOC_ID=y CONFIG_AT91_SOC_SFR=m # # Broadcom SoC drivers # # CONFIG_BCM2835_POWER is not set # CONFIG_SOC_BCM63XX is not set # CONFIG_SOC_BRCMSTB is not set # CONFIG_BCM_PMB is not set # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # CONFIG_QUICC_ENGINE=y CONFIG_FSL_GUTS=y CONFIG_FSL_MC_DPIO=m CONFIG_DPAA2_CONSOLE=y # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # # CONFIG_IMX_GPCV2_PM_DOMAINS is not set # CONFIG_SOC_IMX8M is not set # end of i.MX SoC drivers # # IXP4xx SoC drivers # # CONFIG_IXP4XX_QMGR is not set # CONFIG_IXP4XX_NPE is not set # end of IXP4xx SoC drivers # # Enable LiteX SoC Builder specific drivers # CONFIG_LITEX=y CONFIG_LITEX_SOC_CONTROLLER=m # end of Enable LiteX SoC Builder specific drivers # # MediaTek SoC drivers # CONFIG_MTK_CMDQ=y CONFIG_MTK_DEVAPC=m CONFIG_MTK_INFRACFG=y CONFIG_MTK_PMIC_WRAP=y # CONFIG_MTK_SCPSYS is not set # CONFIG_MTK_SCPSYS_PM_DOMAINS is not set CONFIG_MTK_MMSYS=y # end of MediaTek SoC drivers CONFIG_POLARFIRE_SOC_SYS_CTRL=y CONFIG_PLAT_PXA=y # # Qualcomm SoC drivers # CONFIG_QCOM_AOSS_QMP=m CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_GENI_SE=m # CONFIG_QCOM_GSBI is not set CONFIG_QCOM_LLCC=m CONFIG_QCOM_PDR_HELPERS=m CONFIG_QCOM_QMI_HELPERS=m # CONFIG_QCOM_RPMH is not set CONFIG_QCOM_RPMPD=m # CONFIG_QCOM_SMEM is not set CONFIG_QCOM_SMD_RPM=m CONFIG_QCOM_SPM=y CONFIG_QCOM_WCNSS_CTRL=m CONFIG_QCOM_APR=m CONFIG_QCOM_ICC_BWMON=m # end of Qualcomm SoC drivers CONFIG_SOC_RENESAS=y # CONFIG_RST_RCAR is not set CONFIG_SYSC_RCAR=y CONFIG_SYSC_RCAR_GEN4=y # CONFIG_SYSC_R8A77995 is not set # CONFIG_SYSC_R8A7794 is not set # CONFIG_SYSC_R8A77990 is not set # CONFIG_SYSC_R8A7779 is not set # CONFIG_SYSC_R8A7790 is not set CONFIG_SYSC_R8A7795=y # CONFIG_SYSC_R8A7791 is not set # CONFIG_SYSC_R8A77965 is not set # CONFIG_SYSC_R8A77960 is not set # CONFIG_SYSC_R8A77961 is not set # CONFIG_SYSC_R8A779F0 is not set CONFIG_SYSC_R8A7792=y CONFIG_SYSC_R8A77980=y # CONFIG_SYSC_R8A77970 is not set # CONFIG_SYSC_R8A779A0 is not set CONFIG_SYSC_R8A779G0=y # CONFIG_SYSC_RMOBILE is not set CONFIG_SYSC_R8A77470=y CONFIG_SYSC_R8A7745=y # CONFIG_SYSC_R8A7742 is not set # CONFIG_SYSC_R8A7743 is not set # CONFIG_SYSC_R8A774C0 is not set CONFIG_SYSC_R8A774E1=y CONFIG_SYSC_R8A774A1=y # CONFIG_SYSC_R8A774B1 is not set CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=m # CONFIG_ROCKCHIP_PM_DOMAINS is not set # CONFIG_SOC_SAMSUNG is not set CONFIG_SUNXI_MBUS=y CONFIG_SUNXI_SRAM=y # CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER is not set CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER=y CONFIG_SOC_TI=y CONFIG_UX500_SOC_ID=y CONFIG_SOC_REALVIEW=y # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y # CONFIG_DEVFREQ_GOV_PERFORMANCE is not set CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y CONFIG_ARM_IMX_BUS_DEVFREQ=y CONFIG_ARM_TEGRA_DEVFREQ=y CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m # CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set CONFIG_PM_DEVFREQ_EVENT=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=m CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=y # CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI is not set CONFIG_EXTCON=y # # Extcon Device Drivers # CONFIG_EXTCON_ADC_JACK=y CONFIG_EXTCON_GPIO=m # CONFIG_EXTCON_MAX14577 is not set CONFIG_EXTCON_MAX3355=m CONFIG_EXTCON_PTN5150=y CONFIG_EXTCON_QCOM_SPMI_MISC=m CONFIG_EXTCON_RT8973A=m # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USBC_CROS_EC=m CONFIG_EXTCON_USBC_TUSB320=y CONFIG_MEMORY=y CONFIG_ARM_PL172_MPMC=m CONFIG_ATMEL_SDRAMC=y CONFIG_ATMEL_EBI=y CONFIG_BRCMSTB_DPFE=m # CONFIG_BRCMSTB_MEMC is not set CONFIG_BT1_L2_CTL=y CONFIG_TI_AEMIF=y # CONFIG_TI_EMIF is not set CONFIG_OMAP_GPMC=y CONFIG_OMAP_GPMC_DEBUG=y CONFIG_MVEBU_DEVBUS=y CONFIG_FSL_CORENET_CF=m # CONFIG_FSL_IFC is not set # CONFIG_JZ4780_NEMC is not set CONFIG_MTK_SMI=y # CONFIG_DA8XX_DDRCTL is not set CONFIG_PL353_SMC=m CONFIG_RENESAS_RPCIF=y # CONFIG_STM32_FMC2_EBI is not set # CONFIG_SAMSUNG_MC is not set # CONFIG_TEGRA_MC is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=m CONFIG_IIO_BUFFER_DMA=y CONFIG_IIO_BUFFER_DMAENGINE=y CONFIG_IIO_BUFFER_HW_CONSUMER=y CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_CONFIGFS=y CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_IIO_SW_DEVICE=y CONFIG_IIO_SW_TRIGGER=m CONFIG_IIO_TRIGGERED_EVENT=m # # Accelerometers # CONFIG_ADXL313=y CONFIG_ADXL313_I2C=y # CONFIG_ADXL345_I2C is not set CONFIG_ADXL355=y CONFIG_ADXL355_I2C=y CONFIG_ADXL367=m CONFIG_ADXL367_I2C=m CONFIG_ADXL372=y CONFIG_ADXL372_I2C=y CONFIG_BMA180=y CONFIG_BMA400=y CONFIG_BMA400_I2C=y # CONFIG_BMC150_ACCEL is not set CONFIG_DA280=m CONFIG_DA311=m CONFIG_DMARD06=y # CONFIG_DMARD09 is not set CONFIG_DMARD10=m CONFIG_FXLS8962AF=y CONFIG_FXLS8962AF_I2C=y CONFIG_IIO_ST_ACCEL_3AXIS=y CONFIG_IIO_ST_ACCEL_I2C_3AXIS=y CONFIG_KXSD9=y # CONFIG_KXSD9_I2C is not set CONFIG_KXCJK1013=m # CONFIG_MC3230 is not set # CONFIG_MMA7455_I2C is not set # CONFIG_MMA7660 is not set CONFIG_MMA8452=y CONFIG_MMA9551_CORE=m CONFIG_MMA9551=m CONFIG_MMA9553=m CONFIG_MXC4005=m CONFIG_MXC6255=y CONFIG_STK8312=y # CONFIG_STK8BA50 is not set # end of Accelerometers # # Analog to digital converters # # CONFIG_AD7091R5 is not set # CONFIG_AD7291 is not set CONFIG_AD7606=m CONFIG_AD7606_IFACE_PARALLEL=m # CONFIG_AD799X is not set CONFIG_ADI_AXI_ADC=y # CONFIG_ASPEED_ADC is not set CONFIG_AT91_SAMA5D2_ADC=y CONFIG_BCM_IPROC_ADC=y # CONFIG_BERLIN2_ADC is not set CONFIG_CC10001_ADC=y CONFIG_DA9150_GPADC=m # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EXYNOS_ADC=y CONFIG_MXS_LRADC_ADC=y # CONFIG_HX711 is not set CONFIG_INA2XX_ADC=y CONFIG_INGENIC_ADC=m # CONFIG_IMX7D_ADC is not set CONFIG_IMX8QXP_ADC=m CONFIG_LP8788_ADC=y # CONFIG_LPC18XX_ADC is not set # CONFIG_LPC32XX_ADC is not set # CONFIG_LTC2471 is not set CONFIG_LTC2485=m CONFIG_LTC2497=m # CONFIG_MAX1363 is not set CONFIG_MAX9611=y # CONFIG_MCP3422 is not set CONFIG_MEDIATEK_MT6360_ADC=m CONFIG_MEDIATEK_MT6577_AUXADC=y CONFIG_MEN_Z188_ADC=y CONFIG_MESON_SARADC=y CONFIG_MP2629_ADC=m # CONFIG_NAU7802 is not set CONFIG_NPCM_ADC=m CONFIG_QCOM_VADC_COMMON=m # CONFIG_QCOM_PM8XXX_XOADC is not set # CONFIG_QCOM_SPMI_RRADC is not set CONFIG_QCOM_SPMI_IADC=y # CONFIG_QCOM_SPMI_VADC is not set CONFIG_QCOM_SPMI_ADC5=m CONFIG_RCAR_GYRO_ADC=m CONFIG_ROCKCHIP_SARADC=y CONFIG_RZG2L_ADC=y CONFIG_SC27XX_ADC=m CONFIG_SPEAR_ADC=m CONFIG_SD_ADC_MODULATOR=m # CONFIG_STM32_ADC_CORE is not set CONFIG_STM32_DFSDM_CORE=y CONFIG_STM32_DFSDM_ADC=y # CONFIG_STMPE_ADC is not set CONFIG_SUN4I_GPADC=m CONFIG_TI_ADC081C=y CONFIG_TI_ADS1015=m CONFIG_TI_AM335X_ADC=m # CONFIG_TWL4030_MADC is not set CONFIG_TWL6030_GPADC=y CONFIG_VF610_ADC=m CONFIG_XILINX_XADC=y # CONFIG_XILINX_AMS is not set # end of Analog to digital converters # # Analog to digital and digital to analog converters # # end of Analog to digital and digital to analog converters # # Analog Front Ends # CONFIG_IIO_RESCALE=m # end of Analog Front Ends # # Amplifiers # # CONFIG_HMC425 is not set # end of Amplifiers # # Capacitance to digital converters # # CONFIG_AD7150 is not set # end of Capacitance to digital converters # # Chemical Sensors # CONFIG_ATLAS_PH_SENSOR=y CONFIG_ATLAS_EZO_SENSOR=m CONFIG_BME680=m CONFIG_BME680_I2C=m CONFIG_CCS811=m CONFIG_IAQCORE=y CONFIG_PMS7003=m # CONFIG_SCD30_CORE is not set CONFIG_SCD4X=m CONFIG_SENSIRION_SGP30=y CONFIG_SENSIRION_SGP40=m # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set CONFIG_SENSEAIR_SUNRISE_CO2=m CONFIG_VZ89X=y # end of Chemical Sensors # # Hid Sensor IIO Common # # end of Hid Sensor IIO Common # # IIO SCMI Sensors # # CONFIG_IIO_SCMI is not set # end of IIO SCMI Sensors # # SSP Sensor Common # # end of SSP Sensor Common CONFIG_IIO_ST_SENSORS_I2C=y CONFIG_IIO_ST_SENSORS_CORE=y # # Digital to analog converters # # CONFIG_AD5064 is not set CONFIG_AD5380=m CONFIG_AD5446=m # CONFIG_AD5593R is not set CONFIG_AD5686=m CONFIG_AD5696_I2C=m # CONFIG_DPOT_DAC is not set CONFIG_DS4424=m CONFIG_LPC18XX_DAC=y # CONFIG_M62332 is not set CONFIG_MAX517=m # CONFIG_MAX5821 is not set # CONFIG_MCP4725 is not set # CONFIG_STM32_DAC is not set CONFIG_TI_DAC5571=y # CONFIG_VF610_DAC is not set # end of Digital to analog converters # # IIO dummy driver # # CONFIG_IIO_SIMPLE_DUMMY is not set # end of IIO dummy driver # # Filters # # end of Filters # # Frequency Synthesizers DDS/PLL # # # Clock Generator/Distribution # # end of Clock Generator/Distribution # # Phase-Locked Loop (PLL) frequency synthesizers # # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors # CONFIG_BMG160=y CONFIG_BMG160_I2C=y # CONFIG_FXAS21002C is not set # CONFIG_MPU3050_I2C is not set CONFIG_IIO_ST_GYRO_3AXIS=m CONFIG_IIO_ST_GYRO_I2C_3AXIS=m # CONFIG_ITG3200 is not set # end of Digital gyroscope sensors # # Health Sensors # # # Heart Rate Monitors # CONFIG_AFE4404=y CONFIG_MAX30100=y # CONFIG_MAX30102 is not set # end of Heart Rate Monitors # end of Health Sensors # # Humidity sensors # CONFIG_AM2315=y # CONFIG_DHT11 is not set CONFIG_HDC100X=y CONFIG_HDC2010=m # CONFIG_HTS221 is not set # CONFIG_HTU21 is not set # CONFIG_SI7005 is not set CONFIG_SI7020=y # end of Humidity sensors # # Inertial measurement units # # CONFIG_BMI160_I2C is not set CONFIG_FXOS8700=y CONFIG_FXOS8700_I2C=y # CONFIG_KMX61 is not set # CONFIG_INV_ICM42600_I2C is not set CONFIG_INV_MPU6050_IIO=y CONFIG_INV_MPU6050_I2C=y CONFIG_IIO_ST_LSM6DSX=y CONFIG_IIO_ST_LSM6DSX_I2C=y CONFIG_IIO_ST_LSM6DSX_I3C=m CONFIG_IIO_ST_LSM9DS0=y # CONFIG_IIO_ST_LSM9DS0_I2C is not set # end of Inertial measurement units # # Light sensors # # CONFIG_ADJD_S311 is not set CONFIG_ADUX1020=m # CONFIG_AL3010 is not set CONFIG_AL3320A=m CONFIG_APDS9300=y CONFIG_APDS9960=m # CONFIG_AS73211 is not set CONFIG_BH1750=y # CONFIG_BH1780 is not set CONFIG_CM32181=m # CONFIG_CM3232 is not set CONFIG_CM3323=m CONFIG_CM3605=y CONFIG_CM36651=m # CONFIG_GP2AP002 is not set # CONFIG_GP2AP020A00F is not set CONFIG_IQS621_ALS=m CONFIG_SENSORS_ISL29018=m CONFIG_SENSORS_ISL29028=y CONFIG_ISL29125=m CONFIG_JSA1212=m CONFIG_RPR0521=m # CONFIG_SENSORS_LM3533 is not set # CONFIG_LTR501 is not set # CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set CONFIG_MAX44009=y CONFIG_NOA1305=y CONFIG_OPT3001=y CONFIG_PA12203001=m CONFIG_SI1133=y CONFIG_SI1145=y CONFIG_STK3310=y CONFIG_ST_UVIS25=y CONFIG_ST_UVIS25_I2C=y CONFIG_TCS3414=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set # CONFIG_TSL2591 is not set CONFIG_TSL2772=m CONFIG_TSL4531=m # CONFIG_US5182D is not set CONFIG_VCNL4000=y # CONFIG_VCNL4035 is not set CONFIG_VEML6030=m CONFIG_VEML6070=y CONFIG_VL6180=m CONFIG_ZOPT2201=y # end of Light sensors # # Magnetometer sensors # CONFIG_AK8974=y CONFIG_AK8975=y CONFIG_AK09911=m CONFIG_BMC150_MAGN=y CONFIG_BMC150_MAGN_I2C=y # CONFIG_MAG3110 is not set CONFIG_MMC35240=y CONFIG_IIO_ST_MAGN_3AXIS=y CONFIG_IIO_ST_MAGN_I2C_3AXIS=m # CONFIG_SENSORS_HMC5843_I2C is not set # CONFIG_SENSORS_RM3100_I2C is not set CONFIG_YAMAHA_YAS530=m # end of Magnetometer sensors # # Multiplexers # # CONFIG_IIO_MUX is not set # end of Multiplexers # # Inclinometer sensors # # end of Inclinometer sensors CONFIG_IIO_RESCALE_KUNIT_TEST=m CONFIG_IIO_FORMAT_KUNIT_TEST=y # # Triggers - standalone # CONFIG_IIO_HRTIMER_TRIGGER=m CONFIG_IIO_INTERRUPT_TRIGGER=y CONFIG_IIO_STM32_LPTIMER_TRIGGER=m # CONFIG_IIO_STM32_TIMER_TRIGGER is not set # CONFIG_IIO_TIGHTLOOP_TRIGGER is not set # CONFIG_IIO_SYSFS_TRIGGER is not set # end of Triggers - standalone # # Linear and angular position sensors # CONFIG_IQS624_POS=y # end of Linear and angular position sensors # # Digital potentiometers # CONFIG_AD5110=y CONFIG_AD5272=y CONFIG_DS1803=m CONFIG_MAX5432=m # CONFIG_MCP4018 is not set CONFIG_MCP4531=y # CONFIG_TPL0102 is not set # end of Digital potentiometers # # Digital potentiostats # CONFIG_LMP91000=m # end of Digital potentiostats # # Pressure sensors # CONFIG_ABP060MG=y CONFIG_BMP280=y CONFIG_BMP280_I2C=y CONFIG_DLHL60D=m CONFIG_DPS310=m CONFIG_HP03=y CONFIG_ICP10100=m CONFIG_MPL115=m CONFIG_MPL115_I2C=m # CONFIG_MPL3115 is not set CONFIG_MS5611=m CONFIG_MS5611_I2C=m # CONFIG_MS5637 is not set CONFIG_IIO_ST_PRESS=y CONFIG_IIO_ST_PRESS_I2C=m CONFIG_T5403=y CONFIG_HP206C=y CONFIG_ZPA2326=m CONFIG_ZPA2326_I2C=m # end of Pressure sensors # # Lightning sensors # # end of Lightning sensors # # Proximity and distance sensors # CONFIG_CROS_EC_MKBP_PROXIMITY=m # CONFIG_ISL29501 is not set CONFIG_LIDAR_LITE_V2=m CONFIG_MB1232=y CONFIG_PING=m CONFIG_RFD77402=m CONFIG_SRF04=y CONFIG_SX_COMMON=y # CONFIG_SX9310 is not set CONFIG_SX9324=y CONFIG_SX9360=m CONFIG_SX9500=y CONFIG_SRF08=m # CONFIG_VCNL3020 is not set CONFIG_VL53L0X_I2C=m # end of Proximity and distance sensors # # Resolver to digital converters # # end of Resolver to digital converters # # Temperature sensors # CONFIG_IQS620AT_TEMP=y # CONFIG_MLX90614 is not set CONFIG_MLX90632=y # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set CONFIG_TMP117=m # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # end of Temperature sensors # CONFIG_PWM is not set # # IRQ chip support # CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=2 CONFIG_ARM_VIC=y CONFIG_ARM_VIC_NR=2 # CONFIG_AL_FIC is not set CONFIG_ATMEL_AIC_IRQ=y CONFIG_DW_APB_ICTL=y CONFIG_MADERA_IRQ=y CONFIG_JCORE_AIC=y CONFIG_RENESAS_INTC_IRQPIN=y # CONFIG_RENESAS_IRQC is not set # CONFIG_RENESAS_RZA1_IRQC is not set # CONFIG_RENESAS_RZG2L_IRQC is not set CONFIG_SL28CPLD_INTC=y CONFIG_TS4800_IRQ=y CONFIG_VERSATILE_FPGA_IRQ=y CONFIG_VERSATILE_FPGA_IRQ_NR=4 # CONFIG_XILINX_INTC is not set CONFIG_INGENIC_TCU_IRQ=y CONFIG_IRQ_MXS=y CONFIG_IRQ_UNIPHIER_AIDET=y CONFIG_MESON_IRQ_GPIO=m # CONFIG_IMX_IRQSTEER is not set CONFIG_IMX_INTMUX=y CONFIG_EXYNOS_IRQ_COMBINER=y # CONFIG_MST_IRQ is not set # CONFIG_MCHP_EIC is not set CONFIG_SUNPLUS_SP7021_INTC=y # end of IRQ chip support # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_A10SR=y # CONFIG_RESET_ATH79 is not set CONFIG_RESET_AXS10X=y # CONFIG_RESET_BCM6345 is not set CONFIG_RESET_BERLIN=m # CONFIG_RESET_BRCMSTB is not set CONFIG_RESET_BRCMSTB_RESCAL=y CONFIG_RESET_HSDK=y # CONFIG_RESET_IMX7 is not set # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_K210 is not set CONFIG_RESET_LANTIQ=y CONFIG_RESET_LPC18XX=y # CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_MESON is not set # CONFIG_RESET_MESON_AUDIO_ARB is not set CONFIG_RESET_NPCM=y CONFIG_RESET_OXNAS=y # CONFIG_RESET_PISTACHIO is not set CONFIG_RESET_QCOM_AOSS=m # CONFIG_RESET_QCOM_PDC is not set CONFIG_RESET_RASPBERRYPI=y # CONFIG_RESET_RZG2L_USBPHY_CTRL is not set CONFIG_RESET_SCMI=m CONFIG_RESET_SIMPLE=y CONFIG_RESET_SOCFPGA=y # CONFIG_RESET_STARFIVE_JH7100 is not set CONFIG_RESET_SUNPLUS=y CONFIG_RESET_SUNXI=y CONFIG_RESET_TI_SCI=m # CONFIG_RESET_TI_SYSCON is not set CONFIG_RESET_TI_TPS380X=y CONFIG_RESET_TN48M_CPLD=m CONFIG_RESET_UNIPHIER=y CONFIG_RESET_UNIPHIER_GLUE=y CONFIG_RESET_ZYNQ=y CONFIG_COMMON_RESET_HI3660=m # CONFIG_COMMON_RESET_HI6220 is not set # # PHY Subsystem # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y # CONFIG_PHY_LPC18XX_USB_OTG is not set CONFIG_PHY_PISTACHIO_USB=y CONFIG_PHY_XGENE=y CONFIG_PHY_CAN_TRANSCEIVER=y # CONFIG_PHY_SUN6I_MIPI_DPHY is not set CONFIG_PHY_SUN50I_USB3=y CONFIG_PHY_MESON8_HDMI_TX=m CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m # CONFIG_PHY_MESON_G12A_USB2 is not set # CONFIG_PHY_MESON_G12A_USB3_PCIE is not set # CONFIG_PHY_MESON_AXG_PCIE is not set # CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set CONFIG_PHY_MESON_AXG_MIPI_DPHY=m # # PHY drivers for Broadcom platforms # # CONFIG_PHY_BCM63XX_USBH is not set CONFIG_PHY_CYGNUS_PCIE=m CONFIG_PHY_BCM_SR_USB=y # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_BCM_NS_USB2 is not set CONFIG_PHY_BCM_NS_USB3=m CONFIG_PHY_NS2_PCIE=m CONFIG_PHY_NS2_USB_DRD=m CONFIG_PHY_BRCM_SATA=y # CONFIG_PHY_BRCM_USB is not set CONFIG_PHY_BCM_SR_PCIE=y # end of PHY drivers for Broadcom platforms CONFIG_PHY_CADENCE_TORRENT=y CONFIG_PHY_CADENCE_DPHY=m # CONFIG_PHY_CADENCE_DPHY_RX is not set CONFIG_PHY_CADENCE_SIERRA=y CONFIG_PHY_CADENCE_SALVO=y CONFIG_PHY_FSL_IMX8MQ_USB=m CONFIG_PHY_MIXEL_LVDS_PHY=y # CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_HI6220_USB is not set CONFIG_PHY_HI3660_USB=y CONFIG_PHY_HI3670_USB=y # CONFIG_PHY_HI3670_PCIE is not set CONFIG_PHY_HISTB_COMBPHY=m CONFIG_PHY_HISI_INNO_USB2=m CONFIG_PHY_LANTIQ_VRX200_PCIE=m # CONFIG_PHY_LANTIQ_RCU_USB2 is not set # CONFIG_ARMADA375_USBCLUSTER_PHY is not set # CONFIG_PHY_BERLIN_SATA is not set CONFIG_PHY_BERLIN_USB=y CONFIG_PHY_MVEBU_A3700_UTMI=m CONFIG_PHY_MVEBU_A38X_COMPHY=y # CONFIG_PHY_PXA_28NM_HSIC is not set CONFIG_PHY_PXA_28NM_USB2=y CONFIG_PHY_PXA_USB=m CONFIG_PHY_MMP3_USB=y # CONFIG_PHY_MMP3_HSIC is not set # CONFIG_PHY_MTK_PCIE is not set # CONFIG_PHY_MTK_TPHY is not set # CONFIG_PHY_MTK_UFS is not set # CONFIG_PHY_MTK_XSPHY is not set # CONFIG_PHY_MTK_HDMI is not set # CONFIG_PHY_MTK_MIPI_DSI is not set CONFIG_PHY_MTK_DP=y # CONFIG_PHY_SPARX5_SERDES is not set CONFIG_PHY_LAN966X_SERDES=m # CONFIG_PHY_OCELOT_SERDES is not set CONFIG_PHY_ATH79_USB=m CONFIG_PHY_QCOM_EDP=y # CONFIG_PHY_QCOM_IPQ4019_USB is not set CONFIG_PHY_QCOM_PCIE2=y # CONFIG_PHY_QCOM_QMP is not set CONFIG_PHY_QCOM_QUSB2=y CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y CONFIG_PHY_QCOM_USB_HS_28NM=y CONFIG_PHY_QCOM_USB_SS=y CONFIG_PHY_QCOM_IPQ806X_USB=y CONFIG_PHY_MT7621_PCI=y CONFIG_PHY_RALINK_USB=m CONFIG_PHY_RCAR_GEN3_USB3=m # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m CONFIG_PHY_ROCKCHIP_PCIE=y # CONFIG_PHY_ROCKCHIP_TYPEC is not set # CONFIG_PHY_EXYNOS_DP_VIDEO is not set # CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set # CONFIG_PHY_EXYNOS_PCIE is not set CONFIG_PHY_SAMSUNG_UFS=y # CONFIG_PHY_SAMSUNG_USB2 is not set CONFIG_PHY_UNIPHIER_USB2=m # CONFIG_PHY_UNIPHIER_USB3 is not set CONFIG_PHY_UNIPHIER_PCIE=y CONFIG_PHY_UNIPHIER_AHCI=y # CONFIG_PHY_ST_SPEAR1310_MIPHY is not set # CONFIG_PHY_ST_SPEAR1340_MIPHY is not set CONFIG_PHY_STIH407_USB=y CONFIG_PHY_STM32_USBPHYC=m CONFIG_PHY_TEGRA194_P2U=m CONFIG_PHY_DA8XX_USB=y CONFIG_PHY_AM654_SERDES=y CONFIG_PHY_J721E_WIZ=y CONFIG_OMAP_CONTROL_PHY=m # CONFIG_TI_PIPE3 is not set CONFIG_PHY_INTEL_KEEMBAY_EMMC=y CONFIG_PHY_INTEL_KEEMBAY_USB=m # CONFIG_PHY_INTEL_LGM_COMBO is not set CONFIG_PHY_INTEL_LGM_EMMC=m CONFIG_PHY_INTEL_THUNDERBAY_EMMC=m CONFIG_PHY_XILINX_ZYNQMP=y # end of PHY Subsystem # CONFIG_POWERCAP is not set CONFIG_MCB=y CONFIG_MCB_LPC=m # # Performance monitor support # CONFIG_ARM_CCN=m CONFIG_ARM_CMN=m # CONFIG_ARM_PMU is not set CONFIG_FSL_IMX8_DDR_PMU=y # CONFIG_ARM_DMC620_PMU is not set # end of Performance monitor support # CONFIG_RAS is not set # # Android # CONFIG_ANDROID_BINDER_IPC=y CONFIG_ANDROID_BINDERFS=y CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" CONFIG_ANDROID_BINDER_IPC_SELFTEST=y # end of Android CONFIG_DAX=m # CONFIG_NVMEM is not set # # HW tracing support # CONFIG_STM=m CONFIG_STM_PROTO_BASIC=m # CONFIG_STM_PROTO_SYS_T is not set # CONFIG_STM_DUMMY is not set CONFIG_STM_SOURCE_CONSOLE=m CONFIG_STM_SOURCE_HEARTBEAT=m CONFIG_INTEL_TH=y CONFIG_INTEL_TH_GTH=y # CONFIG_INTEL_TH_STH is not set # CONFIG_INTEL_TH_MSU is not set CONFIG_INTEL_TH_PTI=y CONFIG_INTEL_TH_DEBUG=y # end of HW tracing support CONFIG_FPGA=y CONFIG_FPGA_MGR_SOCFPGA=y CONFIG_FPGA_MGR_SOCFPGA_A10=y CONFIG_ALTERA_PR_IP_CORE=y CONFIG_ALTERA_PR_IP_CORE_PLAT=y # CONFIG_FPGA_MGR_ZYNQ_FPGA is not set # CONFIG_FPGA_BRIDGE is not set # CONFIG_FPGA_DFL is not set # CONFIG_FPGA_MGR_ZYNQMP_FPGA is not set # CONFIG_FPGA_MGR_VERSAL_FPGA is not set CONFIG_FSI=y # CONFIG_FSI_NEW_DEV_NODE is not set CONFIG_FSI_MASTER_GPIO=y # CONFIG_FSI_MASTER_HUB is not set # CONFIG_FSI_MASTER_AST_CF is not set CONFIG_FSI_MASTER_ASPEED=m CONFIG_FSI_SCOM=y CONFIG_FSI_SBEFIFO=m CONFIG_FSI_OCC=m CONFIG_TEE=y CONFIG_MULTIPLEXER=y # # Multiplexer drivers # CONFIG_MUX_ADG792A=y CONFIG_MUX_GPIO=m CONFIG_MUX_MMIO=y # end of Multiplexer drivers CONFIG_PM_OPP=y CONFIG_SIOX=y CONFIG_SIOX_BUS_GPIO=m CONFIG_SLIMBUS=m CONFIG_SLIM_QCOM_CTRL=m CONFIG_INTERCONNECT=y # CONFIG_INTERCONNECT_IMX is not set CONFIG_INTERCONNECT_QCOM_OSM_L3=y # CONFIG_INTERCONNECT_SAMSUNG is not set # CONFIG_COUNTER is not set CONFIG_MOST=y # CONFIG_MOST_CDEV is not set CONFIG_PECI=m CONFIG_PECI_CPU=m CONFIG_PECI_ASPEED=m CONFIG_HTE=y # end of Device Drivers # # File systems # # CONFIG_VALIDATE_FS_PARSER is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=m # CONFIG_EXPORTFS_BLOCK_OPS is not set # CONFIG_FILE_LOCKING is not set # CONFIG_FS_ENCRYPTION is not set # CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y # CONFIG_INOTIFY_USER is not set # CONFIG_FANOTIFY is not set CONFIG_QUOTA=y # CONFIG_QUOTA_NETLINK_INTERFACE is not set CONFIG_PRINT_QUOTA_WARNING=y CONFIG_QUOTA_DEBUG=y CONFIG_QUOTA_TREE=y CONFIG_QFMT_V1=y CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=m CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y # CONFIG_CUSE is not set # CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=m CONFIG_OVERLAY_FS_REDIRECT_DIR=y # CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set # CONFIG_OVERLAY_FS_INDEX is not set # CONFIG_OVERLAY_FS_METACOPY is not set # # Caches # CONFIG_NETFS_SUPPORT=m CONFIG_NETFS_STATS=y CONFIG_FSCACHE=m CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE_DEBUG=y # end of Caches # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_VMCORE=y # CONFIG_PROC_VMCORE_DEVICE_DUMP is not set CONFIG_PROC_SYSCTL=y # CONFIG_PROC_PAGE_MONITOR is not set CONFIG_PROC_CHILDREN=y CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set CONFIG_TMPFS_XATTR=y CONFIG_MEMFD_CREATE=y CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=m # end of Pseudo filesystems CONFIG_MISC_FILESYSTEMS=y CONFIG_ORANGEFS_FS=m # CONFIG_ECRYPT_FS is not set CONFIG_CRAMFS=y CONFIG_PSTORE=m CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 # CONFIG_PSTORE_DEFLATE_COMPRESS is not set CONFIG_PSTORE_LZO_COMPRESS=m # CONFIG_PSTORE_LZ4_COMPRESS is not set CONFIG_PSTORE_LZ4HC_COMPRESS=m # CONFIG_PSTORE_842_COMPRESS is not set # CONFIG_PSTORE_ZSTD_COMPRESS is not set CONFIG_PSTORE_COMPRESS=y CONFIG_PSTORE_LZO_COMPRESS_DEFAULT=y # CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set CONFIG_PSTORE_COMPRESS_DEFAULT="lzo" # CONFIG_PSTORE_CONSOLE is not set # CONFIG_PSTORE_PMSG is not set CONFIG_PSTORE_RAM=m # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_737=m CONFIG_NLS_CODEPAGE_775=m CONFIG_NLS_CODEPAGE_850=m CONFIG_NLS_CODEPAGE_852=m CONFIG_NLS_CODEPAGE_855=m CONFIG_NLS_CODEPAGE_857=m CONFIG_NLS_CODEPAGE_860=m CONFIG_NLS_CODEPAGE_861=m CONFIG_NLS_CODEPAGE_862=m CONFIG_NLS_CODEPAGE_863=m # CONFIG_NLS_CODEPAGE_864 is not set CONFIG_NLS_CODEPAGE_865=m CONFIG_NLS_CODEPAGE_866=m CONFIG_NLS_CODEPAGE_869=m # CONFIG_NLS_CODEPAGE_936 is not set CONFIG_NLS_CODEPAGE_950=m # CONFIG_NLS_CODEPAGE_932 is not set CONFIG_NLS_CODEPAGE_949=m # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set CONFIG_NLS_CODEPAGE_1250=m CONFIG_NLS_CODEPAGE_1251=m # CONFIG_NLS_ASCII is not set # CONFIG_NLS_ISO8859_1 is not set CONFIG_NLS_ISO8859_2=m # CONFIG_NLS_ISO8859_3 is not set CONFIG_NLS_ISO8859_4=m CONFIG_NLS_ISO8859_5=m # CONFIG_NLS_ISO8859_6 is not set CONFIG_NLS_ISO8859_7=m CONFIG_NLS_ISO8859_9=m CONFIG_NLS_ISO8859_13=m CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m # CONFIG_NLS_MAC_ROMAN is not set CONFIG_NLS_MAC_CELTIC=m # CONFIG_NLS_MAC_CENTEURO is not set CONFIG_NLS_MAC_CROATIAN=m CONFIG_NLS_MAC_CYRILLIC=m # CONFIG_NLS_MAC_GAELIC is not set CONFIG_NLS_MAC_GREEK=m # CONFIG_NLS_MAC_ICELAND is not set # CONFIG_NLS_MAC_INUIT is not set CONFIG_NLS_MAC_ROMANIAN=m CONFIG_NLS_MAC_TURKISH=m # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set CONFIG_UNICODE=m CONFIG_UNICODE_NORMALIZATION_SELFTEST=m # end of File systems # # Security options # CONFIG_KEYS=y # CONFIG_KEYS_REQUEST_CACHE is not set CONFIG_PERSISTENT_KEYRINGS=y # CONFIG_TRUSTED_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set CONFIG_KEY_DH_OPERATIONS=y CONFIG_SECURITY_DMESG_RESTRICT=y # CONFIG_SECURITYFS is not set CONFIG_FORTIFY_SOURCE=y # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" # # Kernel hardening options # # # Memory initialization # CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INIT_STACK_ALL_PATTERN=y # CONFIG_INIT_STACK_ALL_ZERO is not set # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set CONFIG_INIT_ON_FREE_DEFAULT_ON=y # end of Memory initialization CONFIG_CC_HAS_RANDSTRUCT=y # CONFIG_RANDSTRUCT_NONE is not set CONFIG_RANDSTRUCT_FULL=y CONFIG_RANDSTRUCT=y # end of Kernel hardening options # end of Security options CONFIG_XOR_BLOCKS=y CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_USER=m # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=y CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ENGINE=y # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y # CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=y CONFIG_CRYPTO_ECDSA=m CONFIG_CRYPTO_ECRDSA=y CONFIG_CRYPTO_SM2=m CONFIG_CRYPTO_CURVE25519=y # # Authenticated Encryption with Associated Data # CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_CHACHA20POLY1305=y # CONFIG_CRYPTO_AEGIS128 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y # # Block modes # CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_LRW is not set CONFIG_CRYPTO_OFB=y CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_KEYWRAP=y CONFIG_CRYPTO_NHPOLY1305=m CONFIG_CRYPTO_ADIANTUM=m # CONFIG_CRYPTO_HCTR2 is not set CONFIG_CRYPTO_ESSIV=m # # Hash modes # CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set CONFIG_CRYPTO_VMAC=m # # Digest # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set # CONFIG_CRYPTO_XXHASH is not set CONFIG_CRYPTO_BLAKE2B=m CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRC64_ROCKSOFT=y CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_POLY1305=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_RMD160=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_SM3=y # CONFIG_CRYPTO_SM3_GENERIC is not set CONFIG_CRYPTO_STREEBOG=y CONFIG_CRYPTO_WP512=m # # Ciphers # CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_AES_TI=y # CONFIG_CRYPTO_ANUBIS is not set CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set CONFIG_CRYPTO_CAST_COMMON=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_FCRYPT=m # CONFIG_CRYPTO_KHAZAD is not set CONFIG_CRYPTO_CHACHA20=y # CONFIG_CRYPTO_SEED is not set CONFIG_CRYPTO_ARIA=y CONFIG_CRYPTO_SERPENT=y CONFIG_CRYPTO_SM4=y CONFIG_CRYPTO_SM4_GENERIC=y CONFIG_CRYPTO_TEA=y # CONFIG_CRYPTO_TWOFISH is not set # # Compression # CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y # CONFIG_CRYPTO_842 is not set # CONFIG_CRYPTO_LZ4 is not set CONFIG_CRYPTO_LZ4HC=y CONFIG_CRYPTO_ZSTD=m # # Random Number Generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_HASH is not set CONFIG_CRYPTO_DRBG_CTR=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=m CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_USER_API_RNG is not set # CONFIG_CRYPTO_USER_API_AEAD is not set CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_STATS=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_ALLWINNER=y # CONFIG_CRYPTO_DEV_SUN4I_SS is not set CONFIG_CRYPTO_DEV_SUN8I_CE=y CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y # CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG is not set # CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG is not set # CONFIG_CRYPTO_DEV_SUN8I_SS is not set CONFIG_CRYPTO_DEV_SL3516=m CONFIG_CRYPTO_DEV_SL3516_DEBUG=y CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=m CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=m CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=m CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m CONFIG_CRYPTO_DEV_EXYNOS_RNG=m CONFIG_CRYPTO_DEV_S5P=m CONFIG_CRYPTO_DEV_ATMEL_AUTHENC=y CONFIG_CRYPTO_DEV_ATMEL_AES=m CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=y CONFIG_CRYPTO_DEV_ATMEL_I2C=y CONFIG_CRYPTO_DEV_ATMEL_ECC=m CONFIG_CRYPTO_DEV_ATMEL_SHA204A=y CONFIG_CRYPTO_DEV_MXS_DCP=m # CONFIG_CRYPTO_DEV_QCE is not set CONFIG_CRYPTO_DEV_QCOM_RNG=y CONFIG_CRYPTO_DEV_IMGTEC_HASH=m CONFIG_CRYPTO_DEV_ZYNQMP_AES=y # CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set CONFIG_CRYPTO_DEV_VIRTIO=m CONFIG_CRYPTO_DEV_SAFEXCEL=y CONFIG_CRYPTO_DEV_ARTPEC6=y CONFIG_CRYPTO_DEV_CCREE=y # CONFIG_CRYPTO_DEV_HISI_SEC is not set # CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_CRYPTO_DEV_SA2UL=m CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4=y # CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB is not set CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS=y CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC=m CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU=m CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224=y CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y # CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=y CONFIG_SIGNED_PE_FILE_VERIFICATION=y # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" CONFIG_MODULE_SIG_KEY_TYPE_RSA=y # CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" CONFIG_SYSTEM_EXTRA_CERTIFICATE=y CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 # CONFIG_SECONDARY_TRUSTED_KEYRING is not set # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y # # Library routines # CONFIG_LINEAR_RANGES=y CONFIG_PACKING=y CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=y CONFIG_PRIME_NUMBERS=m CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_STMP_DEVICE=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=y CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y CONFIG_CRYPTO_LIB_CURVE25519=m CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines CONFIG_LIB_MEMNEQ=y CONFIG_CRC_CCITT=m CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set CONFIG_CRC64_ROCKSOFT=y CONFIG_CRC_ITU_T=y CONFIG_CRC32=y CONFIG_CRC32_SELFTEST=y # CONFIG_CRC32_SLICEBY8 is not set CONFIG_CRC32_SLICEBY4=y # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set CONFIG_CRC64=y CONFIG_CRC4=y CONFIG_CRC7=m CONFIG_LIBCRC32C=y CONFIG_CRC8=y CONFIG_XXHASH=y CONFIG_AUDIT_GENERIC=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4HC_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y CONFIG_ZSTD_COMPRESS=m CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y # CONFIG_XZ_DEC_X86 is not set CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_IA64=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_MICROLZMA is not set CONFIG_XZ_DEC_BCJ=y CONFIG_XZ_DEC_TEST=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y CONFIG_REED_SOLOMON_ENC8=y CONFIG_REED_SOLOMON_DEC8=y CONFIG_REED_SOLOMON_ENC16=y CONFIG_REED_SOLOMON_DEC16=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=y CONFIG_TEXTSEARCH_BM=y CONFIG_TEXTSEARCH_FSM=y CONFIG_INTERVAL_TREE=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_CMA=y CONFIG_DMA_PERNUMA_CMA=y # # Default contiguous memory area size: # CONFIG_CMA_SIZE_MBYTES=16 CONFIG_CMA_SIZE_PERCENTAGE=10 # CONFIG_CMA_SIZE_SEL_MBYTES is not set # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set CONFIG_CMA_SIZE_SEL_MIN=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_DQL=y CONFIG_GLOB=y CONFIG_GLOB_SELFTEST=y CONFIG_NLATTR=y CONFIG_GENERIC_ATOMIC64=y CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y CONFIG_DIMLIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_SG_SPLIT=y CONFIG_STACKDEPOT=y CONFIG_REF_TRACKER=y CONFIG_PARMAN=y # CONFIG_OBJAGG is not set # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # # Kernel hacking # # # printk and dmesg options # CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_SYMBOLIC_ERRNAME is not set # CONFIG_DEBUG_BUGVERBOSE is not set # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_MISC is not set # # Compile-time checks and compiler options # CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO_NONE is not set CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_DEBUG_INFO_REDUCED=y # CONFIG_DEBUG_INFO_SPLIT is not set CONFIG_PAHOLE_HAS_SPLIT_BTF=y CONFIG_PAHOLE_HAS_BTF_TAG=y # CONFIG_GDB_SCRIPTS is not set CONFIG_FRAME_WARN=1024 CONFIG_STRIP_ASM_SYMS=y CONFIG_HEADERS_INSTALL=y CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_FRAME_POINTER=y CONFIG_VMLINUX_MAP=y CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # # CONFIG_MAGIC_SYSRQ is not set CONFIG_DEBUG_FS=y # CONFIG_DEBUG_FS_ALLOW_ALL is not set CONFIG_DEBUG_FS_DISALLOW_MOUNT=y # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set # CONFIG_UBSAN is not set # end of Generic Kernel Debugging Instruments # # Networking Debugging # CONFIG_NET_DEV_REFCNT_TRACKER=y # CONFIG_NET_NS_REFCNT_TRACKER is not set # CONFIG_DEBUG_NET is not set # end of Networking Debugging # # Memory Debugging # CONFIG_PAGE_EXTENSION=y CONFIG_DEBUG_PAGEALLOC=y # CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT is not set CONFIG_PAGE_OWNER=y CONFIG_PAGE_POISONING=y # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_WX is not set CONFIG_DEBUG_OBJECTS=y CONFIG_DEBUG_OBJECTS_SELFTEST=y CONFIG_DEBUG_OBJECTS_FREE=y CONFIG_DEBUG_OBJECTS_TIMERS=y CONFIG_DEBUG_OBJECTS_WORK=y # CONFIG_DEBUG_OBJECTS_RCU_HEAD is not set # CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER is not set CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 # CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 CONFIG_DEBUG_KMEMLEAK_TEST=m # CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set # CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN is not set # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_SCHED_STACK_END_CHECK=y # CONFIG_DEBUG_VM is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y CONFIG_DEBUG_VIRTUAL=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y CONFIG_HAVE_ARCH_KFENCE=y # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y # # Debug Oops, Lockups and Hangs # # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 # CONFIG_SOFTLOCKUP_DETECTOR is not set CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y # CONFIG_WQ_WATCHDOG is not set CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # # CONFIG_SCHED_DEBUG is not set CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y # end of Scheduler Debugging # CONFIG_DEBUG_TIMEKEEPING is not set # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_PROVE_LOCKING is not set # CONFIG_LOCK_STAT is not set CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y CONFIG_LOCKDEP_BITS=15 CONFIG_LOCKDEP_CHAINS_BITS=16 CONFIG_LOCKDEP_STACK_TRACE_BITS=19 CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 CONFIG_DEBUG_LOCKDEP=y CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set CONFIG_LOCK_TORTURE_TEST=y CONFIG_WW_MUTEX_SELFTEST=m CONFIG_SCF_TORTURE_TEST=m # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_DEBUG_IRQFLAGS=y CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set CONFIG_DEBUG_KOBJECT=y CONFIG_DEBUG_KOBJECT_RELEASE=y # # Debug kernel data structures # CONFIG_DEBUG_LIST=y # CONFIG_DEBUG_PLIST is not set CONFIG_DEBUG_SG=y CONFIG_DEBUG_NOTIFIERS=y CONFIG_BUG_ON_DATA_CORRUPTION=y # end of Debug kernel data structures # CONFIG_DEBUG_CREDENTIALS is not set # # RCU Debugging # CONFIG_TORTURE_TEST=y CONFIG_RCU_SCALE_TEST=m CONFIG_RCU_TORTURE_TEST=m CONFIG_RCU_REF_SCALE_TEST=m CONFIG_RCU_TRACE=y CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging CONFIG_DEBUG_WQ_FORCE_RR_CPU=y CONFIG_LATENCYTOP=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACE_CLOCK=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set # # arm Debugging # # CONFIG_ARM_PTDUMP_DEBUGFS is not set CONFIG_UNWINDER_FRAME_POINTER=y # CONFIG_UNWINDER_ARM is not set # CONFIG_BACKTRACE_VERBOSE is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_AT91_RM9200_DBGU=y # CONFIG_DEBUG_AT91_SAM9263_DBGU is not set # CONFIG_DEBUG_IMX23_UART is not set # CONFIG_DEBUG_IMX28_UART is not set # CONFIG_DEBUG_LPC32XX is not set # CONFIG_DEBUG_MMP_UART2 is not set # CONFIG_DEBUG_MMP_UART3 is not set # CONFIG_DEBUG_REALVIEW_STD_PORT is not set # CONFIG_DEBUG_SD5203_UART is not set # CONFIG_DEBUG_SUNXI_UART0 is not set # CONFIG_DEBUG_SUNXI_UART1 is not set # CONFIG_DEBUG_SPEAR3XX is not set # CONFIG_DEBUG_VERSATILE is not set # CONFIG_DEBUG_ICEDCC is not set # CONFIG_DEBUG_SEMIHOSTING is not set # CONFIG_DEBUG_LL_UART_8250 is not set # CONFIG_DEBUG_LL_UART_PL01X is not set CONFIG_DEBUG_AT91_UART=y CONFIG_DEBUG_UART_FLOW_CONTROL=y CONFIG_DEBUG_LL_INCLUDE="debug/at91.S" CONFIG_DEBUG_UART_PHYS=0xfffff200 CONFIG_DEBUG_UART_VIRT=0xf8fff200 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" CONFIG_EARLY_PRINTK=y # CONFIG_ARM_KPROBES_TEST is not set CONFIG_CORESIGHT=m CONFIG_CORESIGHT_LINKS_AND_SINKS=m # CONFIG_CORESIGHT_LINK_AND_SINK_TMC is not set CONFIG_CORESIGHT_SINK_TPIU=m CONFIG_CORESIGHT_SINK_ETBV10=m # CONFIG_CORESIGHT_SOURCE_ETM3X is not set CONFIG_CORESIGHT_STM=m # CONFIG_CORESIGHT_CPU_DEBUG is not set CONFIG_CORESIGHT_CTI=m # CONFIG_CORESIGHT_CTI_INTEGRATION_REGS is not set # end of arm Debugging # # Kernel Testing and Coverage # CONFIG_KUNIT=y CONFIG_KUNIT_DEBUGFS=y CONFIG_KUNIT_TEST=y CONFIG_KUNIT_EXAMPLE_TEST=y CONFIG_KUNIT_ALL_TESTS=y CONFIG_NOTIFIER_ERROR_INJECTION=y # CONFIG_PM_NOTIFIER_ERROR_INJECT is not set # CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT is not set CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set CONFIG_CPUMASK_KUNIT_TEST=y CONFIG_TEST_LIST_SORT=y # CONFIG_TEST_MIN_HEAP is not set CONFIG_TEST_SORT=y CONFIG_TEST_DIV64=m CONFIG_KPROBES_SANITY_TEST=y CONFIG_BACKTRACE_SELF_TEST=m CONFIG_TEST_REF_TRACKER=m # CONFIG_RBTREE_TEST is not set CONFIG_REED_SOLOMON_TEST=y CONFIG_INTERVAL_TREE_TEST=y CONFIG_PERCPU_TEST=m CONFIG_ATOMIC64_SELFTEST=y CONFIG_TEST_HEXDUMP=m CONFIG_STRING_SELFTEST=m # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_STRSCPY is not set CONFIG_TEST_KSTRTOX=y CONFIG_TEST_PRINTF=y CONFIG_TEST_SCANF=m # CONFIG_TEST_BITMAP is not set CONFIG_TEST_UUID=y CONFIG_TEST_XARRAY=y CONFIG_TEST_RHASHTABLE=y # CONFIG_TEST_SIPHASH is not set CONFIG_TEST_IDA=y CONFIG_TEST_PARMAN=y CONFIG_TEST_LKM=m CONFIG_TEST_BITOPS=m CONFIG_TEST_VMALLOC=m # CONFIG_TEST_USER_COPY is not set CONFIG_TEST_BPF=m CONFIG_TEST_BLACKHOLE_DEV=m CONFIG_FIND_BIT_BENCHMARK=m # CONFIG_TEST_FIRMWARE is not set # CONFIG_TEST_SYSCTL is not set CONFIG_BITFIELD_KUNIT=y CONFIG_HASH_KUNIT_TEST=y CONFIG_RESOURCE_KUNIT_TEST=y CONFIG_SYSCTL_KUNIT_TEST=y CONFIG_LIST_KUNIT_TEST=y CONFIG_LINEAR_RANGES_TEST=y CONFIG_CMDLINE_KUNIT_TEST=y CONFIG_BITS_TEST=y CONFIG_RATIONAL_KUNIT_TEST=y CONFIG_MEMCPY_KUNIT_TEST=y CONFIG_OVERFLOW_KUNIT_TEST=y CONFIG_STACKINIT_KUNIT_TEST=y # CONFIG_TEST_UDELAY is not set # CONFIG_TEST_STATIC_KEYS is not set CONFIG_TEST_DEBUG_VIRTUAL=y # CONFIG_TEST_MEMCAT_P is not set CONFIG_TEST_MEMINIT=m CONFIG_TEST_FREE_PAGES=m CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage CONFIG_WARN_MISSING_DOCUMENTS=y CONFIG_WARN_ABI_ERRORS=y # end of Kernel hacking ^ permalink raw reply [flat|nested] 91+ messages in thread
* [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-22 20:24 ` Mauri Sandberg @ 2022-09-22 20:24 ` Mauri Sandberg -1 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-09-22 20:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg Add D-Link DNS-323 that is based on Device Tree. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> --- changes from v1 - split patches, this one modifies source code - add DT based dns323 board file - don't remove any existing code --- arch/arm/mach-orion5x/Kconfig | 7 + arch/arm/mach-orion5x/Makefile | 1 + arch/arm/mach-orion5x/board-dns323.c | 208 +++++++++++++++++++++++++++ arch/arm/mach-orion5x/board-dt.c | 3 + arch/arm/mach-orion5x/common.h | 6 + 5 files changed, 225 insertions(+) create mode 100644 arch/arm/mach-orion5x/board-dns323.c diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 0044b2823710..1ee0d7e06828 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -68,6 +68,13 @@ config MACH_DNS323 Say 'Y' here if you want your kernel to support the D-Link DNS-323 platform. +config MACH_DNS323_DT + bool "D-Link DNS-323 (Flattened Device Tree)" + select ARCH_ORION5X_DT + help + Say 'Y' here if you want your kernel to support the + D-Link DNS-323 platform. + config MACH_TS209 bool "QNAP TS-109/TS-209" depends on ATAGS diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 1a585a62d5e6..2ed6bafa7acb 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -22,5 +22,6 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o +obj-$(CONFIG_MACH_DNS323_DT) += board-dns323.o obj-$(CONFIG_MACH_MSS2_DT) += board-mss2.o obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o diff --git a/arch/arm/mach-orion5x/board-dns323.c b/arch/arm/mach-orion5x/board-dns323.c new file mode 100644 index 000000000000..72a1f3e228b3 --- /dev/null +++ b/arch/arm/mach-orion5x/board-dns323.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + * Flattened Device Tree board initialization + * + * This is adapted from existing mach files and most of the source code is + * originally written by: + * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> + * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org> + * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net> + */ + +#include <linux/of.h> +#include <linux/phy.h> +#include <linux/marvell_phy.h> +#include <linux/of_net.h> +#include <linux/clk.h> +#include "bridge-regs.h" + +/* Exposed to userspace, do not change */ +enum { + DNS323_REV_A1, /* 0 */ + DNS323_REV_B1, /* 1 */ + DNS323_REV_C1, /* 2 */ +}; + +/**************************************************************************** + * Fix-ups + */ + +static int dns323c_phy_fixup(struct phy_device *phy) +{ + phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS; + + return 0; +} + +/**************************************************************************** + * Ethernet + */ + +/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these + * functions be kept somewhere? + */ +static int __init dns323_parse_hex_nibble(char n) +{ + if (n >= '0' && n <= '9') + return n - '0'; + + if (n >= 'A' && n <= 'F') + return n - 'A' + 10; + + if (n >= 'a' && n <= 'f') + return n - 'a' + 10; + + return -1; +} + +static int __init dns323_parse_hex_byte(const char *b) +{ + int hi; + int lo; + + hi = dns323_parse_hex_nibble(b[0]); + lo = dns323_parse_hex_nibble(b[1]); + + if (hi < 0 || lo < 0) + return -1; + + return (hi << 4) | lo; +} + +#define DNS323_NOR_BOOT_BASE 0xf4000000 + +static int __init dns323_read_mac_addr(u8 *addr) +{ + int i; + char *mac_page; + + /* MAC address is stored as a regular ol' string in /dev/mtdblock4 + * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80). + */ + mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024); + if (!mac_page) + return -ENOMEM; + + /* Sanity check the string we're looking at */ + for (i = 0; i < 5; i++) { + if (*(mac_page + (i * 3) + 2) != ':') + goto error_fail; + } + + for (i = 0; i < ETH_ALEN; i++) { + int byte; + + byte = dns323_parse_hex_byte(mac_page + (i * 3)); + if (byte < 0) + goto error_fail; + + addr[i] = byte; + } + + iounmap(mac_page); + + return 0; + +error_fail: + iounmap(mac_page); + return -EINVAL; +} + +static void __init dns323_dt_eth_fixup(void) +{ + struct device_node *np; + u8 addr[ETH_ALEN]; + int ret; + + /* + * The ethernet interfaces forget the MAC address assigned by u-boot + * if the clocks are turned off. Usually, u-boot on orion boards + * has no DT support to properly set local-mac-address property. + * As a workaround, we get the MAC address that is stored in flash + * and update the port device node if no valid MAC address is set. + */ + ret = dns323_read_mac_addr(addr); + + if (ret) { + pr_warn("Unable to find MAC address in flash memory\n"); + return; + } + + np = of_find_compatible_node(NULL, NULL, "marvell,orion-eth-port"); + + if (!IS_ERR(np)) { + struct device_node *pnp = of_get_parent(np); + struct clk *clk; + struct property *pmac; + u8 tmpmac[ETH_ALEN]; + u8 *macaddr; + int i; + + if (!pnp) + return; + + /* skip disabled nodes or nodes with valid MAC address*/ + if (!of_device_is_available(pnp) || + !of_get_mac_address(np, tmpmac)) + goto eth_fixup_skip; + + clk = of_clk_get(pnp, 0); + if (IS_ERR(clk)) + goto eth_fixup_skip; + + /* ensure port clock is not gated to not hang CPU */ + clk_prepare_enable(clk); + + /* store MAC address register contents in local-mac-address */ + pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); + if (!pmac) + goto eth_fixup_no_mem; + + pmac->value = pmac + 1; + pmac->length = ETH_ALEN; + pmac->name = kstrdup("local-mac-address", GFP_KERNEL); + if (!pmac->name) { + kfree(pmac); + goto eth_fixup_no_mem; + } + + macaddr = pmac->value; + for (i = 0; i < ETH_ALEN; i++) + macaddr[i] = addr[i]; + + of_update_property(np, pmac); + +eth_fixup_no_mem: + clk_disable_unprepare(clk); + clk_put(clk); +eth_fixup_skip: + of_node_put(pnp); + } +} + +void __init dns323_init_dt(void) +{ + if (of_machine_is_compatible("dlink,dns323a1")) { + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ + } else if (of_machine_is_compatible("dlink,dns323c1") && + IS_BUILTIN(CONFIG_PHYLIB)) { + /* Register fixup for the PHY LEDs */ + phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118, + MARVELL_PHY_ID_MASK, + dns323c_phy_fixup); + + /* Now, -this- should theorically be done by the sata_mv driver + * once I figure out what's going on there. Maybe the behaviour + * of the LEDs should be somewhat passed via the platform_data. + * for now, just whack the register and make the LEDs happy + * + * Note: AFAIK, rev B1 needs the same treatement but I'll let + * somebody else test it. + */ + writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); + } + + dns323_dt_eth_fixup(); +} diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index e3736ffc8347..670bff5e53f6 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -57,6 +57,9 @@ static void __init orion5x_dt_init(void) cpu_idle_poll_ctrl(true); } + if (of_machine_is_compatible("dlink,dns323")) + dns323_init_dt(); + if (of_machine_is_compatible("maxtor,shared-storage-2")) mss2_init(); diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index eb96009e21c4..7a21f7216c65 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -75,6 +75,12 @@ extern void mss2_init(void); static inline void mss2_init(void) {} #endif +#ifdef CONFIG_MACH_DNS323_DT +extern void dns323_init_dt(void); +#else +static inline void dns323_init_dt(void) {} +#endif + /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree @ 2022-09-22 20:24 ` Mauri Sandberg 0 siblings, 0 replies; 91+ messages in thread From: Mauri Sandberg @ 2022-09-22 20:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, arnd, olof, andrew, sebastian.hesselbarth, gregory.clement, linux Cc: pali, devicetree, linux-kernel, linux-arm-kernel, Mauri Sandberg Add D-Link DNS-323 that is based on Device Tree. Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> --- changes from v1 - split patches, this one modifies source code - add DT based dns323 board file - don't remove any existing code --- arch/arm/mach-orion5x/Kconfig | 7 + arch/arm/mach-orion5x/Makefile | 1 + arch/arm/mach-orion5x/board-dns323.c | 208 +++++++++++++++++++++++++++ arch/arm/mach-orion5x/board-dt.c | 3 + arch/arm/mach-orion5x/common.h | 6 + 5 files changed, 225 insertions(+) create mode 100644 arch/arm/mach-orion5x/board-dns323.c diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 0044b2823710..1ee0d7e06828 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -68,6 +68,13 @@ config MACH_DNS323 Say 'Y' here if you want your kernel to support the D-Link DNS-323 platform. +config MACH_DNS323_DT + bool "D-Link DNS-323 (Flattened Device Tree)" + select ARCH_ORION5X_DT + help + Say 'Y' here if you want your kernel to support the + D-Link DNS-323 platform. + config MACH_TS209 bool "QNAP TS-109/TS-209" depends on ATAGS diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 1a585a62d5e6..2ed6bafa7acb 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -22,5 +22,6 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o +obj-$(CONFIG_MACH_DNS323_DT) += board-dns323.o obj-$(CONFIG_MACH_MSS2_DT) += board-mss2.o obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o diff --git a/arch/arm/mach-orion5x/board-dns323.c b/arch/arm/mach-orion5x/board-dns323.c new file mode 100644 index 000000000000..72a1f3e228b3 --- /dev/null +++ b/arch/arm/mach-orion5x/board-dns323.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Mauri Sandberg <maukka@ext.kapsi.fi> + * + * Flattened Device Tree board initialization + * + * This is adapted from existing mach files and most of the source code is + * originally written by: + * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> + * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org> + * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net> + */ + +#include <linux/of.h> +#include <linux/phy.h> +#include <linux/marvell_phy.h> +#include <linux/of_net.h> +#include <linux/clk.h> +#include "bridge-regs.h" + +/* Exposed to userspace, do not change */ +enum { + DNS323_REV_A1, /* 0 */ + DNS323_REV_B1, /* 1 */ + DNS323_REV_C1, /* 2 */ +}; + +/**************************************************************************** + * Fix-ups + */ + +static int dns323c_phy_fixup(struct phy_device *phy) +{ + phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS; + + return 0; +} + +/**************************************************************************** + * Ethernet + */ + +/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these + * functions be kept somewhere? + */ +static int __init dns323_parse_hex_nibble(char n) +{ + if (n >= '0' && n <= '9') + return n - '0'; + + if (n >= 'A' && n <= 'F') + return n - 'A' + 10; + + if (n >= 'a' && n <= 'f') + return n - 'a' + 10; + + return -1; +} + +static int __init dns323_parse_hex_byte(const char *b) +{ + int hi; + int lo; + + hi = dns323_parse_hex_nibble(b[0]); + lo = dns323_parse_hex_nibble(b[1]); + + if (hi < 0 || lo < 0) + return -1; + + return (hi << 4) | lo; +} + +#define DNS323_NOR_BOOT_BASE 0xf4000000 + +static int __init dns323_read_mac_addr(u8 *addr) +{ + int i; + char *mac_page; + + /* MAC address is stored as a regular ol' string in /dev/mtdblock4 + * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80). + */ + mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024); + if (!mac_page) + return -ENOMEM; + + /* Sanity check the string we're looking at */ + for (i = 0; i < 5; i++) { + if (*(mac_page + (i * 3) + 2) != ':') + goto error_fail; + } + + for (i = 0; i < ETH_ALEN; i++) { + int byte; + + byte = dns323_parse_hex_byte(mac_page + (i * 3)); + if (byte < 0) + goto error_fail; + + addr[i] = byte; + } + + iounmap(mac_page); + + return 0; + +error_fail: + iounmap(mac_page); + return -EINVAL; +} + +static void __init dns323_dt_eth_fixup(void) +{ + struct device_node *np; + u8 addr[ETH_ALEN]; + int ret; + + /* + * The ethernet interfaces forget the MAC address assigned by u-boot + * if the clocks are turned off. Usually, u-boot on orion boards + * has no DT support to properly set local-mac-address property. + * As a workaround, we get the MAC address that is stored in flash + * and update the port device node if no valid MAC address is set. + */ + ret = dns323_read_mac_addr(addr); + + if (ret) { + pr_warn("Unable to find MAC address in flash memory\n"); + return; + } + + np = of_find_compatible_node(NULL, NULL, "marvell,orion-eth-port"); + + if (!IS_ERR(np)) { + struct device_node *pnp = of_get_parent(np); + struct clk *clk; + struct property *pmac; + u8 tmpmac[ETH_ALEN]; + u8 *macaddr; + int i; + + if (!pnp) + return; + + /* skip disabled nodes or nodes with valid MAC address*/ + if (!of_device_is_available(pnp) || + !of_get_mac_address(np, tmpmac)) + goto eth_fixup_skip; + + clk = of_clk_get(pnp, 0); + if (IS_ERR(clk)) + goto eth_fixup_skip; + + /* ensure port clock is not gated to not hang CPU */ + clk_prepare_enable(clk); + + /* store MAC address register contents in local-mac-address */ + pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); + if (!pmac) + goto eth_fixup_no_mem; + + pmac->value = pmac + 1; + pmac->length = ETH_ALEN; + pmac->name = kstrdup("local-mac-address", GFP_KERNEL); + if (!pmac->name) { + kfree(pmac); + goto eth_fixup_no_mem; + } + + macaddr = pmac->value; + for (i = 0; i < ETH_ALEN; i++) + macaddr[i] = addr[i]; + + of_update_property(np, pmac); + +eth_fixup_no_mem: + clk_disable_unprepare(clk); + clk_put(clk); +eth_fixup_skip: + of_node_put(pnp); + } +} + +void __init dns323_init_dt(void) +{ + if (of_machine_is_compatible("dlink,dns323a1")) { + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ + } else if (of_machine_is_compatible("dlink,dns323c1") && + IS_BUILTIN(CONFIG_PHYLIB)) { + /* Register fixup for the PHY LEDs */ + phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118, + MARVELL_PHY_ID_MASK, + dns323c_phy_fixup); + + /* Now, -this- should theorically be done by the sata_mv driver + * once I figure out what's going on there. Maybe the behaviour + * of the LEDs should be somewhat passed via the platform_data. + * for now, just whack the register and make the LEDs happy + * + * Note: AFAIK, rev B1 needs the same treatement but I'll let + * somebody else test it. + */ + writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); + } + + dns323_dt_eth_fixup(); +} diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index e3736ffc8347..670bff5e53f6 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -57,6 +57,9 @@ static void __init orion5x_dt_init(void) cpu_idle_poll_ctrl(true); } + if (of_machine_is_compatible("dlink,dns323")) + dns323_init_dt(); + if (of_machine_is_compatible("maxtor,shared-storage-2")) mss2_init(); diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index eb96009e21c4..7a21f7216c65 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -75,6 +75,12 @@ extern void mss2_init(void); static inline void mss2_init(void) {} #endif +#ifdef CONFIG_MACH_DNS323_DT +extern void dns323_init_dt(void); +#else +static inline void dns323_init_dt(void) {} +#endif + /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ -- 2.25.1 ^ permalink raw reply related [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-22 20:24 ` Mauri Sandberg @ 2022-09-22 21:10 ` Andrew Lunn -1 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-22 21:10 UTC (permalink / raw) To: Mauri Sandberg Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel > +static void __init dns323_dt_eth_fixup(void) > +{ > + struct device_node *np; > + u8 addr[ETH_ALEN]; > + int ret; > + > + /* > + * The ethernet interfaces forget the MAC address assigned by u-boot > + * if the clocks are turned off. Usually, u-boot on orion boards > + * has no DT support to properly set local-mac-address property. > + * As a workaround, we get the MAC address that is stored in flash > + * and update the port device node if no valid MAC address is set. > + */ This is true for Kirkwood, but orion5x does not have any clocks to gate. So i'm pretty sure this is not true. You copied this code for a different reason. Please document here the real reason for this code. > + ret = dns323_read_mac_addr(addr); > + > + if (ret) { > + pr_warn("Unable to find MAC address in flash memory\n"); > + return; > + } > + > + np = of_find_compatible_node(NULL, NULL, "marvell,orion-eth-port"); > + > + if (!IS_ERR(np)) { > + struct device_node *pnp = of_get_parent(np); > + struct clk *clk; > + struct property *pmac; > + u8 tmpmac[ETH_ALEN]; > + u8 *macaddr; > + int i; > + > + if (!pnp) > + return; > + > + /* skip disabled nodes or nodes with valid MAC address*/ > + if (!of_device_is_available(pnp) || > + !of_get_mac_address(np, tmpmac)) > + goto eth_fixup_skip; > + > + clk = of_clk_get(pnp, 0); > + if (IS_ERR(clk)) > + goto eth_fixup_skip; > + > + /* ensure port clock is not gated to not hang CPU */ > + clk_prepare_enable(clk); I'm pretty sure this clock stuff is not needed. Please comment it out and see if the machine locks up. Kirkwood just stops dead if you access registers when there clocks are disabled. For Orion5x, the ethernet should always have a clock. > + > + /* store MAC address register contents in local-mac-address */ > + pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); > + if (!pmac) > + goto eth_fixup_no_mem; > + > + pmac->value = pmac + 1; > + pmac->length = ETH_ALEN; > + pmac->name = kstrdup("local-mac-address", GFP_KERNEL); > + if (!pmac->name) { > + kfree(pmac); > + goto eth_fixup_no_mem; > + } > + > + macaddr = pmac->value; > + for (i = 0; i < ETH_ALEN; i++) > + macaddr[i] = addr[i]; > + > + of_update_property(np, pmac); > + > +eth_fixup_no_mem: > + clk_disable_unprepare(clk); > + clk_put(clk); > +eth_fixup_skip: > + of_node_put(pnp); > + } > +} > + > +void __init dns323_init_dt(void) > +{ > + if (of_machine_is_compatible("dlink,dns323a1")) { > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ I spotted this in dns323-setup.c as well. Do you have any idea what it does? Andrew ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree @ 2022-09-22 21:10 ` Andrew Lunn 0 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-22 21:10 UTC (permalink / raw) To: Mauri Sandberg Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel > +static void __init dns323_dt_eth_fixup(void) > +{ > + struct device_node *np; > + u8 addr[ETH_ALEN]; > + int ret; > + > + /* > + * The ethernet interfaces forget the MAC address assigned by u-boot > + * if the clocks are turned off. Usually, u-boot on orion boards > + * has no DT support to properly set local-mac-address property. > + * As a workaround, we get the MAC address that is stored in flash > + * and update the port device node if no valid MAC address is set. > + */ This is true for Kirkwood, but orion5x does not have any clocks to gate. So i'm pretty sure this is not true. You copied this code for a different reason. Please document here the real reason for this code. > + ret = dns323_read_mac_addr(addr); > + > + if (ret) { > + pr_warn("Unable to find MAC address in flash memory\n"); > + return; > + } > + > + np = of_find_compatible_node(NULL, NULL, "marvell,orion-eth-port"); > + > + if (!IS_ERR(np)) { > + struct device_node *pnp = of_get_parent(np); > + struct clk *clk; > + struct property *pmac; > + u8 tmpmac[ETH_ALEN]; > + u8 *macaddr; > + int i; > + > + if (!pnp) > + return; > + > + /* skip disabled nodes or nodes with valid MAC address*/ > + if (!of_device_is_available(pnp) || > + !of_get_mac_address(np, tmpmac)) > + goto eth_fixup_skip; > + > + clk = of_clk_get(pnp, 0); > + if (IS_ERR(clk)) > + goto eth_fixup_skip; > + > + /* ensure port clock is not gated to not hang CPU */ > + clk_prepare_enable(clk); I'm pretty sure this clock stuff is not needed. Please comment it out and see if the machine locks up. Kirkwood just stops dead if you access registers when there clocks are disabled. For Orion5x, the ethernet should always have a clock. > + > + /* store MAC address register contents in local-mac-address */ > + pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); > + if (!pmac) > + goto eth_fixup_no_mem; > + > + pmac->value = pmac + 1; > + pmac->length = ETH_ALEN; > + pmac->name = kstrdup("local-mac-address", GFP_KERNEL); > + if (!pmac->name) { > + kfree(pmac); > + goto eth_fixup_no_mem; > + } > + > + macaddr = pmac->value; > + for (i = 0; i < ETH_ALEN; i++) > + macaddr[i] = addr[i]; > + > + of_update_property(np, pmac); > + > +eth_fixup_no_mem: > + clk_disable_unprepare(clk); > + clk_put(clk); > +eth_fixup_skip: > + of_node_put(pnp); > + } > +} > + > +void __init dns323_init_dt(void) > +{ > + if (of_machine_is_compatible("dlink,dns323a1")) { > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ I spotted this in dns323-setup.c as well. Do you have any idea what it does? Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-22 21:10 ` Andrew Lunn @ 2022-09-23 9:03 ` maukka -1 siblings, 0 replies; 91+ messages in thread From: maukka @ 2022-09-23 9:03 UTC (permalink / raw) To: Andrew Lunn Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel On 23.9.2022 00:10, Andrew Lunn wrote: >> +static void __init dns323_dt_eth_fixup(void) >> +{ >> + struct device_node *np; >> + u8 addr[ETH_ALEN]; >> + int ret; >> + >> + /* >> + * The ethernet interfaces forget the MAC address assigned by u-boot >> + * if the clocks are turned off. Usually, u-boot on orion boards >> + * has no DT support to properly set local-mac-address property. >> + * As a workaround, we get the MAC address that is stored in flash >> + * and update the port device node if no valid MAC address is set. >> + */ > > This is true for Kirkwood, but orion5x does not have any clocks to > gate. So i'm pretty sure this is not true. You copied this code for a > different reason. Please document here the real reason for this code. > Yes, will do. To my understanding it looks like uboot does not pass anything to the kernel. >> + ret = dns323_read_mac_addr(addr); >> + >> + if (ret) { >> + pr_warn("Unable to find MAC address in flash memory\n"); >> + return; >> + } >> + >> + np = of_find_compatible_node(NULL, NULL, "marvell,orion-eth-port"); >> + >> + if (!IS_ERR(np)) { >> + struct device_node *pnp = of_get_parent(np); >> + struct clk *clk; >> + struct property *pmac; >> + u8 tmpmac[ETH_ALEN]; >> + u8 *macaddr; >> + int i; >> + >> + if (!pnp) >> + return; >> + >> + /* skip disabled nodes or nodes with valid MAC address*/ >> + if (!of_device_is_available(pnp) || >> + !of_get_mac_address(np, tmpmac)) >> + goto eth_fixup_skip; >> + >> + clk = of_clk_get(pnp, 0); >> + if (IS_ERR(clk)) >> + goto eth_fixup_skip; >> + >> + /* ensure port clock is not gated to not hang CPU */ >> + clk_prepare_enable(clk); > > I'm pretty sure this clock stuff is not needed. Please comment it out > and see if the machine locks up. Kirkwood just stops dead if you > access registers when there clocks are disabled. For Orion5x, the > ethernet should always have a clock. > Will do. >> + >> + /* store MAC address register contents in local-mac-address */ >> + pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); >> + if (!pmac) >> + goto eth_fixup_no_mem; >> + >> + pmac->value = pmac + 1; >> + pmac->length = ETH_ALEN; >> + pmac->name = kstrdup("local-mac-address", GFP_KERNEL); >> + if (!pmac->name) { >> + kfree(pmac); >> + goto eth_fixup_no_mem; >> + } >> + >> + macaddr = pmac->value; >> + for (i = 0; i < ETH_ALEN; i++) >> + macaddr[i] = addr[i]; >> + >> + of_update_property(np, pmac); >> + >> +eth_fixup_no_mem: >> + clk_disable_unprepare(clk); >> + clk_put(clk); >> +eth_fixup_skip: >> + of_node_put(pnp); >> + } >> +} >> + >> +void __init dns323_init_dt(void) >> +{ >> + if (of_machine_is_compatible("dlink,dns323a1")) { >> + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ > > I spotted this in dns323-setup.c as well. Do you have any idea what it > does? > No idea. I have tried to replicate what was in dns323-setup.c as exactly as possible. I can try to leave it out and see if anything changes. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree @ 2022-09-23 9:03 ` maukka 0 siblings, 0 replies; 91+ messages in thread From: maukka @ 2022-09-23 9:03 UTC (permalink / raw) To: Andrew Lunn Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel On 23.9.2022 00:10, Andrew Lunn wrote: >> +static void __init dns323_dt_eth_fixup(void) >> +{ >> + struct device_node *np; >> + u8 addr[ETH_ALEN]; >> + int ret; >> + >> + /* >> + * The ethernet interfaces forget the MAC address assigned by u-boot >> + * if the clocks are turned off. Usually, u-boot on orion boards >> + * has no DT support to properly set local-mac-address property. >> + * As a workaround, we get the MAC address that is stored in flash >> + * and update the port device node if no valid MAC address is set. >> + */ > > This is true for Kirkwood, but orion5x does not have any clocks to > gate. So i'm pretty sure this is not true. You copied this code for a > different reason. Please document here the real reason for this code. > Yes, will do. To my understanding it looks like uboot does not pass anything to the kernel. >> + ret = dns323_read_mac_addr(addr); >> + >> + if (ret) { >> + pr_warn("Unable to find MAC address in flash memory\n"); >> + return; >> + } >> + >> + np = of_find_compatible_node(NULL, NULL, "marvell,orion-eth-port"); >> + >> + if (!IS_ERR(np)) { >> + struct device_node *pnp = of_get_parent(np); >> + struct clk *clk; >> + struct property *pmac; >> + u8 tmpmac[ETH_ALEN]; >> + u8 *macaddr; >> + int i; >> + >> + if (!pnp) >> + return; >> + >> + /* skip disabled nodes or nodes with valid MAC address*/ >> + if (!of_device_is_available(pnp) || >> + !of_get_mac_address(np, tmpmac)) >> + goto eth_fixup_skip; >> + >> + clk = of_clk_get(pnp, 0); >> + if (IS_ERR(clk)) >> + goto eth_fixup_skip; >> + >> + /* ensure port clock is not gated to not hang CPU */ >> + clk_prepare_enable(clk); > > I'm pretty sure this clock stuff is not needed. Please comment it out > and see if the machine locks up. Kirkwood just stops dead if you > access registers when there clocks are disabled. For Orion5x, the > ethernet should always have a clock. > Will do. >> + >> + /* store MAC address register contents in local-mac-address */ >> + pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); >> + if (!pmac) >> + goto eth_fixup_no_mem; >> + >> + pmac->value = pmac + 1; >> + pmac->length = ETH_ALEN; >> + pmac->name = kstrdup("local-mac-address", GFP_KERNEL); >> + if (!pmac->name) { >> + kfree(pmac); >> + goto eth_fixup_no_mem; >> + } >> + >> + macaddr = pmac->value; >> + for (i = 0; i < ETH_ALEN; i++) >> + macaddr[i] = addr[i]; >> + >> + of_update_property(np, pmac); >> + >> +eth_fixup_no_mem: >> + clk_disable_unprepare(clk); >> + clk_put(clk); >> +eth_fixup_skip: >> + of_node_put(pnp); >> + } >> +} >> + >> +void __init dns323_init_dt(void) >> +{ >> + if (of_machine_is_compatible("dlink,dns323a1")) { >> + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ > > I spotted this in dns323-setup.c as well. Do you have any idea what it > does? > No idea. I have tried to replicate what was in dns323-setup.c as exactly as possible. I can try to leave it out and see if anything changes. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-23 9:03 ` maukka @ 2022-09-23 12:12 ` Andrew Lunn -1 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-23 12:12 UTC (permalink / raw) To: maukka Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel > > > + if (of_machine_is_compatible("dlink,dns323a1")) { > > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ > > > > I spotted this in dns323-setup.c as well. Do you have any idea what it > > does? > > > > No idea. I have tried to replicate what was in dns323-setup.c as exactly as > possible. > I can try to leave it out and see if anything changes. It is best to keep what we don't understand. It will be there for a reason. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree @ 2022-09-23 12:12 ` Andrew Lunn 0 siblings, 0 replies; 91+ messages in thread From: Andrew Lunn @ 2022-09-23 12:12 UTC (permalink / raw) To: maukka Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, pali, devicetree, linux-kernel, linux-arm-kernel > > > + if (of_machine_is_compatible("dlink,dns323a1")) { > > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ > > > > I spotted this in dns323-setup.c as well. Do you have any idea what it > > does? > > > > No idea. I have tried to replicate what was in dns323-setup.c as exactly as > possible. > I can try to leave it out and see if anything changes. It is best to keep what we don't understand. It will be there for a reason. Andrew ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-23 12:12 ` Andrew Lunn @ 2022-09-23 18:02 ` Pali Rohár -1 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-09-23 18:02 UTC (permalink / raw) To: Andrew Lunn Cc: maukka, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel, linux-arm-kernel On Friday 23 September 2022 14:12:24 Andrew Lunn wrote: > > > > + if (of_machine_is_compatible("dlink,dns323a1")) { > > > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ > > > > > > I spotted this in dns323-setup.c as well. Do you have any idea what it > > > does? > > > > > > > No idea. I have tried to replicate what was in dns323-setup.c as exactly as > > possible. > > I can try to leave it out and see if anything changes. > > It is best to keep what we don't understand. It will be there for a > reason. > > Andrew Hello! I tried to index all publicly available Marvell SoC documentations into kernel documentation subfolder: https://docs.kernel.org/arm/marvell.html For Orion there is linked Datasheet and User Manual, so you could try to find in those documents that mentioned register and check what it is doing. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree @ 2022-09-23 18:02 ` Pali Rohár 0 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-09-23 18:02 UTC (permalink / raw) To: Andrew Lunn Cc: maukka, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel, linux-arm-kernel On Friday 23 September 2022 14:12:24 Andrew Lunn wrote: > > > > + if (of_machine_is_compatible("dlink,dns323a1")) { > > > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ > > > > > > I spotted this in dns323-setup.c as well. Do you have any idea what it > > > does? > > > > > > > No idea. I have tried to replicate what was in dns323-setup.c as exactly as > > possible. > > I can try to leave it out and see if anything changes. > > It is best to keep what we don't understand. It will be there for a > reason. > > Andrew Hello! I tried to index all publicly available Marvell SoC documentations into kernel documentation subfolder: https://docs.kernel.org/arm/marvell.html For Orion there is linked Datasheet and User Manual, so you could try to find in those documents that mentioned register and check what it is doing. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-23 18:02 ` Pali Rohár @ 2022-09-26 11:56 ` maukka -1 siblings, 0 replies; 91+ messages in thread From: maukka @ 2022-09-26 11:56 UTC (permalink / raw) To: Pali Rohár Cc: Andrew Lunn, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel, linux-arm-kernel On 23.9.2022 21:02, Pali Rohár wrote: > On Friday 23 September 2022 14:12:24 Andrew Lunn wrote: >> > > > + if (of_machine_is_compatible("dlink,dns323a1")) { >> > > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ >> > > >> > > I spotted this in dns323-setup.c as well. Do you have any idea what it >> > > does? >> > > >> > >> > No idea. I have tried to replicate what was in dns323-setup.c as exactly as >> > possible. >> > I can try to leave it out and see if anything changes. >> >> It is best to keep what we don't understand. It will be there for a >> reason. >> >> Andrew > > Hello! I tried to index all publicly available Marvell SoC > documentations into kernel documentation subfolder: > https://docs.kernel.org/arm/marvell.html > > For Orion there is linked Datasheet and User Manual, so you could try > to > find in those documents that mentioned register and check what it is > doing. MPP_DEV_CTRL refers to register at address 0x10008. According to the 88F5152 user manual it's 'Device Multiplex Control Register' Offset: 0x10008. Bits Field Type/InitVal Description [31:0] Reserved RES 0x03FF0000 Reserved. NOTE: Must be 0x03FF0000'. DEV_D[31:16] receives no hits in the documentation, only to DEV_D[15:0] are referred. Maybe 88F5151 is different, hard to say. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree @ 2022-09-26 11:56 ` maukka 0 siblings, 0 replies; 91+ messages in thread From: maukka @ 2022-09-26 11:56 UTC (permalink / raw) To: Pali Rohár Cc: Andrew Lunn, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel, linux-arm-kernel On 23.9.2022 21:02, Pali Rohár wrote: > On Friday 23 September 2022 14:12:24 Andrew Lunn wrote: >> > > > + if (of_machine_is_compatible("dlink,dns323a1")) { >> > > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ >> > > >> > > I spotted this in dns323-setup.c as well. Do you have any idea what it >> > > does? >> > > >> > >> > No idea. I have tried to replicate what was in dns323-setup.c as exactly as >> > possible. >> > I can try to leave it out and see if anything changes. >> >> It is best to keep what we don't understand. It will be there for a >> reason. >> >> Andrew > > Hello! I tried to index all publicly available Marvell SoC > documentations into kernel documentation subfolder: > https://docs.kernel.org/arm/marvell.html > > For Orion there is linked Datasheet and User Manual, so you could try > to > find in those documents that mentioned register and check what it is > doing. MPP_DEV_CTRL refers to register at address 0x10008. According to the 88F5152 user manual it's 'Device Multiplex Control Register' Offset: 0x10008. Bits Field Type/InitVal Description [31:0] Reserved RES 0x03FF0000 Reserved. NOTE: Must be 0x03FF0000'. DEV_D[31:16] receives no hits in the documentation, only to DEV_D[15:0] are referred. Maybe 88F5151 is different, hard to say. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-26 11:56 ` maukka (?) @ 2022-09-26 12:23 ` Pali Rohár 2022-09-28 13:32 ` [EXT] " Elad Nachman -1 siblings, 1 reply; 91+ messages in thread From: Pali Rohár @ 2022-09-26 12:23 UTC (permalink / raw) To: Elad Nachman Cc: maukka, Andrew Lunn, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel Hello Elad! I hope that would not bothering you. We are doing here cleanup of kernel code for older Marvell SoCs (Orion) and there one unknown thing about 88F5181's 0x10008 register. See below. On Monday 26 September 2022 14:56:48 maukka@ext.kapsi.fi wrote: > On 23.9.2022 21:02, Pali Rohár wrote: > > On Friday 23 September 2022 14:12:24 Andrew Lunn wrote: > > > > > > + if (of_machine_is_compatible("dlink,dns323a1")) { > > > > > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ > > > > > > > > > > I spotted this in dns323-setup.c as well. Do you have any idea what it > > > > > does? > > > > > > > > > > > > > No idea. I have tried to replicate what was in dns323-setup.c as exactly as > > > > possible. > > > > I can try to leave it out and see if anything changes. > > > > > > It is best to keep what we don't understand. It will be there for a > > > reason. > > > > > > Andrew > > > > Hello! I tried to index all publicly available Marvell SoC > > documentations into kernel documentation subfolder: > > https://docs.kernel.org/arm/marvell.html > > > > For Orion there is linked Datasheet and User Manual, so you could try to > > find in those documents that mentioned register and check what it is > > doing. > > MPP_DEV_CTRL refers to register at address 0x10008. According to the 88F5152 > user manual it's > 'Device Multiplex Control Register' Offset: 0x10008. > > Bits Field Type/InitVal Description > [31:0] Reserved RES 0x03FF0000 Reserved. NOTE: Must be 0x03FF0000'. > > DEV_D[31:16] receives no hits in the documentation, only to DEV_D[15:0] are > referred. In linked public document I found same thing. Register is for 88F5182 reserved. (You have typo in comment, it is 88F5182, not *52). > Maybe 88F5151 is different, hard to say. I have feeling that for 88F5181 it is not reserved and has to be configured correctly. (Also typo in your comment, it is 88F5181, not *51). But I have not found any copy of 88F5181 user manual document on internet. In past 88F518x and 88F528x documents and user manuals were available publicly on Marvell website, visible from web archive: https://web.archive.org/web/20080607215437/http://www.marvell.com/products/media/index.jsp But Marvell deleted these documents from their public website and for kernel developers they are now probably lost. I do not know about any other backups. Elad, could you please help us? Do you have access to functional specifications / user manuals for 88F518x and 88F528x or have information how kernel developers can get access to those documents? Hopefully they were not totally lost. We just need explanation for register 'Device Multiplex Control Register' Offset: 0x10008. ^ permalink raw reply [flat|nested] 91+ messages in thread
* RE: [EXT] Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-26 12:23 ` Pali Rohár @ 2022-09-28 13:32 ` Elad Nachman 2022-09-30 15:40 ` Pali Rohár 0 siblings, 1 reply; 91+ messages in thread From: Elad Nachman @ 2022-09-28 13:32 UTC (permalink / raw) To: Pali Rohár Cc: maukka, Andrew Lunn, robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel Hi Pali, I do not have documentation for this controller, as it is almost 20 years old... I did manage, however, to find some very old u-boot code for it. From reverse engineering this u-boot code, it looks like this is a "DEV" MPP function register, similar to the MPP0_7, MPP8_15 and the MPP16_23 registers. Basically, setting bits of this registers assign the pin to the special purpose, while clearing it makes it a GPP (General Purpose Pin). For all of the boards (over half a dozen) support by this u-boot, this register is set to zero (see above). From user guides I have found for few of these boards, only MPPs up to MPP19 are used, hence it make sense to leave these MPPs as GPPs . Hopefully this helps in some way. FYI, Elad. -----Original Message----- From: Pali Rohár <pali@kernel.org> Sent: Monday, September 26, 2022 3:23 PM To: Elad Nachman <enachman@marvell.com> Cc: maukka@ext.kapsi.fi; Andrew Lunn <andrew@lunn.ch>; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; arnd@arndb.de; olof@lixom.net; sebastian.hesselbarth@gmail.com; gregory.clement@bootlin.com; linux@armlinux.org.uk; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org Subject: [EXT] Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree External Email ---------------------------------------------------------------------- Hello Elad! I hope that would not bothering you. We are doing here cleanup of kernel code for older Marvell SoCs (Orion) and there one unknown thing about 88F5181's 0x10008 register. See below. On Monday 26 September 2022 14:56:48 maukka@ext.kapsi.fi wrote: > On 23.9.2022 21:02, Pali Rohár wrote: > > On Friday 23 September 2022 14:12:24 Andrew Lunn wrote: > > > > > > + if (of_machine_is_compatible("dlink,dns323a1")) { > > > > > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ > > > > > > > > > > I spotted this in dns323-setup.c as well. Do you have any idea > > > > > what it does? > > > > > > > > > > > > > No idea. I have tried to replicate what was in dns323-setup.c as > > > > exactly as possible. > > > > I can try to leave it out and see if anything changes. > > > > > > It is best to keep what we don't understand. It will be there for > > > a reason. > > > > > > Andrew > > > > Hello! I tried to index all publicly available Marvell SoC > > documentations into kernel documentation subfolder: > > https://urldefense.proofpoint.com/v2/url?u=https-3A__docs.kernel.org > > _arm_marvell.html&d=DwIDaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=eTeNTLEK5-TxXc > > zjOcKPhANIFtlB9pP4lq9qhdlFrwQ&m=QnvtICgYrknBcrJ4SBYkL8zUxNtqo3A40bjE > > TmCHhBbdWQOUaRffkiMgtuRkQ2WE&s=QiNvxcOSpDNOTgiK8nuCZ18pgJRKBtgVu-SeG > > E9n7CY&e= > > > > For Orion there is linked Datasheet and User Manual, so you could > > try to find in those documents that mentioned register and check > > what it is doing. > > MPP_DEV_CTRL refers to register at address 0x10008. According to the > 88F5152 user manual it's 'Device Multiplex Control Register' Offset: > 0x10008. > > Bits Field Type/InitVal Description > [31:0] Reserved RES 0x03FF0000 Reserved. NOTE: Must be 0x03FF0000'. > > DEV_D[31:16] receives no hits in the documentation, only to > DEV_D[15:0] are referred. In linked public document I found same thing. Register is for 88F5182 reserved. (You have typo in comment, it is 88F5182, not *52). > Maybe 88F5151 is different, hard to say. I have feeling that for 88F5181 it is not reserved and has to be configured correctly. (Also typo in your comment, it is 88F5181, not *51). But I have not found any copy of 88F5181 user manual document on internet. In past 88F518x and 88F528x documents and user manuals were available publicly on Marvell website, visible from web archive: https://urldefense.proofpoint.com/v2/url?u=https-3A__web.archive.org_web_20080607215437_http-3A__www.marvell.com_products_media_index.jsp&d=DwIDaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=eTeNTLEK5-TxXczjOcKPhANIFtlB9pP4lq9qhdlFrwQ&m=QnvtICgYrknBcrJ4SBYkL8zUxNtqo3A40bjETmCHhBbdWQOUaRffkiMgtuRkQ2WE&s=k1vn2-NVEU2OsJYVTmuWMRKdN2t1MQ9pduTkGaasU4s&e= But Marvell deleted these documents from their public website and for kernel developers they are now probably lost. I do not know about any other backups. Elad, could you please help us? Do you have access to functional specifications / user manuals for 88F518x and 88F528x or have information how kernel developers can get access to those documents? Hopefully they were not totally lost. We just need explanation for register 'Device Multiplex Control Register' Offset: 0x10008. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [EXT] Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-28 13:32 ` [EXT] " Elad Nachman @ 2022-09-30 15:40 ` Pali Rohár 0 siblings, 0 replies; 91+ messages in thread From: Pali Rohár @ 2022-09-30 15:40 UTC (permalink / raw) To: Elad Nachman, maukka, Andrew Lunn Cc: robh+dt, krzysztof.kozlowski+dt, arnd, olof, sebastian.hesselbarth, gregory.clement, linux, devicetree, linux-kernel Hello Elad! Thank you very much for this information! With information from other resources, I think I understood it. Andrew & Mauri: here is my recap: On https://docs.kernel.org/arm/marvell.html is Datasheet document for 88F5281 SoC (it is different! not 88F5181!) and in its section 3.2 Device Pins Multiplexing it is documented. SoC pins named MPP[0], ... MPP[19] are configured via registers 0x10000, 0x10004 and 0x10050 as documented in User Manual. And SoC pins named DEV_D[16], ... DEV_D[31] are configured via that undocumented register 0x10008. Normally 32 DEV_D pins on 88F5281 SoC are used for Device Bus Interface but when SoC has configured only 16-bit or 8-bit Device Bus or it does not use Device Bus Interface at all then pins DEV_D[16] ... DEV_D[31] can be used as GPIOs. Elad wrote that clearing particular bit _i_ in 0x10008 sets DEV_D[i] on 88F5181 to GPIO but datasheet for 88F5281 says that clearing bit i (value 0x0) sets DEV_D[i] to Device Bus mode. I have no idea if 88F5281 and 88F5181 have inverted logic or if documentation has bugs. But at least it this explanation makes sense for me. So code "writel(0, MPP_DEV_CTRL);" either changes all DEV_D pins to GPIO mode or to Device Bus Interface mode. In most cases Device Bus is used for connecting Parallel NAND or any similar Flash memory device. Mauri, you can check if your board has such memory. Or if it uses GPIOs connected on DEV_D pins. If not then it does not matter how you set that register. Anyway, just for completeness, the "proper" way for using MPP_DEV_CTRL should have been in pinctrl/mvebu/pinctrl-orion.c driver. But I think it does not make sense to spend another time for this old board to convert this code into proper pinctrl driver. Hopes that this helps to finally understand that old undocumented mystery. On Wednesday 28 September 2022 13:32:27 Elad Nachman wrote: > Hi Pali, > > I do not have documentation for this controller, as it is almost 20 years old... > > I did manage, however, to find some very old u-boot code for it. > > From reverse engineering this u-boot code, it looks like this is a "DEV" MPP function register, similar to the MPP0_7, MPP8_15 and the MPP16_23 registers. > > Basically, setting bits of this registers assign the pin to the special purpose, while clearing it makes it a GPP (General Purpose Pin). > > For all of the boards (over half a dozen) support by this u-boot, this register is set to zero (see above). > From user guides I have found for few of these boards, only MPPs up to MPP19 are used, hence it make sense to leave these MPPs as GPPs . > > Hopefully this helps in some way. > > FYI, > > Elad. > > > -----Original Message----- > From: Pali Rohár <pali@kernel.org> > Sent: Monday, September 26, 2022 3:23 PM > To: Elad Nachman <enachman@marvell.com> > Cc: maukka@ext.kapsi.fi; Andrew Lunn <andrew@lunn.ch>; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; arnd@arndb.de; olof@lixom.net; sebastian.hesselbarth@gmail.com; gregory.clement@bootlin.com; linux@armlinux.org.uk; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: [EXT] Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree > > External Email > > ---------------------------------------------------------------------- > Hello Elad! I hope that would not bothering you. We are doing here cleanup of kernel code for older Marvell SoCs (Orion) and there one unknown thing about 88F5181's 0x10008 register. See below. > > On Monday 26 September 2022 14:56:48 maukka@ext.kapsi.fi wrote: > > On 23.9.2022 21:02, Pali Rohár wrote: > > > On Friday 23 September 2022 14:12:24 Andrew Lunn wrote: > > > > > > > + if (of_machine_is_compatible("dlink,dns323a1")) { > > > > > > > + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ > > > > > > > > > > > > I spotted this in dns323-setup.c as well. Do you have any idea > > > > > > what it does? > > > > > > > > > > > > > > > > No idea. I have tried to replicate what was in dns323-setup.c as > > > > > exactly as possible. > > > > > I can try to leave it out and see if anything changes. > > > > > > > > It is best to keep what we don't understand. It will be there for > > > > a reason. > > > > > > > > Andrew > > > > > > Hello! I tried to index all publicly available Marvell SoC > > > documentations into kernel documentation subfolder: > > > https://urldefense.proofpoint.com/v2/url?u=https-3A__docs.kernel.org > > > _arm_marvell.html&d=DwIDaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=eTeNTLEK5-TxXc > > > zjOcKPhANIFtlB9pP4lq9qhdlFrwQ&m=QnvtICgYrknBcrJ4SBYkL8zUxNtqo3A40bjE > > > TmCHhBbdWQOUaRffkiMgtuRkQ2WE&s=QiNvxcOSpDNOTgiK8nuCZ18pgJRKBtgVu-SeG > > > E9n7CY&e= > > > > > > For Orion there is linked Datasheet and User Manual, so you could > > > try to find in those documents that mentioned register and check > > > what it is doing. > > > > MPP_DEV_CTRL refers to register at address 0x10008. According to the > > 88F5152 user manual it's 'Device Multiplex Control Register' Offset: > > 0x10008. > > > > Bits Field Type/InitVal Description > > [31:0] Reserved RES 0x03FF0000 Reserved. NOTE: Must be 0x03FF0000'. > > > > DEV_D[31:16] receives no hits in the documentation, only to > > DEV_D[15:0] are referred. > > In linked public document I found same thing. Register is for 88F5182 reserved. (You have typo in comment, it is 88F5182, not *52). > > > Maybe 88F5151 is different, hard to say. > > I have feeling that for 88F5181 it is not reserved and has to be configured correctly. (Also typo in your comment, it is 88F5181, not *51). > But I have not found any copy of 88F5181 user manual document on internet. > > In past 88F518x and 88F528x documents and user manuals were available publicly on Marvell website, visible from web archive: > https://urldefense.proofpoint.com/v2/url?u=https-3A__web.archive.org_web_20080607215437_http-3A__www.marvell.com_products_media_index.jsp&d=DwIDaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=eTeNTLEK5-TxXczjOcKPhANIFtlB9pP4lq9qhdlFrwQ&m=QnvtICgYrknBcrJ4SBYkL8zUxNtqo3A40bjETmCHhBbdWQOUaRffkiMgtuRkQ2WE&s=k1vn2-NVEU2OsJYVTmuWMRKdN2t1MQ9pduTkGaasU4s&e= > > But Marvell deleted these documents from their public website and for kernel developers they are now probably lost. I do not know about any other backups. > > > Elad, could you please help us? Do you have access to functional specifications / user manuals for 88F518x and 88F528x or have information how kernel developers can get access to those documents? > Hopefully they were not totally lost. We just need explanation for register 'Device Multiplex Control Register' Offset: 0x10008. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-22 20:24 ` Mauri Sandberg @ 2022-09-22 21:39 ` Arnd Bergmann -1 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-09-22 21:39 UTC (permalink / raw) To: Mauri Sandberg, Rob Herring, krzysztof.kozlowski+dt, Olof Johansson, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement, Russell King Cc: Pali Rohár, devicetree, linux-kernel, linux-arm-kernel On Thu, Sep 22, 2022, at 10:24 PM, Mauri Sandberg wrote: > + > +/* dns323_parse_hex_*() taken from tsx09-common.c; should a common > copy of these > + * functions be kept somewhere? > + */ > +static int __init dns323_parse_hex_nibble(char n) > +{ > + if (n >= '0' && n <= '9') > + return n - '0'; > + > + if (n >= 'A' && n <= 'F') > + return n - 'A' + 10; > + > + if (n >= 'a' && n <= 'f') > + return n - 'a' + 10; > + > + return -1; > +} > + > +static int __init dns323_parse_hex_byte(const char *b) > +{ > + int hi; > + int lo; > + > + hi = dns323_parse_hex_nibble(b[0]); > + lo = dns323_parse_hex_nibble(b[1]); > + > + if (hi < 0 || lo < 0) > + return -1; > + > + return (hi << 4) | lo; > +} > + Can you use simple_strntoull() to parse the address into a u64 instead? > +static int __init dns323_read_mac_addr(u8 *addr) > +{ > + int i; > + char *mac_page; > + > + /* MAC address is stored as a regular ol' string in /dev/mtdblock4 > + * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80). > + */ > + mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024); > + if (!mac_page) > + return -ENOMEM; It would be nicer to use of_iomap() on the nor device than a hardcoded physical address here, at least if that doesn't add too much extra complexity. Arnd ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree @ 2022-09-22 21:39 ` Arnd Bergmann 0 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-09-22 21:39 UTC (permalink / raw) To: Mauri Sandberg, Rob Herring, krzysztof.kozlowski+dt, Olof Johansson, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement, Russell King Cc: Pali Rohár, devicetree, linux-kernel, linux-arm-kernel On Thu, Sep 22, 2022, at 10:24 PM, Mauri Sandberg wrote: > + > +/* dns323_parse_hex_*() taken from tsx09-common.c; should a common > copy of these > + * functions be kept somewhere? > + */ > +static int __init dns323_parse_hex_nibble(char n) > +{ > + if (n >= '0' && n <= '9') > + return n - '0'; > + > + if (n >= 'A' && n <= 'F') > + return n - 'A' + 10; > + > + if (n >= 'a' && n <= 'f') > + return n - 'a' + 10; > + > + return -1; > +} > + > +static int __init dns323_parse_hex_byte(const char *b) > +{ > + int hi; > + int lo; > + > + hi = dns323_parse_hex_nibble(b[0]); > + lo = dns323_parse_hex_nibble(b[1]); > + > + if (hi < 0 || lo < 0) > + return -1; > + > + return (hi << 4) | lo; > +} > + Can you use simple_strntoull() to parse the address into a u64 instead? > +static int __init dns323_read_mac_addr(u8 *addr) > +{ > + int i; > + char *mac_page; > + > + /* MAC address is stored as a regular ol' string in /dev/mtdblock4 > + * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80). > + */ > + mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024); > + if (!mac_page) > + return -ENOMEM; It would be nicer to use of_iomap() on the nor device than a hardcoded physical address here, at least if that doesn't add too much extra complexity. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-22 21:39 ` Arnd Bergmann @ 2022-09-23 9:13 ` maukka -1 siblings, 0 replies; 91+ messages in thread From: maukka @ 2022-09-23 9:13 UTC (permalink / raw) To: Arnd Bergmann Cc: Rob Herring, krzysztof.kozlowski+dt, Olof Johansson, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement, Russell King, Pali Rohár, devicetree, linux-kernel, linux-arm-kernel On 23.9.2022 00:39, Arnd Bergmann wrote: > On Thu, Sep 22, 2022, at 10:24 PM, Mauri Sandberg wrote: >> + >> +/* dns323_parse_hex_*() taken from tsx09-common.c; should a common >> copy of these >> + * functions be kept somewhere? >> + */ >> +static int __init dns323_parse_hex_nibble(char n) >> +{ >> + if (n >= '0' && n <= '9') >> + return n - '0'; >> + >> + if (n >= 'A' && n <= 'F') >> + return n - 'A' + 10; >> + >> + if (n >= 'a' && n <= 'f') >> + return n - 'a' + 10; >> + >> + return -1; >> +} >> + >> +static int __init dns323_parse_hex_byte(const char *b) >> +{ >> + int hi; >> + int lo; >> + >> + hi = dns323_parse_hex_nibble(b[0]); >> + lo = dns323_parse_hex_nibble(b[1]); >> + >> + if (hi < 0 || lo < 0) >> + return -1; >> + >> + return (hi << 4) | lo; >> +} >> + > > Can you use simple_strntoull() to parse the address into a u64 instead? > Nice idea. Its current replacement seems to be kstrtoull(). I'll have to do it byte by byte, right? Or what do you have in mind with 64bit unsigned? >> +static int __init dns323_read_mac_addr(u8 *addr) >> +{ >> + int i; >> + char *mac_page; >> + >> + /* MAC address is stored as a regular ol' string in /dev/mtdblock4 >> + * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80). >> + */ >> + mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024); >> + if (!mac_page) >> + return -ENOMEM; > > It would be nicer to use of_iomap() on the nor device than a > hardcoded physical address here, at least if that doesn't add > too much extra complexity. > I'll look into this. ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree @ 2022-09-23 9:13 ` maukka 0 siblings, 0 replies; 91+ messages in thread From: maukka @ 2022-09-23 9:13 UTC (permalink / raw) To: Arnd Bergmann Cc: Rob Herring, krzysztof.kozlowski+dt, Olof Johansson, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement, Russell King, Pali Rohár, devicetree, linux-kernel, linux-arm-kernel On 23.9.2022 00:39, Arnd Bergmann wrote: > On Thu, Sep 22, 2022, at 10:24 PM, Mauri Sandberg wrote: >> + >> +/* dns323_parse_hex_*() taken from tsx09-common.c; should a common >> copy of these >> + * functions be kept somewhere? >> + */ >> +static int __init dns323_parse_hex_nibble(char n) >> +{ >> + if (n >= '0' && n <= '9') >> + return n - '0'; >> + >> + if (n >= 'A' && n <= 'F') >> + return n - 'A' + 10; >> + >> + if (n >= 'a' && n <= 'f') >> + return n - 'a' + 10; >> + >> + return -1; >> +} >> + >> +static int __init dns323_parse_hex_byte(const char *b) >> +{ >> + int hi; >> + int lo; >> + >> + hi = dns323_parse_hex_nibble(b[0]); >> + lo = dns323_parse_hex_nibble(b[1]); >> + >> + if (hi < 0 || lo < 0) >> + return -1; >> + >> + return (hi << 4) | lo; >> +} >> + > > Can you use simple_strntoull() to parse the address into a u64 instead? > Nice idea. Its current replacement seems to be kstrtoull(). I'll have to do it byte by byte, right? Or what do you have in mind with 64bit unsigned? >> +static int __init dns323_read_mac_addr(u8 *addr) >> +{ >> + int i; >> + char *mac_page; >> + >> + /* MAC address is stored as a regular ol' string in /dev/mtdblock4 >> + * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80). >> + */ >> + mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024); >> + if (!mac_page) >> + return -ENOMEM; > > It would be nicer to use of_iomap() on the nor device than a > hardcoded physical address here, at least if that doesn't add > too much extra complexity. > I'll look into this. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree 2022-09-23 9:13 ` maukka @ 2022-09-23 9:24 ` Arnd Bergmann -1 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-09-23 9:24 UTC (permalink / raw) To: Mauri Sandberg Cc: Rob Herring, krzysztof.kozlowski+dt, Olof Johansson, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement, Russell King, Pali Rohár, devicetree, linux-kernel, linux-arm-kernel On Fri, Sep 23, 2022, at 11:13 AM, maukka@ext.kapsi.fi wrote: > On 23.9.2022 00:39, Arnd Bergmann wrote: >> Can you use simple_strntoull() to parse the address into a u64 instead? >> > Nice idea. Its current replacement seems to be kstrtoull(). Right. > I'll have to do > it byte by byte, right? Or what do you have in mind with 64bit unsigned? I misread your code and assumed it was stored as a 12-digit hexadecimal number, but you are right: with the colons you still need to iterate the bytes. I looked a little further and found the mac_pton() function that I think does exactly what you need. Arnd ^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree @ 2022-09-23 9:24 ` Arnd Bergmann 0 siblings, 0 replies; 91+ messages in thread From: Arnd Bergmann @ 2022-09-23 9:24 UTC (permalink / raw) To: Mauri Sandberg Cc: Rob Herring, krzysztof.kozlowski+dt, Olof Johansson, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement, Russell King, Pali Rohár, devicetree, linux-kernel, linux-arm-kernel On Fri, Sep 23, 2022, at 11:13 AM, maukka@ext.kapsi.fi wrote: > On 23.9.2022 00:39, Arnd Bergmann wrote: >> Can you use simple_strntoull() to parse the address into a u64 instead? >> > Nice idea. Its current replacement seems to be kstrtoull(). Right. > I'll have to do > it byte by byte, right? Or what do you have in mind with 64bit unsigned? I misread your code and assumed it was stored as a 12-digit hexadecimal number, but you are right: with the colons you still need to iterate the bytes. I looked a little further and found the mac_pton() function that I think does exactly what you need. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 91+ messages in thread
end of thread, other threads:[~2022-09-30 15:40 UTC | newest] Thread overview: 91+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-27 16:21 [RFC RFT PATCH v1 0/1] ARM: orion5x: convert D-Link DNS-323 to the Device Tree Mauri Sandberg 2022-04-27 16:21 ` Mauri Sandberg 2022-04-27 16:21 ` [RFC RFT PATCH v1 1/1] " Mauri Sandberg 2022-04-27 16:21 ` Mauri Sandberg 2022-04-27 18:12 ` Arnd Bergmann 2022-04-27 18:12 ` Arnd Bergmann 2022-04-28 20:06 ` Mauri Sandberg 2022-04-28 20:06 ` Mauri Sandberg 2022-04-28 20:47 ` Arnd Bergmann 2022-04-28 20:47 ` Arnd Bergmann 2022-04-28 7:13 ` Krzysztof Kozlowski 2022-04-28 7:13 ` Krzysztof Kozlowski 2022-04-28 20:09 ` Mauri Sandberg 2022-04-28 20:09 ` Mauri Sandberg 2022-04-27 18:10 ` [RFC RFT PATCH v1 0/1] " Arnd Bergmann 2022-04-27 18:10 ` Arnd Bergmann 2022-04-28 0:18 ` Andrew Lunn 2022-04-28 0:18 ` Andrew Lunn 2022-04-28 20:25 ` Mauri Sandberg 2022-04-28 20:25 ` Mauri Sandberg 2022-04-28 23:26 ` Andrew Lunn 2022-04-28 23:26 ` Andrew Lunn 2022-05-03 8:20 ` Mauri Sandberg 2022-05-03 8:20 ` Mauri Sandberg 2022-04-28 20:01 ` Mauri Sandberg 2022-04-28 20:01 ` Mauri Sandberg 2022-04-28 20:56 ` Arnd Bergmann 2022-04-28 20:56 ` Arnd Bergmann 2022-05-08 14:06 ` Mauri Sandberg 2022-05-08 14:06 ` Mauri Sandberg 2022-05-08 15:02 ` Arnd Bergmann 2022-05-08 15:02 ` Arnd Bergmann 2022-05-08 15:22 ` Pali Rohár 2022-05-08 15:22 ` Pali Rohár 2022-05-08 15:41 ` Pali Rohár 2022-05-08 15:41 ` Pali Rohár 2022-05-09 7:21 ` Arnd Bergmann 2022-05-09 7:21 ` Arnd Bergmann 2022-05-09 10:48 ` Mauri Sandberg 2022-05-09 10:48 ` Mauri Sandberg 2022-05-09 11:03 ` Pali Rohár 2022-05-09 11:03 ` Pali Rohár 2022-05-08 19:34 ` Mauri Sandberg 2022-05-08 19:34 ` Mauri Sandberg 2022-05-08 20:10 ` Pali Rohár 2022-05-08 20:10 ` Pali Rohár 2022-05-09 10:52 ` Mauri Sandberg 2022-05-09 10:52 ` Mauri Sandberg 2022-04-28 0:29 ` Andrew Lunn 2022-04-28 0:29 ` Andrew Lunn 2022-09-22 20:24 ` [PATCH v2 0/3] ARM: orion5x: add D-Link DNS323 based on device treee Mauri Sandberg 2022-09-22 20:24 ` Mauri Sandberg 2022-09-22 20:24 ` [PATCH v2 1/3] dt-bindings: arm: add DT binding for D-Link DNS-323 Mauri Sandberg 2022-09-22 20:24 ` Mauri Sandberg 2022-09-22 20:36 ` Andrew Lunn 2022-09-22 20:36 ` Andrew Lunn 2022-09-23 9:18 ` Krzysztof Kozlowski 2022-09-23 9:18 ` Krzysztof Kozlowski 2022-09-22 20:24 ` [PATCH v2 2/3] ARM: dts: orion5x: Add D-Link DNS-323 Device Tree Mauri Sandberg 2022-09-22 20:24 ` Mauri Sandberg 2022-09-22 20:45 ` Andrew Lunn 2022-09-22 20:45 ` Andrew Lunn 2022-09-22 21:14 ` Pali Rohár 2022-09-22 21:14 ` Pali Rohár 2022-09-22 21:32 ` Andrew Lunn 2022-09-22 21:32 ` Andrew Lunn 2022-09-23 9:19 ` Krzysztof Kozlowski 2022-09-23 9:19 ` Krzysztof Kozlowski 2022-09-27 11:26 ` kernel test robot 2022-09-27 22:56 ` kernel test robot 2022-09-22 20:24 ` [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on " Mauri Sandberg 2022-09-22 20:24 ` Mauri Sandberg 2022-09-22 21:10 ` Andrew Lunn 2022-09-22 21:10 ` Andrew Lunn 2022-09-23 9:03 ` maukka 2022-09-23 9:03 ` maukka 2022-09-23 12:12 ` Andrew Lunn 2022-09-23 12:12 ` Andrew Lunn 2022-09-23 18:02 ` Pali Rohár 2022-09-23 18:02 ` Pali Rohár 2022-09-26 11:56 ` maukka 2022-09-26 11:56 ` maukka 2022-09-26 12:23 ` Pali Rohár 2022-09-28 13:32 ` [EXT] " Elad Nachman 2022-09-30 15:40 ` Pali Rohár 2022-09-22 21:39 ` Arnd Bergmann 2022-09-22 21:39 ` Arnd Bergmann 2022-09-23 9:13 ` maukka 2022-09-23 9:13 ` maukka 2022-09-23 9:24 ` Arnd Bergmann 2022-09-23 9:24 ` Arnd Bergmann
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