From: Arnd Bergmann <arnd@arndb.de> To: Catalin Marinas <catalin.marinas@arm.com> Cc: Arnd Bergmann <arnd@arndb.de>, Christoph Hellwig <hch@infradead.org>, Ard Biesheuvel <ardb@kernel.org>, Herbert Xu <herbert@gondor.apana.org.au>, Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Andrew Morton <akpm@linux-foundation.org>, Linus Torvalds <torvalds@linux-foundation.org>, Linux Memory Management List <linux-mm@kvack.org>, Linux ARM <linux-arm-kernel@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, "David S. Miller" <davem@davemloft.net> Subject: Re: [PATCH 07/10] crypto: Use ARCH_DMA_MINALIGN instead of ARCH_KMALLOC_MINALIGN Date: Thu, 21 Apr 2022 15:47:30 +0200 [thread overview] Message-ID: <CAK8P3a28NuZE628f1Bga_-gGSpHnPFx=2cBW0oDW4MFAzCSb+w@mail.gmail.com> (raw) In-Reply-To: <YmFbQiSFyQ+W85Zx@arm.com> On Thu, Apr 21, 2022 at 3:25 PM Catalin Marinas <catalin.marinas@arm.com> wrote: > On Thu, Apr 21, 2022 at 02:28:45PM +0200, Arnd Bergmann wrote: > > We also know that larger slabs are all cacheline aligned, so simply > > comparing the transfer size is enough to rule out most, in this case > > any transfer larger than 96 bytes must come from the kmalloc-128 > > or larger cache, so that works like before. > > There's also the case with 128-byte cache lines and kmalloc-192. Sure, but that's much less common, as the few machines with 128 byte cache lines tend to also have cache coherent devices IIRC, so we'd skip the bounce buffer entirely. > > For transfers <=96 bytes, the possibilities are: > > > > 1.kmalloc-32 or smaller, always needs to bounce > > 2. kmalloc-96, but at least one byte in partial cache line, > > need to bounce > > 3. kmalloc-64, may skip the bounce. > > 4. kmalloc-128 or larger, or not a slab cache but a partial > > transfer, may skip the bounce. > > > > I would guess that the first case is the most common here, > > so unless bouncing one or two cache lines is extremely > > expensive, I don't expect it to be worth optimizing for the latter > > two cases. > > I think so. If someone complains of a performance regression, we can > look at optimising the bounce. I have a suspicion the cost of copying > two cache lines is small compared to swiotlb_find_slots() etc. That is possible, and we'd definitely have to watch out for performance regressions, I'm just skeptical that the cases that suffer from the extra bouncer buffering on 33..64 byte allocations benefit much from having a special case if the 1...32 and 65..96 byte allocations are still slow. Another simpler way to do this might be to just not create the kmalloc-96 (or kmalloc-192) caches, and assuming that any transfer >=33 (or 65) bytes is safe. Arnd
WARNING: multiple messages have this Message-ID (diff)
From: Arnd Bergmann <arnd@arndb.de> To: Catalin Marinas <catalin.marinas@arm.com> Cc: Arnd Bergmann <arnd@arndb.de>, Christoph Hellwig <hch@infradead.org>, Ard Biesheuvel <ardb@kernel.org>, Herbert Xu <herbert@gondor.apana.org.au>, Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Andrew Morton <akpm@linux-foundation.org>, Linus Torvalds <torvalds@linux-foundation.org>, Linux Memory Management List <linux-mm@kvack.org>, Linux ARM <linux-arm-kernel@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, "David S. Miller" <davem@davemloft.net> Subject: Re: [PATCH 07/10] crypto: Use ARCH_DMA_MINALIGN instead of ARCH_KMALLOC_MINALIGN Date: Thu, 21 Apr 2022 15:47:30 +0200 [thread overview] Message-ID: <CAK8P3a28NuZE628f1Bga_-gGSpHnPFx=2cBW0oDW4MFAzCSb+w@mail.gmail.com> (raw) In-Reply-To: <YmFbQiSFyQ+W85Zx@arm.com> On Thu, Apr 21, 2022 at 3:25 PM Catalin Marinas <catalin.marinas@arm.com> wrote: > On Thu, Apr 21, 2022 at 02:28:45PM +0200, Arnd Bergmann wrote: > > We also know that larger slabs are all cacheline aligned, so simply > > comparing the transfer size is enough to rule out most, in this case > > any transfer larger than 96 bytes must come from the kmalloc-128 > > or larger cache, so that works like before. > > There's also the case with 128-byte cache lines and kmalloc-192. Sure, but that's much less common, as the few machines with 128 byte cache lines tend to also have cache coherent devices IIRC, so we'd skip the bounce buffer entirely. > > For transfers <=96 bytes, the possibilities are: > > > > 1.kmalloc-32 or smaller, always needs to bounce > > 2. kmalloc-96, but at least one byte in partial cache line, > > need to bounce > > 3. kmalloc-64, may skip the bounce. > > 4. kmalloc-128 or larger, or not a slab cache but a partial > > transfer, may skip the bounce. > > > > I would guess that the first case is the most common here, > > so unless bouncing one or two cache lines is extremely > > expensive, I don't expect it to be worth optimizing for the latter > > two cases. > > I think so. If someone complains of a performance regression, we can > look at optimising the bounce. I have a suspicion the cost of copying > two cache lines is small compared to swiotlb_find_slots() etc. That is possible, and we'd definitely have to watch out for performance regressions, I'm just skeptical that the cases that suffer from the extra bouncer buffering on 33..64 byte allocations benefit much from having a special case if the 1...32 and 65..96 byte allocations are still slow. Another simpler way to do this might be to just not create the kmalloc-96 (or kmalloc-192) caches, and assuming that any transfer >=33 (or 65) bytes is safe. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-04-21 13:47 UTC|newest] Thread overview: 287+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-05 13:57 [PATCH 00/10] mm, arm64: Reduce ARCH_KMALLOC_MINALIGN below the cache line size Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-05 13:57 ` [PATCH 01/10] mm/slab: Decouple ARCH_KMALLOC_MINALIGN from ARCH_DMA_MINALIGN Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-05 23:59 ` Hyeonggon Yoo 2022-04-05 23:59 ` Hyeonggon Yoo 2022-04-06 7:29 ` Arnd Bergmann 2022-04-06 7:29 ` Arnd Bergmann 2022-04-06 12:09 ` Hyeonggon Yoo 2022-04-06 12:09 ` Hyeonggon Yoo 2022-04-06 8:53 ` Catalin Marinas 2022-04-06 8:53 ` Catalin Marinas 2022-04-06 2:01 ` kernel test robot 2022-04-06 8:56 ` Catalin Marinas 2022-04-06 8:56 ` Catalin Marinas 2022-04-06 12:18 ` [kbuild-all] " Chen, Rong A 2022-04-08 6:42 ` Hyeonggon Yoo 2022-04-08 6:42 ` Hyeonggon Yoo 2022-04-08 9:06 ` Hyeonggon Yoo 2022-04-08 9:06 ` Hyeonggon Yoo 2022-04-08 9:11 ` Catalin Marinas 2022-04-08 9:11 ` Catalin Marinas 2022-04-11 10:37 ` Hyeonggon Yoo 2022-04-11 10:37 ` Hyeonggon Yoo 2022-04-11 14:02 ` Catalin Marinas 2022-04-11 14:02 ` Catalin Marinas 2022-04-05 13:57 ` [PATCH 02/10] drivers/base: Use ARCH_DMA_MINALIGN instead of ARCH_KMALLOC_MINALIGN Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-11 14:57 ` Andy Shevchenko 2022-04-11 14:57 ` Andy Shevchenko 2022-04-11 17:39 ` Catalin Marinas 2022-04-11 17:39 ` Catalin Marinas 2022-04-05 13:57 ` [PATCH 03/10] drivers/gpu: " Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-05 13:57 ` [PATCH 04/10] drivers/md: " Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-05 13:57 ` [PATCH 05/10] drivers/spi: " Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-05 14:05 ` Mark Brown 2022-04-05 14:05 ` Mark Brown 2022-04-05 13:57 ` [PATCH 06/10] drivers/usb: " Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-05 13:57 ` [PATCH 07/10] crypto: " Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-05 22:57 ` Herbert Xu 2022-04-05 22:57 ` Herbert Xu 2022-04-06 6:53 ` Ard Biesheuvel 2022-04-06 6:53 ` Ard Biesheuvel 2022-04-06 8:49 ` Catalin Marinas 2022-04-06 8:49 ` Catalin Marinas 2022-04-06 9:41 ` Ard Biesheuvel 2022-04-06 9:41 ` Ard Biesheuvel 2022-04-07 4:30 ` Herbert Xu 2022-04-07 4:30 ` Herbert Xu 2022-04-07 11:01 ` Catalin Marinas 2022-04-07 11:01 ` Catalin Marinas 2022-04-07 11:40 ` Herbert Xu 2022-04-07 11:40 ` Herbert Xu 2022-04-07 16:28 ` Catalin Marinas 2022-04-07 16:28 ` Catalin Marinas 2022-04-08 3:25 ` Herbert Xu 2022-04-08 3:25 ` Herbert Xu 2022-04-08 9:04 ` Catalin Marinas 2022-04-08 9:04 ` Catalin Marinas 2022-04-08 9:11 ` Herbert Xu 2022-04-08 9:11 ` Herbert Xu 2022-04-12 9:32 ` Catalin Marinas 2022-04-12 9:32 ` Catalin Marinas 2022-04-12 9:40 ` Herbert Xu 2022-04-12 9:40 ` Herbert Xu 2022-04-12 10:02 ` Catalin Marinas 2022-04-12 10:02 ` Catalin Marinas 2022-04-12 10:18 ` Herbert Xu 2022-04-12 10:18 ` Herbert Xu 2022-04-12 12:31 ` Catalin Marinas 2022-04-12 12:31 ` Catalin Marinas 2022-04-12 22:01 ` Ard Biesheuvel 2022-04-12 22:01 ` Ard Biesheuvel 2022-04-13 8:47 ` Catalin Marinas 2022-04-13 8:47 ` Catalin Marinas 2022-04-13 19:53 ` Linus Torvalds 2022-04-13 19:53 ` Linus Torvalds 2022-04-14 5:38 ` Greg Kroah-Hartman 2022-04-14 5:38 ` Greg Kroah-Hartman 2022-04-14 13:52 ` Ard Biesheuvel 2022-04-14 13:52 ` Ard Biesheuvel 2022-04-14 14:27 ` Greg Kroah-Hartman 2022-04-14 14:27 ` Greg Kroah-Hartman 2022-04-14 14:36 ` Ard Biesheuvel 2022-04-14 14:36 ` Ard Biesheuvel 2022-04-14 14:52 ` Greg Kroah-Hartman 2022-04-14 14:52 ` Greg Kroah-Hartman 2022-04-14 15:01 ` Ard Biesheuvel 2022-04-14 15:01 ` Ard Biesheuvel 2022-04-14 15:10 ` Ard Biesheuvel 2022-04-14 15:10 ` Ard Biesheuvel 2022-04-14 19:49 ` Catalin Marinas 2022-04-14 19:49 ` Catalin Marinas 2022-04-14 22:25 ` Linus Torvalds 2022-04-14 22:25 ` Linus Torvalds 2022-04-15 6:03 ` Ard Biesheuvel 2022-04-15 6:03 ` Ard Biesheuvel 2022-04-15 11:09 ` Arnd Bergmann 2022-04-15 11:09 ` Arnd Bergmann 2022-04-16 9:42 ` Catalin Marinas 2022-04-16 9:42 ` Catalin Marinas 2022-04-20 19:07 ` Catalin Marinas 2022-04-20 19:07 ` Catalin Marinas 2022-04-20 19:33 ` Linus Torvalds 2022-04-20 19:33 ` Linus Torvalds 2022-04-14 14:30 ` Ard Biesheuvel 2022-04-14 14:30 ` Ard Biesheuvel 2022-04-15 6:51 ` Herbert Xu 2022-04-15 6:51 ` Herbert Xu 2022-04-15 7:49 ` Ard Biesheuvel 2022-04-15 7:49 ` Ard Biesheuvel 2022-04-15 7:51 ` Herbert Xu 2022-04-15 7:51 ` Herbert Xu 2022-04-15 8:05 ` Ard Biesheuvel 2022-04-15 8:05 ` Ard Biesheuvel 2022-04-15 8:12 ` Herbert Xu 2022-04-15 8:12 ` Herbert Xu 2022-04-15 9:51 ` Ard Biesheuvel 2022-04-15 9:51 ` Ard Biesheuvel 2022-04-15 10:04 ` Ard Biesheuvel 2022-04-15 10:04 ` Ard Biesheuvel 2022-04-15 10:12 ` Herbert Xu 2022-04-15 10:12 ` Herbert Xu 2022-04-15 10:22 ` Ard Biesheuvel 2022-04-15 10:22 ` Ard Biesheuvel 2022-04-15 10:45 ` Herbert Xu 2022-04-15 10:45 ` Herbert Xu 2022-04-15 11:38 ` Ard Biesheuvel 2022-04-15 11:38 ` Ard Biesheuvel 2022-04-17 8:08 ` Herbert Xu 2022-04-17 8:08 ` Herbert Xu 2022-04-17 8:31 ` Catalin Marinas 2022-04-17 8:31 ` Catalin Marinas 2022-04-17 8:35 ` Herbert Xu 2022-04-17 8:35 ` Herbert Xu 2022-04-17 8:50 ` Catalin Marinas 2022-04-17 8:50 ` Catalin Marinas 2022-04-17 8:58 ` Herbert Xu 2022-04-17 8:58 ` Herbert Xu 2022-04-17 16:30 ` Catalin Marinas 2022-04-17 16:30 ` Catalin Marinas 2022-04-18 8:37 ` Herbert Xu 2022-04-18 8:37 ` Herbert Xu 2022-04-18 9:19 ` Catalin Marinas 2022-04-18 9:19 ` Catalin Marinas 2022-04-18 16:44 ` Catalin Marinas 2022-04-18 16:44 ` Catalin Marinas 2022-04-19 21:50 ` Ard Biesheuvel 2022-04-19 21:50 ` Ard Biesheuvel 2022-04-20 10:36 ` Catalin Marinas 2022-04-20 10:36 ` Catalin Marinas 2022-04-20 11:29 ` Arnd Bergmann 2022-04-20 11:29 ` Arnd Bergmann 2022-04-21 7:20 ` Christoph Hellwig 2022-04-21 7:20 ` Christoph Hellwig 2022-04-21 7:36 ` Arnd Bergmann 2022-04-21 7:36 ` Arnd Bergmann 2022-04-21 7:44 ` Christoph Hellwig 2022-04-21 7:44 ` Christoph Hellwig 2022-04-21 8:05 ` Ard Biesheuvel 2022-04-21 8:05 ` Ard Biesheuvel 2022-04-21 11:06 ` Catalin Marinas 2022-04-21 11:06 ` Catalin Marinas 2022-04-21 12:28 ` Arnd Bergmann 2022-04-21 12:28 ` Arnd Bergmann 2022-04-21 13:25 ` Catalin Marinas 2022-04-21 13:25 ` Catalin Marinas 2022-04-21 13:47 ` Arnd Bergmann [this message] 2022-04-21 13:47 ` Arnd Bergmann 2022-04-21 14:44 ` Catalin Marinas 2022-04-21 14:44 ` Catalin Marinas 2022-04-21 14:47 ` Arnd Bergmann 2022-04-21 14:47 ` Arnd Bergmann 2022-05-10 11:03 ` [RFC PATCH 0/7] crypto: Add helpers for allocating with DMA alignment Herbert Xu 2022-05-10 11:03 ` Herbert Xu 2022-05-10 11:07 ` [RFC PATCH 1/7] crypto: Prepare to move crypto_tfm_ctx Herbert Xu 2022-05-10 11:07 ` Herbert Xu 2022-05-10 11:07 ` [RFC PATCH 2/7] crypto: api - Add crypto_tfm_ctx_dma Herbert Xu 2022-05-10 11:07 ` Herbert Xu 2022-05-10 17:10 ` Catalin Marinas 2022-05-10 17:10 ` Catalin Marinas 2022-05-12 3:57 ` Herbert Xu 2022-05-12 3:57 ` Herbert Xu 2022-05-10 11:07 ` [RFC PATCH 3/7] crypto: aead - Add ctx helpers with DMA alignment Herbert Xu 2022-05-10 11:07 ` Herbert Xu 2022-05-10 11:07 ` [RFC PATCH 4/7] crypto: hash " Herbert Xu 2022-05-10 11:07 ` Herbert Xu 2022-05-10 11:07 ` [RFC PATCH 5/7] crypto: skcipher " Herbert Xu 2022-05-10 11:07 ` Herbert Xu 2022-05-10 11:07 ` [RFC PATCH 6/7] crypto: api - Increase MAX_ALGAPI_ALIGNMASK to 127 Herbert Xu 2022-05-10 11:07 ` Herbert Xu 2022-05-10 11:07 ` [RFC PATCH 7/7] crypto: caam - Explicitly request DMA alignment Herbert Xu 2022-05-10 11:07 ` Herbert Xu 2022-04-15 12:18 ` [PATCH 07/10] crypto: Use ARCH_DMA_MINALIGN instead of ARCH_KMALLOC_MINALIGN Catalin Marinas 2022-04-15 12:18 ` Catalin Marinas 2022-04-15 12:25 ` Ard Biesheuvel 2022-04-15 12:25 ` Ard Biesheuvel 2022-04-15 9:51 ` Catalin Marinas 2022-04-15 9:51 ` Catalin Marinas 2022-04-15 12:31 ` Catalin Marinas 2022-04-15 12:31 ` Catalin Marinas 2022-04-17 8:11 ` Herbert Xu 2022-04-17 8:11 ` Herbert Xu 2022-04-17 8:38 ` Catalin Marinas 2022-04-17 8:38 ` Catalin Marinas 2022-04-17 8:43 ` Herbert Xu 2022-04-17 8:43 ` Herbert Xu 2022-04-17 16:29 ` Catalin Marinas 2022-04-17 16:29 ` Catalin Marinas 2022-07-15 22:23 ` Isaac Manjarres 2022-07-15 22:23 ` Isaac Manjarres 2022-07-16 3:25 ` Herbert Xu 2022-07-16 3:25 ` Herbert Xu 2022-07-18 17:53 ` Catalin Marinas 2022-07-18 17:53 ` Catalin Marinas 2022-09-21 0:47 ` Isaac Manjarres 2022-09-21 0:47 ` Isaac Manjarres 2022-09-30 18:32 ` Catalin Marinas 2022-09-30 18:32 ` Catalin Marinas 2022-09-30 19:35 ` Linus Torvalds 2022-09-30 19:35 ` Linus Torvalds 2022-10-01 22:29 ` Catalin Marinas 2022-10-01 22:29 ` Catalin Marinas 2022-10-02 17:00 ` Linus Torvalds 2022-10-02 17:00 ` Linus Torvalds 2022-10-02 22:08 ` Ard Biesheuvel 2022-10-02 22:08 ` Ard Biesheuvel 2022-10-02 22:24 ` Linus Torvalds 2022-10-02 22:24 ` Linus Torvalds 2022-10-03 17:39 ` Catalin Marinas 2022-10-03 17:39 ` Catalin Marinas 2022-10-12 17:45 ` Isaac Manjarres 2022-10-12 17:45 ` Isaac Manjarres 2022-10-13 16:57 ` Catalin Marinas 2022-10-13 16:57 ` Catalin Marinas 2022-10-13 18:58 ` Saravana Kannan 2022-10-13 18:58 ` Saravana Kannan 2022-10-14 16:25 ` Catalin Marinas 2022-10-14 16:25 ` Catalin Marinas 2022-10-14 20:23 ` Saravana Kannan 2022-10-14 20:23 ` Saravana Kannan 2022-10-14 20:44 ` Linus Torvalds 2022-10-14 20:44 ` Linus Torvalds 2022-10-16 21:37 ` Catalin Marinas 2022-10-16 21:37 ` Catalin Marinas 2022-04-12 10:20 ` Catalin Marinas 2022-04-12 10:20 ` Catalin Marinas 2022-04-07 6:14 ` Muchun Song 2022-04-07 6:14 ` Muchun Song 2022-04-07 9:25 ` Catalin Marinas 2022-04-07 9:25 ` Catalin Marinas 2022-04-07 10:00 ` Muchun Song 2022-04-07 10:00 ` Muchun Song 2022-04-07 11:06 ` Catalin Marinas 2022-04-07 11:06 ` Catalin Marinas 2022-04-05 13:57 ` [PATCH 08/10] mm/slab: Allow dynamic kmalloc() minimum alignment Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-07 3:46 ` Hyeonggon Yoo 2022-04-07 3:46 ` Hyeonggon Yoo 2022-04-07 8:50 ` Catalin Marinas 2022-04-07 8:50 ` Catalin Marinas 2022-04-07 9:18 ` Hyeonggon Yoo 2022-04-07 9:18 ` Hyeonggon Yoo 2022-04-07 9:35 ` Catalin Marinas 2022-04-07 9:35 ` Catalin Marinas 2022-04-07 12:26 ` Hyeonggon Yoo 2022-04-07 12:26 ` Hyeonggon Yoo 2022-04-11 11:55 ` Hyeonggon Yoo 2022-04-11 11:55 ` Hyeonggon Yoo 2022-04-05 13:57 ` [PATCH 09/10] mm/slab: Simplify create_kmalloc_cache() args and make it static Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-06 5:35 ` kernel test robot 2022-04-06 8:57 ` Catalin Marinas 2022-04-06 8:57 ` Catalin Marinas 2022-04-05 13:57 ` [PATCH 10/10] arm64: Enable dynamic kmalloc() minimum alignment Catalin Marinas 2022-04-05 13:57 ` Catalin Marinas 2022-04-07 14:40 ` [PATCH 00/10] mm, arm64: Reduce ARCH_KMALLOC_MINALIGN below the cache line size Vlastimil Babka 2022-04-07 14:40 ` Vlastimil Babka 2022-04-07 17:48 ` Catalin Marinas 2022-04-07 17:48 ` Catalin Marinas 2022-04-08 14:37 ` Vlastimil Babka 2022-04-08 14:37 ` Vlastimil Babka
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