From: Kever Yang <kever.yang@rock-chips.com>
To: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>, sjg <sjg@chromium.org>,
Kever Yang <kever.yang@rock-chips.com>,
Peng Fan <peng.fan@nxp.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
U-Boot-Denx <u-boot@lists.denx.de>
Subject: Re: [PATCH v3 2/3] mmc: rockchip_sdhci: Add support for RK3568
Date: Wed, 11 Aug 2021 17:56:24 +0800 [thread overview]
Message-ID: <CAKUh=RyPKmpn9e0b8YJUjkvkgpiKbQBhvTNZK_9B8Ot_6jpprQ@mail.gmail.com> (raw)
In-Reply-To: <20210629082443.22308-3-yifeng.zhao@rock-chips.com>
Yifeng Zhao <yifeng.zhao@rock-chips.com> 于2021年6月29日周二 下午7:40写道:
>
> This patch adds support for the RK3568 platform to this driver.
>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
>
> Changes in v3:
> - Config the interface clock by clk_set_rate directly
>
> Changes in v2:
> - Used sdhci_set_clock api to set clock.
> - Used read_poll_timeout api to check dll status.
>
> drivers/mmc/rockchip_sdhci.c | 109 +++++++++++++++++++++++++++++++++++
> 1 file changed, 109 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index eff134c8f5..1ac00587d4 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -42,6 +42,34 @@
> ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
> PHYCTRL_DLLRDY_DONE)
>
> +/* Rockchip specific Registers */
> +#define DWCMSHC_EMMC_DLL_CTRL 0x800
> +#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
> +#define DWCMSHC_EMMC_DLL_RXCLK 0x804
> +#define DWCMSHC_EMMC_DLL_TXCLK 0x808
> +#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
> +#define DWCMSHC_EMMC_DLL_STATUS0 0x840
> +#define DWCMSHC_EMMC_DLL_STATUS1 0x844
> +#define DWCMSHC_EMMC_DLL_START BIT(0)
> +#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
> +#define DWCMSHC_EMMC_DLL_START_POINT 16
> +#define DWCMSHC_EMMC_DLL_START_DEFAULT 5
> +#define DWCMSHC_EMMC_DLL_INC_VALUE 2
> +#define DWCMSHC_EMMC_DLL_INC 8
> +#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
> +#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
> +#define DLL_STRBIN_TAPNUM_DEFAULT 0x3
> +#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
> +#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
> +#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
> +#define DLL_RXCLK_NO_INVERTER 1
> +#define DLL_RXCLK_INVERTER 0
> +#define DWCMSHC_ENHANCED_STROBE BIT(8)
> +#define DLL_LOCK_WO_TMOUT(x) \
> + ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
> + (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
> +#define ROCKCHIP_MAX_CLKS 3
> +
> struct rockchip_sdhc_plat {
> struct mmc_config cfg;
> struct mmc mmc;
> @@ -167,6 +195,77 @@ static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
> return 0;
> }
>
> +static int rk3568_emmc_phy_init(struct udevice *dev)
> +{
> + struct rockchip_sdhc *prv = dev_get_priv(dev);
> + struct sdhci_host *host = &prv->host;
> + u32 extra;
> +
> + extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
> + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
> +
> + return 0;
> +}
> +
> +static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
> +{
> + struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
> + int val, ret;
> + u32 extra;
> +
> + if (clock > host->max_clk)
> + clock = host->max_clk;
> + if (clock)
> + clk_set_rate(&priv->emmc_clk, clock);
> +
> + sdhci_set_clock(host->mmc, clock);
> +
> + if (clock >= 100 * MHz) {
> + /* reset DLL */
> + sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
> + udelay(1);
> + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
> +
> + /* Init DLL settings */
> + extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
> + DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
> + DWCMSHC_EMMC_DLL_START;
> + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
> +
> + ret = read_poll_timeout(readl, host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
> + val, DLL_LOCK_WO_TMOUT(val), 1, 500);
> + if (ret)
> + return ret;
> +
> + extra = DWCMSHC_EMMC_DLL_DLYENA |
> + DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
> + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
> +
> + extra = DWCMSHC_EMMC_DLL_DLYENA |
> + DLL_TXCLK_TAPNUM_DEFAULT |
> + DLL_TXCLK_TAPNUM_FROM_SW;
> + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
> +
> + extra = DWCMSHC_EMMC_DLL_DLYENA |
> + DLL_STRBIN_TAPNUM_DEFAULT;
> + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
> + } else {
> + /* reset the clock phase when the frequency is lower than 100MHz */
> + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
> + extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
> + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
> + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
> + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
> + }
> +
> + return 0;
> +}
> +
> +static int rk3568_emmc_get_phy(struct udevice *dev)
> +{
> + return 0;
> +}
> +
> static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
> {
> struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
> @@ -339,11 +438,21 @@ static const struct sdhci_data rk3399_data = {
> .emmc_phy_init = rk3399_emmc_phy_init,
> };
>
> +static const struct sdhci_data rk3568_data = {
> + .emmc_set_clock = rk3568_sdhci_emmc_set_clock,
> + .get_phy = rk3568_emmc_get_phy,
> + .emmc_phy_init = rk3568_emmc_phy_init,
> +};
> +
> static const struct udevice_id sdhci_ids[] = {
> {
> .compatible = "arasan,sdhci-5.1",
> .data = (ulong)&rk3399_data,
> },
> + {
> + .compatible = "rockchip,rk3568-dwcmshc",
> + .data = (ulong)&rk3568_data,
> + },
> { }
> };
>
> --
> 2.17.1
>
>
>
next prev parent reply other threads:[~2021-08-11 9:56 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-29 8:24 [PATCH v3 0/3] Add hs400 support for rk3399 and rk3568 Yifeng Zhao
2021-06-29 8:24 ` [PATCH v3 1/3] mmc: rockchip_sdhci: add phy and clock config for rk3399 Yifeng Zhao
2021-06-29 21:53 ` Jaehoon Chung
2021-08-11 9:55 ` Kever Yang
2021-10-29 15:44 ` Jack Mitchell
2021-11-25 0:12 ` Simon Glass
2021-06-29 8:24 ` [PATCH v3 2/3] mmc: rockchip_sdhci: Add support for RK3568 Yifeng Zhao
2021-06-29 21:53 ` Jaehoon Chung
2021-08-11 9:56 ` Kever Yang [this message]
2021-08-11 10:23 ` Philipp Tomsich
2021-06-29 8:24 ` [PATCH v3 3/3] rockchip: config: evb-rk3399: add hs400 and SDMA support Yifeng Zhao
2021-08-11 9:56 ` Kever Yang
2021-08-11 10:18 ` Philipp Tomsich
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAKUh=RyPKmpn9e0b8YJUjkvkgpiKbQBhvTNZK_9B8Ot_6jpprQ@mail.gmail.com' \
--to=kever.yang@rock-chips.com \
--cc=jh80.chung@samsung.com \
--cc=peng.fan@nxp.com \
--cc=philipp.tomsich@vrull.eu \
--cc=sjg@chromium.org \
--cc=u-boot@lists.denx.de \
--cc=yifeng.zhao@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.