* [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
@ 2020-11-11 9:47 ` Anup Patel
0 siblings, 0 replies; 6+ messages in thread
From: Anup Patel @ 2020-11-11 9:47 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
The sifive_u machine emulates two UARTs but we have only UART0 DT
node in the generated DTB so this patch adds UART1 DT node in the
generated DTB.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/sifive_u.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2f19a9cda2..146944a293 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/serial@%lx",
+ (long)memmap[SIFIVE_U_DEV_UART1].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_DEV_UART1].base,
+ 0x0, memmap[SIFIVE_U_DEV_UART1].size);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
+
+ qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
+ g_free(nodename);
+
nodename = g_strdup_printf("/soc/serial@%lx",
(long)memmap[SIFIVE_U_DEV_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
@ 2020-11-11 9:47 ` Anup Patel
0 siblings, 0 replies; 6+ messages in thread
From: Anup Patel @ 2020-11-11 9:47 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
The sifive_u machine emulates two UARTs but we have only UART0 DT
node in the generated DTB so this patch adds UART1 DT node in the
generated DTB.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/sifive_u.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2f19a9cda2..146944a293 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/serial@%lx",
+ (long)memmap[SIFIVE_U_DEV_UART1].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_DEV_UART1].base,
+ 0x0, memmap[SIFIVE_U_DEV_UART1].size);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
+
+ qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
+ g_free(nodename);
+
nodename = g_strdup_printf("/soc/serial@%lx",
(long)memmap[SIFIVE_U_DEV_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
2020-11-11 9:47 ` Anup Patel
@ 2020-11-11 16:50 ` Alistair Francis
-1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-11-11 16:50 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Wed, Nov 11, 2020 at 1:48 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The sifive_u machine emulates two UARTs but we have only UART0 DT
> node in the generated DTB so this patch adds UART1 DT node in the
> generated DTB.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/sifive_u.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 2f19a9cda2..146944a293 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> g_free(nodename);
>
> + nodename = g_strdup_printf("/soc/serial@%lx",
> + (long)memmap[SIFIVE_U_DEV_UART1].base);
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
> + qemu_fdt_setprop_cells(fdt, nodename, "reg",
> + 0x0, memmap[SIFIVE_U_DEV_UART1].base,
> + 0x0, memmap[SIFIVE_U_DEV_UART1].size);
> + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> + prci_phandle, PRCI_CLK_TLCLK);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
> +
> + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
> + g_free(nodename);
> +
> nodename = g_strdup_printf("/soc/serial@%lx",
> (long)memmap[SIFIVE_U_DEV_UART0].base);
> qemu_fdt_add_subnode(fdt, nodename);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
@ 2020-11-11 16:50 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-11-11 16:50 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Atish Patra, open list:RISC-V,
qemu-devel@nongnu.org Developers, Anup Patel
On Wed, Nov 11, 2020 at 1:48 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The sifive_u machine emulates two UARTs but we have only UART0 DT
> node in the generated DTB so this patch adds UART1 DT node in the
> generated DTB.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/sifive_u.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 2f19a9cda2..146944a293 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> g_free(nodename);
>
> + nodename = g_strdup_printf("/soc/serial@%lx",
> + (long)memmap[SIFIVE_U_DEV_UART1].base);
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
> + qemu_fdt_setprop_cells(fdt, nodename, "reg",
> + 0x0, memmap[SIFIVE_U_DEV_UART1].base,
> + 0x0, memmap[SIFIVE_U_DEV_UART1].size);
> + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> + prci_phandle, PRCI_CLK_TLCLK);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
> +
> + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
> + g_free(nodename);
> +
> nodename = g_strdup_printf("/soc/serial@%lx",
> (long)memmap[SIFIVE_U_DEV_UART0].base);
> qemu_fdt_add_subnode(fdt, nodename);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
2020-11-11 9:47 ` Anup Patel
@ 2020-11-11 21:59 ` Alistair Francis
-1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-11-11 21:59 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Wed, Nov 11, 2020 at 1:48 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The sifive_u machine emulates two UARTs but we have only UART0 DT
> node in the generated DTB so this patch adds UART1 DT node in the
> generated DTB.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/riscv/sifive_u.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 2f19a9cda2..146944a293 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> g_free(nodename);
>
> + nodename = g_strdup_printf("/soc/serial@%lx",
> + (long)memmap[SIFIVE_U_DEV_UART1].base);
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
> + qemu_fdt_setprop_cells(fdt, nodename, "reg",
> + 0x0, memmap[SIFIVE_U_DEV_UART1].base,
> + 0x0, memmap[SIFIVE_U_DEV_UART1].size);
> + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> + prci_phandle, PRCI_CLK_TLCLK);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
> +
> + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
> + g_free(nodename);
> +
> nodename = g_strdup_printf("/soc/serial@%lx",
> (long)memmap[SIFIVE_U_DEV_UART0].base);
> qemu_fdt_add_subnode(fdt, nodename);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
@ 2020-11-11 21:59 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-11-11 21:59 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Atish Patra, open list:RISC-V,
qemu-devel@nongnu.org Developers, Anup Patel
On Wed, Nov 11, 2020 at 1:48 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The sifive_u machine emulates two UARTs but we have only UART0 DT
> node in the generated DTB so this patch adds UART1 DT node in the
> generated DTB.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/riscv/sifive_u.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 2f19a9cda2..146944a293 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> g_free(nodename);
>
> + nodename = g_strdup_printf("/soc/serial@%lx",
> + (long)memmap[SIFIVE_U_DEV_UART1].base);
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
> + qemu_fdt_setprop_cells(fdt, nodename, "reg",
> + 0x0, memmap[SIFIVE_U_DEV_UART1].base,
> + 0x0, memmap[SIFIVE_U_DEV_UART1].size);
> + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> + prci_phandle, PRCI_CLK_TLCLK);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
> +
> + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
> + g_free(nodename);
> +
> nodename = g_strdup_printf("/soc/serial@%lx",
> (long)memmap[SIFIVE_U_DEV_UART0].base);
> qemu_fdt_add_subnode(fdt, nodename);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-11-11 22:12 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-11 9:47 [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Anup Patel
2020-11-11 9:47 ` Anup Patel
2020-11-11 16:50 ` Alistair Francis
2020-11-11 16:50 ` Alistair Francis
2020-11-11 21:59 ` Alistair Francis
2020-11-11 21:59 ` Alistair Francis
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