All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alistair Francis <alistair23@gmail.com>
To: Jim Wilson <jimw@sifive.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	qemu-riscv@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs.
Date: Wed, 6 Feb 2019 15:55:59 -0800	[thread overview]
Message-ID: <CAKmqyKMPYYuD1jRT-9pxgAdBcgA3990MmseMNube_zzP0wmncQ@mail.gmail.com> (raw)
In-Reply-To: <20190130025644.12754-1-jimw@sifive.com>

On Tue, Jan 29, 2019 at 6:57 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Adds a debugger field to CPURISCVState.  Disable mode checks in riscv_csrrw
> when true.
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h |  3 +++
>  target/riscv/csr.c | 16 ++++++++--------
>  2 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 743f02c..faa46d0 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -170,6 +170,9 @@ struct CPURISCVState {
>
>      /* physical memory protection */
>      pmp_table_t pmp_state;
> +
> +    /* True if in debugger mode.  */
> +    bool debugger;
>  #endif
>
>      float_status fp_status;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5e7e7d1..04e6b59 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
>  static int fs(CPURISCVState *env, int csrno)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>  #endif
> @@ -58,7 +58,7 @@ static int ctr(CPURISCVState *env, int csrno)
>  #if !defined(CONFIG_USER_ONLY)
>      target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
>                            env->priv == PRV_S ? env->mcounteren : -1U;
> -    if (!(ctr_en & (1 << (csrno & 31)))) {
> +    if (!env->debugger && !(ctr_en & (1 << (csrno & 31)))) {
>          return -1;
>      }
>  #endif
> @@ -86,7 +86,7 @@ static int pmp(CPURISCVState *env, int csrno)
>  static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>  #endif
> @@ -97,7 +97,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>  static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>      env->mstatus |= MSTATUS_FS;
> @@ -109,7 +109,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>  static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>  #endif
> @@ -120,7 +120,7 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
>  static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>      env->mstatus |= MSTATUS_FS;
> @@ -132,7 +132,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
>  static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>  #endif
> @@ -144,7 +144,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>  static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>      env->mstatus |= MSTATUS_FS;
> --
> 2.7.4
>
>

WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Jim Wilson <jimw@sifive.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	qemu-riscv@nongnu.org
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs.
Date: Wed, 6 Feb 2019 15:55:59 -0800	[thread overview]
Message-ID: <CAKmqyKMPYYuD1jRT-9pxgAdBcgA3990MmseMNube_zzP0wmncQ@mail.gmail.com> (raw)
In-Reply-To: <20190130025644.12754-1-jimw@sifive.com>

On Tue, Jan 29, 2019 at 6:57 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Adds a debugger field to CPURISCVState.  Disable mode checks in riscv_csrrw
> when true.
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h |  3 +++
>  target/riscv/csr.c | 16 ++++++++--------
>  2 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 743f02c..faa46d0 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -170,6 +170,9 @@ struct CPURISCVState {
>
>      /* physical memory protection */
>      pmp_table_t pmp_state;
> +
> +    /* True if in debugger mode.  */
> +    bool debugger;
>  #endif
>
>      float_status fp_status;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5e7e7d1..04e6b59 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
>  static int fs(CPURISCVState *env, int csrno)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>  #endif
> @@ -58,7 +58,7 @@ static int ctr(CPURISCVState *env, int csrno)
>  #if !defined(CONFIG_USER_ONLY)
>      target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
>                            env->priv == PRV_S ? env->mcounteren : -1U;
> -    if (!(ctr_en & (1 << (csrno & 31)))) {
> +    if (!env->debugger && !(ctr_en & (1 << (csrno & 31)))) {
>          return -1;
>      }
>  #endif
> @@ -86,7 +86,7 @@ static int pmp(CPURISCVState *env, int csrno)
>  static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>  #endif
> @@ -97,7 +97,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>  static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>      env->mstatus |= MSTATUS_FS;
> @@ -109,7 +109,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>  static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>  #endif
> @@ -120,7 +120,7 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
>  static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>      env->mstatus |= MSTATUS_FS;
> @@ -132,7 +132,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
>  static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>  #endif
> @@ -144,7 +144,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>  static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    if (!(env->mstatus & MSTATUS_FS)) {
> +    if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>          return -1;
>      }
>      env->mstatus |= MSTATUS_FS;
> --
> 2.7.4
>
>


  reply	other threads:[~2019-02-06 23:56 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-30  2:49 [Qemu-devel] [PATCH 0/5 v3] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
2019-01-30  2:49 ` [Qemu-riscv] " Jim Wilson
2019-01-30  2:54 ` [Qemu-devel] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files Jim Wilson
2019-01-30  2:54   ` [Qemu-riscv] " Jim Wilson
2019-02-06 23:52   ` [Qemu-devel] " Alistair Francis
2019-02-06 23:52     ` [Qemu-riscv] " Alistair Francis
2019-01-30  2:55 ` [Qemu-devel] [PATCH 2/5 v3] RISC-V: Add 64-bit " Jim Wilson
2019-01-30  2:55   ` [Qemu-riscv] " Jim Wilson
2019-02-06 23:53   ` [Qemu-devel] " Alistair Francis
2019-02-06 23:53     ` [Qemu-riscv] " Alistair Francis
2019-01-30  2:55 ` [Qemu-devel] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros Jim Wilson
2019-01-30  2:55   ` [Qemu-riscv] " Jim Wilson
2019-02-06 23:54   ` [Qemu-devel] " Alistair Francis
2019-02-06 23:54     ` [Qemu-riscv] " Alistair Francis
2019-01-30  2:56 ` [Qemu-devel] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs Jim Wilson
2019-01-30  2:56   ` [Qemu-riscv] " Jim Wilson
2019-02-06 23:55   ` Alistair Francis [this message]
2019-02-06 23:55     ` [Qemu-riscv] [Qemu-devel] " Alistair Francis
2019-01-30  2:57 ` [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files Jim Wilson
2019-01-30  2:57   ` [Qemu-riscv] " Jim Wilson
2019-02-07  0:04   ` [Qemu-devel] " Alistair Francis
2019-02-07  0:04     ` [Qemu-riscv] " Alistair Francis
2019-02-07  2:05     ` Jim Wilson
2019-02-07  2:05       ` [Qemu-riscv] " Jim Wilson
2019-02-07 12:04       ` Richard Henderson
2019-02-07 12:04         ` [Qemu-riscv] " Richard Henderson
2019-02-08 18:16       ` Alistair Francis
2019-02-08 18:16         ` [Qemu-riscv] " Alistair Francis
2019-02-08 19:08         ` Jim Wilson
2019-02-08 19:08           ` [Qemu-riscv] " Jim Wilson
2019-02-08 19:28           ` Alistair Francis
2019-02-08 19:28             ` [Qemu-riscv] " Alistair Francis
2019-02-11 18:17             ` Palmer Dabbelt
2019-02-11 18:17               ` [Qemu-riscv] " Palmer Dabbelt

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAKmqyKMPYYuD1jRT-9pxgAdBcgA3990MmseMNube_zzP0wmncQ@mail.gmail.com \
    --to=alistair23@gmail.com \
    --cc=jimw@sifive.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.